update at91sam9263ek board to new SoC access
* convert at91sam9263ek board to use c stucture SoC access * change gpio access to at91_gpio syntax Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
This commit is contained in:
Jens Scharsig
Tom Rix
parent
0cf0b93161
commit
1b34f00c28
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@ -25,13 +25,13 @@
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#include <common.h>
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#include <asm/sizes.h>
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#include <asm/arch/at91sam9263.h>
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#include <asm/arch/at91sam9263_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_matrix.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/arch/hardware.h>
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#include <lcd.h>
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@ -52,49 +52,57 @@ DECLARE_GLOBAL_DATA_PTR;
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static void at91sam9263ek_nand_hw_init(void)
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{
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unsigned long csa;
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at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE;
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at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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/* Enable CS3 */
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csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
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writel(csa, &matrix->csa[0]);
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
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at91_sys_write(AT91_MATRIX_EBI0CSA,
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csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_DBW_8 |
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#endif
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AT91_SMC_TDF_(2));
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
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1 << AT91SAM9263_ID_PIOCDE);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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writel(1 << AT91SAM9263_ID_PIOA | 1 << AT91SAM9263_ID_PIOCDE,
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&pmc->pcer);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#endif
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#ifdef CONFIG_MACB
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static void at91sam9263ek_macb_hw_init(void)
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{
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unsigned long rstc;
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unsigned long erstl;
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
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at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE;
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
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writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
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/*
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* Disable pull-up on:
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@ -104,35 +112,27 @@ static void at91sam9263ek_macb_hw_init(void)
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*
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* PHY has internal pull-down
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*/
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writel(pin_to_mask(AT91_PIN_PC25),
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pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
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writel(pin_to_mask(AT91_PIN_PE25) |
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pin_to_mask(AT91_PIN_PE26),
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pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
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rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
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writel(1 << 25, &pio->pioc.pudr);
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writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
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erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
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/* Need to reset PHY -> 500ms reset */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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(AT91_RSTC_ERSTL & (0x0D << 8)) |
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AT91_RSTC_URSTEN);
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at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
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writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
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AT91_RSTC_MR_URSTEN, &rstc->mr);
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writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
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/* Wait for end hardware reset */
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while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
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while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
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;
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/* Restore NRST value */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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(rstc) |
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AT91_RSTC_URSTEN);
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writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
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/* Re-enable pull-up */
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writel(pin_to_mask(AT91_PIN_PC25),
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pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
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writel(pin_to_mask(AT91_PIN_PE25) |
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pin_to_mask(AT91_PIN_PE26),
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pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
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writel(1 << 25, &pio->pioc.puer);
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writel((1 << 25) | (1 <<26), &pio->pioe.puer);
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at91_macb_hw_init();
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}
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@ -158,41 +158,42 @@ vidinfo_t panel_info = {
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void lcd_enable(void)
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{
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at91_set_gpio_value(AT91_PIN_PA30, 1); /* power up */
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at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power up */
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}
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void lcd_disable(void)
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{
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at91_set_gpio_value(AT91_PIN_PA30, 0); /* power down */
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at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power down */
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}
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static void at91sam9263ek_lcd_hw_init(void)
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{
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at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
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at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
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at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
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at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
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at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
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at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
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at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
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at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
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at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
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at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
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at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
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at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
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at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
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at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
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at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
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at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
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at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
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at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
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at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
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at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
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at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
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at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
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at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
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at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
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at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
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at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
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at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
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at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
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at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
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at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
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at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
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at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
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at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
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at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
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at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
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at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
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at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
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at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
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at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
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at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
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at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
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at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
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at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
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at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
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writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
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gd->fb_base = AT91SAM9263_SRAM0_BASE;
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}
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@ -258,7 +259,7 @@ int board_init(void)
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at91sam9263ek_nand_hw_init();
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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at91_set_gpio_output(AT91_PIN_PE20, 1); /* select spi0 clock */
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at91_set_pio_output(AT91_PIO_PORTE, 20, 1); /* select spi0 clock */
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at91_spi0_hw_init(1 << 0);
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#endif
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#ifdef CONFIG_MACB
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@ -297,7 +298,7 @@ int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
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rc = macb_eth_initialize(0, (void *) AT91_EMAC_BASE, 0x00);
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#endif
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return rc;
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}
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@ -23,22 +23,25 @@
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*/
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#include <common.h>
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#include <asm/arch/at91sam9263.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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void coloured_LED_init(void)
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{
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB |
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1 << AT91SAM9263_ID_PIOCDE);
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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at91_set_gpio_output(CONFIG_RED_LED, 1);
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at91_set_gpio_output(CONFIG_GREEN_LED, 1);
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at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
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writel(1 << AT91SAM9263_ID_PIOB | 1 << AT91SAM9263_ID_PIOCDE,
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&pmc->pcer);
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at91_set_gpio_value(CONFIG_RED_LED, 0);
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at91_set_gpio_value(CONFIG_GREEN_LED, 1);
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at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
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at91_set_pio_output(CONFIG_RED_LED, 1);
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at91_set_pio_output(CONFIG_GREEN_LED, 1);
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at91_set_pio_output(CONFIG_YELLOW_LED, 1);
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at91_set_pio_value(CONFIG_RED_LED, 0);
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at91_set_pio_value(CONFIG_GREEN_LED, 1);
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at91_set_pio_value(CONFIG_YELLOW_LED, 1);
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}
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@ -27,8 +27,6 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
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#define CONFIG_SYS_HZ 1000
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@ -72,9 +70,9 @@
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/* LED */
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#define CONFIG_AT91_LED
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#define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */
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#define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */
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#define CONFIG_YELLOW_LED AT91_PIN_PC29 /* this is the user2 led */
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#define CONFIG_RED_LED AT91_PIO_PORTB, 7 /* the power led */
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#define CONFIG_GREEN_LED AT91_PIO_PORTB, 8 /* the user1 led */
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#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 29 /* the user2 led */
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#define CONFIG_BOOTDELAY 3
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@ -150,39 +148,36 @@
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#define MASTER_PLL_MUL 171
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#define MASTER_PLL_DIV 14
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#define MASTER_PLL_OUT 3
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/* clocks */
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#define CONFIG_SYS_MOR_VAL \
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(AT91_PMC_MOSCEN | \
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(255 << 8)) /* Main Oscillator Start-up Time */
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#define CONFIG_SYS_PLLAR_VAL \
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(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
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AT91_PMC_OUT | \
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AT91_PMC_PLLCOUNT | /* PLL Counter */ \
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(2 << 28) | /* PLL Clock Frequency Range */ \
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((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
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(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
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#define CONFIG_SYS_PLLAR_VAL \
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(AT91_PMC_PLLAR_29 | \
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AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
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AT91_PMC_PLLXR_PLLCOUNT(63) | \
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AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
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AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
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/* PCK/2 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR1_VAL \
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(AT91_PMC_CSS_SLOW | \
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AT91_PMC_PRES_1 | \
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AT91SAM9_PMC_MDIV_2 | \
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AT91_PMC_PDIV_1)
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(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
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AT91_PMC_MCKR_MDIV_2)
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/* PCK/2 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR2_VAL \
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(AT91_PMC_CSS_PLLA | \
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AT91_PMC_PRES_1 | \
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AT91SAM9_PMC_MDIV_2 | \
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AT91_PMC_PDIV_1)
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(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
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AT91_PMC_MCKR_MDIV_2)
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||||
|
||||
/* define PDC[31:16] as DATA[31:16] */
|
||||
#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
|
||||
/* no pull-up for D[31:16] */
|
||||
#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
|
||||
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
|
||||
#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
|
||||
(AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
|
||||
AT91_MATRIX_EBI0_CS1A_SDRAMC)
|
||||
#define CONFIG_SYS_MATRIX_EBICSA_VAL \
|
||||
(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
|
||||
AT91_MATRIX_CSA_EBI_CS1A)
|
||||
|
||||
/* SDRAM */
|
||||
/* SDRAMC_MR Mode register */
|
||||
|
|
@ -224,33 +219,32 @@
|
|||
#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
|
||||
|
||||
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
|
||||
#define CONFIG_SYS_SMC0_SETUP0_VAL \
|
||||
(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
|
||||
AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
|
||||
#define CONFIG_SYS_SMC0_PULSE0_VAL \
|
||||
(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
|
||||
AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
|
||||
#define CONFIG_SYS_SMC0_SETUP0_VAL \
|
||||
(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
|
||||
AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
|
||||
#define CONFIG_SYS_SMC0_PULSE0_VAL \
|
||||
(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
|
||||
AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
|
||||
#define CONFIG_SYS_SMC0_CYCLE0_VAL \
|
||||
(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
|
||||
(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
|
||||
#define CONFIG_SYS_SMC0_MODE0_VAL \
|
||||
(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
|
||||
AT91_SMC_DBW_16 | \
|
||||
AT91_SMC_TDFMODE | \
|
||||
AT91_SMC_TDF_(6))
|
||||
(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
|
||||
AT91_SMC_MODE_DBW_16 | \
|
||||
AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
|
||||
|
||||
/* user reset enable */
|
||||
#define CONFIG_SYS_RSTC_RMR_VAL \
|
||||
(AT91_RSTC_KEY | \
|
||||
AT91_RSTC_PROCRST | \
|
||||
AT91_RSTC_RSTTYP_WAKEUP | \
|
||||
AT91_RSTC_RSTTYP_WATCHDOG)
|
||||
AT91_RSTC_MR_URSTEN | \
|
||||
AT91_RSTC_MR_ERSTL(15))
|
||||
|
||||
/* Disable Watchdog */
|
||||
#define CONFIG_SYS_WDTC_WDMR_VAL \
|
||||
(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
|
||||
AT91_WDT_WDV | \
|
||||
AT91_WDT_WDDIS | \
|
||||
AT91_WDT_WDD)
|
||||
(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
|
||||
AT91_WDT_MR_WDV(0xfff) | \
|
||||
AT91_WDT_MR_WDDIS | \
|
||||
AT91_WDT_MR_WDD(0xfff))
|
||||
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
|
@ -267,9 +261,15 @@
|
|||
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
|
||||
/* our CLE is AD22 */
|
||||
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
|
||||
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
|
||||
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
|
||||
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
|
||||
#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22
|
||||
/*
|
||||
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
|
||||
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
|
||||
*/
|
||||
|
||||
|
||||
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
|
||||
#endif
|
||||
|
||||
/* Ethernet */
|
||||
|
|
|
|||
Loading…
Reference in New Issue