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armv8: fsl-layerscape: Update ddr erratum a008336 

DDR erratum A008336 only applies to DDR controller v5.2.0.
DDR controller v5.2.1 already has default 0x43b30002 in
EDDRTQCR1 register for optimal performance.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Shengzhou Liu 2016-08-26 18:30:38 +08:00 committed by York Sun
parent 77b571da3b
commit 1a87c24fe8
1 changed files with 4 additions and 2 deletions
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6
arch/arm/cpu/armv8/fsl-layerscape/soc.c
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@ -58,11 +58,13 @@ static void erratum_a008336(void)
#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
out_le32(eddrtqcr1, 0x63b30002);
if (fsl_ddr_get_version(0) == 0x50200)
out_le32(eddrtqcr1, 0x63b30002);
#endif
#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
out_le32(eddrtqcr1, 0x63b30002);
if (fsl_ddr_get_version(0) == 0x50200)
out_le32(eddrtqcr1, 0x63b30002);
#endif
#endif
}