Add PCI Express support on MPC8568MDS
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Haiying Wang
Kumar Gala
parent
b90d254976
commit
1563f56e0c
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@ -29,9 +29,7 @@ endif
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o \
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bcsr.o \
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ft_board.o
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COBJS := $(BOARD).o bcsr.o
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SOBJS := init.o
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@ -1,45 +0,0 @@
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/*
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* Copyright 2004-2007 Freescale Semiconductor.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ft_build.h>
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extern void ft_cpu_setup(void *blob, bd_t *bd);
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#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
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void
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ft_board_setup(void *blob, bd_t *bd)
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{
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u32 *p;
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int len;
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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ft_cpu_setup(blob, bd);
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p = ft_get_prop(blob, "/memory/reg", &len);
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if (p != NULL) {
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*p++ = cpu_to_be32(bd->bi_memstart);
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*p = cpu_to_be32(bd->bi_memsize);
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}
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}
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#endif /* CONFIG_OF_FLAT_TREE && CONFIG_OF_BOARD_SETUP */
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@ -28,6 +28,11 @@
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#include <config.h>
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#include <mpc85xx.h>
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#define LAWAR_TRGT_PCI1 0x00000000
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#define LAWAR_TRGT_PCIE1 0x00200000
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#define LAWAR_TRGT_RIO 0x00c00000
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#define LAWAR_TRGT_LBC 0x00400000
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#define LAWAR_TRGT_DDR 0x00f00000
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/*
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* TLB0 and TLB1 Entries
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@ -211,27 +216,27 @@ tlb1_entry:
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*/
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#define LAWBAR0 0
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#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
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#define LAWAR0 ((LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
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#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff)
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
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#define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_8M))
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#define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff)
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
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#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
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#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
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/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
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#define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
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#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
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.section .bootpg, "ax"
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.globl law_entry
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@ -26,10 +26,15 @@
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/immap_fsl_pci.h>
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#include <spd.h>
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#include <i2c.h>
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#include <ioports.h>
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#if defined(CONFIG_OF_FLAT_TREE)
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#include <ft_build.h>
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#endif
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#include "bcsr.h"
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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@ -336,16 +341,19 @@ static struct pci_config_table pci_mpc8568mds_config_table[] = {
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};
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#endif
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static struct pci_controller hose[] = {
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{
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static struct pci_controller pci1_hose = {
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#ifndef CONFIG_PCI_PNP
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config_table: pci_mpc8568mds_config_table,
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#endif
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}
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};
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#endif /* CONFIG_PCI */
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif /* CONFIG_PCIE1 */
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int first_free_busno = 0;
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/*
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* pib_init() -- Initialize the PCA9555 IO expander on the PIB board
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*/
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@ -388,11 +396,170 @@ pib_init(void)
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asm("eieio");
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}
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#ifdef CONFIG_PCI
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void
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pci_init_board(void)
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{
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#ifdef CONFIG_PCI
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
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uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
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#ifdef CONFIG_PCI1
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{
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pib_init();
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pci_mpc85xx_init(hose);
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pci1_hose;
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uint pci_32 = 1; /* PORDEVSR[15] */
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uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
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uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
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uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
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uint pci_speed = 66666000;
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if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
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printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33333000) ? "33" :
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(pci_speed == 66666000) ? "66" : "unknown",
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pci_clk_sel ? "sync" : "async",
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pci_agent ? "agent" : "host",
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pci_arb ? "arbiter" : "external-arbiter"
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);
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/* inbound */
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEMORY_BUS,
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CFG_PCI_MEMORY_PHYS,
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CFG_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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CFG_PCI1_MEM_BASE,
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CFG_PCI1_MEM_PHYS,
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CFG_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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CFG_PCI1_IO_BASE,
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CFG_PCI1_IO_PHYS,
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CFG_PCI1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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hose->first_busno = first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno = hose->last_busno+1;
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printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
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} else {
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printf (" PCI: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
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#endif
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#ifdef CONFIG_PCIE1
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pcie1_hose;
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int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
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int pcie_configured = io_sel >= 1;
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if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
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printf ("\n PCIE connected to slot as %s (base address %x)",
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pcie_ep ? "End Point" : "Root Complex",
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(uint)pci);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
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}
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printf ("\n");
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/* inbound */
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEMORY_BUS,
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CFG_PCI_MEMORY_PHYS,
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CFG_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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CFG_PCIE1_MEM_BASE,
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CFG_PCIE1_MEM_PHYS,
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CFG_PCIE1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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CFG_PCIE1_IO_BASE,
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CFG_PCIE1_IO_PHYS,
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CFG_PCIE1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
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first_free_busno=hose->last_busno+1;
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} else {
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printf (" PCIE: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
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#endif
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}
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
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void
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ft_board_setup(void *blob, bd_t *bd)
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{
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u32 *p;
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int len;
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ft_cpu_setup(blob, bd);
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p = ft_get_prop(blob, "/memory/reg", &len);
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if (p != NULL) {
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*p++ = cpu_to_be32(bd->bi_memstart);
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*p = cpu_to_be32(bd->bi_memsize);
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}
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#ifdef CONFIG_PCI1
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
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if (p != NULL) {
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p[0] = 0;
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p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
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debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
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}
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#endif
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#ifdef CONFIG_PCIE1
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
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if (p != NULL) {
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p[0] = 0;
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p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
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debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
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}
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#endif
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}
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#endif
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@ -33,7 +33,10 @@
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#define CONFIG_MPC8568 1 /* MPC8568 specific */
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#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
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#define CONFIG_PCI
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#define CONFIG_PCI 1 /* Enable PCI/PCIE */
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#define CONFIG_PCI1 1 /* PCI controller */
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#define CONFIG_PCIE1 1 /* PCIE controller */
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#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_QE /* Enable QE */
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#define CONFIG_ENV_OVERWRITE
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@ -87,6 +90,9 @@ extern unsigned long get_clock_freq(void);
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#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
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#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
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#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
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#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
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/*
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* DDR Setup
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*/
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@ -325,12 +331,12 @@ extern unsigned long get_clock_freq(void);
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#define CFG_PCI1_IO_PHYS 0xe2000000
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#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
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#define CFG_PEX_MEM_BASE 0xa0000000
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#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE
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#define CFG_PEX_MEM_SIZE 0x10000000 /* 256M */
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#define CFG_PEX_IO_BASE 0x00000000
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#define CFG_PEX_IO_PHYS 0xe2800000
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#define CFG_PEX_IO_SIZE 0x00800000 /* 8M */
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#define CFG_PCIE1_MEM_BASE 0xa0000000
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#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
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#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CFG_PCIE1_IO_BASE 0x00000000
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#define CFG_PCIE1_IO_PHYS 0xe2800000
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#define CFG_PCIE1_IO_SIZE 0x00800000 /* 8M */
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#define CFG_SRIO_MEM_BASE 0xc0000000
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@ -383,6 +389,11 @@ extern unsigned long get_clock_freq(void);
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
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/* PCI view of System Memory */
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#define CFG_PCI_MEMORY_BUS 0x00000000
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#define CFG_PCI_MEMORY_PHYS 0x00000000
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#define CFG_PCI_MEMORY_SIZE 0x80000000
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#endif /* CONFIG_PCI */
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#ifndef CONFIG_NET_MULTI
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