arm64: mvebu: Fix A8K memory mapping and add documentation
Fix the MMU mapping for A8K device family: - Separate A7K and A8K memory mappings - Fix memory regions by including IO mapping for all 3 PCIe interfaces existing on each connected CP110 controller Add A8K memory mapping documentation with all regions configured by Marvell ATF. Change-Id: I9c930569b1853900f5fba2d5db319b092cc7a2a6 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
This commit is contained in:
Konstantin Porotchkin
Stefan Roese
parent
0bd1f96aa2
commit
0d92f2141a
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@ -21,7 +21,33 @@ DECLARE_GLOBAL_DATA_PTR;
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#define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84)
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#define RFU_SW_RESET_OFFSET 0
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/*
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* The following table includes all memory regions for Armada 7k and
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* 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets
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* define these regions at the beginning of the struct so that they
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* can be easier removed later dynamically if an Armada 7k device is detected.
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* For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt
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*/
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#define ARMADA_7K8K_COMMON_REGIONS_START 2
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static struct mm_region mvebu_mem_map[] = {
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/* Armada 80x0 memory regions include the CP1 (slave) units */
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{
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/* SRAM, MMIO regions - CP110 slave region */
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.phys = 0xf4000000UL,
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.virt = 0xf4000000UL,
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.size = 0x02000000UL, /* 32MiB internal registers */
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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{
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/* PCI CP1 regions */
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.phys = 0xfa000000UL,
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.virt = 0xfa000000UL,
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.size = 0x04000000UL, /* 64MiB CP110 slave PCI space */
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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/* Armada 80x0 and 70x0 common memory regions start here */
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{
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/* RAM */
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.phys = 0x0UL,
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@ -47,29 +73,35 @@ static struct mm_region mvebu_mem_map[] = {
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PTE_BLOCK_NON_SHARE
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},
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{
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/* SRAM, MMIO regions - CP110 slave region */
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.phys = 0xf4000000UL,
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.virt = 0xf4000000UL,
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.size = 0x02000000UL, /* 32MiB internal registers */
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/* PCI CP0 regions */
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.phys = 0xf6000000UL,
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.virt = 0xf6000000UL,
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.size = 0x04000000UL, /* 64MiB CP110 master PCI space */
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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{
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/* PCI regions */
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.phys = 0xf8000000UL,
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.virt = 0xf8000000UL,
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.size = 0x08000000UL, /* 128MiB PCI space (master & slave) */
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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{
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = mvebu_mem_map;
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void enable_caches(void)
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{
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/*
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* Armada 7k is not equipped with the CP110 slave CP. In case this
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* code runs on an Armada 7k device, lets remove the CP110 slave
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* entries from the memory mapping by moving the start to the
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* common regions.
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*/
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if (of_machine_is_compatible("marvell,armada7040"))
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mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START];
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icache_enable();
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dcache_enable();
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}
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void reset_cpu(ulong ignored)
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{
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u32 reg;
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@ -0,0 +1,56 @@
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Memory Layout on Armada-8k SoC's
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================================
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The below desribes the physical memory layout for Marvell's Armada-8k SoC's.
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This assumes that the SoC includes Dual CP configuration, in case the flavor is using
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a single CP configuration, then all secondary-CP mappings are invalid.
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All "Reserved" areas below, are kept for future usage.
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Start End Use
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--------------------------------------------------------------------------
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0x00000000 0xEFFFFFFF DRAM
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0xF0000000 0xF0FFFFFF AP Internal registers space
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0xF1000000 0xF1FFFFFF Reserved.
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0xF2000000 0xF3FFFFFF CP-0 Internal (configuration) registers
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space.
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0xF4000000 0xF5FFFFFF CP-1 Internal (configuration) registers
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space.
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0xF6000000 0xF6FFFFFF CP-0 / PCIe#0 Memory space.
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0xF7000000 0xF7FFFFFF CP-0 / PCIe#1 Memory space.
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0xF8000000 0xF8FFFFFF CP-0 / PCIe#2 Memory space.
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0xF9000000 0xF900FFFF CP-0 / PCIe#0 IO space.
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0xF9010000 0xF901FFFF CP-0 / PCIe#1 IO space.
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0xF9020000 0xF902FFFF CP-0 / PCIe#2 IO space.
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0xF9030000 0xF9FFFFFF Reserved.
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0xFA000000 0xFAFFFFFF CP-1 / PCIe#0 Memory space.
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0xFB000000 0xFBFFFFFF CP-1 / PCIe#1 Memory space.
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0xFC000000 0xFCFFFFFF CP-1 / PCIe#2 Memory space.
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0xFD000000 0xFD00FFFF CP-1 / PCIe#0 IO space.
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0xFD010000 0xFD01FFFF CP-1 / PCIe#1 IO space.
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0xFD020000 0xFD02FFFF CP-1 / PCIe#2 IO space.
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0xFD030000 0xFFEFFFFF Reserved.
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0xFFF00000 0xFFFFFFFF Bootrom
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0x100000000 <DRAM Size>-1 DRAM
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