imx: ventana: switch to SPL
Switch to an SPL image. The SPL for Ventana does the following: - setup i2c and read the factory programmed EEPROM to obtain DRAM config and model for board-specific calibration data - configure DRAM per CPU/size/layout/devices/calibration - load u-boot.img from NAND and jump to it This allows for a single SPL+u-boot.img to replace the previous multiple boa configurations. Cc: Stefan Roese <sr@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Andy Ng <andreas2025@gmail.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
This commit is contained in:
Tim Harvey
Stefano Babic
parent
680e8db450
commit
0cc11dea89
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@ -7,4 +7,5 @@
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#
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obj-y := gw_ventana.o gsc.o eeprom.o
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obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o
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@ -3,53 +3,81 @@ U-Boot for the Gateworks Ventana Product Family boards
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This file contains information for the port of U-Boot to the Gateworks
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Ventana Product family boards.
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1. Boot source, boot from NAND
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1. Secondary Program Loader (SPL)
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---------------------------------
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The i.MX6 has a BOOT ROM PPL (Primary Program Loader) which supports loading
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an executable image from various boot devices.
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The Gateworks Ventana board config uses an SPL build configuration. This
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will build the following artifacts from u-boot source:
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- SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program
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Loader) boots. This detects CPU/DRAM configuration, configures
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The DRAM controller, loads u-boot.img from the detected boot device,
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and jumps to it. As this is booted from the PPL, it has an IVT/DCD
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table.
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- u-boot.img - The main u-boot core which is u-boot.bin with a image header.
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2. Build
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--------
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To build U-Boot for the Gateworks Ventana product family:
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make gwventana_config
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make
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3. Boot source, boot from NAND
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------------------------------
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The i.MX6 BOOT ROM expects some structures that provide details of NAND layout
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and bad block information (referred to as 'bootstreams') which are replicated
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multiple times in NAND. The number of replications is configurable through
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board strapping options and eFUSE settings. The Freescale 'kobs-ng'
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application from the Freescale LTIB BSP, which runs under Linux, must be used
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to program the bootstream in order to setup the replicated headers correctly.
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multiple times in NAND. The number of replications and their spacing (referred
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to as search stride) is configurable through board strapping options and/or
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eFUSE settings (BOOT_SEARCH_COUNT / Pages in block from BOOT_CFG2). In
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addition, the i.MX6 BOOT ROM Flash Configuration Block (FCB) supports two
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copies of a bootloader in flash in the case that a bad block has corrupted one.
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The Freescale 'kobs-ng' application from the Freescale LTIB BSP, which runs
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under Linux and operates on an MTD partition, must be used to program the
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bootstream in order to setup this flash structure correctly.
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The Gateworks Ventana boards with NAND flash have been factory programmed
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such that their eFUSE settings expect 2 copies of the boostream (this is
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specified by providing kobs-ng with the --search_exponent=1 argument). Once in
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Linux with MTD support for the NAND on /dev/mtd0 you can program the boostream
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Linux with MTD support for the NAND on /dev/mtd0 you can program the SPL
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with:
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kobs-ng init -v -x --search_exponent=1 u-boot.imx
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kobs-ng init -v -x --search_exponent=1 SPL
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The kobs-ng application uses an imximage (u-boot.imx) which contains the
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Image Vector Table (IVT) and Device Configuration Data (DCD) structures that
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the i.MX6 BOOT ROM requires to boot. The kobs-ng adds the Firmware
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Configuration Block (FCB) and Discovered Bad Block Table (DBBT).
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The kobs-ng application uses an imximage which contains the Image Vector Table
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(IVT) and Device Configuration Data (DCD) structures that the i.MX6 BOOT ROM
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requires to boot. The kobs-ng adds the Firmware Configuration Block (FCB) and
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Discovered Bad Block Table (DBBT). The SPL build artifact from u-boot is
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an imximage.
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The u-boot.img, which is the non SPL u-boot binary appended to a u-boot image
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header must be programmed in the NAND flash boot device at an offset hard
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coded in the SPL. For the Ventana boards, this has been chosen to be 14MB.
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The image can be programmed from either u-boot or Linux:
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u-boot:
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Ventana > setenv mtdparts mtdparts=nand:14m(spl),2m(uboot),1m(env),-(rootfs)
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Ventana > tftp ${loadaddr} u-boot.img && nand erase.part uboot && \
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nand write ${loadaddr} uboot ${filesize}
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Linux:
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nandwrite /dev/mtd1 u-boot.img
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The above assumes the default Ventana partitioning scheme which is configured
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via the mtdparts env var:
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- spl: 14MB
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- uboot: 2M
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- env: 1M
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- rootfs: the rest
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This information is taken from:
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http://trac.gateworks.com/wiki/ventana/bootloader#NANDFLASH
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More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
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2. Build
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--------
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There are several Gateworks Ventana boards that share a simliar design but
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vary based on CPU, Memory configuration, and subloaded devices. Although
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the subloaded devices are handled dynamically in the bootloader using
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factory configured EEPROM data to modify the device-tree, the CPU choice
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(IMX6Q vs IMX6DL) and memory configurations are currently compile-time
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options.
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The following Gateworks Ventana configurations exist:
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gwventanaq1gspi: MX6Q,1GB,SPI FLASH
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gwventanaq : MX6Q,512MB,NAND FLASH
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gwventanaq1g : MX6Q,1GB,NAND FLASH
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gwventanadl : MX6DL,512MB,NAND FLASH
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gwventanadl1g : MX6DL,1GB,NAND FLASH
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To build U-Boot for the MX6Q,1GB,NAND FLASH for example:
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make gwventanaq1g_config
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make
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@ -1102,6 +1102,7 @@ void get_board_serial(struct tag_serialnr *serialnr)
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* Board Support
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*/
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/* called from SPL board_init_f() */
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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@ -1115,8 +1116,7 @@ int board_early_init_f(void)
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
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CONFIG_DDR_MB*1024*1024);
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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@ -1258,9 +1258,11 @@ int misc_init_r(void)
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* env scripts will try loading each from most specific to
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* least.
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*/
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if (is_cpu_type(MXC_CPU_MX6Q))
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if (is_cpu_type(MXC_CPU_MX6Q) ||
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is_cpu_type(MXC_CPU_MX6D))
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cputype = "imx6q";
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else if (is_cpu_type(MXC_CPU_MX6DL))
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else if (is_cpu_type(MXC_CPU_MX6DL) ||
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is_cpu_type(MXC_CPU_MX6SOLO))
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cputype = "imx6dl";
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memset(str, 0, sizeof(str));
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for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
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@ -24,21 +24,6 @@ BOOT_FROM nand
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#define __ASSEMBLY__
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#include <config.h>
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#include "asm/arch/mx6-ddr.h"
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#include "asm/arch/iomux.h"
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#include "asm/arch/crm_regs.h"
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/* Memory configuration (size is overridden via eeprom config) */
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#include "../../boundary/nitrogen6x/ddr-setup.cfg"
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#if defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 1024
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#include "../../boundary/nitrogen6x/1066mhz_4x128mx16.cfg"
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#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 1024
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#include "../../boundary/nitrogen6x/800mhz_4x128mx16.cfg"
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#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 512
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#include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg"
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#elif defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 512
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#include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg"
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#else
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#error "Unsupported CPU/Memory configuration"
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#endif
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#include "clocks.cfg"
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@ -0,0 +1,419 @@
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/*
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* Copyright (C) 2014 Gateworks Corporation
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* Author: Tim Harvey <tharvey@gateworks.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <spl.h>
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#include "ventana_eeprom.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
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#define I2C_GSC 0
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#define GSC_EEPROM_ADDR 0x51
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#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
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#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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#define CONFIG_SYS_I2C_SPEED 100000
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/* I2C1: GSC */
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static struct i2c_pads_info mx6q_i2c_pad_info0 = {
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.scl = {
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.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
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.gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
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.gp = IMX_GPIO_NR(3, 21)
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},
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.sda = {
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.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
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.gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
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.gp = IMX_GPIO_NR(3, 28)
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}
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};
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static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
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.scl = {
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.i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
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.gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
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.gp = IMX_GPIO_NR(3, 21)
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},
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.sda = {
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.i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
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.gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
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.gp = IMX_GPIO_NR(3, 28)
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}
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};
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static void i2c_setup_iomux(void)
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{
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if (is_cpu_type(MXC_CPU_MX6Q))
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
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else
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
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}
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/* configure MX6Q/DUAL mmdc DDR io registers */
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struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
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/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
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.dram_sdclk_0 = 0x00020030,
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.dram_sdclk_1 = 0x00020030,
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.dram_cas = 0x00020030,
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.dram_ras = 0x00020030,
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.dram_reset = 0x00020030,
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/* SDCKE[0:1]: 100k pull-up */
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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/* SDBA2: pull-up disabled */
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.dram_sdba2 = 0x00000000,
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/* SDODT[0:1]: 100k pull-up, 40 ohm */
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.dram_sdodt0 = 0x00003030,
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.dram_sdodt1 = 0x00003030,
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/* SDQS[0:7]: Differential input, 40 ohm */
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.dram_sdqs0 = 0x00000030,
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.dram_sdqs1 = 0x00000030,
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.dram_sdqs2 = 0x00000030,
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.dram_sdqs3 = 0x00000030,
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.dram_sdqs4 = 0x00000030,
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.dram_sdqs5 = 0x00000030,
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.dram_sdqs6 = 0x00000030,
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.dram_sdqs7 = 0x00000030,
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/* DQM[0:7]: Differential input, 40 ohm */
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.dram_dqm0 = 0x00020030,
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.dram_dqm1 = 0x00020030,
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.dram_dqm2 = 0x00020030,
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.dram_dqm3 = 0x00020030,
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.dram_dqm4 = 0x00020030,
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.dram_dqm5 = 0x00020030,
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.dram_dqm6 = 0x00020030,
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.dram_dqm7 = 0x00020030,
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};
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/* configure MX6Q/DUAL mmdc GRP io registers */
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struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
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/* DDR3 */
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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/* disable DDR pullups */
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.grp_ddrpke = 0x00000000,
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/* ADDR[00:16], SDBA[0:1]: 40 ohm */
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.grp_addds = 0x00000030,
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/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
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.grp_ctlds = 0x00000030,
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/* DATA[00:63]: Differential input, 40 ohm */
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x00000030,
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.grp_b1ds = 0x00000030,
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.grp_b2ds = 0x00000030,
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.grp_b3ds = 0x00000030,
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.grp_b4ds = 0x00000030,
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.grp_b5ds = 0x00000030,
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.grp_b6ds = 0x00000030,
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.grp_b7ds = 0x00000030,
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};
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/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
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struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
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/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
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.dram_sdclk_0 = 0x00020030,
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.dram_sdclk_1 = 0x00020030,
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.dram_cas = 0x00020030,
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.dram_ras = 0x00020030,
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.dram_reset = 0x00020030,
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/* SDCKE[0:1]: 100k pull-up */
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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/* SDBA2: pull-up disabled */
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.dram_sdba2 = 0x00000000,
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/* SDODT[0:1]: 100k pull-up, 40 ohm */
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.dram_sdodt0 = 0x00003030,
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.dram_sdodt1 = 0x00003030,
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/* SDQS[0:7]: Differential input, 40 ohm */
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.dram_sdqs0 = 0x00000030,
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.dram_sdqs1 = 0x00000030,
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.dram_sdqs2 = 0x00000030,
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.dram_sdqs3 = 0x00000030,
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.dram_sdqs4 = 0x00000030,
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.dram_sdqs5 = 0x00000030,
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.dram_sdqs6 = 0x00000030,
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.dram_sdqs7 = 0x00000030,
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/* DQM[0:7]: Differential input, 40 ohm */
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.dram_dqm0 = 0x00020030,
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.dram_dqm1 = 0x00020030,
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.dram_dqm2 = 0x00020030,
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.dram_dqm3 = 0x00020030,
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.dram_dqm4 = 0x00020030,
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.dram_dqm5 = 0x00020030,
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.dram_dqm6 = 0x00020030,
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.dram_dqm7 = 0x00020030,
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};
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/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
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struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
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/* DDR3 */
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.grp_ddr_type = 0x000c0000,
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/* SDQS[0:7]: Differential input, 40 ohm */
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.grp_ddrmode_ctl = 0x00020000,
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/* disable DDR pullups */
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.grp_ddrpke = 0x00000000,
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/* ADDR[00:16], SDBA[0:1]: 40 ohm */
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.grp_addds = 0x00000030,
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/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
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.grp_ctlds = 0x00000030,
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/* DATA[00:63]: Differential input, 40 ohm */
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x00000030,
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.grp_b1ds = 0x00000030,
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.grp_b2ds = 0x00000030,
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.grp_b3ds = 0x00000030,
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.grp_b4ds = 0x00000030,
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.grp_b5ds = 0x00000030,
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.grp_b6ds = 0x00000030,
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.grp_b7ds = 0x00000030,
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};
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/* MT41K128M16JT-125 */
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static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
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.mem_speed = 1600,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
|
||||
|
||||
/* GW54xx specific calibration */
|
||||
static struct mx6_mmdc_calibration gw54xxq_mmdc_calib = {
|
||||
/* write leveling calibration determine */
|
||||
.p0_mpwldectrl0 = 0x00190018,
|
||||
.p0_mpwldectrl1 = 0x0021001D,
|
||||
.p1_mpwldectrl0 = 0x00160027,
|
||||
.p1_mpwldectrl1 = 0x0012001E,
|
||||
/* Read DQS Gating calibration */
|
||||
.p0_mpdgctrl0 = 0x43370346,
|
||||
.p0_mpdgctrl1 = 0x032A0321,
|
||||
.p1_mpdgctrl0 = 0x433A034D,
|
||||
.p1_mpdgctrl1 = 0x032F0235,
|
||||
/* Read Calibration: DQS delay relative to DQ read access */
|
||||
.p0_mprddlctl = 0x3C313539,
|
||||
.p1_mprddlctl = 0x37333140,
|
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */
|
||||
.p0_mpwrdlctl = 0x37393C38,
|
||||
.p1_mpwrdlctl = 0x42334538,
|
||||
};
|
||||
|
||||
/* GW53xx specific calibration */
|
||||
static struct mx6_mmdc_calibration gw53xxq_mmdc_calib = {
|
||||
/* write leveling calibration determine */
|
||||
.p0_mpwldectrl0 = 0x00160013,
|
||||
.p0_mpwldectrl1 = 0x00090024,
|
||||
.p1_mpwldectrl0 = 0x001F0018,
|
||||
.p1_mpwldectrl1 = 0x000C001C,
|
||||
/* Read DQS Gating calibration */
|
||||
.p0_mpdgctrl0 = 0x433A034C,
|
||||
.p0_mpdgctrl1 = 0x0336032F,
|
||||
.p1_mpdgctrl0 = 0x4343034A,
|
||||
.p1_mpdgctrl1 = 0x03370222,
|
||||
/* Read Calibration: DQS delay relative to DQ read access */
|
||||
.p0_mprddlctl = 0x3F343638,
|
||||
.p1_mprddlctl = 0x38373442,
|
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */
|
||||
.p0_mpwrdlctl = 0x343A3E39,
|
||||
.p1_mpwrdlctl = 0x44344239,
|
||||
};
|
||||
static struct mx6_mmdc_calibration gw53xxdl_mmdc_calib = {
|
||||
/* write leveling calibration determine */
|
||||
.p0_mpwldectrl0 = 0x003C003C,
|
||||
.p0_mpwldectrl1 = 0x00330038,
|
||||
.p1_mpwldectrl0 = 0x001F002A,
|
||||
.p1_mpwldectrl1 = 0x0022003F,
|
||||
/* Read DQS Gating calibration */
|
||||
.p0_mpdgctrl0 = 0x42410244,
|
||||
.p0_mpdgctrl1 = 0x022D022D,
|
||||
.p1_mpdgctrl0 = 0x4234023A,
|
||||
.p1_mpdgctrl1 = 0x021C0228,
|
||||
/* Read Calibration: DQS delay relative to DQ read access */
|
||||
.p0_mprddlctl = 0x484A4C4B,
|
||||
.p1_mprddlctl = 0x4B4D4E4B,
|
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */
|
||||
.p0_mpwrdlctl = 0x33342B32,
|
||||
.p1_mpwrdlctl = 0x3933332B,
|
||||
};
|
||||
|
||||
/* GW52xx specific calibration */
|
||||
static struct mx6_mmdc_calibration gw52xxdl_mmdc_calib = {
|
||||
/* write leveling calibration determine */
|
||||
.p0_mpwldectrl0 = 0x0040003F,
|
||||
.p0_mpwldectrl1 = 0x00370037,
|
||||
/* Read DQS Gating calibration */
|
||||
.p0_mpdgctrl0 = 0x42420244,
|
||||
.p0_mpdgctrl1 = 0x022F022F,
|
||||
/* Read Calibration: DQS delay relative to DQ read access */
|
||||
.p0_mprddlctl = 0x49464B4A,
|
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */
|
||||
.p0_mpwrdlctl = 0x32362C32,
|
||||
};
|
||||
|
||||
/* GW51xx specific calibration */
|
||||
static struct mx6_mmdc_calibration gw51xxq_mmdc_calib = {
|
||||
/* write leveling calibration determine */
|
||||
.p0_mpwldectrl0 = 0x00150016,
|
||||
.p0_mpwldectrl1 = 0x001F0017,
|
||||
/* Read DQS Gating calibration */
|
||||
.p0_mpdgctrl0 = 0x433D034D,
|
||||
.p0_mpdgctrl1 = 0x033D032F,
|
||||
/* Read Calibration: DQS delay relative to DQ read access */
|
||||
.p0_mprddlctl = 0x3F313639,
|
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */
|
||||
.p0_mpwrdlctl = 0x33393F36,
|
||||
};
|
||||
|
||||
static struct mx6_mmdc_calibration gw51xxdl_mmdc_calib = {
|
||||
/* write leveling calibration determine */
|
||||
.p0_mpwldectrl0 = 0x003D003F,
|
||||
.p0_mpwldectrl1 = 0x002F0038,
|
||||
/* Read DQS Gating calibration */
|
||||
.p0_mpdgctrl0 = 0x423A023A,
|
||||
.p0_mpdgctrl1 = 0x022A0228,
|
||||
/* Read Calibration: DQS delay relative to DQ read access */
|
||||
.p0_mprddlctl = 0x48494C4C,
|
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */
|
||||
.p0_mpwrdlctl = 0x34352D31,
|
||||
};
|
||||
|
||||
static void spl_dram_init(int width, int size, int board_model)
|
||||
{
|
||||
struct mx6_ddr3_cfg *mem = &mt41k128m16jt_125;
|
||||
struct mx6_mmdc_calibration *calib;
|
||||
struct mx6_ddr_sysinfo sysinfo = {
|
||||
/* width of data bus:0=16,1=32,2=64 */
|
||||
.dsize = width/32,
|
||||
/* config for full 4GB range so that get_mem_size() works */
|
||||
.cs_density = 32, /* 32Gb per CS */
|
||||
/* single chip select */
|
||||
.ncs = 1,
|
||||
.cs1_mirror = 0,
|
||||
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
|
||||
#ifdef RTT_NOM_120OHM
|
||||
.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
|
||||
#else
|
||||
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
|
||||
#endif
|
||||
.walat = 1, /* Write additional latency */
|
||||
.ralat = 5, /* Read additional latency */
|
||||
.mif3_mode = 3, /* Command prediction working mode */
|
||||
.bi_on = 1, /* Bank interleaving enabled */
|
||||
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
|
||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
||||
};
|
||||
|
||||
/*
|
||||
* MMDC Calibration requires the following data:
|
||||
* mx6_mmdc_calibration - board-specific calibration (routing delays)
|
||||
* mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
|
||||
* mx6_ddr_cfg - chip specific timing/layout details
|
||||
*/
|
||||
switch (board_model) {
|
||||
default:
|
||||
case GW51xx:
|
||||
if (is_cpu_type(MXC_CPU_MX6Q))
|
||||
calib = &gw51xxq_mmdc_calib;
|
||||
else
|
||||
calib = &gw51xxdl_mmdc_calib;
|
||||
break;
|
||||
case GW52xx:
|
||||
calib = &gw52xxdl_mmdc_calib;
|
||||
break;
|
||||
case GW53xx:
|
||||
if (is_cpu_type(MXC_CPU_MX6Q))
|
||||
calib = &gw53xxq_mmdc_calib;
|
||||
else
|
||||
calib = &gw53xxdl_mmdc_calib;
|
||||
break;
|
||||
case GW54xx:
|
||||
calib = &gw54xxq_mmdc_calib;
|
||||
break;
|
||||
}
|
||||
|
||||
if (is_cpu_type(MXC_CPU_MX6Q))
|
||||
mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
|
||||
&mx6dq_grp_ioregs);
|
||||
else
|
||||
mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
|
||||
&mx6sdl_grp_ioregs);
|
||||
mx6_dram_cfg(&sysinfo, calib, mem);
|
||||
}
|
||||
|
||||
/*
|
||||
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
|
||||
* - we have a stack and a place to store GD, both in SRAM
|
||||
* - no variable global data is available
|
||||
*/
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
struct ventana_board_info ventana_info;
|
||||
int board_model;
|
||||
|
||||
/*
|
||||
* Zero out global data:
|
||||
* - this shoudl be done by crt0.S
|
||||
* - failure to zero it will cause i2c_setup to fail
|
||||
*/
|
||||
memset((void *)gd, 0, sizeof(struct global_data));
|
||||
|
||||
/* setup AIPS and disable watchdog */
|
||||
arch_cpu_init();
|
||||
|
||||
/* iomux and setup of i2c */
|
||||
board_early_init_f();
|
||||
i2c_setup_iomux();
|
||||
|
||||
/* setup GP timer */
|
||||
timer_init();
|
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */
|
||||
preloader_console_init();
|
||||
|
||||
/* read/validate EEPROM info to determine board model and SDRAM cfg */
|
||||
board_model = read_eeprom(I2C_GSC, &ventana_info);
|
||||
|
||||
/* provide some some default: 32bit 128MB */
|
||||
if (GW_UNKNOWN == board_model) {
|
||||
ventana_info.sdram_width = 2;
|
||||
ventana_info.sdram_size = 3;
|
||||
}
|
||||
|
||||
/* configure MMDC for SDRAM width/size and per-model calibration */
|
||||
spl_dram_init(8 << ventana_info.sdram_width,
|
||||
16 << ventana_info.sdram_size,
|
||||
board_model);
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
/* load/boot image from boot device */
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
}
|
||||
|
|
@ -328,11 +328,7 @@ Active arm armv7 mx6 freescale mx6qsabreauto
|
|||
Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
|
||||
Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
|
||||
Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com>
|
||||
Active arm armv7 mx6 gateworks gw_ventana gwventanadl gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=512 Tim Harvey <tharvey@gateworks.com>
|
||||
Active arm armv7 mx6 gateworks gw_ventana gwventanadl1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=1024 Tim Harvey <tharvey@gateworks.com>
|
||||
Active arm armv7 mx6 gateworks gw_ventana gwventanaq gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=512 Tim Harvey <tharvey@gateworks.com>
|
||||
Active arm armv7 mx6 gateworks gw_ventana gwventanaq1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024 Tim Harvey <tharvey@gateworks.com>
|
||||
Active arm armv7 mx6 gateworks gw_ventana gwventanaq1gspi gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024,SPI_FLASH Tim Harvey <tharvey@gateworks.com>
|
||||
Active arm armv7 mx6 gateworks gw_ventana gwventana gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6QDL,SPL Tim Harvey <tharvey@gateworks.com>
|
||||
Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton@gmail.com>
|
||||
Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com>
|
||||
Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com>
|
||||
|
|
|
|||
|
|
@ -7,6 +7,17 @@
|
|||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* SPL */
|
||||
#define CONFIG_SPL_NAND_SUPPORT
|
||||
#define CONFIG_SPL_MMC_SUPPORT
|
||||
#define CONFIG_SPL_FAT_SUPPORT
|
||||
/*
|
||||
#define CONFIG_SPL_SATA_SUPPORT
|
||||
*/
|
||||
/* Location in NAND to read U-Boot from */
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * 1024 * 1024)
|
||||
|
||||
#include "imx6_spl.h" /* common IMX6 SPL configuration */
|
||||
#include "mx6_common.h"
|
||||
#define CONFIG_MX6
|
||||
#define CONFIG_DISPLAY_CPUINFO /* display cpu info */
|
||||
|
|
|
|||
Loading…
Reference in New Issue