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Merge branch 'master' of git://www.denx.de/git/u-boot-imx 

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	configs/bk4r1_defconfig
	configs/colibri_vf_defconfig
	configs/pcm052_defconfig
	include/configs/colibri_vf.h
	include/configs/pcm052.h
This commit is contained in:
Tom Rini 2017-03-19 14:49:26 -04:00
parent f40574e2d7 d883fcc6bb
commit 02ccab1908
145 changed files with 12964 additions and 481 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
arch/arm/Kconfig
View File

@ -600,6 +600,11 @@ config ARCH_MESON
targeted at media players and tablet computers. We currently
support the S905 (GXBaby) 64-bit SoC.
config ARCH_MX7ULP
bool "NXP MX7ULP"
select CPU_V7
select ROM_UNIFIED_SECTIONS
config ARCH_MX7
bool "Freescale MX7"
select CPU_V7
@ -810,31 +815,11 @@ config TARGET_TS4800
select CPU_V7
select SYS_FSL_ERRATUM_ESDHC_A001
config TARGET_VF610TWR
bool "Support vf610twr"
config ARCH_VF610
bool "Freescale Vybrid"
select CPU_V7
select SYS_FSL_ERRATUM_ESDHC111
config TARGET_COLIBRI_VF
bool "Support Colibri VF50/61"
select BOARD_LATE_INIT
select CPU_V7
select SYS_FSL_ERRATUM_ESDHC111
config TARGET_PCM052
bool "Support pcm-052"
select CPU_V7
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_ERRATUM_ESDHC135
select SYS_FSL_ERRATUM_ESDHC_A001
config TARGET_BK4R1
bool "Support BK4r1"
select CPU_V7
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_ERRATUM_ESDHC135
select SYS_FSL_ERRATUM_ESDHC_A001
config ARCH_ZYNQ
bool "Xilinx Zynq Platform"
select BOARD_LATE_INIT
@ -1192,6 +1177,8 @@ source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
source "arch/arm/cpu/armv7/mx7ulp/Kconfig"
source "arch/arm/cpu/armv7/mx7/Kconfig"
source "arch/arm/cpu/armv7/mx6/Kconfig"
@ -1224,6 +1211,8 @@ source "arch/arm/mach-tegra/Kconfig"
source "arch/arm/mach-uniphier/Kconfig"
source "arch/arm/cpu/armv7/vf610/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
source "arch/arm/cpu/armv7/Kconfig"
@ -1280,7 +1269,6 @@ source "board/freescale/mx53evk/Kconfig"
source "board/freescale/mx53loco/Kconfig"
source "board/freescale/mx53smd/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
source "board/freescale/vf610twr/Kconfig"
source "board/grinn/chiliboard/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
@ -1289,7 +1277,6 @@ source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
source "board/phytec/pcm051/Kconfig"
source "board/phytec/pcm052/Kconfig"
source "board/ppcag/bg0900/Kconfig"
source "board/sandisk/sansa_fuze_plus/Kconfig"
source "board/schulercontrol/sc_sps_1/Kconfig"
@ -1313,7 +1300,6 @@ source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
source "board/technologic/ts4600/Kconfig"
source "board/technologic/ts4800/Kconfig"
source "board/vscom/baltos/Kconfig"

2
arch/arm/Makefile
View File

@ -99,7 +99,7 @@ ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6
libs-y += arch/arm/imx-common/
endif
else
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35 mxs vf610))
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610))
libs-y += arch/arm/imx-common/
endif
endif

3
arch/arm/cpu/armv7/Makefile
View File

@ -12,7 +12,7 @@ obj-y += cache_v7.o cache_v7_asm.o
obj-y += cpu.o cp15.o
obj-y += syslib.o
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_LS102XA),)
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_ARCH_MX7ULP)$(CONFIG_LS102XA),)
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o
endif
@ -37,6 +37,7 @@ obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
obj-$(if $(filter mx5,$(SOC)),y) += mx5/
obj-$(CONFIG_MX6) += mx6/
obj-$(CONFIG_MX7) += mx7/
obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
obj-$(CONFIG_RMOBILE) += rmobile/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/

27
arch/arm/cpu/armv7/mx6/Kconfig
View File

@ -46,6 +46,16 @@ config MX6UL_LITESOM
select DM_THERMAL
select SUPPORT_SPL
config MX6UL_OPOS6UL
bool
select MX6UL
select BOARD_LATE_INIT
select DM
select DM_GPIO
select DM_MMC
select DM_THERMAL
select SUPPORT_SPL
config MX6ULL
bool
select MX6UL
@ -241,6 +251,17 @@ config TARGET_MX6UL_GEAM
select DM_MMC
select DM_THERMAL
select SUPPORT_SPL
config TARGET_MX6UL_ISIOT
bool "Support Engicam Is.IoT MX6UL"
select MX6UL
select OF_CONTROL
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_THERMAL
select SUPPORT_SPL
config TARGET_MX6ULL_14X14_EVK
bool "Support mx6ull_14x14_evk"
@ -252,6 +273,10 @@ config TARGET_MX6ULL_14X14_EVK
config TARGET_NITROGEN6X
bool "nitrogen6x"
config TARGET_OPOS6ULDEV
bool "Armadeus OPOS6ULDev board"
select MX6UL_OPOS6UL
config TARGET_OT1200
bool "Bachmann OT1200"
select SUPPORT_SPL
@ -350,6 +375,7 @@ config SYS_SOC
source "board/ge/bx50v3/Kconfig"
source "board/advantech/dms-ba16/Kconfig"
source "board/aristainetos/Kconfig"
source "board/armadeus/opos6uldev/Kconfig"
source "board/bachmann/ot1200/Kconfig"
source "board/barco/platinum/Kconfig"
source "board/barco/titanium/Kconfig"
@ -362,6 +388,7 @@ source "board/embest/mx6boards/Kconfig"
source "board/engicam/geam6ul/Kconfig"
source "board/engicam/icorem6/Kconfig"
source "board/engicam/icorem6_rqs/Kconfig"
source "board/engicam/isiotmx6ul/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6qsabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"

1
arch/arm/cpu/armv7/mx6/Makefile
View File

@ -11,3 +11,4 @@ obj-y := soc.o clock.o
obj-$(CONFIG_SPL_BUILD) += ddr.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_MX6UL_LITESOM) += litesom.o
obj-$(CONFIG_MX6UL_OPOS6UL) += opos6ul.o

302
arch/arm/cpu/armv7/mx6/opos6ul.c Normal file
View File

@ -0,0 +1,302 @@
/*
* Copyright (C) 2017 Armadeus Systems
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/mx6ul_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
#include <environment.h>
#include <fsl_esdhc.h>
#include <mmc.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FEC_MXC
#include <miiphy.h>
#define MDIO_PAD_CTRL ( \
PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm \
)
#define ENET_PAD_CTRL_PU ( \
PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm \
)
#define ENET_PAD_CTRL_PD ( \
PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm \
)
#define ENET_CLK_PAD_CTRL ( \
PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \
)
static iomux_v3_cfg_t const fec1_pads[] = {
MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
/* PHY Int */
MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
/* PHY Reset */
MX6_PAD_NAND_DATA00__GPIO4_IO02 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
};
int board_phy_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
int board_eth_init(bd_t *bis)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
struct gpio_desc rst;
int ret;
/* Use 50M anatop loopback REF_CLK1 for ENET1,
* clear gpr1[13], set gpr1[17] */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
ret = enable_fec_anatop_clock(0, ENET_50MHZ);
if (ret)
return ret;
enable_enet_clk(1);
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
ret = dm_gpio_lookup_name("GPIO4_2", &rst);
if (ret) {
printf("Cannot get GPIO4_2\n");
return ret;
}
ret = dm_gpio_request(&rst, "phy-rst");
if (ret) {
printf("Cannot request GPIO4_2\n");
return ret;
}
dm_gpio_set_dir_flags(&rst, GPIOD_IS_OUT);
dm_gpio_set_value(&rst, 0);
udelay(1000);
dm_gpio_set_value(&rst, 1);
return fecmxc_initialize(bis);
}
#endif /* CONFIG_FEC_MXC */
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int __weak opos6ul_board_late_init(void)
{
return 0;
}
int board_late_init(void)
{
struct src *psrc = (struct src *)SRC_BASE_ADDR;
unsigned reg = readl(&psrc->sbmr2);
/* In bootstrap don't use the env vars */
if (((reg & 0x3000000) >> 24) == 0x1) {
set_default_env(NULL);
setenv("preboot", "");
}
return opos6ul_board_late_init();
}
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
return cfg->esdhc_base == USDHC1_BASE_ADDR;
}
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
#ifdef CONFIG_SPL_BUILD
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/opos6ul.h>
#include <libfdt.h>
#include <spl.h>
#define USDHC_PAD_CTRL ( \
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST \
)
struct fsl_esdhc_cfg usdhc_cfg[1] = {
{USDHC1_BASE_ADDR, 0, 8},
};
static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000030,
.grp_ddrmode_ctl = 0x00020000,
.grp_b0ds = 0x00000030,
.grp_ctlds = 0x00000030,
.grp_b1ds = 0x00000030,
.grp_ddrpke = 0x00000000,
.grp_ddrmode = 0x00020000,
.grp_ddr_type = 0x000c0000,
};
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm0 = 0x00000030,
.dram_dqm1 = 0x00000030,
.dram_ras = 0x00000030,
.dram_cas = 0x00000030,
.dram_odt0 = 0x00000030,
.dram_odt1 = 0x00000030,
.dram_sdba2 = 0x00000000,
.dram_sdclk_0 = 0x00000008,
.dram_sdqs0 = 0x00000038,
.dram_sdqs1 = 0x00000030,
.dram_reset = 0x00000030,
};
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p0_mpwldectrl0 = 0x00070007,
.p0_mpdgctrl0 = 0x41490145,
.p0_mprddlctl = 0x40404546,
.p0_mpwrdlctl = 0x4040524D,
};
struct mx6_ddr_sysinfo ddr_sysinfo = {
.dsize = 0,
.cs_density = 20,
.ncs = 1,
.cs1_mirror = 0,
.rtt_wr = 2,
.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
};
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 800,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.pagesz = 2,
.trcd = 1500,
.trcmin = 5250,
.trasmin = 3750,
};
int board_mmc_init(bd_t *bis)
{
imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0xFFFFFFFF, &ccm->CCGR0);
writel(0xFFFFFFFF, &ccm->CCGR1);
writel(0xFFFFFFFF, &ccm->CCGR2);
writel(0xFFFFFFFF, &ccm->CCGR3);
writel(0xFFFFFFFF, &ccm->CCGR4);
writel(0xFFFFFFFF, &ccm->CCGR5);
writel(0xFFFFFFFF, &ccm->CCGR6);
writel(0xFFFFFFFF, &ccm->CCGR7);
}
static void spl_dram_init(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
struct fuse_bank *bank = &ocotp->bank[4];
struct fuse_bank4_regs *fuse =
(struct fuse_bank4_regs *)bank->fuse_regs;
int reg = readl(&fuse->gp1);
/* 512MB of RAM */
if (reg & 0x1) {
mem_ddr.density = 4;
mem_ddr.rowaddr = 15;
mem_ddr.trcd = 1375;
mem_ddr.trcmin = 4875;
mem_ddr.trasmin = 3500;
}
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
void board_init_f(ulong dummy)
{
ccgr_init();
/* setup AIPS and disable watchdog */
arch_cpu_init();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
opos6ul_setup_uart_debug();
preloader_console_init();
/* DDR initialization */
spl_dram_init();
}
#endif /* CONFIG_SPL_BUILD */

13
arch/arm/cpu/armv7/mx7/soc.c
View File

@ -103,8 +103,9 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
*/
#define OCOTP_TESTER3_SPEED_SHIFT 8
#define OCOTP_TESTER3_SPEED_800MHZ 0
#define OCOTP_TESTER3_SPEED_850MHZ 1
#define OCOTP_TESTER3_SPEED_500MHZ 1
#define OCOTP_TESTER3_SPEED_1GHZ 2
#define OCOTP_TESTER3_SPEED_1P2GHZ 3
u32 get_cpu_speed_grade_hz(void)
{
@ -120,11 +121,13 @@ u32 get_cpu_speed_grade_hz(void)
switch(val) {
case OCOTP_TESTER3_SPEED_800MHZ:
return 792000000;
case OCOTP_TESTER3_SPEED_850MHZ:
return 852000000;
return 800000000;
case OCOTP_TESTER3_SPEED_500MHZ:
return 500000000;
case OCOTP_TESTER3_SPEED_1GHZ:
return 996000000;
return 1000000000;
case OCOTP_TESTER3_SPEED_1P2GHZ:
return 1200000000;
}
return 0;
}

17
arch/arm/cpu/armv7/mx7ulp/Kconfig Normal file
View File

@ -0,0 +1,17 @@
if ARCH_MX7ULP
config SYS_SOC
default "mx7ulp"
choice
prompt "MX7ULP board select"
optional
config TARGET_MX7ULP_EVK
bool "Support mx7ulp EVK board"
endchoice
source "board/freescale/mx7ulp_evk/Kconfig"
endif

8
arch/arm/cpu/armv7/mx7ulp/Makefile Normal file
View File

@ -0,0 +1,8 @@
#
# (C) Copyright 2016 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
#
obj-y := soc.o clock.o iomux.o pcc.o scg.o

365
arch/arm/cpu/armv7/mx7ulp/clock.c Normal file
View File

@ -0,0 +1,365 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <div64.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#endif
#endif
return 0;
}
static u32 get_fast_plat_clk(void)
{
return scg_clk_get_rate(SCG_NIC0_CLK);
}
static u32 get_slow_plat_clk(void)
{
return scg_clk_get_rate(SCG_NIC1_CLK);
}
static u32 get_ipg_clk(void)
{
return scg_clk_get_rate(SCG_NIC1_BUS_CLK);
}
u32 get_lpuart_clk(void)
{
int index = 0;
const u32 lpuart_array[] = {
LPUART0_RBASE,
LPUART1_RBASE,
LPUART2_RBASE,
LPUART3_RBASE,
LPUART4_RBASE,
LPUART5_RBASE,
LPUART6_RBASE,
LPUART7_RBASE,
};
const enum pcc_clk lpuart_pcc_clks[] = {
PER_CLK_LPUART4,
PER_CLK_LPUART5,
PER_CLK_LPUART6,
PER_CLK_LPUART7,
};
for (index = 0; index < 8; index++) {
if (lpuart_array[index] == LPUART_BASE)
break;
}
if (index < 4 || index > 7)
return 0;
return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]);
}
#ifdef CONFIG_SYS_LPI2C_IMX
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{
/* Set parent to FIRC DIV2 clock */
const enum pcc_clk lpi2c_pcc_clks[] = {
PER_CLK_LPI2C4,
PER_CLK_LPI2C5,
PER_CLK_LPI2C6,
PER_CLK_LPI2C7,
};
if (i2c_num < 4 || i2c_num > 7)
return -EINVAL;
if (enable) {
pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
pcc_clock_sel(lpi2c_pcc_clks[i2c_num - 4], SCG_FIRC_DIV2_CLK);
pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], true);
} else {
pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
}
return 0;
}
u32 imx_get_i2cclk(unsigned i2c_num)
{
const enum pcc_clk lpi2c_pcc_clks[] = {
PER_CLK_LPI2C4,
PER_CLK_LPI2C5,
PER_CLK_LPI2C6,
PER_CLK_LPI2C7,
};
if (i2c_num < 4 || i2c_num > 7)
return 0;
return pcc_clock_get_rate(lpi2c_pcc_clks[i2c_num - 4]);
}
#endif
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
case MXC_ARM_CLK:
return scg_clk_get_rate(SCG_CORE_CLK);
case MXC_AXI_CLK:
return get_fast_plat_clk();
case MXC_AHB_CLK:
return get_slow_plat_clk();
case MXC_IPG_CLK:
return get_ipg_clk();
case MXC_I2C_CLK:
return pcc_clock_get_rate(PER_CLK_LPI2C4);
case MXC_UART_CLK:
return get_lpuart_clk();
case MXC_ESDHC_CLK:
return pcc_clock_get_rate(PER_CLK_USDHC0);
case MXC_ESDHC2_CLK:
return pcc_clock_get_rate(PER_CLK_USDHC1);
case MXC_DDR_CLK:
return scg_clk_get_rate(SCG_DDR_CLK);
default:
printf("Unsupported mxc_clock %d\n", clk);
break;
}
return 0;
}
void init_clk_usdhc(u32 index)
{
switch (index) {
case 0:
/*Disable the clock before configure it */
pcc_clock_enable(PER_CLK_USDHC0, false);
/* 158MHz / 1 = 158MHz */
pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK);
pcc_clock_div_config(PER_CLK_USDHC0, false, 1);
pcc_clock_enable(PER_CLK_USDHC0, true);
break;
case 1:
/*Disable the clock before configure it */
pcc_clock_enable(PER_CLK_USDHC1, false);
/* 158MHz / 1 = 158MHz */
pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK);
pcc_clock_div_config(PER_CLK_USDHC1, false, 1);
pcc_clock_enable(PER_CLK_USDHC1, true);
break;
default:
printf("Invalid index for USDHC %d\n", index);
break;
}
}
#ifdef CONFIG_MXC_OCOTP
#define OCOTP_CTRL_PCC1_SLOT (38)
#define OCOTP_CTRL_HIGH4K_PCC1_SLOT (39)
void enable_ocotp_clk(unsigned char enable)
{
u32 val;
/*
* Seems the OCOTP CLOCKs have been enabled at default,
* check its inuse flag
*/
val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT);
if (!(val & PCC_INUSE_MASK))
writel(PCC_CGC_MASK, (PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT));
val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT);
if (!(val & PCC_INUSE_MASK))
writel(PCC_CGC_MASK,
(PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT));
}
#endif
void enable_usboh3_clk(unsigned char enable)
{
if (enable) {
pcc_clock_enable(PER_CLK_USB0, false);
pcc_clock_sel(PER_CLK_USB0, SCG_NIC1_BUS_CLK);
pcc_clock_enable(PER_CLK_USB0, true);
#ifdef CONFIG_USB_MAX_CONTROLLER_COUNT
if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) {
pcc_clock_enable(PER_CLK_USB1, false);
pcc_clock_sel(PER_CLK_USB1, SCG_NIC1_BUS_CLK);
pcc_clock_enable(PER_CLK_USB1, true);
}
#endif
pcc_clock_enable(PER_CLK_USB_PHY, true);
pcc_clock_enable(PER_CLK_USB_PL301, true);
} else {
pcc_clock_enable(PER_CLK_USB0, false);
pcc_clock_enable(PER_CLK_USB1, false);
pcc_clock_enable(PER_CLK_USB_PHY, false);
pcc_clock_enable(PER_CLK_USB_PL301, false);
}
}
static void lpuart_set_clk(uint32_t index, enum scg_clk clk)
{
const enum pcc_clk lpuart_pcc_clks[] = {
PER_CLK_LPUART4,
PER_CLK_LPUART5,
PER_CLK_LPUART6,
PER_CLK_LPUART7,
};
if (index < 4 || index > 7)
return;
#ifndef CONFIG_CLK_DEBUG
pcc_clock_enable(lpuart_pcc_clks[index - 4], false);
#endif
pcc_clock_sel(lpuart_pcc_clks[index - 4], clk);
pcc_clock_enable(lpuart_pcc_clks[index - 4], true);
}
static void init_clk_lpuart(void)
{
u32 index = 0, i;
const u32 lpuart_array[] = {
LPUART0_RBASE,
LPUART1_RBASE,
LPUART2_RBASE,
LPUART3_RBASE,
LPUART4_RBASE,
LPUART5_RBASE,
LPUART6_RBASE,
LPUART7_RBASE,
};
for (i = 0; i < 8; i++) {
if (lpuart_array[i] == LPUART_BASE) {
index = i;
break;
}
}
lpuart_set_clk(index, SCG_SOSC_DIV2_CLK);
}
static void init_clk_rgpio2p(void)
{
/*Enable RGPIO2P1 clock */
pcc_clock_enable(PER_CLK_RGPIO2P1, true);
/*
* Hard code to enable RGPIO2P0 clock since it is not
* in clock frame for A7 domain
*/
writel(PCC_CGC_MASK, (PCC0_RBASE + 0x3C));
}
/* Configure PLL/PFD freq */
void clock_init(void)
{
/*
* ROM has enabled clocks:
* A4 side: SIRC 16Mhz (DIV1-3 off), FIRC 48Mhz (DIV1-2 on),
* Non-LP-boot: SOSC, SPLL PFD0 (scs selected)
* A7 side: SPLL PFD0 (scs selected, 413Mhz),
* APLL PFD0 (352Mhz), DDRCLK, all NIC clocks
* A7 Plat0 (NIC0) = 176Mhz, Plat1 (NIC1) = 176Mhz,
* IP BUS (NIC1_BUS) = 58.6Mhz
*
* In u-boot:
* 1. Enable PFD1-3 of APLL for A7 side. Enable FIRC and DIVs.
* 2. Enable USB PLL
* 3. Init the clocks of peripherals used in u-boot bu
* without set rate interface.The clocks for these
* peripherals are enabled in this intialization.
* 4.Other peripherals with set clock rate interface
* does not be set in this function.
*/
scg_a7_firc_init();
scg_a7_soscdiv_init();
/* APLL PFD1 = 270Mhz, PFD2=480Mhz, PFD3=800Mhz */
scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 20);
scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
init_clk_lpuart();
init_clk_rgpio2p();
enable_usboh3_clk(1);
}
#ifdef CONFIG_SECURE_BOOT
void hab_caam_clock_enable(unsigned char enable)
{
if (enable)
pcc_clock_enable(PER_CLK_CAAM, true);
else
pcc_clock_enable(PER_CLK_CAAM, false);
}
#endif
/*
* Dump some core clockes.
*/
int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 addr = 0;
u32 freq;
freq = decode_pll(PLL_A7_SPLL);
printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000);
freq = decode_pll(PLL_A7_APLL);
printf("PLL_A7_APLL %8d MHz\n", freq / 1000000);
freq = decode_pll(PLL_USB);
printf("PLL_USB %8d MHz\n", freq / 1000000);
printf("\n");
printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000);
printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
printf("I2C4 %8d kHz\n", mxc_get_clock(MXC_I2C_CLK) / 1000);
addr = (u32) clock_init;
printf("[%s] addr = 0x%08X\r\n", __func__, addr);
scg_a7_info();
return 0;
}
U_BOOT_CMD(
clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
"display clocks",
""
);

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arch/arm/cpu/armv7/mx7ulp/iomux.c Normal file
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/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
static void *base = (void *)IOMUXC_BASE_ADDR;
/*
* iomuxc0 base address. In imx7ulp-pins.h,
* the offsets of pins in iomuxc0 are from 0xD000,
* so we set the base address to (0x4103D000 - 0xD000 = 0x41030000)
*/
static void *base_mports = (void *)(AIPS0_BASE + 0x30000);
/*
* configures a single pad in the iomuxer
*/
void mx7ulp_iomux_setup_pad(iomux_cfg_t pad)
{
u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
u32 sel_input_ofs =
(pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
u32 sel_input =
(pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
u32 pad_ctrl_ofs = mux_ctrl_ofs;
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
debug("[PAD CFG] = 0x%16llX \r\n\tmux_ctl = 0x%X(0x%X) sel_input = 0x%X(0x%X) pad_ctrl = 0x%X(0x%X)\r\n",
pad, mux_ctrl_ofs, mux_mode, sel_input_ofs, sel_input,
pad_ctrl_ofs, pad_ctrl);
if (mux_mode & IOMUX_CONFIG_MPORTS) {
mux_mode &= ~IOMUX_CONFIG_MPORTS;
base = base_mports;
} else {
base = (void *)IOMUXC_BASE_ADDR;
}
__raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
IOMUXC_PCR_MUX_ALT_MASK), base + mux_ctrl_ofs);
if (sel_input_ofs)
__raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT),
base + sel_input_ofs);
if (!(pad_ctrl & NO_PAD_CTRL))
__raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
IOMUXC_PCR_MUX_ALT_MASK) |
(pad_ctrl & (~IOMUXC_PCR_MUX_ALT_MASK)),
base + pad_ctrl_ofs);
}
/* configures a list of pads within declared with IOMUX_PADS macro */
void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list,
unsigned count)
{
iomux_cfg_t const *p = pad_list;
int i;
for (i = 0; i < count; i++) {
mx7ulp_iomux_setup_pad(*p);
p++;
}
}

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/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <div64.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/pcc.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
#define PCC_CLKSRC_TYPES 2
#define PCC_CLKSRC_NUM 7
static enum scg_clk pcc_clksrc[PCC_CLKSRC_TYPES][PCC_CLKSRC_NUM] = {
{ SCG_NIC1_BUS_CLK,
SCG_NIC1_CLK,
SCG_DDR_CLK,
SCG_APLL_PFD2_CLK,
SCG_APLL_PFD1_CLK,
SCG_APLL_PFD0_CLK,
USB_PLL_OUT,
},
{ SCG_SOSC_DIV2_CLK, /* SOSC BUS clock */
MIPI_PLL_OUT,
SCG_FIRC_DIV2_CLK, /* FIRC BUS clock */
SCG_ROSC_CLK,
SCG_NIC1_BUS_CLK,
SCG_NIC1_CLK,
SCG_APLL_PFD3_CLK,
},
};
static struct pcc_entry pcc_arrays[] = {
{PCC2_RBASE, DMA1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
{PCC2_RBASE, RGPIO1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
{PCC2_RBASE, FLEXBUS0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
{PCC2_RBASE, SEMA42_1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
{PCC2_RBASE, DMA1_CH_MUX0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
{PCC2_RBASE, SNVS_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
{PCC2_RBASE, CAAM_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
{PCC2_RBASE, LPTPM4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
{PCC2_RBASE, LPTPM5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
{PCC2_RBASE, LPIT1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
{PCC2_RBASE, LPSPI2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
{PCC2_RBASE, LPSPI3_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
{PCC2_RBASE, LPI2C4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
{PCC2_RBASE, LPI2C5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
{PCC2_RBASE, LPUART4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
{PCC2_RBASE, LPUART5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
{PCC2_RBASE, FLEXIO1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
{PCC2_RBASE, USBOTG0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
{PCC2_RBASE, USBOTG1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
{PCC2_RBASE, USBPHY_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
{PCC2_RBASE, USB_PL301_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
{PCC2_RBASE, USDHC0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
{PCC2_RBASE, USDHC1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
{PCC2_RBASE, WDG1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
{PCC2_RBASE, WDG2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
{PCC3_RBASE, LPTPM6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
{PCC3_RBASE, LPTPM7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
{PCC3_RBASE, LPI2C6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
{PCC3_RBASE, LPI2C7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
{PCC3_RBASE, LPUART6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
{PCC3_RBASE, LPUART7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
{PCC3_RBASE, VIU0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
{PCC3_RBASE, DSI0_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
{PCC3_RBASE, LCDIF0_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
{PCC3_RBASE, MMDC0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
{PCC3_RBASE, PORTC_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
{PCC3_RBASE, PORTD_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
{PCC3_RBASE, PORTE_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
{PCC3_RBASE, PORTF_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
{PCC3_RBASE, GPU3D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
{PCC3_RBASE, GPU2D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
};
int pcc_clock_enable(enum pcc_clk clk, bool enable)
{
u32 reg, val;
if (clk >= ARRAY_SIZE(pcc_arrays))
return -EINVAL;
reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
val = readl(reg);
clk_debug("pcc_clock_enable: clk %d, reg 0x%x, val 0x%x, enable %d\n",
clk, reg, val, enable);
if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK))
return -EPERM;
if (enable)
val |= PCC_CGC_MASK;
else
val &= ~PCC_CGC_MASK;
writel(val, reg);
clk_debug("pcc_clock_enable: val 0x%x\n", val);
return 0;
}
/* The clock source select needs clock is disabled */
int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src)
{
u32 reg, val, i, clksrc_type;
if (clk >= ARRAY_SIZE(pcc_arrays))
return -EINVAL;
clksrc_type = pcc_arrays[clk].clksrc;
if (clksrc_type >= CLKSRC_NO_PCS) {
printf("No PCS field for the PCC %d, clksrc type %d\n",
clk, clksrc_type);
return -EPERM;
}
for (i = 0; i < PCC_CLKSRC_NUM; i++) {
if (pcc_clksrc[clksrc_type][i] == src) {
/* Find the clock src, then set it to PCS */
break;
}
}
if (i == PCC_CLKSRC_NUM) {
printf("Not find the parent scg_clk in PCS of PCC %d, invalid scg_clk %d\n", clk, src);
return -EINVAL;
}
reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
val = readl(reg);
clk_debug("pcc_clock_sel: clk %d, reg 0x%x, val 0x%x, clksrc_type %d\n",
clk, reg, val, clksrc_type);
if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
(val & PCC_CGC_MASK)) {
printf("Not permit to select clock source val = 0x%x\n", val);
return -EPERM;
}
val &= ~PCC_PCS_MASK;
val |= ((i + 1) << PCC_PCS_OFFSET);
writel(val, reg);
clk_debug("pcc_clock_sel: val 0x%x\n", val);
return 0;
}
int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div)
{
u32 reg, val;
if (clk >= ARRAY_SIZE(pcc_arrays) || div > 8 ||
(div == 1 && frac != 0))
return -EINVAL;
if (pcc_arrays[clk].div >= PCC_NO_DIV) {
printf("No DIV/FRAC field for the PCC %d\n", clk);
return -EPERM;
}
reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
val = readl(reg);
if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
(val & PCC_CGC_MASK)) {
printf("Not permit to set div/frac val = 0x%x\n", val);
return -EPERM;
}
if (frac)
val |= PCC_FRAC_MASK;
else
val &= ~PCC_FRAC_MASK;
val &= ~PCC_PCD_MASK;
val |= (div - 1) & PCC_PCD_MASK;
writel(val, reg);
return 0;
}
bool pcc_clock_is_enable(enum pcc_clk clk)
{
u32 reg, val;
if (clk >= ARRAY_SIZE(pcc_arrays))
return -EINVAL;
reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
val = readl(reg);
if ((val & PCC_INUSE_MASK) || (val & PCC_CGC_MASK))
return true;
return false;
}
int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src)
{
u32 reg, val, clksrc_type;
if (clk >= ARRAY_SIZE(pcc_arrays))
return -EINVAL;
clksrc_type = pcc_arrays[clk].clksrc;
if (clksrc_type >= CLKSRC_NO_PCS) {
printf("No PCS field for the PCC %d, clksrc type %d\n",
clk, clksrc_type);
return -EPERM;
}
reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
val = readl(reg);
clk_debug("pcc_clock_get_clksrc: clk %d, reg 0x%x, val 0x%x, type %d\n",
clk, reg, val, clksrc_type);
if (!(val & PCC_PR_MASK)) {
printf("This pcc slot is not present = 0x%x\n", val);
return -EPERM;
}
val &= PCC_PCS_MASK;
val = (val >> PCC_PCS_OFFSET);
if (!val) {
printf("Clock source is off\n");
return -EIO;
}
*src = pcc_clksrc[clksrc_type][val - 1];
clk_debug("pcc_clock_get_clksrc: parent scg clk %d\n", *src);
return 0;
}
u32 pcc_clock_get_rate(enum pcc_clk clk)
{
u32 reg, val, rate, frac, div;
enum scg_clk parent;
int ret;
ret = pcc_clock_get_clksrc(clk, &parent);
if (ret)
return 0;
rate = scg_clk_get_rate(parent);
clk_debug("pcc_clock_get_rate: parent rate %u\n", rate);
if (pcc_arrays[clk].div == PCC_HAS_DIV) {
reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
val = readl(reg);
frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET;
div = (val & PCC_PCD_MASK) >> PCC_PCD_OFFSET;
/*
* Theoretically don't have overflow in the calc,
* the rate won't exceed 2G
*/
rate = rate * (frac + 1) / (div + 1);
}
clk_debug("pcc_clock_get_rate: rate %u\n", rate);
return rate;
}

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arch/arm/cpu/armv7/mx7ulp/scg.c Normal file
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/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/hab.h>
static char *get_reset_cause(char *);
#if defined(CONFIG_SECURE_BOOT)
struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
.bank = 29,
.word = 6,
};
#endif
u32 get_cpu_rev(void)
{
/* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */
return (MXC_CPU_MX7ULP << 12) | (1 << 4);
}
#ifdef CONFIG_REVISION_TAG
u32 __weak get_board_rev(void)
{
return get_cpu_rev();
}
#endif
enum bt_mode get_boot_mode(void)
{
u32 bt0_cfg = 0;
bt0_cfg = readl(CMC0_RBASE + 0x40);
bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
/* No low power boot */
if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
return DUAL_BOOT;
else
return SINGLE_BOOT;
}
return LOW_POWER_BOOT;
}
int arch_cpu_init(void)
{
return 0;
}
#ifdef CONFIG_BOARD_POSTCLK_INIT
int board_postclk_init(void)
{
return 0;
}
#endif
#define UNLOCK_WORD0 0xC520 /* 1st unlock word */
#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
#define REFRESH_WORD0 0xA602 /* 1st refresh word */
#define REFRESH_WORD1 0xB480 /* 2nd refresh word */
static void disable_wdog(u32 wdog_base)
{
writel(UNLOCK_WORD0, (wdog_base + 0x04));
writel(UNLOCK_WORD1, (wdog_base + 0x04));
writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
writel(REFRESH_WORD1, (wdog_base + 0x04));
}
void init_wdog(void)
{
/*
* ROM will configure WDOG1, disable it or enable it
* depending on FUSE. The update bit is set for reconfigurable.
* We have to use unlock sequence to reconfigure it.
* WDOG2 is not touched by ROM, so it will have default value
* which is enabled. We can directly configure it.
* To simplify the codes, we still use same reconfigure
* process as WDOG1. Because the update bit is not set for
* WDOG2, the unlock sequence won't take effect really.
* It actually directly configure the wdog.
* In this function, we will disable both WDOG1 and WDOG2,
* and set update bit for both. So that kernel can reconfigure them.
*/
disable_wdog(WDG1_RBASE);
disable_wdog(WDG2_RBASE);
}
void s_init(void)
{
/* Disable wdog */
init_wdog();
/* clock configuration. */
clock_init();
return;
}
#ifndef CONFIG_ULP_WATCHDOG
void reset_cpu(ulong addr)
{
setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
while (1)
;
}
#endif
#if defined(CONFIG_DISPLAY_CPUINFO)
const char *get_imx_type(u32 imxtype)
{
return "7ULP";
}
int print_cpuinfo(void)
{
u32 cpurev;
char cause[18];
cpurev = get_cpu_rev();
printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
get_imx_type((cpurev & 0xFF000) >> 12),
(cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
printf("Reset cause: %s\n", get_reset_cause(cause));
printf("Boot mode: ");
switch (get_boot_mode()) {
case LOW_POWER_BOOT:
printf("Low power boot\n");
break;
case DUAL_BOOT:
printf("Dual boot\n");
break;
case SINGLE_BOOT:
default:
printf("Single boot\n");
break;
}
return 0;
}
#endif
#define CMC_SRS_TAMPER (1 << 31)
#define CMC_SRS_SECURITY (1 << 30)
#define CMC_SRS_TZWDG (1 << 29)
#define CMC_SRS_JTAG_RST (1 << 28)
#define CMC_SRS_CORE1 (1 << 16)
#define CMC_SRS_LOCKUP (1 << 15)
#define CMC_SRS_SW (1 << 14)
#define CMC_SRS_WDG (1 << 13)
#define CMC_SRS_PIN_RESET (1 << 8)
#define CMC_SRS_WARM (1 << 4)
#define CMC_SRS_HVD (1 << 3)
#define CMC_SRS_LVD (1 << 2)
#define CMC_SRS_POR (1 << 1)
#define CMC_SRS_WUP (1 << 0)
static u32 reset_cause = -1;
static char *get_reset_cause(char *ret)
{
u32 cause1, cause = 0, srs = 0;
u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28);
u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20);
if (!ret)
return "null";
srs = readl(reg_srs);
cause1 = readl(reg_ssrs);
writel(cause1, reg_ssrs);
reset_cause = cause1;
cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
switch (cause) {
case CMC_SRS_POR:
sprintf(ret, "%s", "POR");
break;
case CMC_SRS_WUP:
sprintf(ret, "%s", "WUP");
break;
case CMC_SRS_WARM:
cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
CMC_SRS_JTAG_RST);
switch (cause) {
case CMC_SRS_WDG:
sprintf(ret, "%s", "WARM-WDG");
break;
case CMC_SRS_SW:
sprintf(ret, "%s", "WARM-SW");
break;
case CMC_SRS_JTAG_RST:
sprintf(ret, "%s", "WARM-JTAG");
break;
default:
sprintf(ret, "%s", "WARM-UNKN");
break;
}
break;
default:
sprintf(ret, "%s-%X", "UNKN", cause1);
break;
}
debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1);
return ret;
}
#ifdef CONFIG_ENV_IS_IN_MMC
__weak int board_mmc_get_env_dev(int devno)
{
return CONFIG_SYS_MMC_ENV_DEV;
}
int mmc_get_env_dev(void)
{
int devno = 0;
u32 bt1_cfg = 0;
/* If not boot from sd/mmc, use default value */
if (get_boot_mode() == LOW_POWER_BOOT)
return CONFIG_SYS_MMC_ENV_DEV;
bt1_cfg = readl(CMC1_RBASE + 0x40);
devno = (bt1_cfg >> 9) & 0x7;
return board_mmc_get_env_dev(devno);
}
#endif

36
arch/arm/cpu/armv7/vf610/Kconfig Normal file
View File

@ -0,0 +1,36 @@
if ARCH_VF610
config VF610
bool
default y
choice
prompt "Vybrid board select"
config TARGET_VF610TWR
bool "TWR-VF65GS10-DS5"
config TARGET_COLIBRI_VF
bool "Colibri VF50/61"
select BOARD_LATE_INIT
config TARGET_PCM052
bool "PCM-052"
select SYS_FSL_ERRATUM_ESDHC135
select SYS_FSL_ERRATUM_ESDHC_A001
config TARGET_BK4R1
bool "BK4r1"
select SYS_FSL_ERRATUM_ESDHC135
select SYS_FSL_ERRATUM_ESDHC_A001
endchoice
config SYS_SOC
default "vf610"
source "board/freescale/vf610twr/Kconfig"
source "board/phytec/pcm052/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
endif

5
arch/arm/cpu/armv7/vf610/generic.c
View File

@ -204,6 +204,11 @@ static u32 get_dspi_clk(void)
return get_ipg_clk();
}
u32 get_lpuart_clk(void)
{
return get_uart_clk();
}
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {

8
arch/arm/dts/Makefile
View File

@ -317,10 +317,16 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
imx6q-icore.dtb \
imx6q-icore-rqs.dtb \
imx6sx-sabreauto.dtb \
imx6ul-geam-kit.dtb
imx6ul-geam-kit.dtb \
imx6ul-isiot-emmc.dtb \
imx6ul-isiot-mmc.dtb \
imx6ul-isiot-nand.dtb \
imx6ul-opos6uldev.dtb
dtb-$(CONFIG_MX7) += imx7-colibri.dtb
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
keystone-k2e-evm.dtb \

22
arch/arm/dts/imx6qdl-icore-rqs.dtsi
View File

@ -107,6 +107,13 @@
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
no-1-8-v;
status = "okay";
};
&iomuxc {
pinctrl_enet: enetgrp {
fsl,pins = <
@ -167,4 +174,19 @@
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17070
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10070
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070
>;
};
};

77
arch/arm/dts/imx6ul-isiot-emmc.dts Normal file
View File

@ -0,0 +1,77 @@
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6ul-isiot.dtsi"
/ {
model = "Engicam Is.IoT MX6UL eMMC Starterkit";
compatible = "engicam,imx6ul-isiot", "fsl,imx6ul";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
bus-width = <8>;
no-1-8-v;
status = "okay";
};
&iomuxc {
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070
MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070
>;
};
};

50
arch/arm/dts/imx6ul-isiot-mmc.dts Normal file
View File

@ -0,0 +1,50 @@
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6ul-isiot.dtsi"
/ {
model = "Engicam Is.IoT MX6UL MMC Starterkit";
compatible = "engicam,imx6ul-isiot", "fsl,imx6ul";
};

50
arch/arm/dts/imx6ul-isiot-nand.dts Normal file
View File

@ -0,0 +1,50 @@
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6ul-isiot.dtsi"
/ {
model = "Engicam Is.IoT MX6UL NAND Starterkit";
compatible = "engicam,imx6ul-isiot", "fsl,imx6ul";
};

140
arch/arm/dts/imx6ul-isiot.dtsi Normal file
View File

@ -0,0 +1,140 @@
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6ul.dtsi"
/ {
memory {
reg = <0x80000000 0x20000000>;
};
chosen {
stdout-path = &uart1;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
clock_frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
bus-width = <4>;
no-1-8-v;
status = "okay";
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>;
};
};

192
arch/arm/dts/imx6ul-opos6ul.dtsi Normal file
View File

@ -0,0 +1,192 @@
/*
* Copyright 2017 Armadeus Systems <support@armadeus.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "imx6ul.dtsi"
/ {
memory {
reg = <0x80000000 0>; /* will be filled by U-Boot */
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
usdhc3_pwrseq: usdhc3-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-reset-duration = <1>;
phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
phy-handle = <&ethphy1>;
phy-supply = <&reg_3v3>;
status = "okay";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&gpio4>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
};
};
};
/* Bluetooth */
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8>;
uart-has-rtscts;
status = "okay";
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
no-1-8-v;
non-removable;
status = "okay";
};
/* WiFi */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
no-1-8-v;
non-removable;
mmc-pwrseq = <&usdhc3_pwrseq>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
brcmf: bcrmf@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio2>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
/* INT# */
MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
/* RST# */
MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
pinctrl_uart8: uart8grp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0
/* BT_REG_ON */
MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0
MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0
MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0
MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0
MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0
MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0
/* WL_REG_ON */
MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0
/* WL_IRQ */
MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
>;
};
};

412
arch/arm/dts/imx6ul-opos6uldev.dts Normal file
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@ -0,0 +1,412 @@
/*
* Copyright 2017 Armadeus Systems <support@armadeus.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6ul-opos6ul.dtsi"
/ {
model = "Armadeus Systems OPOS6UL SoM on OPOS6ULDev board";
compatible = "armadeus,opos6uldev", "armadeus,opos6ul", "fsl,imx6ul";
chosen {
stdout-path = &uart1;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 191000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_5v>;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
user-button {
label = "User button";
gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
linux,code = <BTN_MISC>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
user-led {
label = "User";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
onewire {
compatible = "w1-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_w1>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usbotg1_vbus: regulator-usbotg1vbus {
compatible = "regulator-fixed";
regulator-name = "usbotg1vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_vbus>;
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usbotg2_vbus: regulator-usbotg2vbus {
compatible = "regulator-fixed";
regulator-name = "usbotg2vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2_vbus>;
gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&adc1 {
vref-supply = <&reg_3v3>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_5v>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_5v>;
status = "okay";
};
&ecspi4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>;
status = "okay";
spidev0: spi@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <5000000>;
};
spidev1: spi@1 {
compatible = "spidev";
reg = <1>;
spi-max-frequency = <5000000>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock_frequency = <400000>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock_frequency = <400000>;
status = "okay";
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
display = <&display0>;
lcd-supply = <&reg_3v3>;
status = "okay";
display0: display0 {
bits-per-pixel = <32>;
bus-width = <18>;
display-timings {
timing0: timing0 {
clock-frequency = <33000033>;
hactive = <800>;
vactive = <480>;
hback-porch = <96>;
hfront-porch = <96>;
vback-porch = <20>;
vfront-porch = <21>;
hsync-len = <64>;
vsync-len = <4>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&snvs_pwrkey {
status = "disabled";
};
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure-delay-time = <0xffff>;
pre-charge-time = <0xffff>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_id>;
vbus-supply = <&reg_usbotg1_vbus>;
dr_mode = "otg";
disable-over-current;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usbotg2_vbus>;
dr_mode = "host";
disable-over-current;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpios>;
pinctrl_ecspi4: ecspi4grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0
MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0
MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0
MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0
MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
>;
};
pinctrl_gpios: gpiosgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0
MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0
MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0
MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0
MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0
MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
>;
};
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0
>;
};
pinctrl_tsc: tscgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
>;
};
pinctrl_usbotg1_id: usbotg1idgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0
>;
};
pinctrl_usbotg1_vbus: usbotg1vbusgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0
>;
};
pinctrl_usbotg2_vbus: usbotg2vbusgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
>;
};
pinctrl_w1: w1grp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0
>;
};
};

2
arch/arm/dts/imx6ul.dtsi
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@ -43,6 +43,8 @@
spi1 = &ecspi2;
spi2 = &ecspi3;
spi3 = &ecspi4;
usbotg0 = &usbotg1;
usbotg1 = &usbotg2;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
};

426
arch/arm/dts/imx7ulp-evk.dts Normal file
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@ -0,0 +1,426 @@
/*
* Copyright 2016 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "imx7ulp.dtsi"
/ {
model = "NXP i.MX7ULP EVK";
compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
chosen {
bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200";
stdout-path = &lpuart4;
};
bcmdhd_wlan_0: bcmdhd_wlan@0 {
compatible = "android,bcmdhd_wlan";
wlreg_on-supply = <&wlreg_on>;
bcmdhd_fw = "/lib/firmware/bcm/1DX_BCM4343W/fw_bcmdhd.bin";
bcmdhd_nv = "/lib/firmware/bcm/1DX_BCM4343W/bcmdhd.1DX.SDIO.cal";
};
memory {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
backlight {
compatible = "gpio-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;
default-on;
status = "okay";
};
mipi_dsi_reset: mipi-dsi-reset {
compatible = "gpio-reset";
reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
#reset-cells = <0>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
wlreg_on: fixedregulator@100 {
compatible = "regulator-fixed";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "wlreg_on";
gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
startup-delay-us = <100>;
enable-active-high;
};
reg_usb_otg1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vsd_3v3: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vsd_3v3b: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "VSD_3V3B";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_extcon_usb1>;
};
pf1550-rpmsg {
compatible = "fsl,pf1550-rpmsg";
sw1_reg: SW1 {
regulator-name = "SW1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1387500>;
regulator-boot-on;
regulator-always-on;
};
sw2_reg: SW2 {
regulator-name = "SW2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1387500>;
regulator-boot-on;
regulator-always-on;
};
sw3_reg: SW3 {
regulator-name = "SW3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: VREFDDR {
regulator-name = "VREFDDR";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
vldo1_reg: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vldo2_reg: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vldo3_reg: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&iomuxc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_1>;
imx7ulp-evk {
pinctrl_hog_1: hoggrp-1 {
fsl,pins = <
ULP1_PAD_PTC10__PTC10 0x30100 /* USDHC0 CD */
ULP1_PAD_PTC1__PTC1 0x20100
ULP1_PAD_PTD0__PTD0 0x30100 /* USDHC0 RST */
ULP1_PAD_PTE13__PTE13 0x30103 /* USDHC1 CD */
ULP1_PAD_PTE12__PTE12 0x30103 /* USDHC1 WP */
ULP1_PAD_PTE14__SDHC1_VS 0x843 /* USDHC1 VSEL */
>;
};
pinctrl_backlight: backlight_grp {
fsl,pins = <
ULP1_PAD_PTF2__PTF2 0x20100
>;
};
pinctrl_lpi2c5: lpi2c5grp {
fsl,pins = <
ULP1_PAD_PTC4__LPI2C5_SCL 0x527
ULP1_PAD_PTC5__LPI2C5_SDA 0x527
>;
};
pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp {
fsl,pins = <
ULP1_PAD_PTC19__PTC19 0x20103
>;
};
pinctrl_lpuart4: lpuart4grp {
fsl,pins = <
ULP1_PAD_PTC3__LPUART4_RX 0x400
ULP1_PAD_PTC2__LPUART4_TX 0x400
>;
};
pinctrl_lpuart6: lpuart6grp {
fsl,pins = <
ULP1_PAD_PTE10__LPUART6_TX 0x400
ULP1_PAD_PTE11__LPUART6_RX 0x400
ULP1_PAD_PTE9__LPUART6_RTS_B 0x400
ULP1_PAD_PTE8__LPUART6_CTS_B 0x400
ULP1_PAD_PTE7__PTE7 0x00 /* BT_REG_ON */
>;
};
pinctrl_lpuart7: lpuart7grp {
fsl,pins = <
ULP1_PAD_PTF14__LPUART7_TX 0x400
ULP1_PAD_PTF15__LPUART7_RX 0x400
ULP1_PAD_PTF13__LPUART7_RTS_B 0x400
ULP1_PAD_PTF12__LPUART7_CTS_B 0x400
>;
};
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
ULP1_PAD_PTD1__SDHC0_CMD 0x843
ULP1_PAD_PTD2__SDHC0_CLK 0x10843
ULP1_PAD_PTD7__SDHC0_D3 0x843
ULP1_PAD_PTD8__SDHC0_D2 0x843
ULP1_PAD_PTD9__SDHC0_D1 0x843
ULP1_PAD_PTD10__SDHC0_D0 0x843
>;
};
pinctrl_usdhc0_8bit: usdhc0grp_8bit {
fsl,pins = <
ULP1_PAD_PTD1__SDHC0_CMD 0x843
ULP1_PAD_PTD2__SDHC0_CLK 0x843
ULP1_PAD_PTD3__SDHC0_D7 0x843
ULP1_PAD_PTD4__SDHC0_D6 0x843
ULP1_PAD_PTD5__SDHC0_D5 0x843
ULP1_PAD_PTD6__SDHC0_D4 0x843
ULP1_PAD_PTD7__SDHC0_D3 0x843
ULP1_PAD_PTD8__SDHC0_D2 0x843
ULP1_PAD_PTD9__SDHC0_D1 0x843
ULP1_PAD_PTD10__SDHC0_D0 0x843
>;
};
pinctrl_lpi2c7: lpi2c7grp {
fsl,pins = <
ULP1_PAD_PTF12__LPI2C7_SCL 0x527
ULP1_PAD_PTF13__LPI2C7_SDA 0x527
>;
};
pinctrl_lpspi3: lpspi3grp {
fsl,pins = <
ULP1_PAD_PTF16__LPSPI3_SIN 0x300
ULP1_PAD_PTF17__LPSPI3_SOUT 0x300
ULP1_PAD_PTF18__LPSPI3_SCK 0x300
ULP1_PAD_PTF19__LPSPI3_PCS0 0x300
>;
};
pinctrl_usb_otg1: usbotg1grp {
fsl,pins = <
ULP1_PAD_PTC0__PTC0 0x30100
>;
};
pinctrl_extcon_usb1: extcon1grp {
fsl,pins = <
ULP1_PAD_PTC8__PTC8 0x30103
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
ULP1_PAD_PTE3__SDHC1_CMD 0x843
ULP1_PAD_PTE2__SDHC1_CLK 0x843
ULP1_PAD_PTE1__SDHC1_D0 0x843
ULP1_PAD_PTE0__SDHC1_D1 0x843
ULP1_PAD_PTE5__SDHC1_D2 0x843
ULP1_PAD_PTE4__SDHC1_D3 0x843
>;
};
pinctrl_usdhc1_rst: usdhc1grp_rst {
fsl,pins = <
ULP1_PAD_PTE11__PTE11 0x30100 /* USDHC1 RST */
>;
};
pinctrl_wifi: wifigrp {
fsl,pins = <
ULP1_PAD_PTE6__PTE6 0x43 /* WL_REG_ON */
>;
};
};
};
&lcdif {
status = "okay";
disp-dev = "mipi_dsi_northwest";
display = <&display0>;
display0: display {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <9200000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <8>;
hback-porch = <4>;
hsync-len = <41>;
vback-porch = <2>;
vfront-porch = <4>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&lpi2c7 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c7>;
};
&lpi2c5 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c5>;
status = "okay";
fxas2100x@20 {
compatible = "fsl,fxas2100x";
reg = <0x20>;
};
fxos8700@1e {
compatible = "fsl,fxos8700";
reg = <0x1e>;
};
mpl3115@60 {
compatible = "fsl,mpl3115";
reg = <0x60>;
};
};
&lpspi3 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi3>;
status = "okay";
spidev0: spi@0 {
reg = <0>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <1000000>;
};
};
&mipi_dsi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mipi_dsi_reset>;
lcd_panel = "TRULY-WVGA-TFT3P5581E";
resets = <&mipi_dsi_reset>;
status = "okay";
};
&lpuart4 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart4>;
status = "okay";
};
&lpuart6 { /* BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart6>;
status = "okay";
};
&lpuart7 { /* Uart test */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart7>;
status = "disabled";
};
&rpmsg{
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
extcon = <0>, <&extcon_usb1>;
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
&usdhc0 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;
pinctrl-1 = <&pinctrl_usdhc0>;
pinctrl-2 = <&pinctrl_usdhc0>;
pinctrl-3 = <&pinctrl_usdhc0>;
cd-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_vsd_3v3>;
vqmmc-supply = <&vldo2_reg>;
status = "okay";
};

882
arch/arm/dts/imx7ulp-pinfunc.h Normal file
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@ -0,0 +1,882 @@
/*
* Copyright 2014 - 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_ULP1_PINFUNC_H
#define __DTS_ULP1_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_conf_reg mux2_reg mux_mode mux2_val>
*
* !!! IMPORTANT NOTE !!!
*
* There's common mux_reg & conf_reg register for each pad on ULP1 device, so the first
* two values are defined as same value. Extra non-zero mux2_reg value within the tuple
* means that there's additional mux2 control register that must be configured to
* mux2_val accordingly to fetch desired pin functionality on ULP1 device.
*
*/
#define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A 0x0000 0x0000 0x0 0x0
#define ULP1_PAD_PTA0_LLWU0_P0__PTA0 0x0000 0x0000 0x1 0x0
#define ULP1_PAD_PTA0_LLWU0_P0__LLWU0_P0 0x0000 0x0000 0xd 0x0
#define ULP1_PAD_PTA0_LLWU0_P0__LPSPI0_PCS1 0x0000 0xd104 0x3 0x2
#define ULP1_PAD_PTA0_LLWU0_P0__LPUART0_CTS_B 0x0000 0xd1f8 0x4 0x2
#define ULP1_PAD_PTA0_LLWU0_P0__LPI2C0_SCL 0x0000 0xd17c 0x5 0x2
#define ULP1_PAD_PTA0_LLWU0_P0__TPM0_CLKIN 0x0000 0xd1a8 0x6 0x2
#define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0x01b8 0x7 0x2
#define ULP1_PAD_PTA1__CMP0_IN2B 0x0004 0x0000 0x0 0x0
#define ULP1_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0
#define ULP1_PAD_PTA1__LPSPI0_PCS2 0x0004 0xd108 0x3 0x1
#define ULP1_PAD_PTA1__LPUART0_RTS_B 0x0004 0x0000 0x4 0x0
#define ULP1_PAD_PTA1__LPI2C0_SDA 0x0004 0xd180 0x5 0x1
#define ULP1_PAD_PTA1__TPM0_CH0 0x0004 0xd138 0x6 0x1
#define ULP1_PAD_PTA1__I2S0_RX_FS 0x0004 0x01bc 0x7 0x1
#define ULP1_PAD_PTA2__CMP1_IN2A 0x0008 0x0000 0x0 0x0
#define ULP1_PAD_PTA2__PTA2 0x0008 0x0000 0x1 0x0
#define ULP1_PAD_PTA2__LPSPI0_PCS3 0x0008 0xd10c 0x3 0x1
#define ULP1_PAD_PTA2__LPUART0_TX 0x0008 0xd200 0x4 0x1
#define ULP1_PAD_PTA2__LPI2C0_HREQ 0x0008 0xd178 0x5 0x1
#define ULP1_PAD_PTA2__TPM0_CH1 0x0008 0xd13c 0x6 0x1
#define ULP1_PAD_PTA2__I2S0_RXD0 0x0008 0x01dc 0x7 0x1
#define ULP1_PAD_PTA3_LLWU0_P1__CMP1_IN2B 0x000c 0x0000 0x0 0x0
#define ULP1_PAD_PTA3_LLWU0_P1__PTA3 0x000c 0x0000 0x1 0x0
#define ULP1_PAD_PTA3_LLWU0_P1__CMP0_OUT 0x000c 0x0000 0xb 0x0
#define ULP1_PAD_PTA3_LLWU0_P1__LLWU0_P1 0x000c 0x0000 0xd 0x0
#define ULP1_PAD_PTA3_LLWU0_P1__LPUART0_RX 0x000c 0xd1fc 0x4 0x1
#define ULP1_PAD_PTA3_LLWU0_P1__TPM0_CH2 0x000c 0xd140 0x6 0x1
#define ULP1_PAD_PTA3_LLWU0_P1__I2S0_RXD1 0x000c 0x01e0 0x7 0x1
#define ULP1_PAD_PTA4__ADC1_CH2A 0x0010 0x0000 0x0 0x0
#define ULP1_PAD_PTA4__PTA4 0x0010 0x0000 0x1 0x0
#define ULP1_PAD_PTA4__LPSPI0_SIN 0x0010 0xd114 0x3 0x1
#define ULP1_PAD_PTA4__LPUART1_CTS_B 0x0010 0xd204 0x4 0x1
#define ULP1_PAD_PTA4__LPI2C1_SCL 0x0010 0xd188 0x5 0x1
#define ULP1_PAD_PTA4__TPM0_CH3 0x0010 0xd144 0x6 0x1
#define ULP1_PAD_PTA4__I2S0_MCLK 0x0010 0x01b4 0x7 0x1
#define ULP1_PAD_PTA5__ADC1_CH2B 0x0014 0x0000 0x0 0x0
#define ULP1_PAD_PTA5__PTA5 0x0014 0x0000 0x1 0x0
#define ULP1_PAD_PTA5__LPSPI0_SOUT 0x0014 0xd118 0x3 0x1
#define ULP1_PAD_PTA5__LPUART1_RTS_B 0x0014 0x0000 0x4 0x0
#define ULP1_PAD_PTA5__LPI2C1_SDA 0x0014 0xd18c 0x5 0x1
#define ULP1_PAD_PTA5__TPM0_CH4 0x0014 0xd148 0x6 0x1
#define ULP1_PAD_PTA5__I2S0_TX_BCLK 0x0014 0x01c0 0x7 0x1
#define ULP1_PAD_PTA6__ADC1_CH3A 0x0018 0x0000 0x0 0x0
#define ULP1_PAD_PTA6__PTA6 0x0018 0x0000 0x1 0x0
#define ULP1_PAD_PTA6__LPSPI0_SCK 0x0018 0xd110 0x3 0x1
#define ULP1_PAD_PTA6__LPUART1_TX 0x0018 0xd20c 0x4 0x1
#define ULP1_PAD_PTA6__LPI2C1_HREQ 0x0018 0xd184 0x5 0x1
#define ULP1_PAD_PTA6__TPM0_CH5 0x0018 0xd14c 0x6 0x1
#define ULP1_PAD_PTA6__I2S0_TX_FS 0x0018 0x01c4 0x7 0x1
#define ULP1_PAD_PTA7__ADC1_CH3B 0x001c 0x0000 0x0 0x0
#define ULP1_PAD_PTA7__PTA7 0x001c 0x0000 0x1 0x0
#define ULP1_PAD_PTA7__LPSPI0_PCS0 0x001c 0xd100 0x3 0x1
#define ULP1_PAD_PTA7__LPUART1_RX 0x001c 0xd208 0x4 0x1
#define ULP1_PAD_PTA7__TPM1_CH1 0x001c 0xd154 0x6 0x1
#define ULP1_PAD_PTA7__I2S0_TXD0 0x001c 0x0000 0x7 0x0
#define ULP1_PAD_PTA8__ADC1_CH7A 0x0020 0x0000 0x0 0x0
#define ULP1_PAD_PTA8__PTA8 0x0020 0x0000 0x1 0x0
#define ULP1_PAD_PTA8__LPSPI1_PCS1 0x0020 0xd120 0x3 0x1
#define ULP1_PAD_PTA8__LPUART2_CTS_B 0x0020 0xd210 0x4 0x1
#define ULP1_PAD_PTA8__LPI2C2_SCL 0x0020 0xd194 0x5 0x1
#define ULP1_PAD_PTA8__TPM1_CLKIN 0x0020 0xd1ac 0x6 0x1
#define ULP1_PAD_PTA8__I2S0_TXD1 0x0020 0x0000 0x7 0x0
#define ULP1_PAD_PTA9__ADC1_CH7B 0x0024 0x0000 0x0 0x0
#define ULP1_PAD_PTA9__PTA9 0x0024 0x0000 0x1 0x0
#define ULP1_PAD_PTA9__NMI0_B 0x0024 0x0000 0xb 0x0
#define ULP1_PAD_PTA9__LPSPI1_PCS2 0x0024 0xd124 0x3 0x1
#define ULP1_PAD_PTA9__LPUART2_RTS_B 0x0024 0x0000 0x4 0x0
#define ULP1_PAD_PTA9__LPI2C2_SDA 0x0024 0xd198 0x5 0x1
#define ULP1_PAD_PTA9__TPM1_CH0 0x0024 0xd150 0x6 0x1
#define ULP1_PAD_PTA10__ADC1_CH6A 0x0028 0x0000 0x0 0x0
#define ULP1_PAD_PTA10__PTA10 0x0028 0x0000 0x1 0x0
#define ULP1_PAD_PTA10__LPSPI1_PCS3 0x0028 0xd128 0x3 0x1
#define ULP1_PAD_PTA10__LPUART2_TX 0x0028 0xd218 0x4 0x1
#define ULP1_PAD_PTA10__LPI2C2_HREQ 0x0028 0xd190 0x5 0x1
#define ULP1_PAD_PTA10__TPM2_CLKIN 0x0028 0xd1f4 0x6 0x1
#define ULP1_PAD_PTA10__I2S0_RX_BCLK 0x0028 0x01b8 0x7 0x1
#define ULP1_PAD_PTA11__ADC1_CH6B 0x002c 0x0000 0x0 0x0
#define ULP1_PAD_PTA11__PTA11 0x002c 0x0000 0x1 0x0
#define ULP1_PAD_PTA11__LPUART2_RX 0x002c 0xd214 0x4 0x1
#define ULP1_PAD_PTA11__TPM2_CH0 0x002c 0xd158 0x6 0x1
#define ULP1_PAD_PTA11__I2S0_RX_FS 0x002c 0x01bc 0x7 0x2
#define ULP1_PAD_PTA12__ADC1_CH5A 0x0030 0x0000 0x0 0x0
#define ULP1_PAD_PTA12__PTA12 0x0030 0x0000 0x1 0x0
#define ULP1_PAD_PTA12__LPSPI1_SIN 0x0030 0xd130 0x3 0x1
#define ULP1_PAD_PTA12__LPUART3_CTS_B 0x0030 0xd21c 0x4 0x1
#define ULP1_PAD_PTA12__LPI2C3_SCL 0x0030 0xd1a0 0x5 0x1
#define ULP1_PAD_PTA12__TPM2_CH1 0x0030 0xd15c 0x6 0x1
#define ULP1_PAD_PTA12__I2S0_RXD0 0x0030 0x01dc 0x7 0x2
#define ULP1_PAD_PTA13_LLWU0_P2__ADC1_CH5B 0x0034 0x0000 0x0 0x0
#define ULP1_PAD_PTA13_LLWU0_P2__PTA13 0x0034 0x0000 0x1 0x0
#define ULP1_PAD_PTA13_LLWU0_P2__CMP0_OUT 0x0034 0x0000 0xb 0x0
#define ULP1_PAD_PTA13_LLWU0_P2__LLWU0_P2 0x0034 0x0000 0xd 0x0
#define ULP1_PAD_PTA13_LLWU0_P2__LPSPI1_SOUT 0x0034 0xd134 0x3 0x2
#define ULP1_PAD_PTA13_LLWU0_P2__LPUART3_RTS_B 0x0034 0x0000 0x4 0x0
#define ULP1_PAD_PTA13_LLWU0_P2__LPI2C3_SDA 0x0034 0xd1a4 0x5 0x2
#define ULP1_PAD_PTA13_LLWU0_P2__TPM3_CLKIN 0x0034 0xd1b0 0x6 0x1
#define ULP1_PAD_PTA13_LLWU0_P2__I2S0_RXD1 0x0034 0x01e0 0x7 0x2
#define ULP1_PAD_PTA14_LLWU0_P3__ADC1_CH4A 0x0038 0x0000 0x0 0x0
#define ULP1_PAD_PTA14_LLWU0_P3__PTA14 0x0038 0x0000 0x1 0x0
#define ULP1_PAD_PTA14_LLWU0_P3__LLWU0_P3 0x0038 0x0000 0xd 0x0
#define ULP1_PAD_PTA14_LLWU0_P3__LPSPI1_SCK 0x0038 0xd12c 0x3 0x2
#define ULP1_PAD_PTA14_LLWU0_P3__LPUART3_TX 0x0038 0xd224 0x4 0x2
#define ULP1_PAD_PTA14_LLWU0_P3__LPI2C3_HREQ 0x0038 0xd19c 0x5 0x2
#define ULP1_PAD_PTA14_LLWU0_P3__TPM3_CH0 0x0038 0xd160 0x6 0x1
#define ULP1_PAD_PTA14_LLWU0_P3__I2S0_MCLK 0x0038 0x01b4 0x7 0x2
#define ULP1_PAD_PTA15__ADC1_CH4B 0x003c 0x0000 0x0 0x0
#define ULP1_PAD_PTA15__PTA15 0x003c 0x0000 0x1 0x0
#define ULP1_PAD_PTA15__LPSPI1_PCS0 0x003c 0xd11c 0x3 0x1
#define ULP1_PAD_PTA15__LPUART3_RX 0x003c 0xd220 0x4 0x1
#define ULP1_PAD_PTA15__TPM3_CH1 0x003c 0xd164 0x6 0x1
#define ULP1_PAD_PTA15__I2S0_TX_BCLK 0x003c 0x01c0 0x7 0x2
#define ULP1_PAD_PTA16__CMP1_IN0A 0x0040 0x0000 0x0 0x0
#define ULP1_PAD_PTA16__PTA16 0x0040 0x0000 0x1 0x0
#define ULP1_PAD_PTA16__FXIO0_D0 0x0040 0x0000 0x2 0x0
#define ULP1_PAD_PTA16__LPSPI0_PCS1 0x0040 0xd104 0x3 0x1
#define ULP1_PAD_PTA16__LPUART0_CTS_B 0x0040 0xd1f8 0x4 0x1
#define ULP1_PAD_PTA16__LPI2C0_SCL 0x0040 0xd17c 0x5 0x1
#define ULP1_PAD_PTA16__TPM3_CH2 0x0040 0xd168 0x6 0x1
#define ULP1_PAD_PTA16__I2S0_TX_FS 0x0040 0x01c4 0x7 0x2
#define ULP1_PAD_PTA17__CMP1_IN0B 0x0044 0x0000 0x0 0x0
#define ULP1_PAD_PTA17__PTA17 0x0044 0x0000 0x1 0x0
#define ULP1_PAD_PTA17__FXIO0_D1 0x0044 0x0000 0x2 0x0
#define ULP1_PAD_PTA17__LPSPI0_PCS2 0x0044 0xd108 0x3 0x2
#define ULP1_PAD_PTA17__LPUART0_RTS_B 0x0044 0x0000 0x4 0x0
#define ULP1_PAD_PTA17__LPI2C0_SDA 0x0044 0xd180 0x5 0x2
#define ULP1_PAD_PTA17__TPM3_CH3 0x0044 0xd16c 0x6 0x1
#define ULP1_PAD_PTA17__I2S0_TXD0 0x0044 0x0000 0x7 0x0
#define ULP1_PAD_PTA18_LLWU0_P4__CMP1_IN1A 0x0048 0x0000 0x0 0x0
#define ULP1_PAD_PTA18_LLWU0_P4__PTA18 0x0048 0x0000 0x1 0x0
#define ULP1_PAD_PTA18_LLWU0_P4__NMI1_B 0x0048 0x0000 0xb 0x0
#define ULP1_PAD_PTA18_LLWU0_P4__LLWU0_P4 0x0048 0x0000 0xd 0x0
#define ULP1_PAD_PTA18_LLWU0_P4__FXIO0_D2 0x0048 0x0000 0x2 0x0
#define ULP1_PAD_PTA18_LLWU0_P4__LPSPI0_PCS3 0x0048 0xd10c 0x3 0x2
#define ULP1_PAD_PTA18_LLWU0_P4__LPUART0_TX 0x0048 0xd200 0x4 0x2
#define ULP1_PAD_PTA18_LLWU0_P4__LPI2C0_HREQ 0x0048 0xd178 0x5 0x2
#define ULP1_PAD_PTA18_LLWU0_P4__TPM3_CH4 0x0048 0xd170 0x6 0x1
#define ULP1_PAD_PTA18_LLWU0_P4__I2S0_TXD1 0x0048 0x0000 0x7 0x0
#define ULP1_PAD_PTA19_LLWU0_P5__CMP1_IN1B 0x004c 0x0000 0x0 0x0
#define ULP1_PAD_PTA19_LLWU0_P5__PTA19 0x004c 0x0000 0x1 0x0
#define ULP1_PAD_PTA19_LLWU0_P5__LPTMR0_ALT3 0x004c 0x0000 0xb 0x0
#define ULP1_PAD_PTA19_LLWU0_P5__LLWU0_P5 0x004c 0x0000 0xd 0x0
#define ULP1_PAD_PTA19_LLWU0_P5__FXIO0_D3 0x004c 0x0000 0x2 0x0
#define ULP1_PAD_PTA19_LLWU0_P5__LPUART0_RX 0x004c 0xd1fc 0x4 0x2
#define ULP1_PAD_PTA19_LLWU0_P5__TPM3_CH5 0x004c 0xd174 0x6 0x1
#define ULP1_PAD_PTA19_LLWU0_P5__I2S1_RX_BCLK 0x004c 0xd1cc 0x7 0x1
#define ULP1_PAD_PTA20__ADC0_CH7A 0x0050 0x0000 0x0 0x0
#define ULP1_PAD_PTA20__PTA20 0x0050 0x0000 0x1 0x0
#define ULP1_PAD_PTA20__FXIO0_D4 0x0050 0x0000 0x2 0x0
#define ULP1_PAD_PTA20__LPSPI0_SIN 0x0050 0xd114 0x3 0x2
#define ULP1_PAD_PTA20__LPUART1_CTS_B 0x0050 0xd204 0x4 0x2
#define ULP1_PAD_PTA20__LPI2C1_SCL 0x0050 0xd188 0x5 0x2
#define ULP1_PAD_PTA20__TPM0_CLKIN 0x0050 0xd1a8 0x6 0x1
#define ULP1_PAD_PTA20__I2S1_RX_FS 0x0050 0xd1d0 0x7 0x1
#define ULP1_PAD_PTA21__ADC0_CH7B 0x0054 0x0000 0x0 0x0
#define ULP1_PAD_PTA21__PTA21 0x0054 0x0000 0x1 0x0
#define ULP1_PAD_PTA21__FXIO0_D5 0x0054 0x0000 0x2 0x0
#define ULP1_PAD_PTA21__LPSPI0_SOUT 0x0054 0xd118 0x3 0x2
#define ULP1_PAD_PTA21__LPUART1_RTS_B 0x0054 0x0000 0x4 0x0
#define ULP1_PAD_PTA21__LPI2C1_SDA 0x0054 0xd18c 0x5 0x2
#define ULP1_PAD_PTA21__TPM0_CH0 0x0054 0xd138 0x6 0x2
#define ULP1_PAD_PTA21__I2S1_RXD0 0x0054 0xd1e4 0x7 0x1
#define ULP1_PAD_PTA22__ADC0_CH6A 0x0058 0x0000 0x0 0x0
#define ULP1_PAD_PTA22__PTA22 0x0058 0x0000 0x1 0x0
#define ULP1_PAD_PTA22__LPTMR0_ALT2 0x0058 0x0000 0xb 0x0
#define ULP1_PAD_PTA22__EWM_OUT_B 0x0058 0x0000 0xc 0x0
#define ULP1_PAD_PTA22__FXIO0_D6 0x0058 0x0000 0x2 0x0
#define ULP1_PAD_PTA22__LPSPI0_SCK 0x0058 0xd110 0x3 0x2
#define ULP1_PAD_PTA22__LPUART1_TX 0x0058 0xd20c 0x4 0x2
#define ULP1_PAD_PTA22__LPI2C1_HREQ 0x0058 0xd184 0x5 0x2
#define ULP1_PAD_PTA22__TPM0_CH1 0x0058 0xd13c 0x6 0x2
#define ULP1_PAD_PTA22__I2S1_RXD1 0x0058 0xd1e8 0x7 0x1
#define ULP1_PAD_PTA23_LLWU0_P6__ADC0_CH6B 0x005c 0x0000 0x0 0x0
#define ULP1_PAD_PTA23_LLWU0_P6__PTA23 0x005c 0x0000 0x1 0x0
#define ULP1_PAD_PTA23_LLWU0_P6__LLWU0_P6 0x005c 0x0000 0xd 0x0
#define ULP1_PAD_PTA23_LLWU0_P6__FXIO0_D7 0x005c 0x0000 0x2 0x0
#define ULP1_PAD_PTA23_LLWU0_P6__LPSPI0_PCS0 0x005c 0xd100 0x3 0x2
#define ULP1_PAD_PTA23_LLWU0_P6__LPUART1_RX 0x005c 0xd208 0x4 0x2
#define ULP1_PAD_PTA23_LLWU0_P6__TPM0_CH2 0x005c 0xd140 0x6 0x2
#define ULP1_PAD_PTA23_LLWU0_P6__I2S1_MCLK 0x005c 0xd1c8 0x7 0x1
#define ULP1_PAD_PTA24__ADC0_CH5A 0x0060 0x0000 0x0 0x0
#define ULP1_PAD_PTA24__PTA24 0x0060 0x0000 0x1 0x0
#define ULP1_PAD_PTA24__FXIO0_D8 0x0060 0x0000 0x2 0x0
#define ULP1_PAD_PTA24__LPSPI1_PCS1 0x0060 0xd120 0x3 0x2
#define ULP1_PAD_PTA24__LPUART2_CTS_B 0x0060 0xd210 0x4 0x2
#define ULP1_PAD_PTA24__LPI2C2_SCL 0x0060 0xd194 0x5 0x2
#define ULP1_PAD_PTA24__TPM0_CH3 0x0060 0xd144 0x6 0x2
#define ULP1_PAD_PTA24__I2S1_TX_BCLK 0x0060 0xd1d4 0x7 0x1
#define ULP1_PAD_PTA25__ADC0_CH5B 0x0064 0x0000 0x0 0x0
#define ULP1_PAD_PTA25__PTA25 0x0064 0x0000 0x1 0x0
#define ULP1_PAD_PTA25__FXIO0_D9 0x0064 0x0000 0x2 0x0
#define ULP1_PAD_PTA25__LPSPI1_PCS2 0x0064 0xd124 0x3 0x2
#define ULP1_PAD_PTA25__LPUART2_RTS_B 0x0064 0x0000 0x4 0x0
#define ULP1_PAD_PTA25__LPI2C2_SDA 0x0064 0xd198 0x5 0x2
#define ULP1_PAD_PTA25__TPM0_CH4 0x0064 0xd148 0x6 0x2
#define ULP1_PAD_PTA25__I2S1_TX_FS 0x0064 0xd1d8 0x7 0x1
#define ULP1_PAD_PTA26__PTA26 0x0068 0x0000 0x1 0x0
#define ULP1_PAD_PTA26__JTAG_TMS_SWD_DIO 0x0068 0x0000 0xa 0x0
#define ULP1_PAD_PTA26__FXIO0_D10 0x0068 0x0000 0x2 0x0
#define ULP1_PAD_PTA26__LPSPI1_PCS3 0x0068 0xd128 0x3 0x2
#define ULP1_PAD_PTA26__LPUART2_TX 0x0068 0xd218 0x4 0x2
#define ULP1_PAD_PTA26__LPI2C2_HREQ 0x0068 0xd190 0x5 0x2
#define ULP1_PAD_PTA26__TPM0_CH5 0x0068 0xd14c 0x6 0x2
#define ULP1_PAD_PTA26__I2S1_RXD2 0x0068 0xd1ec 0x7 0x1
#define ULP1_PAD_PTA27__PTA27 0x006c 0x0000 0x1 0x0
#define ULP1_PAD_PTA27__JTAG_TDO 0x006c 0x0000 0xa 0x0
#define ULP1_PAD_PTA27__FXIO0_D11 0x006c 0x0000 0x2 0x0
#define ULP1_PAD_PTA27__LPUART2_RX 0x006c 0xd214 0x4 0x2
#define ULP1_PAD_PTA27__TPM1_CH1 0x006c 0xd154 0x6 0x2
#define ULP1_PAD_PTA27__I2S1_RXD3 0x006c 0xd1f0 0x7 0x1
#define ULP1_PAD_PTA28__PTA28 0x0070 0x0000 0x1 0x0
#define ULP1_PAD_PTA28__JTAG_TDI 0x0070 0x0000 0xa 0x0
#define ULP1_PAD_PTA28__FXIO0_D12 0x0070 0x0000 0x2 0x0
#define ULP1_PAD_PTA28__LPSPI1_SIN 0x0070 0xd130 0x3 0x2
#define ULP1_PAD_PTA28__LPUART3_CTS_B 0x0070 0xd21c 0x4 0x2
#define ULP1_PAD_PTA28__LPI2C3_SCL 0x0070 0xd1a0 0x5 0x2
#define ULP1_PAD_PTA28__TPM1_CLKIN 0x0070 0xd1ac 0x6 0x2
#define ULP1_PAD_PTA28__I2S1_TXD2 0x0070 0x0000 0x7 0x0
#define ULP1_PAD_PTA29__PTA29 0x0074 0x0000 0x1 0x0
#define ULP1_PAD_PTA29__JTAG_TCLK_SWD_CLK 0x0074 0x0000 0xa 0x0
#define ULP1_PAD_PTA29__FXIO0_D13 0x0074 0x0000 0x2 0x0
#define ULP1_PAD_PTA29__LPSPI1_SOUT 0x0074 0xd134 0x3 0x1
#define ULP1_PAD_PTA29__LPUART3_RTS_B 0x0074 0x0000 0x4 0x0
#define ULP1_PAD_PTA29__LPI2C3_SDA 0x0074 0xd1a4 0x5 0x1
#define ULP1_PAD_PTA29__TPM1_CH0 0x0074 0xd150 0x6 0x2
#define ULP1_PAD_PTA29__I2S1_TXD3 0x0074 0x0000 0x7 0x0
#define ULP1_PAD_PTA30__ADC0_CH4A 0x0078 0x0000 0x0 0x0
#define ULP1_PAD_PTA30__PTA30 0x0078 0x0000 0x1 0x0
#define ULP1_PAD_PTA30__JTAG_TRST_B 0x0078 0x0000 0xa 0x0
#define ULP1_PAD_PTA30__FXIO0_D14 0x0078 0x0000 0x2 0x0
#define ULP1_PAD_PTA30__LPSPI1_SCK 0x0078 0xd12c 0x3 0x1
#define ULP1_PAD_PTA30__LPUART3_TX 0x0078 0xd224 0x4 0x1
#define ULP1_PAD_PTA30__LPI2C3_HREQ 0x0078 0xd19c 0x5 0x1
#define ULP1_PAD_PTA30__TPM2_CLKIN 0x0078 0xd1f4 0x6 0x2
#define ULP1_PAD_PTA30__I2S1_TXD0 0x0078 0x0000 0x7 0x0
#define ULP1_PAD_PTA31_LLWU0_P7__ADC0_CH4B 0x007c 0x0000 0x0 0x0
#define ULP1_PAD_PTA31_LLWU0_P7__PTA31 0x007c 0x0000 0x1 0x0
#define ULP1_PAD_PTA31_LLWU0_P7__LPTMR0_ALT1 0x007c 0x0000 0xb 0x0
#define ULP1_PAD_PTA31_LLWU0_P7__EWM_IN 0x007c 0xd228 0xc 0x1
#define ULP1_PAD_PTA31_LLWU0_P7__LLWU0_P7 0x007c 0x0000 0xd 0x0
#define ULP1_PAD_PTA31_LLWU0_P7__FXIO0_D15 0x007c 0x0000 0x2 0x0
#define ULP1_PAD_PTA31_LLWU0_P7__LPSPI1_PCS0 0x007c 0xd11c 0x3 0x2
#define ULP1_PAD_PTA31_LLWU0_P7__LPUART3_RX 0x007c 0xd220 0x4 0x2
#define ULP1_PAD_PTA31_LLWU0_P7__TPM2_CH0 0x007c 0xd158 0x6 0x2
#define ULP1_PAD_PTA31_LLWU0_P7__I2S1_TXD1 0x007c 0x0000 0x7 0x0
#define ULP1_PAD_PTB0__ADC0_CH0A 0x0080 0x0000 0x0 0x0
#define ULP1_PAD_PTB0__PTB0 0x0080 0x0000 0x1 0x0
#define ULP1_PAD_PTB0__CMP1_OUT 0x0080 0x0000 0xb 0x0
#define ULP1_PAD_PTB0__EWM_OUT_B 0x0080 0x0000 0xc 0x0
#define ULP1_PAD_PTB0__FXIO0_D16 0x0080 0x0000 0x2 0x0
#define ULP1_PAD_PTB0__LPSPI0_SIN 0x0080 0xd114 0x3 0x3
#define ULP1_PAD_PTB0__LPUART0_TX 0x0080 0xd200 0x4 0x3
#define ULP1_PAD_PTB0__TPM2_CH1 0x0080 0xd15c 0x6 0x2
#define ULP1_PAD_PTB0__CLKOUT 0x0080 0x0000 0x9 0x0
#define ULP1_PAD_PTB1_LLWU0_P8__ADC0_CH0B 0x0084 0x0000 0x0 0x0
#define ULP1_PAD_PTB1_LLWU0_P8__PTB1 0x0084 0x0000 0x1 0x0
#define ULP1_PAD_PTB1_LLWU0_P8__RTC_CLKOUT 0x0084 0x0000 0xb 0x0
#define ULP1_PAD_PTB1_LLWU0_P8__EWM_IN 0x0084 0xd228 0xc 0x2
#define ULP1_PAD_PTB1_LLWU0_P8__LLWU0_P8 0x0084 0x0000 0xd 0x0
#define ULP1_PAD_PTB1_LLWU0_P8__FXIO0_D17 0x0084 0x0000 0x2 0x0
#define ULP1_PAD_PTB1_LLWU0_P8__LPSPI0_SOUT 0x0084 0xd118 0x3 0x3
#define ULP1_PAD_PTB1_LLWU0_P8__LPUART0_RX 0x0084 0xd1fc 0x4 0x3
#define ULP1_PAD_PTB1_LLWU0_P8__TPM3_CLKIN 0x0084 0xd1b0 0x6 0x3
#define ULP1_PAD_PTB1_LLWU0_P8__I2S1_TX_BCLK 0x0084 0xd1d4 0x7 0x2
#define ULP1_PAD_PTB2__ADC0_CH1A 0x0088 0x0000 0x0 0x0
#define ULP1_PAD_PTB2__PTB2 0x0088 0x0000 0x1 0x0
#define ULP1_PAD_PTB2__TRACE_CLKOUT 0x0088 0x0000 0xa 0x0
#define ULP1_PAD_PTB2__FXIO0_D18 0x0088 0x0000 0x2 0x0
#define ULP1_PAD_PTB2__LPSPI0_SCK 0x0088 0xd110 0x3 0x3
#define ULP1_PAD_PTB2__LPUART1_TX 0x0088 0xd20c 0x4 0x3
#define ULP1_PAD_PTB2__TPM3_CH0 0x0088 0xd160 0x6 0x2
#define ULP1_PAD_PTB2__I2S1_TX_FS 0x0088 0xd1d8 0x7 0x2
#define ULP1_PAD_PTB3_LLWU0_P9__ADC0_CH1B 0x008c 0x0000 0x0 0x0
#define ULP1_PAD_PTB3_LLWU0_P9__PTB3 0x008c 0x0000 0x1 0x0
#define ULP1_PAD_PTB3_LLWU0_P9__TRACE_D0 0x008c 0x0000 0xa 0x0
#define ULP1_PAD_PTB3_LLWU0_P9__LPTMR1_ALT2 0x008c 0x0000 0xb 0x0
#define ULP1_PAD_PTB3_LLWU0_P9__LLWU0_P9 0x008c 0x0000 0xd 0x0
#define ULP1_PAD_PTB3_LLWU0_P9__FXIO0_D19 0x008c 0x0000 0x2 0x0
#define ULP1_PAD_PTB3_LLWU0_P9__LPSPI0_PCS0 0x008c 0xd100 0x3 0x3
#define ULP1_PAD_PTB3_LLWU0_P9__LPUART1_RX 0x008c 0xd208 0x4 0x3
#define ULP1_PAD_PTB3_LLWU0_P9__TPM3_CH1 0x008c 0xd164 0x6 0x2
#define ULP1_PAD_PTB3_LLWU0_P9__I2S1_TXD0 0x008c 0x0000 0x7 0x0
#define ULP1_PAD_PTB4__PTB4 0x0090 0x0000 0x1 0x0
#define ULP1_PAD_PTB4__TRACE_D1 0x0090 0x0000 0xa 0x0
#define ULP1_PAD_PTB4__BOOTCFG0 0x0090 0x0000 0xd 0x0
#define ULP1_PAD_PTB4__FXIO0_D20 0x0090 0x0000 0x2 0x0
#define ULP1_PAD_PTB4__LPSPI0_PCS1 0x0090 0xd104 0x3 0x3
#define ULP1_PAD_PTB4__LPUART2_TX 0x0090 0xd218 0x4 0x3
#define ULP1_PAD_PTB4__LPI2C0_HREQ 0x0090 0xd178 0x5 0x3
#define ULP1_PAD_PTB4__TPM3_CH2 0x0090 0xd168 0x6 0x2
#define ULP1_PAD_PTB4__I2S1_TXD1 0x0090 0x0000 0x7 0x0
#define ULP1_PAD_PTB5__PTB5 0x0094 0x0000 0x1 0x0
#define ULP1_PAD_PTB5__TRACE_D2 0x0094 0x0000 0xa 0x0
#define ULP1_PAD_PTB5__BOOTCFG1 0x0094 0x0000 0xd 0x0
#define ULP1_PAD_PTB5__FXIO0_D21 0x0094 0x0000 0x2 0x0
#define ULP1_PAD_PTB5__LPSPI0_PCS2 0x0094 0xd108 0x3 0x3
#define ULP1_PAD_PTB5__LPUART2_RX 0x0094 0xd214 0x4 0x3
#define ULP1_PAD_PTB5__LPI2C1_HREQ 0x0094 0xd184 0x5 0x3
#define ULP1_PAD_PTB5__TPM3_CH3 0x0094 0xd16c 0x6 0x2
#define ULP1_PAD_PTB5__I2S1_TXD2 0x0094 0x0000 0x7 0x0
#define ULP1_PAD_PTB6_LLWU0_P10__PTB6 0x0098 0x0000 0x1 0x0
#define ULP1_PAD_PTB6_LLWU0_P10__TRACE_D3 0x0098 0x0000 0xa 0x0
#define ULP1_PAD_PTB6_LLWU0_P10__LPTMR1_ALT3 0x0098 0x0000 0xb 0x0
#define ULP1_PAD_PTB6_LLWU0_P10__LLWU0_P10 0x0098 0x0000 0xd 0x0
#define ULP1_PAD_PTB6_LLWU0_P10__FXIO0_D22 0x0098 0x0000 0x2 0x0
#define ULP1_PAD_PTB6_LLWU0_P10__LPSPI0_PCS3 0x0098 0xd10c 0x3 0x3
#define ULP1_PAD_PTB6_LLWU0_P10__LPUART3_TX 0x0098 0xd224 0x4 0x3
#define ULP1_PAD_PTB6_LLWU0_P10__LPI2C0_SCL 0x0098 0xd17c 0x5 0x3
#define ULP1_PAD_PTB6_LLWU0_P10__TPM3_CH4 0x0098 0xd170 0x6 0x2
#define ULP1_PAD_PTB6_LLWU0_P10__I2S1_TXD3 0x0098 0x0000 0x7 0x0
#define ULP1_PAD_PTB7_LLWU0_P11__PTB7 0x009c 0x0000 0x1 0x0
#define ULP1_PAD_PTB7_LLWU0_P11__CMP1_OUT 0x009c 0x0000 0xb 0x0
#define ULP1_PAD_PTB7_LLWU0_P11__LLWU0_P11 0x009c 0x0000 0xd 0x0
#define ULP1_PAD_PTB7_LLWU0_P11__FXIO0_D23 0x009c 0x0000 0x2 0x0
#define ULP1_PAD_PTB7_LLWU0_P11__LPSPI1_SIN 0x009c 0xd130 0x3 0x3
#define ULP1_PAD_PTB7_LLWU0_P11__LPUART3_RX 0x009c 0xd220 0x4 0x3
#define ULP1_PAD_PTB7_LLWU0_P11__LPI2C0_SDA 0x009c 0xd180 0x5 0x3
#define ULP1_PAD_PTB7_LLWU0_P11__TPM3_CH5 0x009c 0xd174 0x6 0x2
#define ULP1_PAD_PTB7_LLWU0_P11__I2S1_MCLK 0x009c 0xd1c8 0x7 0x2
#define ULP1_PAD_PTB7_LLWU0_P11__QSPIA_SS1_B 0x009c 0x0000 0x8 0x0
#define ULP1_PAD_PTB8__CMP0_IN0A 0x00a0 0x0000 0x0 0x0
#define ULP1_PAD_PTB8__PTB8 0x00a0 0x0000 0x1 0x0
#define ULP1_PAD_PTB8__RTC_CLKOUT 0x00a0 0x0000 0xb 0x0
#define ULP1_PAD_PTB8__FXIO0_D24 0x00a0 0x0000 0x2 0x0
#define ULP1_PAD_PTB8__LPSPI1_SOUT 0x00a0 0xd134 0x3 0x3
#define ULP1_PAD_PTB8__LPI2C1_SCL 0x00a0 0xd188 0x5 0x3
#define ULP1_PAD_PTB8__TPM0_CLKIN 0x00a0 0xd1a8 0x6 0x3
#define ULP1_PAD_PTB8__I2S1_RX_BCLK 0x00a0 0xd1cc 0x7 0x2
#define ULP1_PAD_PTB8__QSPIA_SS0_B 0x00a0 0x0000 0x8 0x0
#define ULP1_PAD_PTB9_LLWU0_P12__CMP0_IN0B 0x00a4 0x0000 0x0 0x0
#define ULP1_PAD_PTB9_LLWU0_P12__PTB9 0x00a4 0x0000 0x1 0x0
#define ULP1_PAD_PTB9_LLWU0_P12__LLWU0_P12 0x00a4 0x0000 0xd 0x0
#define ULP1_PAD_PTB9_LLWU0_P12__FXIO0_D25 0x00a4 0x0000 0x2 0x0
#define ULP1_PAD_PTB9_LLWU0_P12__LPSPI1_SCK 0x00a4 0xd12c 0x3 0x3
#define ULP1_PAD_PTB9_LLWU0_P12__LPI2C1_SDA 0x00a4 0xd18c 0x5 0x3
#define ULP1_PAD_PTB9_LLWU0_P12__TPM0_CH0 0x00a4 0xd138 0x6 0x3
#define ULP1_PAD_PTB9_LLWU0_P12__I2S1_RX_FS 0x00a4 0xd1d0 0x7 0x2
#define ULP1_PAD_PTB9_LLWU0_P12__QSPIA_DQS 0x00a4 0x0000 0x8 0x0
#define ULP1_PAD_PTB10__CMP0_IN1A 0x00a8 0x0000 0x0 0x0
#define ULP1_PAD_PTB10__PTB10 0x00a8 0x0000 0x1 0x0
#define ULP1_PAD_PTB10__TRACE_D4 0x00a8 0x0000 0xa 0x0
#define ULP1_PAD_PTB10__FXIO0_D26 0x00a8 0x0000 0x2 0x0
#define ULP1_PAD_PTB10__LPSPI1_PCS0 0x00a8 0xd11c 0x3 0x3
#define ULP1_PAD_PTB10__LPI2C2_SCL 0x00a8 0xd194 0x5 0x3
#define ULP1_PAD_PTB10__TPM0_CH1 0x00a8 0xd13c 0x6 0x3
#define ULP1_PAD_PTB10__I2S1_RXD0 0x00a8 0xd1e4 0x7 0x2
#define ULP1_PAD_PTB10__QSPIA_DATA7 0x00a8 0x0000 0x8 0x0
#define ULP1_PAD_PTB11__CMP0_IN1B 0x00ac 0x0000 0x0 0x0
#define ULP1_PAD_PTB11__PTB11 0x00ac 0x0000 0x1 0x0
#define ULP1_PAD_PTB11__TRACE_D5 0x00ac 0x0000 0xa 0x0
#define ULP1_PAD_PTB11__FXIO0_D27 0x00ac 0x0000 0x2 0x0
#define ULP1_PAD_PTB11__LPSPI1_PCS1 0x00ac 0xd120 0x3 0x3
#define ULP1_PAD_PTB11__LPI2C2_SDA 0x00ac 0xd198 0x5 0x3
#define ULP1_PAD_PTB11__TPM1_CLKIN 0x00ac 0xd1ac 0x6 0x3
#define ULP1_PAD_PTB11__I2S1_RXD1 0x00ac 0xd1e8 0x7 0x2
#define ULP1_PAD_PTB11__QSPIA_DATA6 0x00ac 0x0000 0x8 0x0
#define ULP1_PAD_PTB12__ADC1_CH0A 0x00b0 0x0000 0x0 0x0
#define ULP1_PAD_PTB12__PTB12 0x00b0 0x0000 0x1 0x0
#define ULP1_PAD_PTB12__TRACE_D6 0x00b0 0x0000 0xa 0x0
#define ULP1_PAD_PTB12__FXIO0_D28 0x00b0 0x0000 0x2 0x0
#define ULP1_PAD_PTB12__LPSPI1_PCS2 0x00b0 0xd124 0x3 0x3
#define ULP1_PAD_PTB12__LPI2C3_SCL 0x00b0 0xd1a0 0x5 0x3
#define ULP1_PAD_PTB12__TPM1_CH0 0x00b0 0xd150 0x6 0x3
#define ULP1_PAD_PTB12__I2S1_RXD2 0x00b0 0xd1ec 0x7 0x2
#define ULP1_PAD_PTB12__QSPIA_DATA5 0x00b0 0x0000 0x8 0x0
#define ULP1_PAD_PTB13__ADC1_CH0B 0x00b4 0x0000 0x0 0x0
#define ULP1_PAD_PTB13__PTB13 0x00b4 0x0000 0x1 0x0
#define ULP1_PAD_PTB13__TRACE_D7 0x00b4 0x0000 0xa 0x0
#define ULP1_PAD_PTB13__FXIO0_D29 0x00b4 0x0000 0x2 0x0
#define ULP1_PAD_PTB13__LPSPI1_PCS3 0x00b4 0xd128 0x3 0x3
#define ULP1_PAD_PTB13__LPI2C3_SDA 0x00b4 0xd1a4 0x5 0x3
#define ULP1_PAD_PTB13__TPM1_CH1 0x00b4 0xd154 0x6 0x3
#define ULP1_PAD_PTB13__I2S1_RXD3 0x00b4 0xd1f0 0x7 0x2
#define ULP1_PAD_PTB13__QSPIA_DATA4 0x00b4 0x0000 0x8 0x0
#define ULP1_PAD_PTB14_LLWU0_P13__ADC1_CH1A 0x00b8 0x0000 0x0 0x0
#define ULP1_PAD_PTB14_LLWU0_P13__PTB14 0x00b8 0x0000 0x1 0x0
#define ULP1_PAD_PTB14_LLWU0_P13__LLWU0_P13 0x00b8 0x0000 0xd 0x0
#define ULP1_PAD_PTB14_LLWU0_P13__FXIO0_D30 0x00b8 0x0000 0x2 0x0
#define ULP1_PAD_PTB14_LLWU0_P13__LPI2C2_HREQ 0x00b8 0xd190 0x5 0x3
#define ULP1_PAD_PTB14_LLWU0_P13__TPM2_CLKIN 0x00b8 0xd1f4 0x6 0x3
#define ULP1_PAD_PTB14_LLWU0_P13__QSPIA_SS0_B 0x00b8 0x0000 0x8 0x0
#define ULP1_PAD_PTB14_LLWU0_P13__QSPIA_SCLK_B 0x00b8 0x0000 0x9 0x0
#define ULP1_PAD_PTB15__ADC1_CH1B 0x00bc 0x0000 0x0 0x0
#define ULP1_PAD_PTB15__PTB15 0x00bc 0x0000 0x1 0x0
#define ULP1_PAD_PTB15__FXIO0_D31 0x00bc 0x0000 0x2 0x0
#define ULP1_PAD_PTB15__LPI2C3_HREQ 0x00bc 0xd19c 0x5 0x3
#define ULP1_PAD_PTB15__TPM2_CH0 0x00bc 0xd158 0x6 0x3
#define ULP1_PAD_PTB15__QSPIA_SCLK 0x00bc 0x0000 0x8 0x0
#define ULP1_PAD_PTB16_LLWU0_P14__ADC0_CH2A 0x00c0 0x0000 0x0 0x0
#define ULP1_PAD_PTB16_LLWU0_P14__PTB16 0x00c0 0x0000 0x1 0x0
#define ULP1_PAD_PTB16_LLWU0_P14__LLWU0_P14 0x00c0 0x0000 0xd 0x0
#define ULP1_PAD_PTB16_LLWU0_P14__TPM2_CH1 0x00c0 0xd15c 0x6 0x3
#define ULP1_PAD_PTB16_LLWU0_P14__QSPIA_DATA3 0x00c0 0x0000 0x8 0x0
#define ULP1_PAD_PTB17__ADC0_CH2B 0x00c4 0x0000 0x0 0x0
#define ULP1_PAD_PTB17__PTB17 0x00c4 0x0000 0x1 0x0
#define ULP1_PAD_PTB17__TPM3_CLKIN 0x00c4 0xd1b0 0x6 0x2
#define ULP1_PAD_PTB17__QSPIA_DATA2 0x00c4 0x0000 0x8 0x0
#define ULP1_PAD_PTB18__ADC0_CH3A 0x00c8 0x0000 0x0 0x0
#define ULP1_PAD_PTB18__PTB18 0x00c8 0x0000 0x1 0x0
#define ULP1_PAD_PTB18__TPM3_CH0 0x00c8 0xd160 0x6 0x3
#define ULP1_PAD_PTB18__QSPIA_DATA1 0x00c8 0x0000 0x8 0x0
#define ULP1_PAD_PTB19_LLWU0_P15__ADC0_CH3B 0x00cc 0x0000 0x0 0x0
#define ULP1_PAD_PTB19_LLWU0_P15__PTB19 0x00cc 0x0000 0x1 0x0
#define ULP1_PAD_PTB19_LLWU0_P15__USB0_ID 0x00cc 0x0000 0xa 0x0
#define ULP1_PAD_PTB19_LLWU0_P15__LLWU0_P15 0x00cc 0x0000 0xd 0x0
#define ULP1_PAD_PTB19_LLWU0_P15__TPM3_CH1 0x00cc 0xd164 0x6 0x3
#define ULP1_PAD_PTB19_LLWU0_P15__QSPIA_DATA0 0x00cc 0x0000 0x8 0x0
#define ULP1_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
#define ULP1_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
#define ULP1_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
#define ULP1_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
#define ULP1_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
#define ULP1_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
#define ULP1_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
#define ULP1_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
#define ULP1_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
#define ULP1_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
#define ULP1_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1
#define ULP1_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0
#define ULP1_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0
#define ULP1_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0
#define ULP1_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1
#define ULP1_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1
#define ULP1_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1
#define ULP1_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0
#define ULP1_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0
#define ULP1_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0
#define ULP1_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1
#define ULP1_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1
#define ULP1_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0
#define ULP1_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0
#define ULP1_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0
#define ULP1_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1
#define ULP1_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1
#define ULP1_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1
#define ULP1_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1
#define ULP1_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1
#define ULP1_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0
#define ULP1_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0
#define ULP1_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0
#define ULP1_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1
#define ULP1_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1
#define ULP1_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0
#define ULP1_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1
#define ULP1_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1
#define ULP1_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0
#define ULP1_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0
#define ULP1_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0
#define ULP1_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1
#define ULP1_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1
#define ULP1_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1
#define ULP1_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1
#define ULP1_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1
#define ULP1_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0
#define ULP1_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0
#define ULP1_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0
#define ULP1_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1
#define ULP1_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1
#define ULP1_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1
#define ULP1_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0
#define ULP1_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0
#define ULP1_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0
#define ULP1_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1
#define ULP1_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1
#define ULP1_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1
#define ULP1_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1
#define ULP1_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1
#define ULP1_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0
#define ULP1_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0
#define ULP1_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0
#define ULP1_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1
#define ULP1_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1
#define ULP1_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0
#define ULP1_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1
#define ULP1_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1
#define ULP1_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0
#define ULP1_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0
#define ULP1_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0
#define ULP1_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1
#define ULP1_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1
#define ULP1_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1
#define ULP1_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1
#define ULP1_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1
#define ULP1_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0
#define ULP1_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0
#define ULP1_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0
#define ULP1_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1
#define ULP1_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1
#define ULP1_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1
#define ULP1_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1
#define ULP1_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0
#define ULP1_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0
#define ULP1_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0
#define ULP1_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1
#define ULP1_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1
#define ULP1_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1
#define ULP1_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1
#define ULP1_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1
#define ULP1_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0
#define ULP1_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0
#define ULP1_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0
#define ULP1_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1
#define ULP1_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1
#define ULP1_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0
#define ULP1_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1
#define ULP1_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1
#define ULP1_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0
#define ULP1_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0
#define ULP1_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0
#define ULP1_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1
#define ULP1_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1
#define ULP1_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1
#define ULP1_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1
#define ULP1_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1
#define ULP1_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0
#define ULP1_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0
#define ULP1_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0
#define ULP1_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1
#define ULP1_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1
#define ULP1_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1
#define ULP1_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0
#define ULP1_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0
#define ULP1_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0
#define ULP1_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1
#define ULP1_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1
#define ULP1_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1
#define ULP1_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0
#define ULP1_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0
#define ULP1_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1
#define ULP1_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1
#define ULP1_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1
#define ULP1_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0
#define ULP1_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0
#define ULP1_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1
#define ULP1_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1
#define ULP1_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1
#define ULP1_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0
#define ULP1_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0
#define ULP1_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1
#define ULP1_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1
#define ULP1_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1
#define ULP1_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0
#define ULP1_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0
#define ULP1_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0
#define ULP1_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0
#define ULP1_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0
#define ULP1_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0
#define ULP1_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0
#define ULP1_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0
#define ULP1_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0
#define ULP1_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0
#define ULP1_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0
#define ULP1_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0
#define ULP1_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0
#define ULP1_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0
#define ULP1_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0
#define ULP1_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0
#define ULP1_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0
#define ULP1_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0
#define ULP1_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2
#define ULP1_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0
#define ULP1_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0
#define ULP1_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2
#define ULP1_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0
#define ULP1_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0
#define ULP1_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2
#define ULP1_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0
#define ULP1_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0
#define ULP1_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2
#define ULP1_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0
#define ULP1_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0
#define ULP1_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0
#define ULP1_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2
#define ULP1_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2
#define ULP1_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2
#define ULP1_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0
#define ULP1_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0
#define ULP1_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0
#define ULP1_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0
#define ULP1_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2
#define ULP1_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0
#define ULP1_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2
#define ULP1_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0
#define ULP1_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0
#define ULP1_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0
#define ULP1_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0
#define ULP1_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2
#define ULP1_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2
#define ULP1_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2
#define ULP1_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0
#define ULP1_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0
#define ULP1_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0
#define ULP1_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2
#define ULP1_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2
#define ULP1_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0
#define ULP1_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0
#define ULP1_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0
#define ULP1_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2
#define ULP1_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2
#define ULP1_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2
#define ULP1_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2
#define ULP1_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0
#define ULP1_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0
#define ULP1_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0
#define ULP1_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2
#define ULP1_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0
#define ULP1_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2
#define ULP1_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2
#define ULP1_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0
#define ULP1_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0
#define ULP1_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0
#define ULP1_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2
#define ULP1_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2
#define ULP1_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2
#define ULP1_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2
#define ULP1_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0
#define ULP1_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0
#define ULP1_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0
#define ULP1_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0
#define ULP1_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0
#define ULP1_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0
#define ULP1_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2
#define ULP1_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2
#define ULP1_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2
#define ULP1_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0
#define ULP1_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0
#define ULP1_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0
#define ULP1_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0
#define ULP1_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0
#define ULP1_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0
#define ULP1_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2
#define ULP1_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2
#define ULP1_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2
#define ULP1_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2
#define ULP1_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1
#define ULP1_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0
#define ULP1_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0
#define ULP1_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0
#define ULP1_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0
#define ULP1_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0
#define ULP1_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0
#define ULP1_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2
#define ULP1_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0
#define ULP1_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2
#define ULP1_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2
#define ULP1_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1
#define ULP1_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0
#define ULP1_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0
#define ULP1_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0
#define ULP1_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0
#define ULP1_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0
#define ULP1_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0
#define ULP1_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2
#define ULP1_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2
#define ULP1_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2
#define ULP1_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2
#define ULP1_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0
#define ULP1_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0
#define ULP1_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0
#define ULP1_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0
#define ULP1_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0
#define ULP1_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0
#define ULP1_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0
#define ULP1_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2
#define ULP1_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2
#define ULP1_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0
#define ULP1_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0
#define ULP1_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0
#define ULP1_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0
#define ULP1_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0
#define ULP1_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0
#define ULP1_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2
#define ULP1_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2
#define ULP1_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2
#define ULP1_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2
#define ULP1_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2
#define ULP1_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0
#define ULP1_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0
#define ULP1_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0
#define ULP1_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0
#define ULP1_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0
#define ULP1_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2
#define ULP1_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0
#define ULP1_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2
#define ULP1_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2
#define ULP1_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2
#define ULP1_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0
#define ULP1_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0
#define ULP1_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0
#define ULP1_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0
#define ULP1_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0
#define ULP1_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2
#define ULP1_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2
#define ULP1_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2
#define ULP1_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2
#define ULP1_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0
#define ULP1_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0
#define ULP1_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0
#define ULP1_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0
#define ULP1_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0
#define ULP1_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0
#define ULP1_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2
#define ULP1_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2
#define ULP1_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2
#define ULP1_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0
#define ULP1_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0
#define ULP1_PAD_PTF0__VIU_DE 0x0180 0x0000 0xc 0x0
#define ULP1_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3
#define ULP1_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3
#define ULP1_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3
#define ULP1_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0
#define ULP1_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0
#define ULP1_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0
#define ULP1_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0
#define ULP1_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3
#define ULP1_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3
#define ULP1_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0
#define ULP1_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0
#define ULP1_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0
#define ULP1_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3
#define ULP1_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3
#define ULP1_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3
#define ULP1_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0
#define ULP1_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0
#define ULP1_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0
#define ULP1_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3
#define ULP1_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3
#define ULP1_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0
#define ULP1_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0
#define ULP1_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0
#define ULP1_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2
#define ULP1_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3
#define ULP1_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3
#define ULP1_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3
#define ULP1_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2
#define ULP1_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0
#define ULP1_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0
#define ULP1_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0
#define ULP1_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2
#define ULP1_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3
#define ULP1_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0
#define ULP1_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3
#define ULP1_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2
#define ULP1_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0
#define ULP1_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0
#define ULP1_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0
#define ULP1_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2
#define ULP1_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3
#define ULP1_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3
#define ULP1_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3
#define ULP1_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2
#define ULP1_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0
#define ULP1_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0
#define ULP1_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0
#define ULP1_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2
#define ULP1_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3
#define ULP1_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3
#define ULP1_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0
#define ULP1_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0
#define ULP1_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0
#define ULP1_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0
#define ULP1_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2
#define ULP1_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3
#define ULP1_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3
#define ULP1_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3
#define ULP1_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3
#define ULP1_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0
#define ULP1_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0
#define ULP1_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0
#define ULP1_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0
#define ULP1_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2
#define ULP1_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3
#define ULP1_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0
#define ULP1_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3
#define ULP1_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3
#define ULP1_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0
#define ULP1_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0
#define ULP1_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0
#define ULP1_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0
#define ULP1_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2
#define ULP1_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3
#define ULP1_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3
#define ULP1_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3
#define ULP1_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3
#define ULP1_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0
#define ULP1_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0
#define ULP1_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0
#define ULP1_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0
#define ULP1_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2
#define ULP1_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3
#define ULP1_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3
#define ULP1_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3
#define ULP1_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0
#define ULP1_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0
#define ULP1_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0
#define ULP1_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0
#define ULP1_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2
#define ULP1_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3
#define ULP1_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3
#define ULP1_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3
#define ULP1_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3
#define ULP1_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0
#define ULP1_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0
#define ULP1_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0
#define ULP1_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0
#define ULP1_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2
#define ULP1_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3
#define ULP1_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0
#define ULP1_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3
#define ULP1_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3
#define ULP1_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0
#define ULP1_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0
#define ULP1_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0
#define ULP1_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0
#define ULP1_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2
#define ULP1_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3
#define ULP1_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3
#define ULP1_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3
#define ULP1_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3
#define ULP1_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0
#define ULP1_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0
#define ULP1_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0
#define ULP1_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0
#define ULP1_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2
#define ULP1_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3
#define ULP1_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3
#define ULP1_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0
#define ULP1_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0
#define ULP1_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0
#define ULP1_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0
#define ULP1_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2
#define ULP1_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3
#define ULP1_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3
#define ULP1_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0
#define ULP1_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0
#define ULP1_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0
#define ULP1_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0
#define ULP1_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2
#define ULP1_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3
#define ULP1_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3
#define ULP1_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0
#define ULP1_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0
#define ULP1_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0
#define ULP1_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0
#define ULP1_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2
#define ULP1_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3
#define ULP1_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3
#define ULP1_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0
#define ULP1_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0
#define ULP1_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0
#define ULP1_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0
#define ULP1_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2
#define ULP1_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3
#define ULP1_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3
#define ULP1_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0
#endif /* __DTS_ULP1_PINFUNC_H */

43
arch/arm/dts/imx7ulp-uboot.dtsi Normal file
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@ -0,0 +1,43 @@
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&soc {
u-boot,dm-pre-reloc;
};
&ahbbridge0 {
u-boot,dm-pre-reloc;
};
&ahbbridge1 {
u-boot,dm-pre-reloc;
};
&iomuxc {
u-boot,dm-pre-reloc;
};
&iomuxc1 {
u-boot,dm-pre-reloc;
};
&lpuart4 {
u-boot,dm-pre-reloc;
};
&lpuart5 {
u-boot,dm-pre-reloc;
};
&lpuart6 {
u-boot,dm-pre-reloc;
};
&lpuart7 {
u-boot,dm-pre-reloc;
};

598
arch/arm/dts/imx7ulp.dtsi Normal file
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@ -0,0 +1,598 @@
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/clock/imx7ulp-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include "skeleton.dtsi"
#include "imx7ulp-pinfunc.h"
/ {
interrupt-parent = <&intc>;
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
mmc0 = &usdhc0;
mmc1 = &usdhc1;
serial0 = &lpuart4;
serial1 = &lpuart5;
serial2 = &lpuart6;
serial3 = &lpuart7;
usbphy0 = &usbphy1;
i2c0 = &lpi2c4;
i2c1 = &lpi2c5;
i2c2 = &lpi2c6;
i2c3 = &lpi2c7;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0xC000000>;
alignment = <0x2000>;
linux,cma-default;
};
rpmsg_reserved: rpmsg@9FFF0000 {
no-map;
reg = <0x9FF00000 0x100000>;
};
};
intc: interrupt-controller@40021000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x40021000 0x1000>,
<0x40022000 0x100>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
ckil: clock@0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "ckil";
};
osc: clock@1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "osc";
};
sirc: clock@2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
clock-output-names = "sirc";
};
firc: clock@3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
clock-output-names = "firc";
};
upll: clock@4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <480000000>;
clock-output-names = "upll";
};
mpll: clock@5 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <480000000>;
clock-output-names = "mpll";
};
};
sram: sram@20000000 {
compatible = "fsl,lpm-sram";
reg = <0x1fffc000 0x4000>;
};
ahbbridge0: ahb-bridge0@40000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40000000 0x800000>;
ranges;
edma0: dma-controller@40080000 {
#dma-cells = <2>;
compatible = "nxp,imx7ulp-edma";
reg = <0x40080000 0x2000>,
<0x40210000 0x1000>;
dma-channels = <32>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dma", "dmamux0";
clocks = <&clks IMX7ULP_CLK_DMA1>, <&clks IMX7ULP_CLK_DMA_MUX1>;
};
mu: mu@40220000 {
compatible = "fsl,imx7ulp-mu", "fsl,imx6sx-mu";
reg = <0x40220000 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
nmi: nmi@40220000 {
compatible = "fsl,imx7ulp-nmi";
reg = <0x40220000 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
rpmsg: rpmsg{
compatible = "fsl,imx7ulp-rpmsg";
memory-region = <&rpmsg_reserved>;
status = "disabled";
};
snvs: snvs@40230000 {
compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
reg = <0x40230000 0x10000>;
snvs_rtc: snvs-rtc-lp{
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap =<&snvs>;
offset = <0x34>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "snvs-rtc";
clocks = <&clks IMX7ULP_CLK_SNVS>;
};
};
tpm5: tpm@40260000 {
compatible = "fsl,imx7ulp-tpm";
reg = <0x40260000 0x1000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPTPM5>;
};
lpit: 1@40270000 {
compatible = "fsl,imx-lpit";
reg = <0x40270000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
/* clocks = <&lpclk>;*/
clocks = <&clks IMX7ULP_CLK_LPIT1>;
assigned-clock-rates = <48000000>;
assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
};
lpi2c4: lpi2c4@402B0000 {
compatible = "fsl,imx7ulp-lpi2c";
reg = <0x402B0000 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPI2C4>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpi2c5: lpi2c4@402C0000 {
compatible = "fsl,imx7ulp-lpi2c";
reg = <0x402C0000 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPI2C5>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpspi2: lpspi@40290000 {
compatible = "fsl,imx7ulp-spi";
reg = <0x40290000 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPSPI2>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpspi3: lpspi@402A0000 {
compatible = "fsl,imx7ulp-spi";
reg = <0x402A0000 0x10000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPSPI3>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpuart4: serial@402D0000 {
compatible = "fsl,imx7ulp-lpuart";
reg = <0x402D0000 0x1000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPUART4>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>;
assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>;
assigned-clock-rates = <24000000>;
status = "disabled";
};
lpuart5: serial@402E0000 {
compatible = "fsl,imx7ulp-lpuart";
reg = <0x402E0000 0x1000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPUART5>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
dmas = <&edma0 0 20>, <&edma0 0 19>;
dma-names = "tx","rx";
status = "disabled";
};
usbotg1: usb@40330000 {
compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb",
"fsl,imx27-usb";
reg = <0x40330000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_USB0>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc1 0>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x8>;
rx-burst-size-dword = <0x8>;
status = "disabled";
};
usbmisc1: usbmisc@40330200 {
#index-cells = <1>;
compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc",
"fsl,imx6q-usbmisc";
reg = <0x40330200 0x200>;
};
usbphy1: usbphy@0x40350000 {
compatible = "fsl,imx7ulp-usbphy",
"fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
reg = <0x40350000 0x1000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_USB_PHY>;
nxp,sim = <&sim>;
};
usdhc0: usdhc@40370000 {
compatible = "fsl,imx7ulp-usdhc";
reg = <0x40370000 0x10000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
<&clks IMX7ULP_CLK_NIC1_DIV>,
<&clks IMX7ULP_CLK_USDHC0>;
clock-names ="ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled";
};
usdhc1: usdhc@40380000 {
compatible = "fsl,imx7ulp-usdhc";
reg = <0x40380000 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
<&clks IMX7ULP_CLK_NIC1_DIV>,
<&clks IMX7ULP_CLK_USDHC1>;
clock-names ="ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled";
};
wdog1: wdog@403D0000 {
compatible = "fsl,imx7ulp-wdt";
reg = <0x403D0000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_WDG1>;
assigned-clocks = <&clks IMX7ULP_CLK_WDG1>;
assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
/*
* As the 1KHz LPO clock rate is not trimed,the actually clock
* is about 667Hz, so the init timeout 60s should set 40*1000
* in the TOVAL register.
*/
timeout-sec = <40>;
};
wdog2: wdog@40430000 {
compatible = "fsl,imx7ulp-wdt";
reg = <0x40430000 0x10000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_WDG2>;
assigned-clocks = <&clks IMX7ULP_CLK_WDG2>;
assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
timeout-sec = <40>;
};
clks: scg1@403E0000 {
compatible = "fsl,imx7ulp-scg1";
reg = <0x403E0000 0x10000>;
clocks = <&ckil>, <&osc>, <&sirc>,
<&firc>, <&upll>, <&mpll>;
clock-names = "ckil", "osc", "sirc",
"firc", "upll", "mpll";
#clock-cells = <1>;
assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>,
<&clks IMX7ULP_CLK_USDHC1>;
assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>,
<&clks IMX7ULP_CLK_NIC1_DIV>;
};
pcc2: pcc2@403F0000 {
compatible = "fsl,imx7ulp-pcc2";
reg = <0x403F0000 0x10000>;
};
pmc1: pmc1@40400000 {
compatible = "fsl,imx7ulp-pmc1";
reg = <0x40400000 0x1000>;
};
smc1: smc1@40410000 {
compatible = "fsl,imx7ulp-smc1";
reg = <0x40410000 0x1000>;
};
};
ahbbridge1: ahb-bridge1@40800000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40800000 0x800000>;
ranges;
lpi2c6: lpi2c6@40A40000 {
compatible = "fsl,imx7ulp-lpi2c";
reg = <0x40A40000 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPI2C6>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpi2c7: lpi2c7@40A50000 {
compatible = "fsl,imx7ulp-lpi2c";
reg = <0x40A50000 0x10000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPI2C7>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpuart6: serial@40A60000 {
compatible = "fsl,imx7ulp-lpuart";
reg = <0x40A60000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPUART6>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPUART6>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <48000000>;
dmas = <&edma0 0 22>, <&edma0 0 21>;
dma-names = "tx","rx";
status = "disabled";
};
lpuart7: serial@40A70000 {
compatible = "fsl,imx7ulp-lpuart";
reg = <0x40A70000 0x1000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_LPUART7>;
clock-names = "ipg";
assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>;
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
assigned-clock-rates = <50000000>;
dmas = <&edma0 0 24>, <&edma0 0 23>;
dma-names = "tx","rx";
status = "disabled";
};
lcdif: lcdif@40AA0000 {
compatible = "fsl,imx7ulp-lcdif";
reg = <0x40aa0000 0x10000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_DUMMY>,
<&clks IMX7ULP_CLK_LCDIF>,
<&clks IMX7ULP_CLK_DUMMY>;
clock-names = "axi", "pix", "disp_axi";
status = "disabled";
};
mipi_dsi: mipi_dsi@40A90000 {
compatible = "fsl,imx7ulp-mipi-dsi";
reg = <0x40A90000 0x10000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_DSI>;
clock-names = "mipi_dsi_clk";
sim = <&sim>;
status = "disabled";
};
mmdc: mmdc@40ab0000 {
compatible = "fsl,imx7ulp-mmdc";
reg = <0x40ab0000 0x4000>;
};
pcc3: pcc3@40B30000 {
compatible = "fsl,imx7ulp-pcc3";
reg = <0x40B30000 0x10000>;
};
iomuxc: iomuxc@4103D000 {
compatible = "fsl,imx7ulp-iomuxc-0";
reg = <0x4103D000 0x1000>;
fsl,mux_mask = <0xf00>;
status = "disabled";
};
iomuxc1: iomuxc1@40ac0000 {
compatible = "fsl,imx7ulp-iomuxc-1";
reg = <0x40ac0000 0x1000>;
fsl,mux_mask = <0xf00>;
};
gpio0: gpio@40ae0000 {
compatible = "fsl,imx7ulp-gpio";
reg = <0x40ae0000 0x1000 0x400F0000 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc1 0 0 32>;
};
gpio1: gpio@40af0000 {
compatible = "fsl,imx7ulp-gpio";
reg = <0x40af0000 0x1000 0x400F0040 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc1 0 32 32>;
};
gpio2: gpio@40b00000 {
compatible = "fsl,imx7ulp-gpio";
reg = <0x40b00000 0x1000 0x400F0080 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc1 0 64 32>;
};
gpio3: gpio@40b10000 {
compatible = "fsl,imx7ulp-gpio";
reg = <0x40b10000 0x1000 0x400F00c0 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc1 0 96 32>;
};
pmc0: pmc0@410a1000 {
compatible = "fsl,imx7ulp-pmc0";
reg = <0x410a1000 0x1000>;
};
sim: sim@410a3000 {
compatible = "fsl,imx7ulp-sim", "syscon";
reg = <0x410a3000 0x1000>;
};
qspi1: qspi@410A5000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7ulp-qspi";
reg = <0x410A5000 0x10000>, <0xC0000000 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_DUMMY>,
<&clks IMX7ULP_CLK_DUMMY>;
clock-names = "qspi_en", "qspi";
status = "disabled";
};
gpu: gpu@41800000 {
compatible = "fsl,imx6q-gpu";
reg = <0x41800000 0x80000>, <0x41880000 0x80000>,
<0x60000000 0x40000000>, <0x0 0x4000000>;
reg-names = "iobase_3d", "iobase_2d",
"phys_baseaddr", "contiguous_mem";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_3d", "irq_2d";
clocks = <&clks IMX7ULP_CLK_GPU3D>,
<&clks IMX7ULP_CLK_NIC1_DIV>,
<&clks IMX7ULP_CLK_GPU_DIV>,
<&clks IMX7ULP_CLK_GPU2D>,
<&clks IMX7ULP_CLK_NIC1_DIV>,
<&clks IMX7ULP_CLK_NIC1_DIV>;
clock-names = "gpu3d_clk", "gpu3d_shader_clk",
"gpu3d_axi_clk", "gpu2d_clk",
"gpu2d_shader_clk", "gpu2d_axi_clk";
};
};
imx_ion {
compatible = "fsl,mxc-ion";
fsl,heap-id = <0>;
};
};

4
arch/arm/imx-common/Makefile
View File

@ -31,6 +31,10 @@ obj-$(CONFIG_IMX_RDC) += rdc-sema.o
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
obj-$(CONFIG_SECURE_BOOT) += hab.o
endif
ifeq ($(SOC),$(filter $(SOC),mx7ulp))
obj-y += cache.o
obj-$(CONFIG_SECURE_BOOT) += hab.o
endif
ifeq ($(SOC),$(filter $(SOC),vf610))
obj-y += ddrmc-vf610.o
endif

3
arch/arm/imx-common/hab.c
View File

@ -77,7 +77,8 @@
#define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0
#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18
#define IS_HAB_ENABLED_BIT \
(is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)
(is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \
(is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2))
/*
* +------------+ 0x0 (DDR_UIMAGE_START) -

10
arch/arm/imx-common/init.c
View File

@ -115,3 +115,13 @@ void boot_mode_apply(unsigned cfg_val)
writel(reg, &psrc->gpr10);
}
#endif
#if defined(CONFIG_MX6)
u32 imx6_src_get_boot_mode(void)
{
if (imx6_is_bmode_from_gpr9())
return readl(&src_base->gpr9);
else
return readl(&src_base->sbmr1);
}
#endif

49
arch/arm/imx-common/spl.c
View File

@ -10,6 +10,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/spl.h>
#include <spl.h>
#include <asm/imx-common/hab.h>
@ -18,10 +19,8 @@
/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
u32 spl_boot_device(void)
{
struct src *psrc = (struct src *)SRC_BASE_ADDR;
unsigned int gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
unsigned int bmode = readl(&psrc->sbmr2);
unsigned int bmode = readl(&src_base->sbmr2);
u32 reg = imx6_src_get_boot_mode();
/*
* Check for BMODE if serial downloader is enabled
@ -29,42 +28,52 @@ u32 spl_boot_device(void)
*/
if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
return BOOT_DEVICE_UART;
/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
switch ((reg & 0x000000FF) >> 4) {
switch ((reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
/* EIM: See 8.5.1, Table 8-9 */
case 0x0:
case IMX6_BMODE_EMI:
/* BOOT_CFG1[3]: NOR/OneNAND Selection */
if ((reg & 0x00000008) >> 3)
switch ((reg & IMX6_BMODE_EMI_MASK) >> IMX6_BMODE_EMI_SHIFT) {
case IMX6_BMODE_ONENAND:
return BOOT_DEVICE_ONENAND;
else
case IMX6_BMODE_NOR:
return BOOT_DEVICE_NOR;
break;
}
/* Reserved: Used to force Serial Downloader */
case 0x1:
case IMX6_BMODE_UART:
return BOOT_DEVICE_UART;
/* SATA: See 8.5.4, Table 8-20 */
case 0x2:
case IMX6_BMODE_SATA:
return BOOT_DEVICE_SATA;
/* Serial ROM: See 8.5.5.1, Table 8-22 */
case 0x3:
case IMX6_BMODE_SERIAL_ROM:
/* BOOT_CFG4[2:0] */
switch ((reg & 0x07000000) >> 24) {
case 0x0 ... 0x4:
switch ((reg & IMX6_BMODE_SERIAL_ROM_MASK) >>
IMX6_BMODE_SERIAL_ROM_SHIFT) {
case IMX6_BMODE_ECSPI1:
case IMX6_BMODE_ECSPI2:
case IMX6_BMODE_ECSPI3:
case IMX6_BMODE_ECSPI4:
case IMX6_BMODE_ECSPI5:
return BOOT_DEVICE_SPI;
case 0x5 ... 0x7:
case IMX6_BMODE_I2C1:
case IMX6_BMODE_I2C2:
case IMX6_BMODE_I2C3:
return BOOT_DEVICE_I2C;
}
break;
/* SD/eSD: 8.5.3, Table 8-15 */
case 0x4:
case 0x5:
case IMX6_BMODE_SD:
case IMX6_BMODE_ESD:
return BOOT_DEVICE_MMC1;
/* MMC/eMMC: 8.5.3 */
case 0x6:
case 0x7:
case IMX6_BMODE_MMC:
case IMX6_BMODE_EMMC:
return BOOT_DEVICE_MMC1;
/* NAND Flash: 8.5.2 */
case 0x8 ... 0xf:
/* NAND Flash: 8.5.2, Table 8-10 */
case IMX6_BMODE_NAND:
return BOOT_DEVICE_NAND;
}
return BOOT_DEVICE_NONE;

42
arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
View File

@ -10,46 +10,4 @@
#define I2C_QUIRK_REG /* enable 8-bit driver */
#ifdef CONFIG_FSL_LPUART
#ifdef CONFIG_LPUART_32B_REG
struct lpuart_fsl {
u32 baud;
u32 stat;
u32 ctrl;
u32 data;
u32 match;
u32 modir;
u32 fifo;
u32 water;
};
#else
struct lpuart_fsl {
u8 ubdh;
u8 ubdl;
u8 uc1;
u8 uc2;
u8 us1;
u8 us2;
u8 uc3;
u8 ud;
u8 uma1;
u8 uma2;
u8 uc4;
u8 uc5;
u8 ued;
u8 umodem;
u8 uir;
u8 reserved;
u8 upfifo;
u8 ucfifo;
u8 usfifo;
u8 utwfifo;
u8 utcfifo;
u8 urwfifo;
u8 urcfifo;
u8 rsvd[28];
};
#endif
#endif /* CONFIG_FSL_LPUART */
#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */

2
arch/arm/include/asm/arch-imx/cpu.h
View File

@ -25,10 +25,12 @@
#define MXC_CPU_MX6QP 0x69
#define MXC_CPU_MX7S 0x71 /* dummy ID */
#define MXC_CPU_MX7D 0x72
#define MXC_CPU_MX7ULP 0x81 /* Temporally hard code */
#define MXC_CPU_VF610 0xF6 /* dummy ID */
#define MXC_SOC_MX6 0x60
#define MXC_SOC_MX7 0x70
#define MXC_SOC_MX7ULP 0x80 /* dummy */
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_1 0x11

40
arch/arm/include/asm/arch-ls102xa/imx-regs.h
View File

@ -10,44 +10,4 @@
#define I2C_QUIRK_REG /* enable 8-bit driver */
#ifdef CONFIG_LPUART_32B_REG
struct lpuart_fsl {
u32 baud;
u32 stat;
u32 ctrl;
u32 data;
u32 match;
u32 modir;
u32 fifo;
u32 water;
};
#else
struct lpuart_fsl {
u8 ubdh;
u8 ubdl;
u8 uc1;
u8 uc2;
u8 us1;
u8 us2;
u8 uc3;
u8 ud;
u8 uma1;
u8 uma2;
u8 uc4;
u8 uc5;
u8 ued;
u8 umodem;
u8 uir;
u8 reserved;
u8 upfifo;
u8 ucfifo;
u8 usfifo;
u8 utwfifo;
u8 utcfifo;
u8 urwfifo;
u8 urcfifo;
u8 rsvd[28];
};
#endif
#endif /* __ASM_ARCH_IMX_REGS_H__ */

2
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@ -473,6 +473,8 @@ struct src {
u32 gpr10;
};
#define src_base ((struct src *)SRC_BASE_ADDR)
#define SRC_SCR_M4_ENABLE_OFFSET 22
#define SRC_SCR_M4_ENABLE_MASK (1 << 22)
#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4

16
arch/arm/include/asm/arch-mx6/opos6ul.h Normal file
View File

@ -0,0 +1,16 @@
/*
* Copyright (C) 2017 Armadeus Systems
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ARCH_ARM_MX6UL_OPOS6UL_H__
#define __ARCH_ARM_MX6UL_OPOS6UL_H__
int opos6ul_board_late_init(void);
#ifdef CONFIG_SPL_BUILD
void opos6ul_setup_uart_debug(void);
#endif
#endif

43
arch/arm/include/asm/arch-mx7ulp/clock.h Normal file
View File

@ -0,0 +1,43 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_CLOCK_H
#define _ASM_ARCH_CLOCK_H
#include <common.h>
#include <asm/arch/pcc.h>
#include <asm/arch/scg.h>
/* Mainly for compatible to imx common code. */
enum mxc_clock {
MXC_ARM_CLK = 0,
MXC_AHB_CLK,
MXC_IPG_CLK,
MXC_UART_CLK,
MXC_CSPI_CLK,
MXC_AXI_CLK,
MXC_DDR_CLK,
MXC_ESDHC_CLK,
MXC_ESDHC2_CLK,
MXC_I2C_CLK,
};
u32 mxc_get_clock(enum mxc_clock clk);
u32 get_lpuart_clk(void);
#ifdef CONFIG_SYS_LPI2C_IMX
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
u32 imx_get_i2cclk(unsigned i2c_num);
#endif
#ifdef CONFIG_MXC_OCOTP
void enable_ocotp_clk(unsigned char enable);
#endif
#ifdef CONFIG_USB_EHCI
void enable_usboh3_clk(unsigned char enable);
#endif
void init_clk_usdhc(u32 index);
void clock_init(void);
void hab_caam_clock_enable(unsigned char enable);
#endif

22
arch/arm/include/asm/arch-mx7ulp/gpio.h Normal file
View File

@ -0,0 +1,22 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX7ULP_GPIO_H
#define __ASM_ARCH_MX7ULP_GPIO_H
struct gpio_regs {
u32 gpio_pdor;
u32 gpio_psor;
u32 gpio_pcor;
u32 gpio_ptor;
u32 gpio_pdir;
u32 gpio_pddr;
u32 gpio_gacr;
};
#define IMX_GPIO_NR(port, index) ((((port)-1)*32)+((index)&31))
#endif /* __ASM_ARCH_MX7ULP_GPIO_H */

1120
arch/arm/include/asm/arch-mx7ulp/imx-regs.h Normal file
View File

File diff suppressed because it is too large Load Diff

520
arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h Normal file
View File

@ -0,0 +1,520 @@
/*
* Copyright 2016 Freescale Semiconductors, Inc.
*
* I2CLP driver for i.MX
*
* SPDX-License-Identifier: GPL-2.0+
*
*/
#ifndef __IMX_LPI2C_H__
#define __IMX_LPI2C_H__
struct imx_lpi2c_bus {
int index;
ulong base;
ulong driver_data;
int speed;
struct i2c_pads_info *pads_info;
struct udevice *bus;
};
struct imx_lpi2c_reg {
u32 verid;
u32 param;
u8 reserved_0[8];
u32 mcr;
u32 msr;
u32 mier;
u32 mder;
u32 mcfgr0;
u32 mcfgr1;
u32 mcfgr2;
u32 mcfgr3;
u8 reserved_1[16];
u32 mdmr;
u8 reserved_2[4];
u32 mccr0;
u8 reserved_3[4];
u32 mccr1;
u8 reserved_4[4];
u32 mfcr;
u32 mfsr;
u32 mtdr;
u8 reserved_5[12];
u32 mrdr;
u8 reserved_6[156];
u32 scr;
u32 ssr;
u32 sier;
u32 sder;
u8 reserved_7[4];
u32 scfgr1;
u32 scfgr2;
u8 reserved_8[20];
u32 samr;
u8 reserved_9[12];
u32 sasr;
u32 star;
u8 reserved_10[8];
u32 stdr;
u8 reserved_11[12];
u32 srdr;
};
typedef enum lpi2c_status {
LPI2C_SUCESS = 0,
LPI2C_END_PACKET_ERR,
LPI2C_STOP_ERR,
LPI2C_NAK_ERR,
LPI2C_ARB_LOST_ERR,
LPI2C_FIFO_ERR,
LPI2C_PIN_LOW_TIMEOUT_ERR,
LPI2C_DATA_MATCH_ERR,
LPI2C_BUSY,
LPI2C_IDLE,
LPI2C_BIT_ERR,
LPI2C_NO_TRANS_PROG,
LPI2C_DMA_REQ_FAIL,
} lpi2c_status_t;
/* ----------------------------------------------------------------------------
-- LPI2C Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPI2C_Register_Masks LPI2C Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
#define LPI2C_VERID_FEATURE_MASK (0xFFFFU)
#define LPI2C_VERID_FEATURE_SHIFT (0U)
#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
#define LPI2C_VERID_MINOR_MASK (0xFF0000U)
#define LPI2C_VERID_MINOR_SHIFT (16U)
#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
#define LPI2C_VERID_MAJOR_MASK (0xFF000000U)
#define LPI2C_VERID_MAJOR_SHIFT (24U)
#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
/*! @name PARAM - Parameter Register */
#define LPI2C_PARAM_MTXFIFO_MASK (0xFU)
#define LPI2C_PARAM_MTXFIFO_SHIFT (0U)
#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U)
#define LPI2C_PARAM_MRXFIFO_SHIFT (8U)
#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
/*! @name MCR - Master Control Register */
#define LPI2C_MCR_MEN_MASK (0x1U)
#define LPI2C_MCR_MEN_SHIFT (0U)
#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
#define LPI2C_MCR_RST_MASK (0x2U)
#define LPI2C_MCR_RST_SHIFT (1U)
#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
#define LPI2C_MCR_DOZEN_MASK (0x4U)
#define LPI2C_MCR_DOZEN_SHIFT (2U)
#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
#define LPI2C_MCR_DBGEN_MASK (0x8U)
#define LPI2C_MCR_DBGEN_SHIFT (3U)
#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
#define LPI2C_MCR_RTF_MASK (0x100U)
#define LPI2C_MCR_RTF_SHIFT (8U)
#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
#define LPI2C_MCR_RRF_MASK (0x200U)
#define LPI2C_MCR_RRF_SHIFT (9U)
#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
/*! @name MSR - Master Status Register */
#define LPI2C_MSR_TDF_MASK (0x1U)
#define LPI2C_MSR_TDF_SHIFT (0U)
#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
#define LPI2C_MSR_RDF_MASK (0x2U)
#define LPI2C_MSR_RDF_SHIFT (1U)
#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
#define LPI2C_MSR_EPF_MASK (0x100U)
#define LPI2C_MSR_EPF_SHIFT (8U)
#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
#define LPI2C_MSR_SDF_MASK (0x200U)
#define LPI2C_MSR_SDF_SHIFT (9U)
#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
#define LPI2C_MSR_NDF_MASK (0x400U)
#define LPI2C_MSR_NDF_SHIFT (10U)
#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
#define LPI2C_MSR_ALF_MASK (0x800U)
#define LPI2C_MSR_ALF_SHIFT (11U)
#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
#define LPI2C_MSR_FEF_MASK (0x1000U)
#define LPI2C_MSR_FEF_SHIFT (12U)
#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
#define LPI2C_MSR_PLTF_MASK (0x2000U)
#define LPI2C_MSR_PLTF_SHIFT (13U)
#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
#define LPI2C_MSR_DMF_MASK (0x4000U)
#define LPI2C_MSR_DMF_SHIFT (14U)
#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
#define LPI2C_MSR_MBF_MASK (0x1000000U)
#define LPI2C_MSR_MBF_SHIFT (24U)
#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
#define LPI2C_MSR_BBF_MASK (0x2000000U)
#define LPI2C_MSR_BBF_SHIFT (25U)
#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
/*! @name MIER - Master Interrupt Enable Register */
#define LPI2C_MIER_TDIE_MASK (0x1U)
#define LPI2C_MIER_TDIE_SHIFT (0U)
#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
#define LPI2C_MIER_RDIE_MASK (0x2U)
#define LPI2C_MIER_RDIE_SHIFT (1U)
#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
#define LPI2C_MIER_EPIE_MASK (0x100U)
#define LPI2C_MIER_EPIE_SHIFT (8U)
#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
#define LPI2C_MIER_SDIE_MASK (0x200U)
#define LPI2C_MIER_SDIE_SHIFT (9U)
#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
#define LPI2C_MIER_NDIE_MASK (0x400U)
#define LPI2C_MIER_NDIE_SHIFT (10U)
#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
#define LPI2C_MIER_ALIE_MASK (0x800U)
#define LPI2C_MIER_ALIE_SHIFT (11U)
#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
#define LPI2C_MIER_FEIE_MASK (0x1000U)
#define LPI2C_MIER_FEIE_SHIFT (12U)
#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
#define LPI2C_MIER_PLTIE_MASK (0x2000U)
#define LPI2C_MIER_PLTIE_SHIFT (13U)
#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
#define LPI2C_MIER_DMIE_MASK (0x4000U)
#define LPI2C_MIER_DMIE_SHIFT (14U)
#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
/*! @name MDER - Master DMA Enable Register */
#define LPI2C_MDER_TDDE_MASK (0x1U)
#define LPI2C_MDER_TDDE_SHIFT (0U)
#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
#define LPI2C_MDER_RDDE_MASK (0x2U)
#define LPI2C_MDER_RDDE_SHIFT (1U)
#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
/*! @name MCFGR0 - Master Configuration Register 0 */
#define LPI2C_MCFGR0_HREN_MASK (0x1U)
#define LPI2C_MCFGR0_HREN_SHIFT (0U)
#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
#define LPI2C_MCFGR0_HRPOL_MASK (0x2U)
#define LPI2C_MCFGR0_HRPOL_SHIFT (1U)
#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
#define LPI2C_MCFGR0_HRSEL_MASK (0x4U)
#define LPI2C_MCFGR0_HRSEL_SHIFT (2U)
#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)
#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)
#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
#define LPI2C_MCFGR0_RDMO_MASK (0x200U)
#define LPI2C_MCFGR0_RDMO_SHIFT (9U)
#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
/*! @name MCFGR1 - Master Configuration Register 1 */
#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U)
#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U)
#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)
#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)
#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
#define LPI2C_MCFGR1_IGNACK_MASK (0x200U)
#define LPI2C_MCFGR1_IGNACK_SHIFT (9U)
#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U)
#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U)
#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U)
#define LPI2C_MCFGR1_MATCFG_SHIFT (16U)
#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)
#define LPI2C_MCFGR1_PINCFG_SHIFT (24U)
#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
/*! @name MCFGR2 - Master Configuration Register 2 */
#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)
#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)
#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)
#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U)
#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)
#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U)
#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
/*! @name MCFGR3 - Master Configuration Register 3 */
#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)
#define LPI2C_MCFGR3_PINLOW_SHIFT (8U)
#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
/*! @name MDMR - Master Data Match Register */
#define LPI2C_MDMR_MATCH0_MASK (0xFFU)
#define LPI2C_MDMR_MATCH0_SHIFT (0U)
#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U)
#define LPI2C_MDMR_MATCH1_SHIFT (16U)
#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
/*! @name MCCR0 - Master Clock Configuration Register 0 */
#define LPI2C_MCCR0_CLKLO_MASK (0x3FU)
#define LPI2C_MCCR0_CLKLO_SHIFT (0U)
#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U)
#define LPI2C_MCCR0_CLKHI_SHIFT (8U)
#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)
#define LPI2C_MCCR0_SETHOLD_SHIFT (16U)
#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)
#define LPI2C_MCCR0_DATAVD_SHIFT (24U)
#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
/*! @name MCCR1 - Master Clock Configuration Register 1 */
#define LPI2C_MCCR1_CLKLO_MASK (0x3FU)
#define LPI2C_MCCR1_CLKLO_SHIFT (0U)
#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U)
#define LPI2C_MCCR1_CLKHI_SHIFT (8U)
#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)
#define LPI2C_MCCR1_SETHOLD_SHIFT (16U)
#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)
#define LPI2C_MCCR1_DATAVD_SHIFT (24U)
#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
/*! @name MFCR - Master FIFO Control Register */
#define LPI2C_MFCR_TXWATER_MASK (0xFFU)
#define LPI2C_MFCR_TXWATER_SHIFT (0U)
#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
#define LPI2C_MFCR_RXWATER_MASK (0xFF0000U)
#define LPI2C_MFCR_RXWATER_SHIFT (16U)
#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
/*! @name MFSR - Master FIFO Status Register */
#define LPI2C_MFSR_TXCOUNT_MASK (0xFFU)
#define LPI2C_MFSR_TXCOUNT_SHIFT (0U)
#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
#define LPI2C_MFSR_RXCOUNT_MASK (0xFF0000U)
#define LPI2C_MFSR_RXCOUNT_SHIFT (16U)
#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
/*! @name MTDR - Master Transmit Data Register */
#define LPI2C_MTDR_DATA_MASK (0xFFU)
#define LPI2C_MTDR_DATA_SHIFT (0U)
#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
#define LPI2C_MTDR_CMD_MASK (0x700U)
#define LPI2C_MTDR_CMD_SHIFT (8U)
#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
/*! @name MRDR - Master Receive Data Register */
#define LPI2C_MRDR_DATA_MASK (0xFFU)
#define LPI2C_MRDR_DATA_SHIFT (0U)
#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U)
#define LPI2C_MRDR_RXEMPTY_SHIFT (14U)
#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
/*! @name SCR - Slave Control Register */
#define LPI2C_SCR_SEN_MASK (0x1U)
#define LPI2C_SCR_SEN_SHIFT (0U)
#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
#define LPI2C_SCR_RST_MASK (0x2U)
#define LPI2C_SCR_RST_SHIFT (1U)
#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
#define LPI2C_SCR_FILTEN_MASK (0x10U)
#define LPI2C_SCR_FILTEN_SHIFT (4U)
#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
#define LPI2C_SCR_FILTDZ_MASK (0x20U)
#define LPI2C_SCR_FILTDZ_SHIFT (5U)
#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
#define LPI2C_SCR_RTF_MASK (0x100U)
#define LPI2C_SCR_RTF_SHIFT (8U)
#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
#define LPI2C_SCR_RRF_MASK (0x200U)
#define LPI2C_SCR_RRF_SHIFT (9U)
#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
/*! @name SSR - Slave Status Register */
#define LPI2C_SSR_TDF_MASK (0x1U)
#define LPI2C_SSR_TDF_SHIFT (0U)
#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
#define LPI2C_SSR_RDF_MASK (0x2U)
#define LPI2C_SSR_RDF_SHIFT (1U)
#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
#define LPI2C_SSR_AVF_MASK (0x4U)
#define LPI2C_SSR_AVF_SHIFT (2U)
#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
#define LPI2C_SSR_TAF_MASK (0x8U)
#define LPI2C_SSR_TAF_SHIFT (3U)
#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
#define LPI2C_SSR_RSF_MASK (0x100U)
#define LPI2C_SSR_RSF_SHIFT (8U)
#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
#define LPI2C_SSR_SDF_MASK (0x200U)
#define LPI2C_SSR_SDF_SHIFT (9U)
#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
#define LPI2C_SSR_BEF_MASK (0x400U)
#define LPI2C_SSR_BEF_SHIFT (10U)
#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
#define LPI2C_SSR_FEF_MASK (0x800U)
#define LPI2C_SSR_FEF_SHIFT (11U)
#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
#define LPI2C_SSR_AM0F_MASK (0x1000U)
#define LPI2C_SSR_AM0F_SHIFT (12U)
#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
#define LPI2C_SSR_AM1F_MASK (0x2000U)
#define LPI2C_SSR_AM1F_SHIFT (13U)
#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
#define LPI2C_SSR_GCF_MASK (0x4000U)
#define LPI2C_SSR_GCF_SHIFT (14U)
#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
#define LPI2C_SSR_SARF_MASK (0x8000U)
#define LPI2C_SSR_SARF_SHIFT (15U)
#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
#define LPI2C_SSR_SBF_MASK (0x1000000U)
#define LPI2C_SSR_SBF_SHIFT (24U)
#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
#define LPI2C_SSR_BBF_MASK (0x2000000U)
#define LPI2C_SSR_BBF_SHIFT (25U)
#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
/*! @name SIER - Slave Interrupt Enable Register */
#define LPI2C_SIER_TDIE_MASK (0x1U)
#define LPI2C_SIER_TDIE_SHIFT (0U)
#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
#define LPI2C_SIER_RDIE_MASK (0x2U)
#define LPI2C_SIER_RDIE_SHIFT (1U)
#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
#define LPI2C_SIER_AVIE_MASK (0x4U)
#define LPI2C_SIER_AVIE_SHIFT (2U)
#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
#define LPI2C_SIER_TAIE_MASK (0x8U)
#define LPI2C_SIER_TAIE_SHIFT (3U)
#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
#define LPI2C_SIER_RSIE_MASK (0x100U)
#define LPI2C_SIER_RSIE_SHIFT (8U)
#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
#define LPI2C_SIER_SDIE_MASK (0x200U)
#define LPI2C_SIER_SDIE_SHIFT (9U)
#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
#define LPI2C_SIER_BEIE_MASK (0x400U)
#define LPI2C_SIER_BEIE_SHIFT (10U)
#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
#define LPI2C_SIER_FEIE_MASK (0x800U)
#define LPI2C_SIER_FEIE_SHIFT (11U)
#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
#define LPI2C_SIER_AM0IE_MASK (0x1000U)
#define LPI2C_SIER_AM0IE_SHIFT (12U)
#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
#define LPI2C_SIER_AM1F_MASK (0x2000U)
#define LPI2C_SIER_AM1F_SHIFT (13U)
#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
#define LPI2C_SIER_GCIE_MASK (0x4000U)
#define LPI2C_SIER_GCIE_SHIFT (14U)
#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
#define LPI2C_SIER_SARIE_MASK (0x8000U)
#define LPI2C_SIER_SARIE_SHIFT (15U)
#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
/*! @name SDER - Slave DMA Enable Register */
#define LPI2C_SDER_TDDE_MASK (0x1U)
#define LPI2C_SDER_TDDE_SHIFT (0U)
#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
#define LPI2C_SDER_RDDE_MASK (0x2U)
#define LPI2C_SDER_RDDE_SHIFT (1U)
#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
#define LPI2C_SDER_AVDE_MASK (0x4U)
#define LPI2C_SDER_AVDE_SHIFT (2U)
#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
/*! @name SCFGR1 - Slave Configuration Register 1 */
#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)
#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)
#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U)
#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U)
#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)
#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)
#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)
#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)
#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
#define LPI2C_SCFGR1_GCEN_MASK (0x100U)
#define LPI2C_SCFGR1_GCEN_SHIFT (8U)
#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
#define LPI2C_SCFGR1_SAEN_MASK (0x200U)
#define LPI2C_SCFGR1_SAEN_SHIFT (9U)
#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
#define LPI2C_SCFGR1_TXCFG_MASK (0x400U)
#define LPI2C_SCFGR1_TXCFG_SHIFT (10U)
#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
#define LPI2C_SCFGR1_RXCFG_MASK (0x800U)
#define LPI2C_SCFGR1_RXCFG_SHIFT (11U)
#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U)
#define LPI2C_SCFGR1_IGNACK_SHIFT (12U)
#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U)
#define LPI2C_SCFGR1_HSMEN_SHIFT (13U)
#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)
#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)
#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
/*! @name SCFGR2 - Slave Configuration Register 2 */
#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)
#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)
#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)
#define LPI2C_SCFGR2_DATAVD_SHIFT (8U)
#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)
#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U)
#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)
#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U)
#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
/*! @name SAMR - Slave Address Match Register */
#define LPI2C_SAMR_ADDR0_MASK (0x7FEU)
#define LPI2C_SAMR_ADDR0_SHIFT (1U)
#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)
#define LPI2C_SAMR_ADDR1_SHIFT (17U)
#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
/*! @name SASR - Slave Address Status Register */
#define LPI2C_SASR_RADDR_MASK (0x7FFU)
#define LPI2C_SASR_RADDR_SHIFT (0U)
#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
#define LPI2C_SASR_ANV_MASK (0x4000U)
#define LPI2C_SASR_ANV_SHIFT (14U)
#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
/*! @name STAR - Slave Transmit ACK Register */
#define LPI2C_STAR_TXNACK_MASK (0x1U)
#define LPI2C_STAR_TXNACK_SHIFT (0U)
#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
/*! @name STDR - Slave Transmit Data Register */
#define LPI2C_STDR_DATA_MASK (0xFFU)
#define LPI2C_STDR_DATA_SHIFT (0U)
#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
/*! @name SRDR - Slave Receive Data Register */
#define LPI2C_SRDR_DATA_MASK (0xFFU)
#define LPI2C_SRDR_DATA_SHIFT (0U)
#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U)
#define LPI2C_SRDR_RXEMPTY_SHIFT (14U)
#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
#define LPI2C_SRDR_SOF_MASK (0x8000U)
#define LPI2C_SRDR_SOF_SHIFT (15U)
#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
#endif /* __ASM_ARCH_IMX_I2C_H__ */

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/*
* Based on Linux i.MX iomux-v3.h file:
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
* <armlinux@phytec.de>
*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MACH_IOMUX_H__
#define __MACH_IOMUX_H__
/*
* build IOMUX_PAD structure
*
* This iomux scheme is based around pads, which are the physical balls
* on the processor.
*
* - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
* things like driving strength and pullup/pulldown.
* - Each pad can have but not necessarily does have an output routing register
* (IOMUXC_SW_MUX_CTL_PAD_x).
* - Each pad can have but not necessarily does have an input routing register
* (IOMUXC_x_SELECT_INPUT)
*
* The three register sets do not have a fixed offset to each other,
* hence we order this table by pad control registers (which all pads
* have) and put the optional i/o routing registers into additional
* fields.
*
* The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
*
* IOMUX/PAD Bit field definitions
*
* MUX_CTRL_OFS: 0..15 (16)
* SEL_INPUT_OFS: 16..31 (16)
* MUX_MODE: 32..37 (6)
* SEL_INP: 38..41 (4)
* PAD_CTRL + NO_PAD_CTRL: 42..60 (19)
* reserved: 61-63 (3)
*/
typedef u64 iomux_cfg_t;
#define MUX_CTRL_OFS_SHIFT 0
#define MUX_CTRL_OFS_MASK ((iomux_cfg_t)0xffff << MUX_CTRL_OFS_SHIFT)
#define MUX_SEL_INPUT_OFS_SHIFT 16
#define MUX_SEL_INPUT_OFS_MASK ((iomux_cfg_t)0xffff << \
MUX_SEL_INPUT_OFS_SHIFT)
#define MUX_MODE_SHIFT 32
#define MUX_MODE_MASK ((iomux_cfg_t)0x3f << MUX_MODE_SHIFT)
#define MUX_SEL_INPUT_SHIFT 38
#define MUX_SEL_INPUT_MASK ((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
#define MUX_PAD_CTRL_SHIFT 42
#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT)
#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
sel_input, pad_ctrl) \
(((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
((iomux_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
((iomux_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
((iomux_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \
MUX_PAD_CTRL(pad))
#define IOMUX_CONFIG_MPORTS 0x20
#define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \
MUX_MODE_SHIFT)
/* Bit definition below needs to be fixed acccording to ulp rm */
#define NO_PAD_CTRL (1 << 18)
#define PAD_CTL_OBE_ENABLE (1 << 17)
#define PAD_CTL_IBE_ENABLE (1 << 16)
#define PAD_CTL_DSE (1 << 6)
#define PAD_CTL_ODE (1 << 5)
#define PAD_CTL_SRE_FAST (0 << 2)
#define PAD_CTL_SRE_SLOW (1 << 2)
#define PAD_CTL_PUE (1 << 1)
#define PAD_CTL_PUS_UP ((1 << 0) | PAD_CTL_PUE)
#define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE)
void mx7ulp_iomux_setup_pad(iomux_cfg_t pad);
void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list,
unsigned count);
#endif /* __MACH_IOMUX_H__*/

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/*
* Copyright 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_IMX7ULP_PINS_H__
#define __ASM_ARCH_IMX7ULP_PINS_H__
#include <asm/arch/iomux.h>
enum {
MX7ULP_PAD_PTA0__CMP0_IN1_3V = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA0__PTA0 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA0__LPSPI0_PCS1 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x2, 0),
MX7ULP_PAD_PTA0__LPUART0_CTS_b = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x2, 0),
MX7ULP_PAD_PTA0__LPI2C0_SCL = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x2, 0),
MX7ULP_PAD_PTA0__TPM0_CLKIN = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x2, 0),
MX7ULP_PAD_PTA0__I2S0_RX_BCLK = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x2, 0),
MX7ULP_PAD_PTA0__LLWU0_P0 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA1__CMP0_IN2_3V = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA1__PTA1 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA1__LPSPI0_PCS2 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x1, 0),
MX7ULP_PAD_PTA1__LPUART0_RTS_b = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA1__LPI2C0_SDA = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x1, 0),
MX7ULP_PAD_PTA1__TPM0_CH0 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x1, 0),
MX7ULP_PAD_PTA1__I2S0_RX_FS = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x1, 0),
MX7ULP_PAD_PTA2__CMP1_IN2_3V = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA2__PTA2 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA2__LPSPI0_PCS3 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x1, 0),
MX7ULP_PAD_PTA2__LPUART0_TX = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x1, 0),
MX7ULP_PAD_PTA2__LPI2C0_HREQ = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x1, 0),
MX7ULP_PAD_PTA2__TPM0_CH1 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x1, 0),
MX7ULP_PAD_PTA2__I2S0_RXD0 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x7, 0xD1DC, 0x1, 0),
MX7ULP_PAD_PTA3__CMP1_IN4_3V = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA3__PTA3 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA3__LPSPI0_PCS0 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x1, 0),
MX7ULP_PAD_PTA3__LPUART0_RX = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x1, 0),
MX7ULP_PAD_PTA3__TPM0_CH2 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x6, 0xD140, 0x1, 0),
MX7ULP_PAD_PTA3__I2S0_RXD1 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E0, 0x1, 0),
MX7ULP_PAD_PTA3__CMP0_OUT = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA3__LLWU0_P1 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA4__ADC1_CH3A = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA4__PTA4 = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA4__LPSPI0_SIN = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x1, 0),
MX7ULP_PAD_PTA4__LPUART1_CTS_b = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x1, 0),
MX7ULP_PAD_PTA4__LPI2C1_SCL = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x1, 0),
MX7ULP_PAD_PTA4__TPM0_CH3 = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x1, 0),
MX7ULP_PAD_PTA4__I2S0_MCLK = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x1, 0),
MX7ULP_PAD_PTA5__ADC1_CH3B = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA5__PTA5 = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA5__LPSPI0_SOUT = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x1, 0),
MX7ULP_PAD_PTA5__LPUART1_RTS_b = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA5__LPI2C1_SDA = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x1, 0),
MX7ULP_PAD_PTA5__TPM0_CH4 = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x1, 0),
MX7ULP_PAD_PTA5__I2S0_TX_BCLK = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C0, 0x1, 0),
MX7ULP_PAD_PTA6__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA6__PTA6 = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA6__LPSPI0_SCK = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x1, 0),
MX7ULP_PAD_PTA6__LPUART1_TX = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x1, 0),
MX7ULP_PAD_PTA6__LPI2C1_HREQ = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x1, 0),
MX7ULP_PAD_PTA6__TPM0_CH5 = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x6, 0xD14C, 0x1, 0),
MX7ULP_PAD_PTA6__I2S0_TX_FS = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x1, 0),
MX7ULP_PAD_PTA7__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA7__PTA7 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA7__LPUART1_RX = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x1, 0),
MX7ULP_PAD_PTA7__TPM1_CH1 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x1, 0),
MX7ULP_PAD_PTA7__I2S0_TXD0 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA8__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA8__PTA8 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA8__LPSPI1_PCS1 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x1, 0),
MX7ULP_PAD_PTA8__LPUART2_CTS_b = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x1, 0),
MX7ULP_PAD_PTA8__LPI2C2_SCL = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x1, 0),
MX7ULP_PAD_PTA8__TPM1_CLKIN = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x1, 0),
MX7ULP_PAD_PTA8__I2S0_TXD1 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA9__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA9__PTA9 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA9__LPSPI1_PCS2 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x1, 0),
MX7ULP_PAD_PTA9__LPUART2_RTS_b = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA9__LPI2C2_SDA = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x1, 0),
MX7ULP_PAD_PTA9__TPM1_CH0 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x1, 0),
MX7ULP_PAD_PTA9__NMI0_b = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA10__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA10__PTA10 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA10__LPSPI1_PCS3 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x1, 0),
MX7ULP_PAD_PTA10__LPUART2_TX = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x1, 0),
MX7ULP_PAD_PTA10__LPI2C2_HREQ = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x1, 0),
MX7ULP_PAD_PTA10__TPM2_CLKIN = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x1, 0),
MX7ULP_PAD_PTA10__I2S0_RX_BCLK = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x1, 0),
MX7ULP_PAD_PTA11__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA11__PTA11 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA11__LPUART2_RX = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x1, 0),
MX7ULP_PAD_PTA11__TPM2_CH0 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x1, 0),
MX7ULP_PAD_PTA11__I2S0_RX_FS = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x2, 0),
MX7ULP_PAD_PTA12__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA12__PTA12 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA12__LPSPI1_SIN = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x1, 0),
MX7ULP_PAD_PTA12__LPUART3_CTS_b = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x1, 0),
MX7ULP_PAD_PTA12__LPI2C3_SCL = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x1, 0),
MX7ULP_PAD_PTA12__TPM2_CH1 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x1, 0),
MX7ULP_PAD_PTA12__I2S0_RXD0 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x7, 0xD1DC, 0x2, 0),
MX7ULP_PAD_PTA13__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA13__PTA13 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA13__LPSPI1_SOUT = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x2, 0),
MX7ULP_PAD_PTA13__LPUART3_RTS_b = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA13__LPI2C3_SDA = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x2, 0),
MX7ULP_PAD_PTA13__TPM3_CLKIN = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x1, 0),
MX7ULP_PAD_PTA13__I2S0_RXD1 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E0, 0x2, 0),
MX7ULP_PAD_PTA13__CMP0_OUT = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA13__LLWU0_P2 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA14__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA14__PTA14 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA14__LPSPI1_SCK = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x2, 0),
MX7ULP_PAD_PTA14__LPUART3_TX = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x2, 0),
MX7ULP_PAD_PTA14__LPI2C3_HREQ = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x2, 0),
MX7ULP_PAD_PTA14__TPM3_CH0 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x1, 0),
MX7ULP_PAD_PTA14__I2S0_MCLK = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x2, 0),
MX7ULP_PAD_PTA14__LLWU0_P3 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA15__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA15__PTA15 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA15__LPSPI1_PCS0 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x1, 0),
MX7ULP_PAD_PTA15__LPUART3_RX = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x1, 0),
MX7ULP_PAD_PTA15__TPM3_CH1 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x1, 0),
MX7ULP_PAD_PTA15__I2S0_TX_BCLK = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C0, 0x2, 0),
MX7ULP_PAD_PTA16__CMP1_IN5_3V = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA16__PTA16 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA16__FXIO0_D0 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA16__LPSPI0_SOUT = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x2, 0),
MX7ULP_PAD_PTA16__LPUART0_CTS_b = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x1, 0),
MX7ULP_PAD_PTA16__LPI2C0_SCL = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x1, 0),
MX7ULP_PAD_PTA16__TPM3_CH2 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x6, 0xD168, 0x1, 0),
MX7ULP_PAD_PTA16__I2S0_TX_FS = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x2, 0),
MX7ULP_PAD_PTA17__CMP1_IN6_3V = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA17__PTA17 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA17__FXIO0_D1 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA17__LPSPI0_SCK = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x2, 0),
MX7ULP_PAD_PTA17__LPUART0_RTS_b = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA17__LPI2C0_SDA = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x2, 0),
MX7ULP_PAD_PTA17__TPM3_CH3 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x6, 0xD16C, 0x1, 0),
MX7ULP_PAD_PTA17__I2S0_TXD0 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA18__CMP1_IN1_3V = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA18__PTA18 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA18__FXIO0_D2 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA18__LPSPI0_PCS0 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x2, 0),
MX7ULP_PAD_PTA18__LPUART0_TX = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x2, 0),
MX7ULP_PAD_PTA18__LPI2C0_HREQ = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x2, 0),
MX7ULP_PAD_PTA18__TPM3_CH4 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x6, 0xD170, 0x1, 0),
MX7ULP_PAD_PTA18__I2S0_TXD1 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA18__LLWU0_P4 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA19__CMP1_IN3_3V = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA19__PTA19 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA19__FXIO0_D3 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA19__LPUART0_RX = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x2, 0),
MX7ULP_PAD_PTA19__TPM3_CH5 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x6, 0xD174, 0x1, 0),
MX7ULP_PAD_PTA19__I2S1_RX_BCLK = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1CC, 0x1, 0),
MX7ULP_PAD_PTA19__LPTMR0_ALT3 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA19__LLWU0_P5 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA20__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA20__PTA20 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA20__FXIO0_D4 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA20__LPSPI0_SIN = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x2, 0),
MX7ULP_PAD_PTA20__LPUART1_CTS_b = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x2, 0),
MX7ULP_PAD_PTA20__LPI2C1_SCL = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x2, 0),
MX7ULP_PAD_PTA20__TPM0_CLKIN = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x1, 0),
MX7ULP_PAD_PTA20__I2S1_RX_FS = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D0, 0x1, 0),
MX7ULP_PAD_PTA21__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA21__PTA21 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA21__FXIO0_D5 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA21__LPSPI0_PCS1 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x1, 0),
MX7ULP_PAD_PTA21__LPUART1_RTS_b = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA21__LPI2C1_SDA = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x2, 0),
MX7ULP_PAD_PTA21__TPM0_CH0 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x2, 0),
MX7ULP_PAD_PTA21__I2S1_RXD0 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E4, 0x1, 0),
MX7ULP_PAD_PTA22__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA22__PTA22 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA22__FXIO0_D6 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA22__LPSPI0_PCS2 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x2, 0),
MX7ULP_PAD_PTA22__LPUART1_TX = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x2, 0),
MX7ULP_PAD_PTA22__LPI2C1_HREQ = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x2, 0),
MX7ULP_PAD_PTA22__TPM0_CH1 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x2, 0),
MX7ULP_PAD_PTA22__I2S1_RXD1 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E8, 0x1, 0),
MX7ULP_PAD_PTA22__LPTMR0_ALT2 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA22__EWM_OUT_b = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA23__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA23__PTA23 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA23__FXIO0_D7 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA23__LPSPI0_PCS3 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x2, 0),
MX7ULP_PAD_PTA23__LPUART1_RX = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x2, 0),
MX7ULP_PAD_PTA23__TPM0_CH2 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x6, 0xD140, 0x2, 0),
MX7ULP_PAD_PTA23__I2S1_MCLK = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C8, 0x1, 0),
MX7ULP_PAD_PTA23__LLWU0_P6 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA24__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA24__PTA24 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA24__FXIO0_D8 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA24__LPSPI1_PCS1 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x2, 0),
MX7ULP_PAD_PTA24__LPUART2_CTS_b = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x2, 0),
MX7ULP_PAD_PTA24__LPI2C2_SCL = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x2, 0),
MX7ULP_PAD_PTA24__TPM0_CH3 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x2, 0),
MX7ULP_PAD_PTA24__I2S1_TX_BCLK = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D4, 0x1, 0),
MX7ULP_PAD_PTA25__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA25__PTA25 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA25__FXIO0_D9 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA25__LPSPI1_PCS2 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x2, 0),
MX7ULP_PAD_PTA25__LPUART2_RTS_b = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA25__LPI2C2_SDA = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x2, 0),
MX7ULP_PAD_PTA25__TPM0_CH4 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x2, 0),
MX7ULP_PAD_PTA25__I2S1_TX_FS = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x1, 0),
MX7ULP_PAD_PTA26__PTA26 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA26__JTAG_TMS_SWD_DIO = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA26__FXIO0_D10 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA26__LPSPI1_PCS3 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x2, 0),
MX7ULP_PAD_PTA26__LPUART2_TX = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x2, 0),
MX7ULP_PAD_PTA26__LPI2C2_HREQ = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x2, 0),
MX7ULP_PAD_PTA26__TPM0_CH5 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x6, 0xD14C, 0x2, 0),
MX7ULP_PAD_PTA26__I2S1_RXD2 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x7, 0xD1EC, 0x1, 0),
MX7ULP_PAD_PTA27__PTA27 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA27__JTAG_TDO = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA27__FXIO0_D11 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA27__LPUART2_RX = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x2, 0),
MX7ULP_PAD_PTA27__TPM1_CH1 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x2, 0),
MX7ULP_PAD_PTA27__I2S1_RXD3 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1F0, 0x1, 0),
MX7ULP_PAD_PTA28__PTA28 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA28__JTAG_TDI = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA28__FXIO0_D12 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA28__LPSPI1_SIN = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x2, 0),
MX7ULP_PAD_PTA28__LPUART3_CTS_b = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x2, 0),
MX7ULP_PAD_PTA28__LPI2C3_SCL = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x2, 0),
MX7ULP_PAD_PTA28__TPM1_CLKIN = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x2, 0),
MX7ULP_PAD_PTA28__I2S1_TXD2 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA29__PTA29 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA29__JTAG_TCLK_SWD_CLK = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA29__FXIO0_D13 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA29__LPSPI1_SOUT = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x1, 0),
MX7ULP_PAD_PTA29__LPUART3_RTS_b = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA29__LPI2C3_SDA = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x1, 0),
MX7ULP_PAD_PTA29__TPM1_CH0 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x2, 0),
MX7ULP_PAD_PTA29__I2S1_TXD3 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA30__ADC0_CH1A = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA30__PTA30 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA30__FXIO0_D14 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA30__LPSPI1_SCK = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x1, 0),
MX7ULP_PAD_PTA30__LPUART3_TX = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x1, 0),
MX7ULP_PAD_PTA30__LPI2C3_HREQ = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x1, 0),
MX7ULP_PAD_PTA30__TPM2_CLKIN = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x2, 0),
MX7ULP_PAD_PTA30__I2S1_TXD0 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA30__JTAG_TRST_b = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA31__ADC0_CH1B = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA31__PTA31 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA31__FXIO0_D15 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA31__LPSPI1_PCS0 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x2, 0),
MX7ULP_PAD_PTA31__LPUART3_RX = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x2, 0),
MX7ULP_PAD_PTA31__TPM2_CH0 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x2, 0),
MX7ULP_PAD_PTA31__I2S1_TXD1 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA31__LPTMR0_ALT1 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTA31__EWM_IN = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xc, 0xD228, 0x1, 0),
MX7ULP_PAD_PTA31__LLWU0_P7 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB0__ADC0_CH0A = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB0__PTB0 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB0__FXIO0_D16 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB0__LPSPI0_SIN = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x3, 0),
MX7ULP_PAD_PTB0__LPUART0_TX = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x3, 0),
MX7ULP_PAD_PTB0__TPM2_CH1 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x2, 0),
MX7ULP_PAD_PTB0__CLKOUT0 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB0__CMP1_OUT = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB0__EWM_OUT_b = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB1__ADC0_CH0B = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB1__PTB1 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB1__FXIO0_D17 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB1__LPSPI0_SOUT = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x3, 0),
MX7ULP_PAD_PTB1__LPUART0_RX = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x3, 0),
MX7ULP_PAD_PTB1__TPM3_CLKIN = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x3, 0),
MX7ULP_PAD_PTB1__I2S1_TX_BCLK = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D4, 0x2, 0),
MX7ULP_PAD_PTB1__RTC_CLKOUT = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB1__EWM_IN = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xc, 0xD228, 0x2, 0),
MX7ULP_PAD_PTB1__LLWU0_P8 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB2__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB2__PTB2 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB2__FXIO0_D18 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB2__LPSPI0_SCK = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x3, 0),
MX7ULP_PAD_PTB2__LPUART1_TX = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x3, 0),
MX7ULP_PAD_PTB2__TPM3_CH0 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x2, 0),
MX7ULP_PAD_PTB2__I2S1_TX_FS = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x2, 0),
MX7ULP_PAD_PTB2__TRACE_CLKOUT = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB3__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB3__PTB3 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB3__FXIO0_D19 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB3__LPSPI0_PCS0 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x3, 0),
MX7ULP_PAD_PTB3__LPUART1_RX = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x3, 0),
MX7ULP_PAD_PTB3__TPM3_CH1 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x2, 0),
MX7ULP_PAD_PTB3__I2S1_TXD0 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB3__TRACE_D0 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB3__LPTMR1_ALT2 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB3__LLWU0_P9 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB4__PTB4 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB4__FXIO0_D20 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB4__LPSPI0_PCS1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x3, 0),
MX7ULP_PAD_PTB4__LPUART2_TX = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x3, 0),
MX7ULP_PAD_PTB4__LPI2C0_HREQ = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x3, 0),
MX7ULP_PAD_PTB4__TPM3_CH2 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x6, 0xD168, 0x2, 0),
MX7ULP_PAD_PTB4__I2S1_TXD1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB4__QSPIA_DATA7 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB4__TRACE_D1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB5__PTB5 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB5__FXIO0_D21 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB5__LPSPI0_PCS2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x3, 0),
MX7ULP_PAD_PTB5__LPUART2_RX = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x3, 0),
MX7ULP_PAD_PTB5__LPI2C1_HREQ = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x3, 0),
MX7ULP_PAD_PTB5__TPM3_CH3 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x6, 0xD16C, 0x2, 0),
MX7ULP_PAD_PTB5__I2S1_TXD2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB5__QSPIA_DATA6 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB5__TRACE_D2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB6__ADC1_CH1A = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB6__PTB6 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB6__FXIO0_D22 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB6__LPSPI0_PCS3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x3, 0),
MX7ULP_PAD_PTB6__LPUART3_TX = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x3, 0),
MX7ULP_PAD_PTB6__LPI2C0_SCL = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x3, 0),
MX7ULP_PAD_PTB6__TPM3_CH4 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x6, 0xD170, 0x2, 0),
MX7ULP_PAD_PTB6__I2S1_TXD3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB6__QSPIA_DATA5 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB6__TRACE_D3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB6__LPTMR1_ALT3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB6__LLWU0_P10 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB7__ADC1_CH1B = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB7__PTB7 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB7__FXIO0_D23 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB7__LPSPI1_SIN = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x3, 0),
MX7ULP_PAD_PTB7__LPUART3_RX = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x3, 0),
MX7ULP_PAD_PTB7__LPI2C0_SDA = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x3, 0),
MX7ULP_PAD_PTB7__TPM3_CH5 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x6, 0xD174, 0x2, 0),
MX7ULP_PAD_PTB7__I2S1_MCLK = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C8, 0x2, 0),
MX7ULP_PAD_PTB7__QSPIA_SS1_B = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB7__CMP1_OUT = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB7__LLWU0_P11 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB8__ADC0_CH14A_CMP0_IN0 = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB8__PTB8 = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB8__FXIO0_D24 = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB8__LPSPI1_SOUT = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x3, 0),
MX7ULP_PAD_PTB8__LPI2C1_SCL = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x3, 0),
MX7ULP_PAD_PTB8__TPM0_CLKIN = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x3, 0),
MX7ULP_PAD_PTB8__I2S1_RX_BCLK = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x7, 0xD1CC, 0x2, 0),
MX7ULP_PAD_PTB8__QSPIA_SS0_B = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB8__RTC_CLKOUT = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB9__ADC0_CH14B_CMP0_IN2 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB9__PTB9 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB9__FXIO0_D25 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB9__LPSPI1_SCK = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x3, 0),
MX7ULP_PAD_PTB9__LPI2C1_SDA = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x3, 0),
MX7ULP_PAD_PTB9__TPM0_CH0 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x3, 0),
MX7ULP_PAD_PTB9__I2S1_RX_FS = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D0, 0x2, 0),
MX7ULP_PAD_PTB9__QSPIA_DQS = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB9__LLWU0_P12 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB10__CMP0_IN1 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB10__PTB10 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB10__FXIO0_D26 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB10__LPSPI1_PCS0 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x3, 0),
MX7ULP_PAD_PTB10__LPI2C2_SCL = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x3, 0),
MX7ULP_PAD_PTB10__TPM0_CH1 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x3, 0),
MX7ULP_PAD_PTB10__I2S1_RXD0 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E4, 0x2, 0),
MX7ULP_PAD_PTB10__TRACE_D4 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB11__CMP0_IN3 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB11__PTB11 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB11__FXIO0_D27 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB11__LPSPI1_PCS1 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x3, 0),
MX7ULP_PAD_PTB11__LPI2C2_SDA = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x3, 0),
MX7ULP_PAD_PTB11__TPM1_CLKIN = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x3, 0),
MX7ULP_PAD_PTB11__I2S1_RXD1 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E8, 0x2, 0),
MX7ULP_PAD_PTB11__TRACE_D5 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB12__ADC1_CH13A_CMP1_IN0 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB12__PTB12 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB12__FXIO0_D28 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB12__LPSPI1_PCS2 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x3, 0),
MX7ULP_PAD_PTB12__LPI2C3_SCL = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x3, 0),
MX7ULP_PAD_PTB12__TPM1_CH0 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x3, 0),
MX7ULP_PAD_PTB12__I2S1_RXD2 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x7, 0xD1EC, 0x2, 0),
MX7ULP_PAD_PTB12__TRACE_D6 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB13__ADC1_CH13B_CMP1_IN1 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB13__PTB13 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB13__FXIO0_D29 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB13__LPSPI1_PCS3 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x3, 0),
MX7ULP_PAD_PTB13__LPI2C3_SDA = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x3, 0),
MX7ULP_PAD_PTB13__TPM1_CH1 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x3, 0),
MX7ULP_PAD_PTB13__I2S1_RXD3 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x7, 0xD1F0, 0x2, 0),
MX7ULP_PAD_PTB13__QSPIA_DATA4 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB13__TRACE_D7 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB14__ADC1_CH2A = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB14__PTB14 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB14__FXIO0_D30 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB14__LPI2C2_HREQ = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x3, 0),
MX7ULP_PAD_PTB14__TPM2_CLKIN = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x3, 0),
MX7ULP_PAD_PTB14__QSPIA_SS1_B = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB14__QSPIA_SCLK_b = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB14__LLWU0_P13 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB15__ADC1_CH2B = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB15__PTB15 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB15__FXIO0_D31 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB15__LPI2C3_HREQ = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x3, 0),
MX7ULP_PAD_PTB15__TPM2_CH0 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x3, 0),
MX7ULP_PAD_PTB15__QSPIA_SCLK = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB16__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB16__PTB16 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB16__TPM2_CH1 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x3, 0),
MX7ULP_PAD_PTB16__QSPIA_DATA3 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB16__LLWU0_P14 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB17__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB17__PTB17 = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB17__TPM3_CLKIN = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x2, 0),
MX7ULP_PAD_PTB17__QSPIA_DATA2 = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB18__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB18__PTB18 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB18__TPM3_CH0 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x3, 0),
MX7ULP_PAD_PTB18__QSPIA_DATA1 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB19__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB19__PTB19 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB19__TPM3_CH1 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x3, 0),
MX7ULP_PAD_PTB19__QSPIA_DATA0 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB19__USB0_ID = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTB19__LLWU0_P15 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC0__PTC0 = IOMUX_PAD(0x0000, 0x0000, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC0__LPUART4_CTS_b = IOMUX_PAD(0x0000, 0x0000, 0x4, 0x0244, 0x1, 0),
MX7ULP_PAD_PTC0__LPI2C4_SCL = IOMUX_PAD(0x0000, 0x0000, 0x5, 0x0278, 0x1, 0),
MX7ULP_PAD_PTC0__TPM4_CLKIN = IOMUX_PAD(0x0000, 0x0000, 0x6, 0x0298, 0x1, 0),
MX7ULP_PAD_PTC0__FB_AD0 = IOMUX_PAD(0x0000, 0x0000, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC0__TRACE_D15 = IOMUX_PAD(0x0000, 0x0000, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC0__DEBUG_MUX0 = IOMUX_PAD(0x0000, 0x0000, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC1__PTC1 = IOMUX_PAD(0x0004, 0x0004, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC1__LPUART4_RTS_b = IOMUX_PAD(0x0004, 0x0004, 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC1__LPI2C4_SDA = IOMUX_PAD(0x0004, 0x0004, 0x5, 0x027C, 0x1, 0),
MX7ULP_PAD_PTC1__TPM4_CH0 = IOMUX_PAD(0x0004, 0x0004, 0x6, 0x0280, 0x1, 0),
MX7ULP_PAD_PTC1__FB_AD1 = IOMUX_PAD(0x0004, 0x0004, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC1__TRACE_D14 = IOMUX_PAD(0x0004, 0x0004, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC1__DEBUG_MUX1 = IOMUX_PAD(0x0004, 0x0004, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC2__PTC2 = IOMUX_PAD(0x0008, 0x0008, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC2__LPUART4_TX = IOMUX_PAD(0x0008, 0x0008, 0x4, 0x024C, 0x1, 0),
MX7ULP_PAD_PTC2__LPI2C4_HREQ = IOMUX_PAD(0x0008, 0x0008, 0x5, 0x0274, 0x1, 0),
MX7ULP_PAD_PTC2__TPM4_CH1 = IOMUX_PAD(0x0008, 0x0008, 0x6, 0x0284, 0x1, 0),
MX7ULP_PAD_PTC2__FB_AD2 = IOMUX_PAD(0x0008, 0x0008, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC2__TRACE_D13 = IOMUX_PAD(0x0008, 0x0008, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC2__DEBUG_MUX2 = IOMUX_PAD(0x0008, 0x0008, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC3__PTC3 = IOMUX_PAD(0x000C, 0x000C, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC3__LPUART4_RX = IOMUX_PAD(0x000C, 0x000C, 0x4, 0x0248, 0x1, 0),
MX7ULP_PAD_PTC3__TPM4_CH2 = IOMUX_PAD(0x000C, 0x000C, 0x6, 0x0288, 0x1, 0),
MX7ULP_PAD_PTC3__FB_AD3 = IOMUX_PAD(0x000C, 0x000C, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC3__TRACE_D12 = IOMUX_PAD(0x000C, 0x000C, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC3__DEBUG_MUX3 = IOMUX_PAD(0x000C, 0x000C, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC4__PTC4 = IOMUX_PAD(0x0010, 0x0010, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC4__FXIO1_D0 = IOMUX_PAD(0x0010, 0x0010, 0x2, 0x0204, 0x1, 0),
MX7ULP_PAD_PTC4__LPSPI2_PCS1 = IOMUX_PAD(0x0010, 0x0010, 0x3, 0x02A0, 0x1, 0),
MX7ULP_PAD_PTC4__LPUART5_CTS_b = IOMUX_PAD(0x0010, 0x0010, 0x4, 0x0250, 0x1, 0),
MX7ULP_PAD_PTC4__LPI2C5_SCL = IOMUX_PAD(0x0010, 0x0010, 0x5, 0x02BC, 0x1, 0),
MX7ULP_PAD_PTC4__TPM4_CH3 = IOMUX_PAD(0x0010, 0x0010, 0x6, 0x028C, 0x1, 0),
MX7ULP_PAD_PTC4__FB_AD4 = IOMUX_PAD(0x0010, 0x0010, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC4__TRACE_D11 = IOMUX_PAD(0x0010, 0x0010, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC4__DEBUG_MUX4 = IOMUX_PAD(0x0010, 0x0010, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC5__PTC5 = IOMUX_PAD(0x0014, 0x0014, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC5__FXIO1_D1 = IOMUX_PAD(0x0014, 0x0014, 0x2, 0x0208, 0x1, 0),
MX7ULP_PAD_PTC5__LPSPI2_PCS2 = IOMUX_PAD(0x0014, 0x0014, 0x3, 0x02A4, 0x1, 0),
MX7ULP_PAD_PTC5__LPUART5_RTS_b = IOMUX_PAD(0x0014, 0x0014, 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC5__LPI2C5_SDA = IOMUX_PAD(0x0014, 0x0014, 0x5, 0x02C0, 0x1, 0),
MX7ULP_PAD_PTC5__TPM4_CH4 = IOMUX_PAD(0x0014, 0x0014, 0x6, 0x0290, 0x1, 0),
MX7ULP_PAD_PTC5__FB_AD5 = IOMUX_PAD(0x0014, 0x0014, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC5__TRACE_D10 = IOMUX_PAD(0x0014, 0x0014, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC5__DEBUG_MUX5 = IOMUX_PAD(0x0014, 0x0014, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC6__PTC6 = IOMUX_PAD(0x0018, 0x0018, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC6__FXIO1_D2 = IOMUX_PAD(0x0018, 0x0018, 0x2, 0x020C, 0x1, 0),
MX7ULP_PAD_PTC6__LPSPI2_PCS3 = IOMUX_PAD(0x0018, 0x0018, 0x3, 0x02A8, 0x1, 0),
MX7ULP_PAD_PTC6__LPUART5_TX = IOMUX_PAD(0x0018, 0x0018, 0x4, 0x0258, 0x1, 0),
MX7ULP_PAD_PTC6__LPI2C5_HREQ = IOMUX_PAD(0x0018, 0x0018, 0x5, 0x02B8, 0x1, 0),
MX7ULP_PAD_PTC6__TPM4_CH5 = IOMUX_PAD(0x0018, 0x0018, 0x6, 0x0294, 0x1, 0),
MX7ULP_PAD_PTC6__FB_AD6 = IOMUX_PAD(0x0018, 0x0018, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC6__TRACE_D9 = IOMUX_PAD(0x0018, 0x0018, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC6__DEBUG_MUX6 = IOMUX_PAD(0x0018, 0x0018, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC7__PTC7 = IOMUX_PAD(0x001C, 0x001C, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC7__FXIO1_D3 = IOMUX_PAD(0x001C, 0x001C, 0x2, 0x0210, 0x1, 0),
MX7ULP_PAD_PTC7__LPUART5_RX = IOMUX_PAD(0x001C, 0x001C, 0x4, 0x0254, 0x1, 0),
MX7ULP_PAD_PTC7__TPM5_CH1 = IOMUX_PAD(0x001C, 0x001C, 0x6, 0x02C8, 0x1, 0),
MX7ULP_PAD_PTC7__FB_AD7 = IOMUX_PAD(0x001C, 0x001C, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC7__TRACE_D8 = IOMUX_PAD(0x001C, 0x001C, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC7__DEBUG_MUX7 = IOMUX_PAD(0x001C, 0x001C, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC8__PTC8 = IOMUX_PAD(0x0020, 0x0020, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC8__FXIO1_D4 = IOMUX_PAD(0x0020, 0x0020, 0x2, 0x0214, 0x1, 0),
MX7ULP_PAD_PTC8__LPSPI2_SIN = IOMUX_PAD(0x0020, 0x0020, 0x3, 0x02B0, 0x1, 0),
MX7ULP_PAD_PTC8__LPUART6_CTS_b = IOMUX_PAD(0x0020, 0x0020, 0x4, 0x025C, 0x1, 0),
MX7ULP_PAD_PTC8__LPI2C6_SCL = IOMUX_PAD(0x0020, 0x0020, 0x5, 0x02FC, 0x1, 0),
MX7ULP_PAD_PTC8__TPM5_CLKIN = IOMUX_PAD(0x0020, 0x0020, 0x6, 0x02CC, 0x1, 0),
MX7ULP_PAD_PTC8__FB_AD8 = IOMUX_PAD(0x0020, 0x0020, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC8__TRACE_D7 = IOMUX_PAD(0x0020, 0x0020, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC8__DEBUG_MUX8 = IOMUX_PAD(0x0020, 0x0020, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC9__PTC9 = IOMUX_PAD(0x0024, 0x0024, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC9__FXIO1_D5 = IOMUX_PAD(0x0024, 0x0024, 0x2, 0x0218, 0x1, 0),
MX7ULP_PAD_PTC9__LPSPI2_SOUT = IOMUX_PAD(0x0024, 0x0024, 0x3, 0x02B4, 0x1, 0),
MX7ULP_PAD_PTC9__LPUART6_RTS_b = IOMUX_PAD(0x0024, 0x0024, 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC9__LPI2C6_SDA = IOMUX_PAD(0x0024, 0x0024, 0x5, 0x0300, 0x1, 0),
MX7ULP_PAD_PTC9__TPM5_CH0 = IOMUX_PAD(0x0024, 0x0024, 0x6, 0x02C4, 0x1, 0),
MX7ULP_PAD_PTC9__FB_AD9 = IOMUX_PAD(0x0024, 0x0024, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC9__TRACE_D6 = IOMUX_PAD(0x0024, 0x0024, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC9__DEBUG_MUX9 = IOMUX_PAD(0x0024, 0x0024, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC10__PTC10 = IOMUX_PAD(0x0028, 0x0028, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC10__FXIO1_D6 = IOMUX_PAD(0x0028, 0x0028, 0x2, 0x021C, 0x1, 0),
MX7ULP_PAD_PTC10__LPSPI2_SCK = IOMUX_PAD(0x0028, 0x0028, 0x3, 0x02AC, 0x1, 0),
MX7ULP_PAD_PTC10__LPUART6_TX = IOMUX_PAD(0x0028, 0x0028, 0x4, 0x0264, 0x1, 0),
MX7ULP_PAD_PTC10__LPI2C6_HREQ = IOMUX_PAD(0x0028, 0x0028, 0x5, 0x02F8, 0x1, 0),
MX7ULP_PAD_PTC10__TPM7_CH3 = IOMUX_PAD(0x0028, 0x0028, 0x6, 0x02E8, 0x1, 0),
MX7ULP_PAD_PTC10__FB_AD10 = IOMUX_PAD(0x0028, 0x0028, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC10__TRACE_D5 = IOMUX_PAD(0x0028, 0x0028, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC10__DEBUG_MUX10 = IOMUX_PAD(0x0028, 0x0028, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC11__PTC11 = IOMUX_PAD(0x002C, 0x002C, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC11__FXIO1_D7 = IOMUX_PAD(0x002C, 0x002C, 0x2, 0x0220, 0x1, 0),
MX7ULP_PAD_PTC11__LPSPI2_PCS0 = IOMUX_PAD(0x002C, 0x002C, 0x3, 0x029C, 0x1, 0),
MX7ULP_PAD_PTC11__LPUART6_RX = IOMUX_PAD(0x002C, 0x002C, 0x4, 0x0260, 0x1, 0),
MX7ULP_PAD_PTC11__TPM7_CH4 = IOMUX_PAD(0x002C, 0x002C, 0x6, 0x02EC, 0x1, 0),
MX7ULP_PAD_PTC11__FB_AD11 = IOMUX_PAD(0x002C, 0x002C, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC11__TRACE_D4 = IOMUX_PAD(0x002C, 0x002C, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC11__DEBUG_MUX11 = IOMUX_PAD(0x002C, 0x002C, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC12__PTC12 = IOMUX_PAD(0x0030, 0x0030, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC12__FXIO1_D8 = IOMUX_PAD(0x0030, 0x0030, 0x2, 0x0224, 0x1, 0),
MX7ULP_PAD_PTC12__LPSPI3_PCS1 = IOMUX_PAD(0x0030, 0x0030, 0x3, 0x0314, 0x1, 0),
MX7ULP_PAD_PTC12__LPUART7_CTS_b = IOMUX_PAD(0x0030, 0x0030, 0x4, 0x0268, 0x1, 0),
MX7ULP_PAD_PTC12__LPI2C7_SCL = IOMUX_PAD(0x0030, 0x0030, 0x5, 0x0308, 0x1, 0),
MX7ULP_PAD_PTC12__TPM7_CH5 = IOMUX_PAD(0x0030, 0x0030, 0x6, 0x02F0, 0x1, 0),
MX7ULP_PAD_PTC12__FB_AD12 = IOMUX_PAD(0x0030, 0x0030, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC12__TRACE_D3 = IOMUX_PAD(0x0030, 0x0030, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC12__DEBUG_MUX12 = IOMUX_PAD(0x0030, 0x0030, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC13__PTC13 = IOMUX_PAD(0x0034, 0x0034, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC13__FXIO1_D9 = IOMUX_PAD(0x0034, 0x0034, 0x2, 0x0228, 0x1, 0),
MX7ULP_PAD_PTC13__LPSPI3_PCS2 = IOMUX_PAD(0x0034, 0x0034, 0x3, 0x0318, 0x1, 0),
MX7ULP_PAD_PTC13__LPUART7_RTS_b = IOMUX_PAD(0x0034, 0x0034, 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC13__LPI2C7_SDA = IOMUX_PAD(0x0034, 0x0034, 0x5, 0x030C, 0x1, 0),
MX7ULP_PAD_PTC13__TPM7_CLKIN = IOMUX_PAD(0x0034, 0x0034, 0x6, 0x02F4, 0x1, 0),
MX7ULP_PAD_PTC13__FB_AD13 = IOMUX_PAD(0x0034, 0x0034, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC13__TRACE_D2 = IOMUX_PAD(0x0034, 0x0034, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC13__DEBUG_MUX13 = IOMUX_PAD(0x0034, 0x0034, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC14__PTC14 = IOMUX_PAD(0x0038, 0x0038, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC14__FXIO1_D10 = IOMUX_PAD(0x0038, 0x0038, 0x2, 0x022C, 0x1, 0),
MX7ULP_PAD_PTC14__LPSPI3_PCS3 = IOMUX_PAD(0x0038, 0x0038, 0x3, 0x031C, 0x1, 0),
MX7ULP_PAD_PTC14__LPUART7_TX = IOMUX_PAD(0x0038, 0x0038, 0x4, 0x0270, 0x1, 0),
MX7ULP_PAD_PTC14__LPI2C7_HREQ = IOMUX_PAD(0x0038, 0x0038, 0x5, 0x0304, 0x1, 0),
MX7ULP_PAD_PTC14__TPM7_CH0 = IOMUX_PAD(0x0038, 0x0038, 0x6, 0x02DC, 0x1, 0),
MX7ULP_PAD_PTC14__FB_AD14 = IOMUX_PAD(0x0038, 0x0038, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC14__TRACE_D1 = IOMUX_PAD(0x0038, 0x0038, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC14__DEBUG_MUX14 = IOMUX_PAD(0x0038, 0x0038, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC15__PTC15 = IOMUX_PAD(0x003C, 0x003C, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC15__FXIO1_D11 = IOMUX_PAD(0x003C, 0x003C, 0x2, 0x0230, 0x1, 0),
MX7ULP_PAD_PTC15__LPUART7_RX = IOMUX_PAD(0x003C, 0x003C, 0x4, 0x026C, 0x1, 0),
MX7ULP_PAD_PTC15__TPM7_CH1 = IOMUX_PAD(0x003C, 0x003C, 0x6, 0x02E0, 0x1, 0),
MX7ULP_PAD_PTC15__FB_AD15 = IOMUX_PAD(0x003C, 0x003C, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC15__TRACE_D0 = IOMUX_PAD(0x003C, 0x003C, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC15__DEBUG_MUX15 = IOMUX_PAD(0x003C, 0x003C, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC16__PTC16 = IOMUX_PAD(0x0040, 0x0040, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC16__FXIO1_D12 = IOMUX_PAD(0x0040, 0x0040, 0x2, 0x0234, 0x1, 0),
MX7ULP_PAD_PTC16__LPSPI3_SIN = IOMUX_PAD(0x0040, 0x0040, 0x3, 0x0324, 0x1, 0),
MX7ULP_PAD_PTC16__TPM7_CH2 = IOMUX_PAD(0x0040, 0x0040, 0x6, 0x02E4, 0x1, 0),
MX7ULP_PAD_PTC16__FB_ALE_FB_CS1_b_FB_TS_b = IOMUX_PAD(0x0040, 0x0040, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC16__TRACE_CLKOUT = IOMUX_PAD(0x0040, 0x0040, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC16__USB1_ULPI_OC2 = IOMUX_PAD(0x0040, 0x0040, 0xb, 0x0334, 0x1, 0),
MX7ULP_PAD_PTC17__PTC17 = IOMUX_PAD(0x0044, 0x0044, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC17__FXIO1_D13 = IOMUX_PAD(0x0044, 0x0044, 0x2, 0x0238, 0x1, 0),
MX7ULP_PAD_PTC17__LPSPI3_SOUT = IOMUX_PAD(0x0044, 0x0044, 0x3, 0x0328, 0x1, 0),
MX7ULP_PAD_PTC17__TPM6_CLKIN = IOMUX_PAD(0x0044, 0x0044, 0x6, 0x02D8, 0x1, 0),
MX7ULP_PAD_PTC17__FB_CS0_b = IOMUX_PAD(0x0044, 0x0044, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC17__DEBUG_MUX16 = IOMUX_PAD(0x0044, 0x0044, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC18__PTC18 = IOMUX_PAD(0x0048, 0x0048, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC18__FXIO1_D14 = IOMUX_PAD(0x0048, 0x0048, 0x2, 0x023C, 0x1, 0),
MX7ULP_PAD_PTC18__LPSPI3_SCK = IOMUX_PAD(0x0048, 0x0048, 0x3, 0x0320, 0x1, 0),
MX7ULP_PAD_PTC18__TPM6_CH0 = IOMUX_PAD(0x0048, 0x0048, 0x6, 0x02D0, 0x1, 0),
MX7ULP_PAD_PTC18__FB_OE_b = IOMUX_PAD(0x0048, 0x0048, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC18__DEBUG_MUX17 = IOMUX_PAD(0x0048, 0x0048, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC19__PTC19 = IOMUX_PAD(0x004C, 0x004C, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC19__FXIO1_D15 = IOMUX_PAD(0x004C, 0x004C, 0x2, 0x0240, 0x1, 0),
MX7ULP_PAD_PTC19__LPSPI3_PCS0 = IOMUX_PAD(0x004C, 0x004C, 0x3, 0x0310, 0x1, 0),
MX7ULP_PAD_PTC19__TPM6_CH1 = IOMUX_PAD(0x004C, 0x004C, 0x6, 0x02D4, 0x1, 0),
MX7ULP_PAD_PTC19__FB_A16 = IOMUX_PAD(0x004C, 0x004C, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTC19__USB1_ULPI_PWR2 = IOMUX_PAD(0x004C, 0x004C, 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD0__PTD0 = IOMUX_PAD(0x0080, 0x0080, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD0__SDHC0_RESET_b = IOMUX_PAD(0x0080, 0x0080, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD0__DEBUG_MUX18 = IOMUX_PAD(0x0080, 0x0080, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD1__PTD1 = IOMUX_PAD(0x0084, 0x0084, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD1__SDHC0_CMD = IOMUX_PAD(0x0084, 0x0084, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD1__DEBUG_MUX19 = IOMUX_PAD(0x0084, 0x0084, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD2__PTD2 = IOMUX_PAD(0x0088, 0x0088, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD2__SDHC0_CLK = IOMUX_PAD(0x0088, 0x0088, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD2__DEBUG_MUX20 = IOMUX_PAD(0x0088, 0x0088, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD3__PTD3 = IOMUX_PAD(0x008C, 0x008C, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD3__SDHC0_D7 = IOMUX_PAD(0x008C, 0x008C, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD3__DEBUG_MUX21 = IOMUX_PAD(0x008C, 0x008C, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD4__PTD4 = IOMUX_PAD(0x0090, 0x0090, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD4__SDHC0_D6 = IOMUX_PAD(0x0090, 0x0090, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD4__DEBUG_MUX22 = IOMUX_PAD(0x0090, 0x0090, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD5__PTD5 = IOMUX_PAD(0x0094, 0x0094, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD5__SDHC0_D5 = IOMUX_PAD(0x0094, 0x0094, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD5__DEBUG_MUX23 = IOMUX_PAD(0x0094, 0x0094, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD6__PTD6 = IOMUX_PAD(0x0098, 0x0098, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD6__SDHC0_D4 = IOMUX_PAD(0x0098, 0x0098, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD6__DEBUG_MUX24 = IOMUX_PAD(0x0098, 0x0098, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD7__PTD7 = IOMUX_PAD(0x009C, 0x009C, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD7__SDHC0_D3 = IOMUX_PAD(0x009C, 0x009C, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD7__DEBUG_MUX25 = IOMUX_PAD(0x009C, 0x009C, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD8__PTD8 = IOMUX_PAD(0x00A0, 0x00A0, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD8__TPM4_CLKIN = IOMUX_PAD(0x00A0, 0x00A0, 0x6, 0x0298, 0x2, 0),
MX7ULP_PAD_PTD8__SDHC0_D2 = IOMUX_PAD(0x00A0, 0x00A0, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD8__DEBUG_MUX26 = IOMUX_PAD(0x00A0, 0x00A0, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD9__PTD9 = IOMUX_PAD(0x00A4, 0x00A4, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD9__TPM4_CH0 = IOMUX_PAD(0x00A4, 0x00A4, 0x6, 0x0280, 0x2, 0),
MX7ULP_PAD_PTD9__SDHC0_D1 = IOMUX_PAD(0x00A4, 0x00A4, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD9__DEBUG_MUX27 = IOMUX_PAD(0x00A4, 0x00A4, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD10__PTD10 = IOMUX_PAD(0x00A8, 0x00A8, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD10__TPM4_CH1 = IOMUX_PAD(0x00A8, 0x00A8, 0x6, 0x0284, 0x2, 0),
MX7ULP_PAD_PTD10__SDHC0_D0 = IOMUX_PAD(0x00A8, 0x00A8, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD10__DEBUG_MUX28 = IOMUX_PAD(0x00A8, 0x00A8, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD11__PTD11 = IOMUX_PAD(0x00AC, 0x00AC, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD11__TPM4_CH2 = IOMUX_PAD(0x00AC, 0x00AC, 0x6, 0x0288, 0x2, 0),
MX7ULP_PAD_PTD11__SDHC0_DQS = IOMUX_PAD(0x00AC, 0x00AC, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTD11__DEBUG_MUX29 = IOMUX_PAD(0x00AC, 0x00AC, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE0__PTE0 = IOMUX_PAD(0x0100, 0x0100, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE0__FXIO1_D31 = IOMUX_PAD(0x0100, 0x0100, 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE0__LPSPI2_PCS1 = IOMUX_PAD(0x0100, 0x0100, 0x3, 0x02A0, 0x2, 0),
MX7ULP_PAD_PTE0__LPUART4_CTS_b = IOMUX_PAD(0x0100, 0x0100, 0x4, 0x0244, 0x2, 0),
MX7ULP_PAD_PTE0__LPI2C4_SCL = IOMUX_PAD(0x0100, 0x0100, 0x5, 0x0278, 0x2, 0),
MX7ULP_PAD_PTE0__SDHC1_D1 = IOMUX_PAD(0x0100, 0x0100, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE0__FB_A25 = IOMUX_PAD(0x0100, 0x0100, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE0__DEBUG_MUX30 = IOMUX_PAD(0x0100, 0x0100, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE1__PTE1 = IOMUX_PAD(0x0104, 0x0104, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE1__FXIO1_D30 = IOMUX_PAD(0x0104, 0x0104, 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE1__LPSPI2_PCS2 = IOMUX_PAD(0x0104, 0x0104, 0x3, 0x02A4, 0x2, 0),
MX7ULP_PAD_PTE1__LPUART4_RTS_b = IOMUX_PAD(0x0104, 0x0104, 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE1__LPI2C4_SDA = IOMUX_PAD(0x0104, 0x0104, 0x5, 0x027C, 0x2, 0),
MX7ULP_PAD_PTE1__SDHC1_D0 = IOMUX_PAD(0x0104, 0x0104, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE1__FB_A26 = IOMUX_PAD(0x0104, 0x0104, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE1__DEBUG_MUX31 = IOMUX_PAD(0x0104, 0x0104, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE2__PTE2 = IOMUX_PAD(0x0108, 0x0108, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE2__FXIO1_D29 = IOMUX_PAD(0x0108, 0x0108, 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE2__LPSPI2_PCS3 = IOMUX_PAD(0x0108, 0x0108, 0x3, 0x02A8, 0x2, 0),
MX7ULP_PAD_PTE2__LPUART4_TX = IOMUX_PAD(0x0108, 0x0108, 0x4, 0x024C, 0x2, 0),
MX7ULP_PAD_PTE2__LPI2C4_HREQ = IOMUX_PAD(0x0108, 0x0108, 0x5, 0x0274, 0x2, 0),
MX7ULP_PAD_PTE2__SDHC1_CLK = IOMUX_PAD(0x0108, 0x0108, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE2__DEBUG_MUX32 = IOMUX_PAD(0x0108, 0x0108, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE3__PTE3 = IOMUX_PAD(0x010C, 0x010C, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE3__FXIO1_D28 = IOMUX_PAD(0x010C, 0x010C, 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE3__LPUART4_RX = IOMUX_PAD(0x010C, 0x010C, 0x4, 0x0248, 0x2, 0),
MX7ULP_PAD_PTE3__TPM5_CH1 = IOMUX_PAD(0x010C, 0x010C, 0x6, 0x02C8, 0x2, 0),
MX7ULP_PAD_PTE3__SDHC1_CMD = IOMUX_PAD(0x010C, 0x010C, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE3__DEBUG_MUX33 = IOMUX_PAD(0x010C, 0x010C, 0xe, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE4__PTE4 = IOMUX_PAD(0x0110, 0x0110, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE4__FXIO1_D27 = IOMUX_PAD(0x0110, 0x0110, 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE4__LPSPI2_SIN = IOMUX_PAD(0x0110, 0x0110, 0x3, 0x02B0, 0x2, 0),
MX7ULP_PAD_PTE4__LPUART5_CTS_b = IOMUX_PAD(0x0110, 0x0110, 0x4, 0x0250, 0x2, 0),
MX7ULP_PAD_PTE4__LPI2C5_SCL = IOMUX_PAD(0x0110, 0x0110, 0x5, 0x02BC, 0x2, 0),
MX7ULP_PAD_PTE4__TPM5_CLKIN = IOMUX_PAD(0x0110, 0x0110, 0x6, 0x02CC, 0x2, 0),
MX7ULP_PAD_PTE4__SDHC1_D3 = IOMUX_PAD(0x0110, 0x0110, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE5__PTE5 = IOMUX_PAD(0x0114, 0x0114, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE5__FXIO1_D26 = IOMUX_PAD(0x0114, 0x0114, 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE5__LPSPI2_SOUT = IOMUX_PAD(0x0114, 0x0114, 0x3, 0x02B4, 0x2, 0),
MX7ULP_PAD_PTE5__LPUART5_RTS_b = IOMUX_PAD(0x0114, 0x0114, 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE5__LPI2C5_SDA = IOMUX_PAD(0x0114, 0x0114, 0x5, 0x02C0, 0x2, 0),
MX7ULP_PAD_PTE5__TPM5_CH0 = IOMUX_PAD(0x0114, 0x0114, 0x6, 0x02C4, 0x2, 0),
MX7ULP_PAD_PTE5__SDHC1_D2 = IOMUX_PAD(0x0114, 0x0114, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE6__PTE6 = IOMUX_PAD(0x0118, 0x0118, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE6__FXIO1_D25 = IOMUX_PAD(0x0118, 0x0118, 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE6__LPSPI2_SCK = IOMUX_PAD(0x0118, 0x0118, 0x3, 0x02AC, 0x2, 0),
MX7ULP_PAD_PTE6__LPUART5_TX = IOMUX_PAD(0x0118, 0x0118, 0x4, 0x0258, 0x2, 0),
MX7ULP_PAD_PTE6__LPI2C5_HREQ = IOMUX_PAD(0x0118, 0x0118, 0x5, 0x02B8, 0x2, 0),
MX7ULP_PAD_PTE6__TPM7_CH3 = IOMUX_PAD(0x0118, 0x0118, 0x6, 0x02E8, 0x2, 0),
MX7ULP_PAD_PTE6__SDHC1_D4 = IOMUX_PAD(0x0118, 0x0118, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE6__FB_A17 = IOMUX_PAD(0x0118, 0x0118, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE6__USB0_OC = IOMUX_PAD(0x0118, 0x0118, 0xb, 0x0330, 0x1, 0),
MX7ULP_PAD_PTE7__PTE7 = IOMUX_PAD(0x011C, 0x011C, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE7__FXIO1_D24 = IOMUX_PAD(0x011C, 0x011C, 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE7__LPSPI2_PCS0 = IOMUX_PAD(0x011C, 0x011C, 0x3, 0x029C, 0x2, 0),
MX7ULP_PAD_PTE7__LPUART5_RX = IOMUX_PAD(0x011C, 0x011C, 0x4, 0x0254, 0x2, 0),
MX7ULP_PAD_PTE7__TPM7_CH4 = IOMUX_PAD(0x011C, 0x011C, 0x6, 0x02EC, 0x2, 0),
MX7ULP_PAD_PTE7__SDHC1_D5 = IOMUX_PAD(0x011C, 0x011C, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE7__FB_A18 = IOMUX_PAD(0x011C, 0x011C, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE7__TRACE_D7 = IOMUX_PAD(0x011C, 0x011C, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE7__USB0_PWR = IOMUX_PAD(0x011C, 0x011C, 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE7__VIU_FID = IOMUX_PAD(0x011C, 0x011C, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE8__PTE8 = IOMUX_PAD(0x0120, 0x0120, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE8__TRACE_D6 = IOMUX_PAD(0x0120, 0x0120, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE8__VIU_D16 = IOMUX_PAD(0x0120, 0x0120, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE8__FXIO1_D23 = IOMUX_PAD(0x0120, 0x0120, 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE8__LPSPI3_PCS1 = IOMUX_PAD(0x0120, 0x0120, 0x3, 0x0314, 0x2, 0),
MX7ULP_PAD_PTE8__LPUART6_CTS_b = IOMUX_PAD(0x0120, 0x0120, 0x4, 0x025C, 0x2, 0),
MX7ULP_PAD_PTE8__LPI2C6_SCL = IOMUX_PAD(0x0120, 0x0120, 0x5, 0x02FC, 0x2, 0),
MX7ULP_PAD_PTE8__TPM7_CH5 = IOMUX_PAD(0x0120, 0x0120, 0x6, 0x02F0, 0x2, 0),
MX7ULP_PAD_PTE8__SDHC1_WP = IOMUX_PAD(0x0120, 0x0120, 0x7, 0x0200, 0x1, 0),
MX7ULP_PAD_PTE8__SDHC1_D6 = IOMUX_PAD(0x0120, 0x0120, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE8__FB_CS3_b_FB_BE7_0_BLS31_24_b = IOMUX_PAD(0x0120, 0x0120, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE9__PTE9 = IOMUX_PAD(0x0124, 0x0124, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE9__TRACE_D5 = IOMUX_PAD(0x0124, 0x0124, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE9__VIU_D17 = IOMUX_PAD(0x0124, 0x0124, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE9__FXIO1_D22 = IOMUX_PAD(0x0124, 0x0124, 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE9__LPSPI3_PCS2 = IOMUX_PAD(0x0124, 0x0124, 0x3, 0x0318, 0x2, 0),
MX7ULP_PAD_PTE9__LPUART6_RTS_b = IOMUX_PAD(0x0124, 0x0124, 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE9__LPI2C6_SDA = IOMUX_PAD(0x0124, 0x0124, 0x5, 0x0300, 0x2, 0),
MX7ULP_PAD_PTE9__TPM7_CLKIN = IOMUX_PAD(0x0124, 0x0124, 0x6, 0x02F4, 0x2, 0),
MX7ULP_PAD_PTE9__SDHC1_CD = IOMUX_PAD(0x0124, 0x0124, 0x7, 0x032C, 0x1, 0),
MX7ULP_PAD_PTE9__SDHC1_D7 = IOMUX_PAD(0x0124, 0x0124, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE9__FB_TBST_b_FB_CS2_b_FB_BE15_8_BLS23_16_b = IOMUX_PAD(0x0124, 0x0124, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE10__PTE10 = IOMUX_PAD(0x0128, 0x0128, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE10__TRACE_D4 = IOMUX_PAD(0x0128, 0x0128, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE10__VIU_D18 = IOMUX_PAD(0x0128, 0x0128, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE10__FXIO1_D21 = IOMUX_PAD(0x0128, 0x0128, 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE10__LPSPI3_PCS3 = IOMUX_PAD(0x0128, 0x0128, 0x3, 0x031C, 0x2, 0),
MX7ULP_PAD_PTE10__LPUART6_TX = IOMUX_PAD(0x0128, 0x0128, 0x4, 0x0264, 0x2, 0),
MX7ULP_PAD_PTE10__LPI2C6_HREQ = IOMUX_PAD(0x0128, 0x0128, 0x5, 0x02F8, 0x2, 0),
MX7ULP_PAD_PTE10__TPM7_CH0 = IOMUX_PAD(0x0128, 0x0128, 0x6, 0x02DC, 0x2, 0),
MX7ULP_PAD_PTE10__SDHC1_VS = IOMUX_PAD(0x0128, 0x0128, 0x7, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE10__SDHC1_DQS = IOMUX_PAD(0x0128, 0x0128, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE10__FB_A19 = IOMUX_PAD(0x0128, 0x0128, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE11__PTE11 = IOMUX_PAD(0x012C, 0x012C, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE11__TRACE_D3 = IOMUX_PAD(0x012C, 0x012C, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE11__VIU_D19 = IOMUX_PAD(0x012C, 0x012C, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE11__FXIO1_D20 = IOMUX_PAD(0x012C, 0x012C, 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE11__LPUART6_RX = IOMUX_PAD(0x012C, 0x012C, 0x4, 0x0260, 0x2, 0),
MX7ULP_PAD_PTE11__TPM7_CH1 = IOMUX_PAD(0x012C, 0x012C, 0x6, 0x02E0, 0x2, 0),
MX7ULP_PAD_PTE11__SDHC1_RESET_b = IOMUX_PAD(0x012C, 0x012C, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE11__FB_A20 = IOMUX_PAD(0x012C, 0x012C, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE12__PTE12 = IOMUX_PAD(0x0130, 0x0130, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE12__FXIO1_D19 = IOMUX_PAD(0x0130, 0x0130, 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE12__LPSPI3_SIN = IOMUX_PAD(0x0130, 0x0130, 0x3, 0x0324, 0x2, 0),
MX7ULP_PAD_PTE12__LPUART7_CTS_b = IOMUX_PAD(0x0130, 0x0130, 0x4, 0x0268, 0x2, 0),
MX7ULP_PAD_PTE12__LPI2C7_SCL = IOMUX_PAD(0x0130, 0x0130, 0x5, 0x0308, 0x2, 0),
MX7ULP_PAD_PTE12__TPM7_CH2 = IOMUX_PAD(0x0130, 0x0130, 0x6, 0x02E4, 0x2, 0),
MX7ULP_PAD_PTE12__SDHC1_WP = IOMUX_PAD(0x0130, 0x0130, 0x8, 0x0200, 0x2, 0),
MX7ULP_PAD_PTE12__FB_A21 = IOMUX_PAD(0x0130, 0x0130, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE12__TRACE_D2 = IOMUX_PAD(0x0130, 0x0130, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE12__USB1_ULPI_OC2 = IOMUX_PAD(0x0130, 0x0130, 0xb, 0x0334, 0x2, 0),
MX7ULP_PAD_PTE12__VIU_D20 = IOMUX_PAD(0x0130, 0x0130, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE13__PTE13 = IOMUX_PAD(0x0134, 0x0134, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE13__FXIO1_D18 = IOMUX_PAD(0x0134, 0x0134, 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE13__LPSPI3_SOUT = IOMUX_PAD(0x0134, 0x0134, 0x3, 0x0328, 0x2, 0),
MX7ULP_PAD_PTE13__LPUART7_RTS_b = IOMUX_PAD(0x0134, 0x0134, 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE13__LPI2C7_SDA = IOMUX_PAD(0x0134, 0x0134, 0x5, 0x030C, 0x2, 0),
MX7ULP_PAD_PTE13__TPM6_CLKIN = IOMUX_PAD(0x0134, 0x0134, 0x6, 0x02D8, 0x2, 0),
MX7ULP_PAD_PTE13__SDHC1_CD = IOMUX_PAD(0x0134, 0x0134, 0x8, 0x032C, 0x2, 0),
MX7ULP_PAD_PTE13__FB_A22 = IOMUX_PAD(0x0134, 0x0134, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE13__TRACE_D1 = IOMUX_PAD(0x0134, 0x0134, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE13__USB1_ULPI_PWR2 = IOMUX_PAD(0x0134, 0x0134, 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE13__VIU_D21 = IOMUX_PAD(0x0134, 0x0134, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE14__PTE14 = IOMUX_PAD(0x0138, 0x0138, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE14__FXIO1_D17 = IOMUX_PAD(0x0138, 0x0138, 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE14__LPSPI3_SCK = IOMUX_PAD(0x0138, 0x0138, 0x3, 0x0320, 0x2, 0),
MX7ULP_PAD_PTE14__LPUART7_TX = IOMUX_PAD(0x0138, 0x0138, 0x4, 0x0270, 0x2, 0),
MX7ULP_PAD_PTE14__LPI2C7_HREQ = IOMUX_PAD(0x0138, 0x0138, 0x5, 0x0304, 0x2, 0),
MX7ULP_PAD_PTE14__TPM6_CH0 = IOMUX_PAD(0x0138, 0x0138, 0x6, 0x02D0, 0x2, 0),
MX7ULP_PAD_PTE14__SDHC1_VS = IOMUX_PAD(0x0138, 0x0138, 0x8, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE14__FB_A23 = IOMUX_PAD(0x0138, 0x0138, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE14__TRACE_D0 = IOMUX_PAD(0x0138, 0x0138, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE14__USB0_OC = IOMUX_PAD(0x0138, 0x0138, 0xb, 0x0330, 0x2, 0),
MX7ULP_PAD_PTE14__VIU_D22 = IOMUX_PAD(0x0138, 0x0138, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE15__PTE15 = IOMUX_PAD(0x013C, 0x013C, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE15__FXIO1_D16 = IOMUX_PAD(0x013C, 0x013C, 0x2, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE15__LPSPI3_PCS0 = IOMUX_PAD(0x013C, 0x013C, 0x3, 0x0310, 0x2, 0),
MX7ULP_PAD_PTE15__LPUART7_RX = IOMUX_PAD(0x013C, 0x013C, 0x4, 0x026C, 0x2, 0),
MX7ULP_PAD_PTE15__TPM6_CH1 = IOMUX_PAD(0x013C, 0x013C, 0x6, 0x02D4, 0x2, 0),
MX7ULP_PAD_PTE15__FB_A24 = IOMUX_PAD(0x013C, 0x013C, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE15__TRACE_CLKOUT = IOMUX_PAD(0x013C, 0x013C, 0xa, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE15__USB0_PWR = IOMUX_PAD(0x013C, 0x013C, 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTE15__VIU_D23 = IOMUX_PAD(0x013C, 0x013C, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF0__PTF0 = IOMUX_PAD(0x0180, 0x0180, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF0__LPUART4_CTS_b = IOMUX_PAD(0x0180, 0x0180, 0x4, 0x0244, 0x3, 0),
MX7ULP_PAD_PTF0__LPI2C4_SCL = IOMUX_PAD(0x0180, 0x0180, 0x5, 0x0278, 0x3, 0),
MX7ULP_PAD_PTF0__TPM4_CLKIN = IOMUX_PAD(0x0180, 0x0180, 0x6, 0x0298, 0x3, 0),
MX7ULP_PAD_PTF0__FB_RW_b = IOMUX_PAD(0x0180, 0x0180, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF0__VIU_DE = IOMUX_PAD(0x0180, 0x0180, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF1__PTF1 = IOMUX_PAD(0x0184, 0x0184, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF1__LPUART4_RTS_b = IOMUX_PAD(0x0184, 0x0184, 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF1__LPI2C4_SDA = IOMUX_PAD(0x0184, 0x0184, 0x5, 0x027C, 0x3, 0),
MX7ULP_PAD_PTF1__TPM4_CH0 = IOMUX_PAD(0x0184, 0x0184, 0x6, 0x0280, 0x3, 0),
MX7ULP_PAD_PTF1__CLKOUT = IOMUX_PAD(0x0184, 0x0184, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF1__VIU_HSYNC = IOMUX_PAD(0x0184, 0x0184, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF2__PTF2 = IOMUX_PAD(0x0188, 0x0188, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF2__LPUART4_TX = IOMUX_PAD(0x0188, 0x0188, 0x4, 0x024C, 0x3, 0),
MX7ULP_PAD_PTF2__LPI2C4_HREQ = IOMUX_PAD(0x0188, 0x0188, 0x5, 0x0274, 0x3, 0),
MX7ULP_PAD_PTF2__TPM4_CH1 = IOMUX_PAD(0x0188, 0x0188, 0x6, 0x0284, 0x3, 0),
MX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_b_FB_BE23_16_BLS15_8_b = IOMUX_PAD(0x0188, 0x0188, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF2__VIU_VSYNC = IOMUX_PAD(0x0188, 0x0188, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF3__PTF3 = IOMUX_PAD(0x018C, 0x018C, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF3__LPUART4_RX = IOMUX_PAD(0x018C, 0x018C, 0x4, 0x0248, 0x3, 0),
MX7ULP_PAD_PTF3__TPM4_CH2 = IOMUX_PAD(0x018C, 0x018C, 0x6, 0x0288, 0x3, 0),
MX7ULP_PAD_PTF3__FB_AD16 = IOMUX_PAD(0x018C, 0x018C, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF3__VIU_PCLK = IOMUX_PAD(0x018C, 0x018C, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF4__PTF4 = IOMUX_PAD(0x0190, 0x0190, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF4__FXIO1_D0 = IOMUX_PAD(0x0190, 0x0190, 0x2, 0x0204, 0x2, 0),
MX7ULP_PAD_PTF4__LPSPI2_PCS1 = IOMUX_PAD(0x0190, 0x0190, 0x3, 0x02A0, 0x3, 0),
MX7ULP_PAD_PTF4__LPUART5_CTS_b = IOMUX_PAD(0x0190, 0x0190, 0x4, 0x0250, 0x3, 0),
MX7ULP_PAD_PTF4__LPI2C5_SCL = IOMUX_PAD(0x0190, 0x0190, 0x5, 0x02BC, 0x3, 0),
MX7ULP_PAD_PTF4__TPM4_CH3 = IOMUX_PAD(0x0190, 0x0190, 0x6, 0x028C, 0x2, 0),
MX7ULP_PAD_PTF4__FB_AD17 = IOMUX_PAD(0x0190, 0x0190, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF4__VIU_D0 = IOMUX_PAD(0x0190, 0x0190, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF5__PTF5 = IOMUX_PAD(0x0194, 0x0194, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF5__FXIO1_D1 = IOMUX_PAD(0x0194, 0x0194, 0x2, 0x0208, 0x2, 0),
MX7ULP_PAD_PTF5__LPSPI2_PCS2 = IOMUX_PAD(0x0194, 0x0194, 0x3, 0x02A4, 0x3, 0),
MX7ULP_PAD_PTF5__LPUART5_RTS_b = IOMUX_PAD(0x0194, 0x0194, 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF5__LPI2C5_SDA = IOMUX_PAD(0x0194, 0x0194, 0x5, 0x02C0, 0x3, 0),
MX7ULP_PAD_PTF5__TPM4_CH4 = IOMUX_PAD(0x0194, 0x0194, 0x6, 0x0290, 0x2, 0),
MX7ULP_PAD_PTF5__FB_AD18 = IOMUX_PAD(0x0194, 0x0194, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF5__VIU_D1 = IOMUX_PAD(0x0194, 0x0194, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF6__PTF6 = IOMUX_PAD(0x0198, 0x0198, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF6__FXIO1_D2 = IOMUX_PAD(0x0198, 0x0198, 0x2, 0x020C, 0x2, 0),
MX7ULP_PAD_PTF6__LPSPI2_PCS3 = IOMUX_PAD(0x0198, 0x0198, 0x3, 0x02A8, 0x3, 0),
MX7ULP_PAD_PTF6__LPUART5_TX = IOMUX_PAD(0x0198, 0x0198, 0x4, 0x0258, 0x3, 0),
MX7ULP_PAD_PTF6__LPI2C5_HREQ = IOMUX_PAD(0x0198, 0x0198, 0x5, 0x02B8, 0x3, 0),
MX7ULP_PAD_PTF6__TPM4_CH5 = IOMUX_PAD(0x0198, 0x0198, 0x6, 0x0294, 0x2, 0),
MX7ULP_PAD_PTF6__FB_AD19 = IOMUX_PAD(0x0198, 0x0198, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF6__VIU_D2 = IOMUX_PAD(0x0198, 0x0198, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF7__PTF7 = IOMUX_PAD(0x019C, 0x019C, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF7__FXIO1_D3 = IOMUX_PAD(0x019C, 0x019C, 0x2, 0x0210, 0x2, 0),
MX7ULP_PAD_PTF7__LPUART5_RX = IOMUX_PAD(0x019C, 0x019C, 0x4, 0x0254, 0x3, 0),
MX7ULP_PAD_PTF7__TPM5_CH1 = IOMUX_PAD(0x019C, 0x019C, 0x6, 0x02C8, 0x3, 0),
MX7ULP_PAD_PTF7__FB_AD20 = IOMUX_PAD(0x019C, 0x019C, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF7__VIU_D3 = IOMUX_PAD(0x019C, 0x019C, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF8__PTF8 = IOMUX_PAD(0x01A0, 0x01A0, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF8__FXIO1_D4 = IOMUX_PAD(0x01A0, 0x01A0, 0x2, 0x0214, 0x2, 0),
MX7ULP_PAD_PTF8__LPSPI2_SIN = IOMUX_PAD(0x01A0, 0x01A0, 0x3, 0x02B0, 0x3, 0),
MX7ULP_PAD_PTF8__LPUART6_CTS_b = IOMUX_PAD(0x01A0, 0x01A0, 0x4, 0x025C, 0x3, 0),
MX7ULP_PAD_PTF8__LPI2C6_SCL = IOMUX_PAD(0x01A0, 0x01A0, 0x5, 0x02FC, 0x3, 0),
MX7ULP_PAD_PTF8__TPM5_CLKIN = IOMUX_PAD(0x01A0, 0x01A0, 0x6, 0x02CC, 0x3, 0),
MX7ULP_PAD_PTF8__FB_AD21 = IOMUX_PAD(0x01A0, 0x01A0, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF8__USB1_ULPI_CLK = IOMUX_PAD(0x01A0, 0x01A0, 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF8__VIU_D4 = IOMUX_PAD(0x01A0, 0x01A0, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF9__PTF9 = IOMUX_PAD(0x01A4, 0x01A4, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF9__FXIO1_D5 = IOMUX_PAD(0x01A4, 0x01A4, 0x2, 0x0218, 0x2, 0),
MX7ULP_PAD_PTF9__LPSPI2_SOUT = IOMUX_PAD(0x01A4, 0x01A4, 0x3, 0x02B4, 0x3, 0),
MX7ULP_PAD_PTF9__LPUART6_RTS_b = IOMUX_PAD(0x01A4, 0x01A4, 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF9__LPI2C6_SDA = IOMUX_PAD(0x01A4, 0x01A4, 0x5, 0x0300, 0x3, 0),
MX7ULP_PAD_PTF9__TPM5_CH0 = IOMUX_PAD(0x01A4, 0x01A4, 0x6, 0x02C4, 0x3, 0),
MX7ULP_PAD_PTF9__FB_AD22 = IOMUX_PAD(0x01A4, 0x01A4, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF9__USB1_ULPI_NXT = IOMUX_PAD(0x01A4, 0x01A4, 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF9__VIU_D5 = IOMUX_PAD(0x01A4, 0x01A4, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF10__PTF10 = IOMUX_PAD(0x01A8, 0x01A8, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF10__FXIO1_D6 = IOMUX_PAD(0x01A8, 0x01A8, 0x2, 0x021C, 0x2, 0),
MX7ULP_PAD_PTF10__LPSPI2_SCK = IOMUX_PAD(0x01A8, 0x01A8, 0x3, 0x02AC, 0x3, 0),
MX7ULP_PAD_PTF10__LPUART6_TX = IOMUX_PAD(0x01A8, 0x01A8, 0x4, 0x0264, 0x3, 0),
MX7ULP_PAD_PTF10__LPI2C6_HREQ = IOMUX_PAD(0x01A8, 0x01A8, 0x5, 0x02F8, 0x3, 0),
MX7ULP_PAD_PTF10__TPM7_CH3 = IOMUX_PAD(0x01A8, 0x01A8, 0x6, 0x02E8, 0x3, 0),
MX7ULP_PAD_PTF10__FB_AD23 = IOMUX_PAD(0x01A8, 0x01A8, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF10__USB1_ULPI_STP = IOMUX_PAD(0x01A8, 0x01A8, 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF10__VIU_D6 = IOMUX_PAD(0x01A8, 0x01A8, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF11__PTF11 = IOMUX_PAD(0x01AC, 0x01AC, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF11__FXIO1_D7 = IOMUX_PAD(0x01AC, 0x01AC, 0x2, 0x0220, 0x2, 0),
MX7ULP_PAD_PTF11__LPSPI2_PCS0 = IOMUX_PAD(0x01AC, 0x01AC, 0x3, 0x029C, 0x3, 0),
MX7ULP_PAD_PTF11__LPUART6_RX = IOMUX_PAD(0x01AC, 0x01AC, 0x4, 0x0260, 0x3, 0),
MX7ULP_PAD_PTF11__TPM7_CH4 = IOMUX_PAD(0x01AC, 0x01AC, 0x6, 0x02EC, 0x3, 0),
MX7ULP_PAD_PTF11__FB_CS4_b_FB_TSIZ0_FB_BE31_24_BLS7_0_b = IOMUX_PAD(0x01AC, 0x01AC, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF11__USB1_ULPI_DIR = IOMUX_PAD(0x01AC, 0x01AC, 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF11__VIU_D7 = IOMUX_PAD(0x01AC, 0x01AC, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF12__PTF12 = IOMUX_PAD(0x01B0, 0x01B0, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF12__FXIO1_D8 = IOMUX_PAD(0x01B0, 0x01B0, 0x2, 0x0224, 0x2, 0),
MX7ULP_PAD_PTF12__LPSPI3_PCS1 = IOMUX_PAD(0x01B0, 0x01B0, 0x3, 0x0314, 0x3, 0),
MX7ULP_PAD_PTF12__LPUART7_CTS_b = IOMUX_PAD(0x01B0, 0x01B0, 0x4, 0x0268, 0x3, 0),
MX7ULP_PAD_PTF12__LPI2C7_SCL = IOMUX_PAD(0x01B0, 0x01B0, 0x5, 0x0308, 0x3, 0),
MX7ULP_PAD_PTF12__TPM7_CH5 = IOMUX_PAD(0x01B0, 0x01B0, 0x6, 0x02F0, 0x3, 0),
MX7ULP_PAD_PTF12__FB_AD24 = IOMUX_PAD(0x01B0, 0x01B0, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF12__USB1_ULPI_DATA0 = IOMUX_PAD(0x01B0, 0x01B0, 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF12__VIU_D8 = IOMUX_PAD(0x01B0, 0x01B0, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF13__PTF13 = IOMUX_PAD(0x01B4, 0x01B4, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF13__FXIO1_D9 = IOMUX_PAD(0x01B4, 0x01B4, 0x2, 0x0228, 0x2, 0),
MX7ULP_PAD_PTF13__LPSPI3_PCS2 = IOMUX_PAD(0x01B4, 0x01B4, 0x3, 0x0318, 0x3, 0),
MX7ULP_PAD_PTF13__LPUART7_RTS_b = IOMUX_PAD(0x01B4, 0x01B4, 0x4, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF13__LPI2C7_SDA = IOMUX_PAD(0x01B4, 0x01B4, 0x5, 0x030C, 0x3, 0),
MX7ULP_PAD_PTF13__TPM7_CLKIN = IOMUX_PAD(0x01B4, 0x01B4, 0x6, 0x02F4, 0x3, 0),
MX7ULP_PAD_PTF13__FB_AD25 = IOMUX_PAD(0x01B4, 0x01B4, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF13__USB1_ULPI_DATA1 = IOMUX_PAD(0x01B4, 0x01B4, 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF13__VIU_D9 = IOMUX_PAD(0x01B4, 0x01B4, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF14__PTF14 = IOMUX_PAD(0x01B8, 0x01B8, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF14__FXIO1_D10 = IOMUX_PAD(0x01B8, 0x01B8, 0x2, 0x022C, 0x2, 0),
MX7ULP_PAD_PTF14__LPSPI3_PCS3 = IOMUX_PAD(0x01B8, 0x01B8, 0x3, 0x031C, 0x3, 0),
MX7ULP_PAD_PTF14__LPUART7_TX = IOMUX_PAD(0x01B8, 0x01B8, 0x4, 0x0270, 0x3, 0),
MX7ULP_PAD_PTF14__LPI2C7_HREQ = IOMUX_PAD(0x01B8, 0x01B8, 0x5, 0x0304, 0x3, 0),
MX7ULP_PAD_PTF14__TPM7_CH0 = IOMUX_PAD(0x01B8, 0x01B8, 0x6, 0x02DC, 0x3, 0),
MX7ULP_PAD_PTF14__FB_AD26 = IOMUX_PAD(0x01B8, 0x01B8, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF14__USB1_ULPI_DATA2 = IOMUX_PAD(0x01B8, 0x01B8, 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF14__VIU_D10 = IOMUX_PAD(0x01B8, 0x01B8, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF15__PTF15 = IOMUX_PAD(0x01BC, 0x01BC, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF15__FXIO1_D11 = IOMUX_PAD(0x01BC, 0x01BC, 0x2, 0x0230, 0x2, 0),
MX7ULP_PAD_PTF15__LPUART7_RX = IOMUX_PAD(0x01BC, 0x01BC, 0x4, 0x026C, 0x3, 0),
MX7ULP_PAD_PTF15__TPM7_CH1 = IOMUX_PAD(0x01BC, 0x01BC, 0x6, 0x02E0, 0x3, 0),
MX7ULP_PAD_PTF15__FB_AD27 = IOMUX_PAD(0x01BC, 0x01BC, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF15__USB1_ULPI_DATA3 = IOMUX_PAD(0x01BC, 0x01BC, 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF15__VIU_D11 = IOMUX_PAD(0x01BC, 0x01BC, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF16__PTF16 = IOMUX_PAD(0x01C0, 0x01C0, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF16__USB1_ULPI_DATA4 = IOMUX_PAD(0x01C0, 0x01C0, 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF16__VIU_D12 = IOMUX_PAD(0x01C0, 0x01C0, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF16__FXIO1_D12 = IOMUX_PAD(0x01C0, 0x01C0, 0x2, 0x0234, 0x2, 0),
MX7ULP_PAD_PTF16__LPSPI3_SIN = IOMUX_PAD(0x01C0, 0x01C0, 0x3, 0x0324, 0x3, 0),
MX7ULP_PAD_PTF16__TPM7_CH2 = IOMUX_PAD(0x01C0, 0x01C0, 0x6, 0x02E4, 0x3, 0),
MX7ULP_PAD_PTF16__FB_AD28 = IOMUX_PAD(0x01C0, 0x01C0, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF17__PTF17 = IOMUX_PAD(0x01C4, 0x01C4, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF17__USB1_ULPI_DATA5 = IOMUX_PAD(0x01C4, 0x01C4, 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF17__VIU_D13 = IOMUX_PAD(0x01C4, 0x01C4, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF17__FXIO1_D13 = IOMUX_PAD(0x01C4, 0x01C4, 0x2, 0x0238, 0x2, 0),
MX7ULP_PAD_PTF17__LPSPI3_SOUT = IOMUX_PAD(0x01C4, 0x01C4, 0x3, 0x0328, 0x3, 0),
MX7ULP_PAD_PTF17__TPM6_CLKIN = IOMUX_PAD(0x01C4, 0x01C4, 0x6, 0x02D8, 0x3, 0),
MX7ULP_PAD_PTF17__FB_AD29 = IOMUX_PAD(0x01C4, 0x01C4, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF18__PTF18 = IOMUX_PAD(0x01C8, 0x01C8, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF18__USB1_ULPI_DATA6 = IOMUX_PAD(0x01C8, 0x01C8, 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF18__VIU_D14 = IOMUX_PAD(0x01C8, 0x01C8, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF18__FXIO1_D14 = IOMUX_PAD(0x01C8, 0x01C8, 0x2, 0x023C, 0x2, 0),
MX7ULP_PAD_PTF18__LPSPI3_SCK = IOMUX_PAD(0x01C8, 0x01C8, 0x3, 0x0320, 0x3, 0),
MX7ULP_PAD_PTF18__TPM6_CH0 = IOMUX_PAD(0x01C8, 0x01C8, 0x6, 0x02D0, 0x3, 0),
MX7ULP_PAD_PTF18__FB_AD30 = IOMUX_PAD(0x01C8, 0x01C8, 0x9, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF19__PTF19 = IOMUX_PAD(0x01CC, 0x01CC, 0x1, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF19__USB1_ULPI_DATA7 = IOMUX_PAD(0x01CC, 0x01CC, 0xb, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF19__VIU_D15 = IOMUX_PAD(0x01CC, 0x01CC, 0xc, 0x0000, 0x0, 0),
MX7ULP_PAD_PTF19__FXIO1_D15 = IOMUX_PAD(0x01CC, 0x01CC, 0x2, 0x0240, 0x2, 0),
MX7ULP_PAD_PTF19__LPSPI3_PCS0 = IOMUX_PAD(0x01CC, 0x01CC, 0x3, 0x0310, 0x3, 0),
MX7ULP_PAD_PTF19__TPM6_CH1 = IOMUX_PAD(0x01CC, 0x01CC, 0x6, 0x02D4, 0x3, 0),
MX7ULP_PAD_PTF19__FB_AD31 = IOMUX_PAD(0x01CC, 0x01CC, 0x9, 0x0000, 0x0, 0),
};
#endif /* __ASM_ARCH_IMX7ULP_PINS_H__ */

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/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_PCC_H
#define _ASM_ARCH_PCC_H
#include <common.h>
#include <asm/arch/scg.h>
/* PCC2 */
enum pcc2_entry {
/* On-Platform (32 entries) */
RSVD0_PCC2_SLOT = 0,
RSVD1_PCC2_SLOT = 1,
CA7_GIC_PCC2_SLOT = 2,
RSVD3_PCC2_SLOT = 3,
RSVD4_PCC2_SLOT = 4,
RSVD5_PCC2_SLOT = 5,
RSVD6_PCC2_SLOT = 6,
RSVD7_PCC2_SLOT = 7,
DMA1_PCC2_SLOT = 8,
RSVD9_PCC2_SLOT = 9,
RSVD10_PCC2_SLOT = 10,
RSVD11_PCC2_SLOT = 11,
RSVD12_PCC2_SLOT = 12,
RSVD13_PCC2_SLOT = 13,
RSVD14_PCC2_SLOT = 14,
RGPIO1_PCC2_SLOT = 15,
FLEXBUS0_PCC2_SLOT = 16,
RSVD17_PCC2_SLOT = 17,
RSVD18_PCC2_SLOT = 18,
RSVD19_PCC2_SLOT = 19,
RSVD20_PCC2_SLOT = 20,
RSVD21_PCC2_SLOT = 21,
RSVD22_PCC2_SLOT = 22,
RSVD23_PCC2_SLOT = 23,
RSVD24_PCC2_SLOT = 24,
RSVD25_PCC2_SLOT = 25,
RSVD26_PCC2_SLOT = 26,
SEMA42_1_PCC2_SLOT = 27,
RSVD28_PCC2_SLOT = 28,
RSVD29_PCC2_SLOT = 29,
RSVD30_PCC2_SLOT = 30,
RSVD31_PCC2_SLOT = 31,
/* Off-Platform (96 entries) */
RSVD32_PCC2_SLOT = 32,
DMA1_CH_MUX0_PCC2_SLOT = 33,
MU_B_PCC2_SLOT = 34,
SNVS_PCC2_SLOT = 35,
CAAM_PCC2_SLOT = 36,
LPTPM4_PCC2_SLOT = 37,
LPTPM5_PCC2_SLOT = 38,
LPIT1_PCC2_SLOT = 39,
RSVD40_PCC2_SLOT = 40,
LPSPI2_PCC2_SLOT = 41,
LPSPI3_PCC2_SLOT = 42,
LPI2C4_PCC2_SLOT = 43,
LPI2C5_PCC2_SLOT = 44,
LPUART4_PCC2_SLOT = 45,
LPUART5_PCC2_SLOT = 46,
RSVD47_PCC2_SLOT = 47,
RSVD48_PCC2_SLOT = 48,
FLEXIO1_PCC2_SLOT = 49,
RSVD50_PCC2_SLOT = 50,
USBOTG0_PCC2_SLOT = 51,
USBOTG1_PCC2_SLOT = 52,
USBPHY_PCC2_SLOT = 53,
USB_PL301_PCC2_SLOT = 54,
USDHC0_PCC2_SLOT = 55,
USDHC1_PCC2_SLOT = 56,
RSVD57_PCC2_SLOT = 57,
TRGMUX1_PCC2_SLOT = 58,
RSVD59_PCC2_SLOT = 59,
RSVD60_PCC2_SLOT = 60,
WDG1_PCC2_SLOT = 61,
SCG1_PCC2_SLOT = 62,
PCC2_PCC2_SLOT = 63,
PMC1_PCC2_SLOT = 64,
SMC1_PCC2_SLOT = 65,
RCM1_PCC2_SLOT = 66,
WDG2_PCC2_SLOT = 67,
RSVD68_PCC2_SLOT = 68,
TEST_SPACE1_PCC2_SLOT = 69,
TEST_SPACE2_PCC2_SLOT = 70,
TEST_SPACE3_PCC2_SLOT = 71,
RSVD72_PCC2_SLOT = 72,
RSVD73_PCC2_SLOT = 73,
RSVD74_PCC2_SLOT = 74,
RSVD75_PCC2_SLOT = 75,
RSVD76_PCC2_SLOT = 76,
RSVD77_PCC2_SLOT = 77,
RSVD78_PCC2_SLOT = 78,
RSVD79_PCC2_SLOT = 79,
RSVD80_PCC2_SLOT = 80,
RSVD81_PCC2_SLOT = 81,
RSVD82_PCC2_SLOT = 82,
RSVD83_PCC2_SLOT = 83,
RSVD84_PCC2_SLOT = 84,
RSVD85_PCC2_SLOT = 85,
RSVD86_PCC2_SLOT = 86,
RSVD87_PCC2_SLOT = 87,
RSVD88_PCC2_SLOT = 88,
RSVD89_PCC2_SLOT = 89,
RSVD90_PCC2_SLOT = 90,
RSVD91_PCC2_SLOT = 91,
RSVD92_PCC2_SLOT = 92,
RSVD93_PCC2_SLOT = 93,
RSVD94_PCC2_SLOT = 94,
RSVD95_PCC2_SLOT = 95,
RSVD96_PCC2_SLOT = 96,
RSVD97_PCC2_SLOT = 97,
RSVD98_PCC2_SLOT = 98,
RSVD99_PCC2_SLOT = 99,
RSVD100_PCC2_SLOT = 100,
RSVD101_PCC2_SLOT = 101,
RSVD102_PCC2_SLOT = 102,
RSVD103_PCC2_SLOT = 103,
RSVD104_PCC2_SLOT = 104,
RSVD105_PCC2_SLOT = 105,
RSVD106_PCC2_SLOT = 106,
RSVD107_PCC2_SLOT = 107,
RSVD108_PCC2_SLOT = 108,
RSVD109_PCC2_SLOT = 109,
RSVD110_PCC2_SLOT = 110,
RSVD111_PCC2_SLOT = 111,
RSVD112_PCC2_SLOT = 112,
RSVD113_PCC2_SLOT = 113,
RSVD114_PCC2_SLOT = 114,
RSVD115_PCC2_SLOT = 115,
RSVD116_PCC2_SLOT = 116,
RSVD117_PCC2_SLOT = 117,
RSVD118_PCC2_SLOT = 118,
RSVD119_PCC2_SLOT = 119,
RSVD120_PCC2_SLOT = 120,
RSVD121_PCC2_SLOT = 121,
RSVD122_PCC2_SLOT = 122,
RSVD123_PCC2_SLOT = 123,
RSVD124_PCC2_SLOT = 124,
RSVD125_PCC2_SLOT = 125,
RSVD126_PCC2_SLOT = 126,
RSVD127_PCC2_SLOT = 127,
};
enum pcc3_entry {
/* On-Platform (32 entries) */
RSVD0_PCC3_SLOT = 0,
RSVD1_PCC3_SLOT = 1,
RSVD2_PCC3_SLOT = 2,
RSVD3_PCC3_SLOT = 3,
RSVD4_PCC3_SLOT = 4,
RSVD5_PCC3_SLOT = 5,
RSVD6_PCC3_SLOT = 6,
RSVD7_PCC3_SLOT = 7,
RSVD8_PCC3_SLOT = 8,
RSVD9_PCC3_SLOT = 9,
RSVD10_PCC3_SLOT = 10,
RSVD11_PCC3_SLOT = 11,
RSVD12_PCC3_SLOT = 12,
RSVD13_PCC3_SLOT = 13,
RSVD14_PCC3_SLOT = 14,
RSVD15_PCC3_SLOT = 15,
ROMCP1_PCC3_SLOT = 16,
RSVD17_PCC3_SLOT = 17,
RSVD18_PCC3_SLOT = 18,
RSVD19_PCC3_SLOT = 19,
RSVD20_PCC3_SLOT = 20,
RSVD21_PCC3_SLOT = 21,
RSVD22_PCC3_SLOT = 22,
RSVD23_PCC3_SLOT = 23,
RSVD24_PCC3_SLOT = 24,
RSVD25_PCC3_SLOT = 25,
RSVD26_PCC3_SLOT = 26,
RSVD27_PCC3_SLOT = 27,
RSVD28_PCC3_SLOT = 28,
RSVD29_PCC3_SLOT = 29,
RSVD30_PCC3_SLOT = 30,
RSVD31_PCC3_SLOT = 31,
/* Off-Platform (96 entries) */
RSVD32_PCC3_SLOT = 32,
LPTPM6_PCC3_SLOT = 33,
LPTPM7_PCC3_SLOT = 34,
RSVD35_PCC3_SLOT = 35,
LPI2C6_PCC3_SLOT = 36,
LPI2C7_PCC3_SLOT = 37,
LPUART6_PCC3_SLOT = 38,
LPUART7_PCC3_SLOT = 39,
VIU0_PCC3_SLOT = 40,
DSI0_PCC3_SLOT = 41,
LCDIF0_PCC3_SLOT = 42,
MMDC0_PCC3_SLOT = 43,
IOMUXC1_PCC3_SLOT = 44,
IOMUXC_DDR_PCC3_SLOT = 45,
PORTC_PCC3_SLOT = 46,
PORTD_PCC3_SLOT = 47,
PORTE_PCC3_SLOT = 48,
PORTF_PCC3_SLOT = 49,
RSVD50_PCC3_SLOT = 50,
PCC3_PCC3_SLOT = 51,
RSVD52_PCC3_SLOT = 52,
WKPU_PCC3_SLOT = 53,
RSVD54_PCC3_SLOT = 54,
RSVD55_PCC3_SLOT = 55,
RSVD56_PCC3_SLOT = 56,
RSVD57_PCC3_SLOT = 57,
RSVD58_PCC3_SLOT = 58,
RSVD59_PCC3_SLOT = 59,
RSVD60_PCC3_SLOT = 60,
RSVD61_PCC3_SLOT = 61,
RSVD62_PCC3_SLOT = 62,
RSVD63_PCC3_SLOT = 63,
RSVD64_PCC3_SLOT = 64,
RSVD65_PCC3_SLOT = 65,
RSVD66_PCC3_SLOT = 66,
RSVD67_PCC3_SLOT = 67,
RSVD68_PCC3_SLOT = 68,
RSVD69_PCC3_SLOT = 69,
RSVD70_PCC3_SLOT = 70,
RSVD71_PCC3_SLOT = 71,
RSVD72_PCC3_SLOT = 72,
RSVD73_PCC3_SLOT = 73,
RSVD74_PCC3_SLOT = 74,
RSVD75_PCC3_SLOT = 75,
RSVD76_PCC3_SLOT = 76,
RSVD77_PCC3_SLOT = 77,
RSVD78_PCC3_SLOT = 78,
RSVD79_PCC3_SLOT = 79,
RSVD80_PCC3_SLOT = 80,
GPU3D_PCC3_SLOT = 81,
GPU2D_PCC3_SLOT = 82,
RSVD83_PCC3_SLOT = 83,
RSVD84_PCC3_SLOT = 84,
RSVD85_PCC3_SLOT = 85,
RSVD86_PCC3_SLOT = 86,
RSVD87_PCC3_SLOT = 87,
RSVD88_PCC3_SLOT = 88,
RSVD89_PCC3_SLOT = 89,
RSVD90_PCC3_SLOT = 90,
RSVD91_PCC3_SLOT = 91,
RSVD92_PCC3_SLOT = 92,
RSVD93_PCC3_SLOT = 93,
RSVD94_PCC3_SLOT = 94,
RSVD95_PCC3_SLOT = 95,
RSVD96_PCC3_SLOT = 96,
RSVD97_PCC3_SLOT = 97,
RSVD98_PCC3_SLOT = 98,
RSVD99_PCC3_SLOT = 99,
RSVD100_PCC3_SLOT = 100,
RSVD101_PCC3_SLOT = 101,
RSVD102_PCC3_SLOT = 102,
RSVD103_PCC3_SLOT = 103,
RSVD104_PCC3_SLOT = 104,
RSVD105_PCC3_SLOT = 105,
RSVD106_PCC3_SLOT = 106,
RSVD107_PCC3_SLOT = 107,
RSVD108_PCC3_SLOT = 108,
RSVD109_PCC3_SLOT = 109,
RSVD110_PCC3_SLOT = 110,
RSVD111_PCC3_SLOT = 111,
RSVD112_PCC3_SLOT = 112,
RSVD113_PCC3_SLOT = 113,
RSVD114_PCC3_SLOT = 114,
RSVD115_PCC3_SLOT = 115,
RSVD116_PCC3_SLOT = 116,
RSVD117_PCC3_SLOT = 117,
RSVD118_PCC3_SLOT = 118,
RSVD119_PCC3_SLOT = 119,
RSVD120_PCC3_SLOT = 120,
RSVD121_PCC3_SLOT = 121,
RSVD122_PCC3_SLOT = 122,
RSVD123_PCC3_SLOT = 123,
RSVD124_PCC3_SLOT = 124,
RSVD125_PCC3_SLOT = 125,
RSVD126_PCC3_SLOT = 126,
RSVD127_PCC3_SLOT = 127,
};
/* PCC registers */
#define PCC_PR_OFFSET 31
#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET)
#define PCC_CGC_OFFSET 30
#define PCC_CGC_MASK (0x1 << PCC_CGC_OFFSET)
#define PCC_INUSE_OFFSET 29
#define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET)
#define PCC_PCS_OFFSET 24
#define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET)
#define PCC_FRAC_OFFSET 4
#define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET)
#define PCC_PCD_OFFSET 0
#define PCC_PCD_MASK (0xf << PCC_PCD_OFFSET)
enum pcc_clksrc_type {
CLKSRC_PER_PLAT = 0,
CLKSRC_PER_BUS = 1,
CLKSRC_NO_PCS = 2,
};
enum pcc_div_type {
PCC_HAS_DIV,
PCC_NO_DIV,
};
/* All peripheral clocks on A7 PCCs */
enum pcc_clk {
/*PCC2 clocks*/
PER_CLK_DMA1 = 0,
PER_CLK_RGPIO2P1,
PER_CLK_FLEXBUS,
PER_CLK_SEMA42_1,
PER_CLK_DMA_MUX1,
PER_CLK_SNVS,
PER_CLK_CAAM,
PER_CLK_LPTPM4,
PER_CLK_LPTPM5,
PER_CLK_LPIT1,
PER_CLK_LPSPI2,
PER_CLK_LPSPI3,
PER_CLK_LPI2C4,
PER_CLK_LPI2C5,
PER_CLK_LPUART4,
PER_CLK_LPUART5,
PER_CLK_FLEXIO1,
PER_CLK_USB0,
PER_CLK_USB1,
PER_CLK_USB_PHY,
PER_CLK_USB_PL301,
PER_CLK_USDHC0,
PER_CLK_USDHC1,
PER_CLK_WDG1,
PER_CLK_WDG2,
/*PCC3 clocks*/
PER_CLK_LPTPM6,
PER_CLK_LPTPM7,
PER_CLK_LPI2C6,
PER_CLK_LPI2C7,
PER_CLK_LPUART6,
PER_CLK_LPUART7,
PER_CLK_VIU,
PER_CLK_DSI,
PER_CLK_LCDIF,
PER_CLK_MMDC,
PER_CLK_PCTLC,
PER_CLK_PCTLD,
PER_CLK_PCTLE,
PER_CLK_PCTLF,
PER_CLK_GPU3D,
PER_CLK_GPU2D,
};
/* This structure keeps info for each pcc slot */
struct pcc_entry {
u32 pcc_base;
u32 pcc_slot;
enum pcc_clksrc_type clksrc;
enum pcc_div_type div;
};
int pcc_clock_enable(enum pcc_clk clk, bool enable);
int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src);
int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div);
bool pcc_clock_is_enable(enum pcc_clk clk);
int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src);
u32 pcc_clock_get_rate(enum pcc_clk clk);
#endif

342
arch/arm/include/asm/arch-mx7ulp/scg.h Normal file
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@ -0,0 +1,342 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SCG_H
#define _ASM_ARCH_SCG_H
#include <common.h>
#ifdef CONFIG_CLK_DEBUG
#define clk_debug(fmt, args...) printf(fmt, ##args)
#else
#define clk_debug(fmt, args...)
#endif
#define SCG_CCR_SCS_SHIFT (24)
#define SCG_CCR_SCS_MASK ((0xFUL) << SCG_CCR_SCS_SHIFT)
#define SCG_CCR_DIVCORE_SHIFT (16)
#define SCG_CCR_DIVCORE_MASK ((0xFUL) << SCG_CCR_DIVCORE_SHIFT)
#define SCG_CCR_DIVPLAT_SHIFT (12)
#define SCG_CCR_DIVPLAT_MASK ((0xFUL) << SCG_CCR_DIVPLAT_SHIFT)
#define SCG_CCR_DIVEXT_SHIFT (8)
#define SCG_CCR_DIVEXT_MASK ((0xFUL) << SCG_CCR_DIVEXT_SHIFT)
#define SCG_CCR_DIVBUS_SHIFT (4)
#define SCG_CCR_DIVBUS_MASK ((0xFUL) << SCG_CCR_DIVBUS_SHIFT)
#define SCG_CCR_DIVSLOW_SHIFT (0)
#define SCG_CCR_DIVSLOW_MASK ((0xFUL) << SCG_CCR_DIVSLOW_SHIFT)
/* SCG DDR Clock Control Register */
#define SCG_DDRCCR_DDRCS_SHIFT (24)
#define SCG_DDRCCR_DDRCS_MASK ((0x1UL) << SCG_DDRCCR_DDRCS_SHIFT)
#define SCG_DDRCCR_DDRDIV_SHIFT (0)
#define SCG_DDRCCR_DDRDIV_MASK ((0x7UL) << SCG_DDRCCR_DDRDIV_SHIFT)
/* SCG NIC Clock Control Register */
#define SCG_NICCCR_NICCS_SHIFT (28)
#define SCG_NICCCR_NICCS_MASK ((0x1UL) << SCG_NICCCR_NICCS_SHIFT)
#define SCG_NICCCR_NIC0_DIV_SHIFT (24)
#define SCG_NICCCR_NIC0_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC0_DIV_SHIFT)
#define SCG_NICCCR_GPU_DIV_SHIFT (20)
#define SCG_NICCCR_GPU_DIV_MASK ((0xFUL) << SCG_NICCCR_GPU_DIV_SHIFT)
#define SCG_NICCCR_NIC1_DIV_SHIFT (16)
#define SCG_NICCCR_NIC1_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIV_SHIFT)
#define SCG_NICCCR_NIC1_DIVEXT_SHIFT (8)
#define SCG_NICCCR_NIC1_DIVEXT_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVEXT_SHIFT)
#define SCG_NICCCR_NIC1_DIVBUS_SHIFT (4)
#define SCG_NICCCR_NIC1_DIVBUS_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVBUS_SHIFT)
/* SCG NIC clock status register */
#define SCG_NICCSR_NICCS_SHIFT (28)
#define SCG_NICCSR_NICCS_MASK ((0x1UL) << SCG_NICCSR_NICCS_SHIFT)
#define SCG_NICCSR_NIC0DIV_SHIFT (24)
#define SCG_NICCSR_NIC0DIV_MASK ((0xFUL) << SCG_NICCSR_NIC0DIV_SHIFT)
#define SCG_NICCSR_GPUDIV_SHIFT (20)
#define SCG_NICCSR_GPUDIV_MASK ((0xFUL) << SCG_NICCSR_GPUDIV_SHIFT)
#define SCG_NICCSR_NIC1DIV_SHIFT (16)
#define SCG_NICCSR_NIC1DIV_MASK ((0xFUL) << SCG_NICCSR_NIC1DIV_SHIFT)
#define SCG_NICCSR_NIC1EXTDIV_SHIFT (8)
#define SCG_NICCSR_NIC1EXTDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1EXTDIV_SHIFT)
#define SCG_NICCSR_NIC1BUSDIV_SHIFT (4)
#define SCG_NICCSR_NIC1BUSDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1BUSDIV_SHIFT)
/* SCG Slow IRC Control Status Register */
#define SCG_SIRC_CSR_SIRCVLD_SHIFT (24)
#define SCG_SIRC_CSR_SIRCVLD_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCVLD_SHIFT)
#define SCG_SIRC_CSR_SIRCEN_SHIFT (0)
#define SCG_SIRC_CSR_SIRCEN_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCEN_SHIFT)
/* SCG Slow IRC Configuration Register */
#define SCG_SIRCCFG_RANGE_SHIFT (0)
#define SCG_SIRCCFG_RANGE_MASK ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT)
#define SCG_SIRCCFG_RANGE_4M ((0x0UL) << SCG_SIRCCFG_RANGE_SHIFT)
#define SCG_SIRCCFG_RANGE_16M ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT)
/* SCG Slow IRC Divide Register */
#define SCG_SIRCDIV_DIV3_SHIFT (16)
#define SCG_SIRCDIV_DIV3_MASK ((0x7UL) << SCG_SIRCDIV_DIV3_SHIFT)
#define SCG_SIRCDIV_DIV2_SHIFT (8)
#define SCG_SIRCDIV_DIV2_MASK ((0x7UL) << SCG_SIRCDIV_DIV2_SHIFT)
#define SCG_SIRCDIV_DIV1_SHIFT (0)
#define SCG_SIRCDIV_DIV1_MASK ((0x7UL) << SCG_SIRCDIV_DIV1_SHIFT)
/*
* FIRC/SIRC DIV1 ==> xIRC_PLAT_CLK
* FIRC/SIRC DIV2 ==> xIRC_BUS_CLK
* FIRC/SIRC DIV3 ==> xIRC_SLOW_CLK
*/
/* SCG Fast IRC Control Status Register */
#define SCG_FIRC_CSR_FIRCVLD_SHIFT (24)
#define SCG_FIRC_CSR_FIRCVLD_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCVLD_SHIFT)
#define SCG_FIRC_CSR_FIRCEN_SHIFT (0)
#define SCG_FIRC_CSR_FIRCEN_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCEN_SHIFT)
/* SCG Fast IRC Divide Register */
#define SCG_FIRCDIV_DIV3_SHIFT (16)
#define SCG_FIRCDIV_DIV3_MASK ((0x7UL) << SCG_FIRCDIV_DIV3_SHIFT)
#define SCG_FIRCDIV_DIV2_SHIFT (8)
#define SCG_FIRCDIV_DIV2_MASK ((0x7UL) << SCG_FIRCDIV_DIV2_SHIFT)
#define SCG_FIRCDIV_DIV1_SHIFT (0)
#define SCG_FIRCDIV_DIV1_MASK ((0x7UL) << SCG_FIRCDIV_DIV1_SHIFT)
#define SCG_FIRCCFG_RANGE_SHIFT (0)
#define SCG_FIRCCFG_RANGE_MASK ((0x3UL) << SCG_FIRCCFG_RANGE_SHIFT)
#define SCG_FIRCCFG_RANGE_SHIFT (0)
#define SCG_FIRCCFG_RANGE_48M ((0x0UL) << SCG_FIRCCFG_RANGE_SHIFT)
/* SCG System OSC Control Status Register */
#define SCG_SOSC_CSR_SOSCVLD_SHIFT (24)
#define SCG_SOSC_CSR_SOSCVLD_MASK ((0x1UL) << SCG_SOSC_CSR_SOSCVLD_SHIFT)
/* SCG Fast IRC Divide Register */
#define SCG_SOSCDIV_DIV3_SHIFT (16)
#define SCG_SOSCDIV_DIV3_MASK ((0x7UL) << SCG_SOSCDIV_DIV3_SHIFT)
#define SCG_SOSCDIV_DIV2_SHIFT (8)
#define SCG_SOSCDIV_DIV2_MASK ((0x7UL) << SCG_SOSCDIV_DIV2_SHIFT)
#define SCG_SOSCDIV_DIV1_SHIFT (0)
#define SCG_SOSCDIV_DIV1_MASK ((0x7UL) << SCG_SOSCDIV_DIV1_SHIFT)
/* SCG RTC OSC Control Status Register */
#define SCG_ROSC_CSR_ROSCVLD_SHIFT (24)
#define SCG_ROSC_CSR_ROSCVLD_MASK ((0x1UL) << SCG_ROSC_CSR_ROSCVLD_SHIFT)
#define SCG_SPLL_CSR_SPLLVLD_SHIFT (24)
#define SCG_SPLL_CSR_SPLLVLD_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLVLD_SHIFT)
#define SCG_SPLL_CSR_SPLLEN_SHIFT (0)
#define SCG_SPLL_CSR_SPLLEN_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLEN_SHIFT)
#define SCG_APLL_CSR_APLLEN_SHIFT (0)
#define SCG_APLL_CSR_APLLEN_MASK (0x1UL)
#define SCG_APLL_CSR_APLLVLD_MASK (0x01000000)
#define SCG_UPLL_CSR_UPLLVLD_MASK (0x01000000)
#define SCG_PLL_PFD3_GATE_MASK (0x80000000)
#define SCG_PLL_PFD2_GATE_MASK (0x00800000)
#define SCG_PLL_PFD1_GATE_MASK (0x00008000)
#define SCG_PLL_PFD0_GATE_MASK (0x00000080)
#define SCG_PLL_PFD3_VALID_MASK (0x40000000)
#define SCG_PLL_PFD2_VALID_MASK (0x00400000)
#define SCG_PLL_PFD1_VALID_MASK (0x00004000)
#define SCG_PLL_PFD0_VALID_MASK (0x00000040)
#define SCG_PLL_PFD0_FRAC_SHIFT (0)
#define SCG_PLL_PFD0_FRAC_MASK ((0x3F) << SCG_PLL_PFD0_FRAC_SHIFT)
#define SCG_PLL_PFD1_FRAC_SHIFT (8)
#define SCG_PLL_PFD1_FRAC_MASK ((0x3F) << SCG_PLL_PFD1_FRAC_SHIFT)
#define SCG_PLL_PFD2_FRAC_SHIFT (16)
#define SCG_PLL_PFD2_FRAC_MASK ((0x3F) << SCG_PLL_PFD2_FRAC_SHIFT)
#define SCG_PLL_PFD3_FRAC_SHIFT (24)
#define SCG_PLL_PFD3_FRAC_MASK ((0x3F) << SCG_PLL_PFD3_FRAC_SHIFT)
#define SCG_PLL_CFG_POSTDIV2_SHIFT (28)
#define SCG_PLL_CFG_POSTDIV2_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV2_SHIFT)
#define SCG_PLL_CFG_POSTDIV1_SHIFT (24)
#define SCG_PLL_CFG_POSTDIV1_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV1_SHIFT)
#define SCG_PLL_CFG_MULT_SHIFT (16)
#define SCG1_SPLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT)
#define SCG_APLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT)
#define SCG_PLL_CFG_PFDSEL_SHIFT (14)
#define SCG_PLL_CFG_PFDSEL_MASK ((0x3UL) << SCG_PLL_CFG_PFDSEL_SHIFT)
#define SCG_PLL_CFG_PREDIV_SHIFT (8)
#define SCG_PLL_CFG_PREDIV_MASK ((0x7UL) << SCG_PLL_CFG_PREDIV_SHIFT)
#define SCG_PLL_CFG_BYPASS_SHIFT (2)
/* 0: SPLL, 1: bypass */
#define SCG_PLL_CFG_BYPASS_MASK ((0x1UL) << SCG_PLL_CFG_BYPASS_SHIFT)
#define SCG_PLL_CFG_PLLSEL_SHIFT (1)
/* 0: pll, 1: pfd */
#define SCG_PLL_CFG_PLLSEL_MASK ((0x1UL) << SCG_PLL_CFG_PLLSEL_SHIFT)
#define SCG_PLL_CFG_CLKSRC_SHIFT (0)
/* 0: Sys-OSC, 1: FIRC */
#define SCG_PLL_CFG_CLKSRC_MASK ((0x1UL) << SCG_PLL_CFG_CLKSRC_SHIFT)
#define SCG0_SPLL_CFG_MULT_SHIFT (17)
/* 0: Multiplier = 20, 1: Multiplier = 22 */
#define SCG0_SPLL_CFG_MULT_MASK ((0x1UL) << SCG0_SPLL_CFG_MULT_SHIFT)
#define PLL_USB_EN_USB_CLKS_MASK (0x01 << 6)
#define PLL_USB_PWR_MASK (0x01 << 12)
#define PLL_USB_ENABLE_MASK (0x01 << 13)
#define PLL_USB_BYPASS_MASK (0x01 << 16)
#define PLL_USB_REG_ENABLE_MASK (0x01 << 21)
#define PLL_USB_DIV_SEL_MASK (0x07 << 22)
#define PLL_USB_LOCK_MASK (0x01 << 31)
enum scg_clk {
SCG_SOSC_CLK,
SCG_FIRC_CLK,
SCG_SIRC_CLK,
SCG_ROSC_CLK,
SCG_SIRC_DIV1_CLK,
SCG_SIRC_DIV2_CLK,
SCG_SIRC_DIV3_CLK,
SCG_FIRC_DIV1_CLK,
SCG_FIRC_DIV2_CLK,
SCG_FIRC_DIV3_CLK,
SCG_SOSC_DIV1_CLK,
SCG_SOSC_DIV2_CLK,
SCG_SOSC_DIV3_CLK,
SCG_CORE_CLK,
SCG_BUS_CLK,
SCG_SPLL_PFD0_CLK,
SCG_SPLL_PFD1_CLK,
SCG_SPLL_PFD2_CLK,
SCG_SPLL_PFD3_CLK,
SCG_DDR_CLK,
SCG_NIC0_CLK,
SCG_GPU_CLK,
SCG_NIC1_CLK,
SCG_NIC1_BUS_CLK,
SCG_NIC1_EXT_CLK,
SCG_APLL_PFD0_CLK,
SCG_APLL_PFD1_CLK,
SCG_APLL_PFD2_CLK,
SCG_APLL_PFD3_CLK,
USB_PLL_OUT,
MIPI_PLL_OUT
};
enum scg_sys_src {
SCG_SCS_SYS_OSC = 1,
SCG_SCS_SLOW_IRC,
SCG_SCS_FAST_IRC,
SCG_SCS_RTC_OSC,
SCG_SCS_AUX_PLL,
SCG_SCS_SYS_PLL,
SCG_SCS_USBPHY_PLL,
};
/* PLL supported by i.mx7ulp */
enum pll_clocks {
PLL_M4_SPLL, /* M4 SPLL */
PLL_M4_APLL, /* M4 APLL*/
PLL_A7_SPLL, /* A7 SPLL */
PLL_A7_APLL, /* A7 APLL */
PLL_USB, /* USB PLL*/
PLL_MIPI, /* MIPI PLL */
};
typedef struct scg_regs {
u32 verid; /* VERSION_ID */
u32 param; /* PARAMETER */
u32 rsvd11[2];
u32 csr; /* Clock Status Register */
u32 rccr; /* Run Clock Control Register */
u32 vccr; /* VLPR Clock Control Register */
u32 hccr; /* HSRUN Clock Control Register */
u32 clkoutcnfg; /* SCG CLKOUT Configuration Register */
u32 rsvd12[3];
u32 ddrccr; /* SCG DDR Clock Control Register */
u32 rsvd13[3];
u32 nicccr; /* NIC Clock Control Register */
u32 niccsr; /* NIC Clock Status Register */
u32 rsvd10[46];
u32 sosccsr; /* System OSC Control Status Register, offset 0x100 */
u32 soscdiv; /* System OSC Divide Register */
u32 sosccfg; /* System Oscillator Configuration Register */
u32 sosctest; /* System Oscillator Test Register */
u32 rsvd20[60];
u32 sirccsr; /* Slow IRC Control Status Register, offset 0x200 */
u32 sircdiv; /* Slow IRC Divide Register */
u32 sirccfg; /* Slow IRC Configuration Register */
u32 sirctrim; /* Slow IRC Trim Register */
u32 loptrim; /* Low Power Oscillator Trim Register */
u32 sirctest; /* Slow IRC Test Register */
u32 rsvd30[58];
u32 firccsr; /* Fast IRC Control Status Register, offset 0x300 */
u32 fircdiv;
u32 firccfg;
u32 firctcfg; /* Fast IRC Trim Configuration Register */
u32 firctriml; /* Fast IRC Trim Low Register */
u32 firctrimh;
u32 fircstat; /* Fast IRC Status Register */
u32 firctest; /* Fast IRC Test Register */
u32 rsvd40[56];
u32 rtccsr; /* RTC OSC Control Status Register, offset 0x400 */
u32 rsvd50[63];
u32 apllcsr; /* Auxiliary PLL Control Status Register, offset 0x500 */
u32 aplldiv; /* Auxiliary PLL Divider Register */
u32 apllcfg; /* Auxiliary PLL Configuration Register */
u32 apllpfd; /* Auxiliary PLL PFD Register */
u32 apllnum; /* Auxiliary PLL Numerator Register */
u32 aplldenom; /* Auxiliary PLL Denominator Register */
u32 apllss; /* Auxiliary PLL Spread Spectrum Register */
u32 rsvd60[55];
u32 apllock_cnfg; /* Auxiliary PLL LOCK Configuration Register */
u32 rsvd61[1];
u32 spllcsr; /* System PLL Control Status Register, offset 0x600 */
u32 splldiv; /* System PLL Divide Register */
u32 spllcfg; /* System PLL Configuration Register */
u32 spllpfd; /* System PLL Test Register */
u32 spllnum; /* System PLL Numerator Register */
u32 splldenom; /* System PLL Denominator Register */
u32 spllss; /* System PLL Spread Spectrum Register */
u32 rsvd70[55];
u32 spllock_cnfg; /* System PLL LOCK Configuration Register */
u32 rsvd71[1];
u32 upllcsr; /* USB PLL Control Status Register, offset 0x700 */
u32 uplldiv; /* USB PLL Divide Register */
u32 upllcfg; /* USB PLL Configuration Register */
} scg_t, *scg_p;
u32 scg_clk_get_rate(enum scg_clk clk);
int scg_enable_pll_pfd(enum scg_clk clk, u32 frac);
int scg_enable_usb_pll(bool usb_control);
u32 decode_pll(enum pll_clocks pll);
void scg_a7_rccr_init(void);
void scg_a7_spll_init(void);
void scg_a7_ddrclk_init(void);
void scg_a7_apll_init(void);
void scg_a7_firc_init(void);
void scg_a7_nicclk_init(void);
void scg_a7_sys_clk_sel(enum scg_sys_src clk);
void scg_a7_info(void);
void scg_a7_soscdiv_init(void);
#endif

21
arch/arm/include/asm/arch-mx7ulp/sys_proto.h Normal file
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@ -0,0 +1,21 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SYS_PROTO_MX7ULP_H_
#define _SYS_PROTO_MX7ULP_H_
#include <asm/imx-common/sys_proto.h>
#define BT0CFG_LPBOOT_MASK 0x1
#define BT0CFG_DUALBOOT_MASK 0x2
enum bt_mode {
LOW_POWER_BOOT, /* LP_BT = 1 */
DUAL_BOOT, /* LP_BT = 0, DUAL_BT = 1 */
SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */
};
#endif

1
arch/arm/include/asm/arch-vf610/clock.h
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@ -22,6 +22,7 @@ enum mxc_clock {
void enable_ocotp_clk(unsigned char enable);
unsigned int mxc_get_clock(enum mxc_clock clk);
u32 get_lpuart_clk(void);
#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)

28
arch/arm/include/asm/arch-vf610/imx-regs.h
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@ -429,34 +429,6 @@ struct fuse_bank4_regs {
u32 rsvd7[3];
};
/* UART */
struct lpuart_fsl {
u8 ubdh;
u8 ubdl;
u8 uc1;
u8 uc2;
u8 us1;
u8 us2;
u8 uc3;
u8 ud;
u8 uma1;
u8 uma2;
u8 uc4;
u8 uc5;
u8 ued;
u8 umodem;
u8 uir;
u8 reserved;
u8 upfifo;
u8 ucfifo;
u8 usfifo;
u8 utwfifo;
u8 utcfifo;
u8 urwfifo;
u8 urcfifo;
u8 rsvd[28];
};
/* MSCM Interrupt Router */
struct mscm_ir {
u32 ircp0ir;

49
arch/arm/include/asm/imx-common/sys_proto.h
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@ -8,6 +8,7 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
#include <asm/io.h>
#include <asm/imx-common/regs-common.h>
#include <common.h>
#include "../arch-imx/cpu.h"
@ -38,6 +39,54 @@
#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
#define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
#ifdef CONFIG_MX6
#define IMX6_SRC_GPR10_BMODE BIT(28)
#define IMX6_BMODE_MASK GENMASK(7, 0)
#define IMX6_BMODE_SHIFT 4
#define IMX6_BMODE_EMI_MASK BIT(3)
#define IMX6_BMODE_EMI_SHIFT 3
#define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24)
#define IMX6_BMODE_SERIAL_ROM_SHIFT 24
enum imx6_bmode_serial_rom {
IMX6_BMODE_ECSPI1,
IMX6_BMODE_ECSPI2,
IMX6_BMODE_ECSPI3,
IMX6_BMODE_ECSPI4,
IMX6_BMODE_ECSPI5,
IMX6_BMODE_I2C1,
IMX6_BMODE_I2C2,
IMX6_BMODE_I2C3,
};
enum imx6_bmode_emi {
IMX6_BMODE_ONENAND,
IMX6_BMODE_NOR,
};
enum imx6_bmode {
IMX6_BMODE_EMI,
IMX6_BMODE_UART,
IMX6_BMODE_SATA,
IMX6_BMODE_SERIAL_ROM,
IMX6_BMODE_SD,
IMX6_BMODE_ESD,
IMX6_BMODE_MMC,
IMX6_BMODE_EMMC,
IMX6_BMODE_NAND,
};
static inline u8 imx6_is_bmode_from_gpr9(void)
{
return readl(&src_base->gpr10) & IMX6_SRC_GPR10_BMODE;
}
u32 imx6_src_get_boot_mode(void);
#endif /* CONFIG_MX6 */
u32 get_nr_cpus(void);
u32 get_cpu_rev(void);
u32 get_cpu_speed_grade_hz(void);

15
board/armadeus/opos6uldev/Kconfig Normal file
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@ -0,0 +1,15 @@
if TARGET_OPOS6ULDEV
config SYS_BOARD
default "opos6uldev"
config SYS_VENDOR
default "armadeus"
config SYS_CONFIG_NAME
default "opos6uldev"
config IMX_CONFIG
default "arch/arm/imx-common/spl_sd.cfg"
endif

6
board/armadeus/opos6uldev/MAINTAINERS Normal file
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@ -0,0 +1,6 @@
OPOS6ULDev BOARD
M: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
S: Maintained
F: board/armadeus/opos6uldev/
F: include/configs/opos6uldev.h
F: configs/opos6uldev_defconfig

6
board/armadeus/opos6uldev/Makefile Normal file
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@ -0,0 +1,6 @@
# (C) Copyright 2017 Armadeus Systems
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := board.o

125
board/armadeus/opos6uldev/board.c Normal file
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@ -0,0 +1,125 @@
/*
* Copyright (C) 2017 Armadeus Systems
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/opos6ul.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_VIDEO_MXS
#define LCD_PAD_CTRL ( \
PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm \
)
static iomux_v3_cfg_t const lcd_pads[] = {
MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)
};
int setup_lcd(void)
{
struct gpio_desc backlight;
int ret;
enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
/* Set Brightness to high */
ret = dm_gpio_lookup_name("GPIO4_10", &backlight);
if (ret) {
printf("Cannot get GPIO4_10\n");
return ret;
}
ret = dm_gpio_request(&backlight, "backlight");
if (ret) {
printf("Cannot request GPIO4_10\n");
return ret;
}
dm_gpio_set_dir_flags(&backlight, GPIOD_IS_OUT);
dm_gpio_set_value(&backlight, 1);
return 0;
}
#endif
#ifdef CONFIG_USB_EHCI_MX6
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
int board_ehci_hcd_init(int port)
{
u32 *usbnc_usb_ctrl;
if (port > 1)
return -EINVAL;
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
port * 4);
/* Set Power polarity */
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
return 0;
}
#endif
int opos6ul_board_late_init(void)
{
#ifdef CONFIG_VIDEO_MXS
setup_lcd();
#endif
return 0;
}
#ifdef CONFIG_SPL_BUILD
#define UART_PAD_CTRL ( \
PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \
)
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
void opos6ul_setup_uart_debug(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
#endif /* CONFIG_SPL_BUILD */

1
board/engicam/geam6ul/MAINTAINERS
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@ -5,3 +5,4 @@ F: board/engicam/geam6ul
F: include/configs/imx6ul_geam.h
F: configs/imx6ul_geam_mmc_defconfig
F: configs/imx6ul_geam_nand_defconfig
F: arch/arm/dts/imx6ul-geam-kit.dts

3
board/engicam/icorem6/MAINTAINERS
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@ -7,3 +7,6 @@ F: configs/imx6q_icore_mmc_defconfig
F: configs/imx6q_icore_nand_defconfig
F: configs/imx6dl_icore_mmc_defconfig
F: configs/imx6dl_icore_nand_defconfig
F: arch/arm/dts/imx6qdl-icore.dtsi
F: arch/arm/dts/imx6q-icore.dts
F: arch/arm/dts/imx6dl-icore.dts

3
board/engicam/icorem6_rqs/MAINTAINERS
View File

@ -5,3 +5,6 @@ F: board/engicam/icorem6_rqs
F: include/configs/imx6qdl_icore_rqs.h
F: configs/imx6q_icore_rqs_mmc_defconfig
F: configs/imx6dl_icore_rqs_mmc_defconfig
F: arch/arm/dts/imx6qdl-icore-rqs.dtsi
F: arch/arm/dts/imx6q-icore-rqs.dts
F: arch/arm/dts/imx6dl-icore-rqs.dts

96
board/engicam/icorem6_rqs/icorem6_rqs.c
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@ -7,6 +7,7 @@
*/
#include <common.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/gpio.h>
@ -45,6 +46,51 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_ENV_IS_IN_MMC
int board_mmc_get_env_dev(int devno)
{
/* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
return (devno == 3) ? 1 : 0;
}
static void mmc_late_init(void)
{
char cmd[32];
char mmcblk[32];
u32 dev_no = mmc_get_env_dev();
setenv_ulong("mmcdev", dev_no);
/* Set mmcblk env */
sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
setenv("mmcroot", mmcblk);
sprintf(cmd, "mmc dev %d", dev_no);
run_command(cmd, 0);
}
#endif
int board_late_init(void)
{
switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
IMX6_BMODE_SHIFT) {
case IMX6_BMODE_SD:
case IMX6_BMODE_ESD:
case IMX6_BMODE_MMC:
case IMX6_BMODE_EMMC:
#ifdef CONFIG_ENV_IS_IN_MMC
mmc_late_init();
#endif
setenv("modeboot", "mmcboot");
break;
default:
setenv("modeboot", "");
break;
}
return 0;
}
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@ -77,8 +123,22 @@ static iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
struct fsl_esdhc_cfg usdhc_cfg[1] = {
static iomux_v3_cfg_t const usdhc4_pads[] = {
IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR, 1, 4},
{USDHC4_BASE_ADDR, 1, 8},
};
int board_mmc_getcd(struct mmc *mmc)
@ -88,6 +148,7 @@ int board_mmc_getcd(struct mmc *mmc)
switch (cfg->esdhc_base) {
case USDHC3_BASE_ADDR:
case USDHC4_BASE_ADDR:
ret = 1;
break;
}
@ -102,7 +163,8 @@ int board_mmc_init(bd_t *bis)
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* mmc0 USDHC3
* mmc0 USDHC3
* mmc1 USDHC4
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
@ -110,6 +172,10 @@ int board_mmc_init(bd_t *bis)
SETUP_IOMUX_PADS(usdhc3_pads);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
case 1:
SETUP_IOMUX_PADS(usdhc4_pads);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
break;
default:
printf("Warning - USDHC%d controller not supporting\n",
i + 1);
@ -125,6 +191,32 @@ int board_mmc_init(bd_t *bis)
return 0;
}
#ifdef CONFIG_ENV_IS_IN_MMC
void board_boot_order(u32 *spl_boot_list)
{
u32 bmode = imx6_src_get_boot_mode();
u8 boot_dev = BOOT_DEVICE_MMC1;
switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
case IMX6_BMODE_SD:
case IMX6_BMODE_ESD:
/* SD/eSD - BOOT_DEVICE_MMC1 */
break;
case IMX6_BMODE_MMC:
case IMX6_BMODE_EMMC:
/* MMC/eMMC */
boot_dev = BOOT_DEVICE_MMC2;
break;
default:
/* Default - BOOT_DEVICE_MMC1 */
printf("Wrong board boot order\n");
break;
}
spl_boot_list[0] = boot_dev;
}
#endif
#endif
/*

12
board/engicam/isiotmx6ul/Kconfig Normal file
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@ -0,0 +1,12 @@
if TARGET_MX6UL_ISIOT
config SYS_BOARD
default "isiotmx6ul"
config SYS_VENDOR
default "engicam"
config SYS_CONFIG_NAME
default "imx6ul_isiot"
endif

12
board/engicam/isiotmx6ul/MAINTAINERS Normal file
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@ -0,0 +1,12 @@
ISIOTMX6UL BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: board/engicam/isiotmx6ul
F: include/configs/imx6ul_isiot.h
F: configs/imx6ul_isiot_mmc_defconfig
F: configs/imx6ul_isiot_emmc_defconfig
F: configs/imx6ul_isiot_nand_defconfig
F: arch/arm/dts/imx6ul-isiot.dtsi
F: arch/arm/dts/imx6ul-isiot-mmc.dts
F: arch/arm/dts/imx6ul-isiot-emmc.dts
F: arch/arm/dts/imx6ul-isiot-nand.dts

6
board/engicam/isiotmx6ul/Makefile Normal file
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@ -0,0 +1,6 @@
# Copyright (C) 2016 Amarula Solutions B.V.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := isiotmx6ul.o

28
board/engicam/isiotmx6ul/README Normal file
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@ -0,0 +1,28 @@
How to use U-Boot on Engicam Is.IoT MX6UL Starter Kit:
-----------------------------------------------------
- Configure U-Boot for Engicam Is.IoT MX6UL
$ make mrproper
$ make imx6ul_isiot_mmc_defconfig
$ make
This will generate the SPL image called SPL and the u-boot-dtb.img.
- Flash the SPL image into the micro SD card:
sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
- Flash the u-boot-dtb.img image into the micro SD card:
sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
- Jumper settings:
MMC Boot: JM3 Closed
- Connect the Serial cable between the Starter Kit and the PC for the console.
(J28 is the Linux Serial console connector)
- Insert the micro SD card in the board, power it up and U-Boot messages should
come up.

414
board/engicam/isiotmx6ul/isiotmx6ul.c Normal file
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@ -0,0 +1,414 @@
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
* Author: Jagan Teki <jagan@amarulasolutions.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/sizes.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/iomux-v3.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
int board_early_init_f(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
return 0;
}
#ifdef CONFIG_NAND_MXS
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
static iomux_v3_cfg_t const nand_pads[] = {
MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
};
static void setup_gpmi_nand(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* config gpmi nand iomux */
imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
clrbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
/*
* config gpmi and bch clock to 100 MHz
* bch/gpmi select PLL2 PFD2 400M
* 100M = 400M / 4
*/
clrbits_le32(&mxc_ccm->cscmr1,
MXC_CCM_CSCMR1_BCH_CLK_SEL |
MXC_CCM_CSCMR1_GPMI_CLK_SEL);
clrsetbits_le32(&mxc_ccm->cscdr1,
MXC_CCM_CSCDR1_BCH_PODF_MASK |
MXC_CCM_CSCDR1_GPMI_PODF_MASK,
(3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
/* enable gpmi and bch clock gating */
setbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
/* enable apbh clock gating */
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
}
#endif /* CONFIG_NAND_MXS */
#ifdef CONFIG_ENV_IS_IN_MMC
int board_mmc_get_env_dev(int devno)
{
/* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
return (devno == 0) ? 0 : 1;
}
static void mmc_late_init(void)
{
char cmd[32];
char mmcblk[32];
u32 dev_no = mmc_get_env_dev();
setenv_ulong("mmcdev", dev_no);
/* Set mmcblk env */
sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
setenv("mmcroot", mmcblk);
sprintf(cmd, "mmc dev %d", dev_no);
run_command(cmd, 0);
}
#endif
int board_late_init(void)
{
switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
IMX6_BMODE_SHIFT) {
case IMX6_BMODE_SD:
case IMX6_BMODE_ESD:
case IMX6_BMODE_MMC:
case IMX6_BMODE_EMMC:
#ifdef CONFIG_ENV_IS_IN_MMC
mmc_late_init();
#endif
setenv("modeboot", "mmcboot");
break;
case IMX6_BMODE_NAND:
setenv("modeboot", "nandboot");
break;
default:
setenv("modeboot", "");
break;
}
return 0;
}
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
#endif
return 0;
}
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
#ifdef CONFIG_SPL_BUILD
#include <libfdt.h>
#include <spl.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-ddr.h>
/* MMC board initialization is needed till adding DM support in SPL */
#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
#include <mmc.h>
#include <fsl_esdhc.h>
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* VSELECT */
MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* CD */
MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* RST_B */
MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR, 0, 4},
{USDHC2_BASE_ADDR, 0, 8},
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = !gpio_get_value(USDHC1_CD_GPIO);
break;
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* mmc0 USDHC1
* mmc1 USDHC2
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
gpio_direction_input(USDHC1_CD_GPIO);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc1_pads, ARRAY_SIZE(usdhc2_pads));
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
default:
printf("Warning - USDHC%d controller not supporting\n",
i + 1);
return 0;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret) {
printf("Warning: failed to initialize mmc dev %d\n", i);
return ret;
}
}
return 0;
}
#ifdef CONFIG_ENV_IS_IN_MMC
void board_boot_order(u32 *spl_boot_list)
{
u32 bmode = imx6_src_get_boot_mode();
u8 boot_dev = BOOT_DEVICE_MMC1;
switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
case IMX6_BMODE_SD:
case IMX6_BMODE_ESD:
/* SD/eSD - BOOT_DEVICE_MMC1 */
break;
case IMX6_BMODE_MMC:
case IMX6_BMODE_EMMC:
/* MMC/eMMC */
boot_dev = BOOT_DEVICE_MMC2;
break;
default:
/* Default - BOOT_DEVICE_MMC1 */
printf("Wrong board boot order\n");
break;
}
spl_boot_list[0] = boot_dev;
}
#endif
#endif /* CONFIG_FSL_ESDHC */
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000030,
.grp_ddrmode_ctl = 0x00020000,
.grp_b0ds = 0x00000030,
.grp_ctlds = 0x00000030,
.grp_b1ds = 0x00000030,
.grp_ddrpke = 0x00000000,
.grp_ddrmode = 0x00020000,
.grp_ddr_type = 0x000c0000,
};
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm0 = 0x00000030,
.dram_dqm1 = 0x00000030,
.dram_ras = 0x00000030,
.dram_cas = 0x00000030,
.dram_odt0 = 0x00000030,
.dram_odt1 = 0x00000030,
.dram_sdba2 = 0x00000000,
.dram_sdclk_0 = 0x00000008,
.dram_sdqs0 = 0x00000038,
.dram_sdqs1 = 0x00000030,
.dram_reset = 0x00000030,
};
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p0_mpwldectrl0 = 0x00070007,
.p0_mpdgctrl0 = 0x41490145,
.p0_mprddlctl = 0x40404546,
.p0_mpwrdlctl = 0x4040524D,
};
struct mx6_ddr_sysinfo ddr_sysinfo = {
.dsize = 0,
.cs_density = 20,
.ncs = 1,
.cs1_mirror = 0,
.rtt_wr = 2,
.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
};
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 800,
.density = 4,
.width = 16,
.banks = 8,
.rowaddr = 15,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
};
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0x00c03f3f, &ccm->CCGR0);
writel(0xfcffff00, &ccm->CCGR1);
writel(0x0cffffcc, &ccm->CCGR2);
writel(0x3f3c3030, &ccm->CCGR3);
writel(0xff00fffc, &ccm->CCGR4);
writel(0x033f30ff, &ccm->CCGR5);
writel(0x00c00fff, &ccm->CCGR6);
}
static void spl_dram_init(void)
{
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
/* iomux and setup of i2c */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
#endif /* CONFIG_SPL_BUILD */

12
board/freescale/mx7ulp_evk/Kconfig Normal file
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@ -0,0 +1,12 @@
if TARGET_MX7ULP_EVK
config SYS_BOARD
default "mx7ulp_evk"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "mx7ulp_evk"
endif

7
board/freescale/mx7ulp_evk/MAINTAINERS Normal file
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@ -0,0 +1,7 @@
MX7ULPEVK BOARD
M: Peng Fan <peng.fan@nxp.com>
S: Maintained
F: board/freescale/mx7ulp_evk/
F: include/configs/mx7ulp_evk.h
F: configs/mx7ulp_evk_defconfig
F: configs/mx7ulp_evk_plugin_defconfig

10
board/freescale/mx7ulp_evk/Makefile Normal file
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@ -0,0 +1,10 @@
# (C) Copyright 2016 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := mx7ulp_evk.o
extra-$(CONFIG_USE_PLUGIN) := plugin.bin
$(obj)/plugin.bin: $(obj)/plugin.o
$(OBJCOPY) -O binary --gap-fill 0xff $< $@

137
board/freescale/mx7ulp_evk/imximage.cfg Normal file
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@ -0,0 +1,137 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi/sd/nand/onenand, qspi/nor
*/
BOOT_FROM sd
#ifdef CONFIG_USE_IMXIMG_PLUGIN
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
PLUGIN board/freescale/mx7ulp_evk/plugin.bin 0x2F020000
#else
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x403f00dc 0x00000000
DATA 4 0x403e0040 0x01000020
DATA 4 0x403e0500 0x01000000
DATA 4 0x403e050c 0x80808080
DATA 4 0x403e0508 0x00140000
DATA 4 0x403E0510 0x00000004
DATA 4 0x403E0514 0x00000002
DATA 4 0x403e0500 0x00000001
CHECK_BITS_SET 4 0x403e0500 0x01000000
DATA 4 0x403e050c 0x8080801E
CHECK_BITS_SET 4 0x403e050c 0x00000040
DATA 4 0x403E0030 0x00000001
DATA 4 0x403e0040 0x11000020
DATA 4 0x403f00dc 0x42000000
DATA 4 0x40B300AC 0x40000000
DATA 4 0x40AD0128 0x00040000
DATA 4 0x40AD00F8 0x00000000
DATA 4 0x40AD00D8 0x00000180
DATA 4 0x40AD0108 0x00000180
DATA 4 0x40AD0104 0x00000180
DATA 4 0x40AD0124 0x00010000
DATA 4 0x40AD0080 0x0000018C
DATA 4 0x40AD0084 0x0000018C
DATA 4 0x40AD0088 0x0000018C
DATA 4 0x40AD008C 0x0000018C
DATA 4 0x40AD0120 0x00010000
DATA 4 0x40AD010C 0x00000180
DATA 4 0x40AD0110 0x00000180
DATA 4 0x40AD0114 0x00000180
DATA 4 0x40AD0118 0x00000180
DATA 4 0x40AD0090 0x00000180
DATA 4 0x40AD0094 0x00000180
DATA 4 0x40AD0098 0x00000180
DATA 4 0x40AD009C 0x00000180
DATA 4 0x40AD00E0 0x00040000
DATA 4 0x40AD00E4 0x00040000
DATA 4 0x40AB001C 0x00008000
DATA 4 0x40AB0800 0xA1390003
DATA 4 0x40AB085C 0x0D3900A0
DATA 4 0x40AB0890 0x00400000
DATA 4 0x40AB0848 0x40404040
DATA 4 0x40AB0850 0x40404040
DATA 4 0x40AB081C 0x33333333
DATA 4 0x40AB0820 0x33333333
DATA 4 0x40AB0824 0x33333333
DATA 4 0x40AB0828 0x33333333
DATA 4 0x40AB082C 0xf3333333
DATA 4 0x40AB0830 0xf3333333
DATA 4 0x40AB0834 0xf3333333
DATA 4 0x40AB0838 0xf3333333
DATA 4 0x40AB08C0 0x24922492
DATA 4 0x40AB08B8 0x00000800
DATA 4 0x40AB0004 0x00020052
DATA 4 0x40AB000C 0x292C42F3
DATA 4 0x40AB0010 0x00100A22
DATA 4 0x40AB0038 0x00120556
DATA 4 0x40AB0014 0x00C700DB
DATA 4 0x40AB0018 0x00211718
DATA 4 0x40AB002C 0x0F9F26D2
DATA 4 0x40AB0030 0x009F0E10
DATA 4 0x40AB0040 0x0000003F
DATA 4 0x40AB0000 0xC3190000
DATA 4 0x40AB001C 0x00008050
DATA 4 0x40AB001C 0x00008058
DATA 4 0x40AB001C 0x003F8030
DATA 4 0x40AB001C 0x003F8038
DATA 4 0x40AB001C 0xFF0A8030
DATA 4 0x40AB001C 0xFF0A8038
DATA 4 0x40AB001C 0x04028030
DATA 4 0x40AB001C 0x04028038
DATA 4 0x40AB001C 0x83018030
DATA 4 0x40AB001C 0x83018038
DATA 4 0x40AB001C 0x01038030
DATA 4 0x40AB001C 0x01038038
DATA 4 0x40AB083C 0x20000000
DATA 4 0x40AB0020 0x00001800
DATA 4 0x40AB0800 0xA1310000
DATA 4 0x40AB0004 0x00020052
DATA 4 0x40AB0404 0x00011006
DATA 4 0x40AB001C 0x00000000
#endif

48
board/freescale/mx7ulp_evk/mx7ulp_evk.c Normal file
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@ -0,0 +1,48 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mx7ulp-pins.h>
#include <asm/arch/iomux.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_UP)
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
static iomux_cfg_t const lpuart4_pads[] = {
MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
mx7ulp_iomux_setup_multiple_pads(lpuart4_pads,
ARRAY_SIZE(lpuart4_pads));
}
int board_early_init_f(void)
{
setup_iomux_uart();
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
return 0;
}

224
board/freescale/mx7ulp_evk/plugin.S Normal file
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@ -0,0 +1,224 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
.macro imx7ulp_ddr_freq_decrease
ldr r2, =0x403f0000
ldr r3, =0x00000000
str r3, [r2, #0xdc]
ldr r2, =0x403e0000
ldr r3, =0x01000020
str r3, [r2, #0x40]
ldr r3, =0x01000000
str r3, [r2, #0x500]
ldr r3, =0x80808080
str r3, [r2, #0x50c]
ldr r3, =0x00140000
str r3, [r2, #0x508]
ldr r3, =0x00000004
str r3, [r2, #0x510]
ldr r3, =0x00000002
str r3, [r2, #0x514]
ldr r3, =0x00000001
str r3, [r2, #0x500]
ldr r3, =0x01000000
wait1:
ldr r4, [r2, #0x500]
and r4, r3
cmp r4, r3
bne wait1
ldr r3, =0x8080801E
str r3, [r2, #0x50c]
ldr r3, =0x00000040
wait2:
ldr r4, [r2, #0x50c]
and r4, r3
cmp r4, r3
bne wait2
ldr r3, =0x00000001
str r3, [r2, #0x30]
ldr r3, =0x11000020
str r3, [r2, #0x40]
ldr r2, =0x403f0000
ldr r3, =0x42000000
str r3, [r2, #0xdc]
.endm
.macro imx7ulp_evk_ddr_setting
imx7ulp_ddr_freq_decrease
/* Enable MMDC PCC clock */
ldr r2, =0x40b30000
ldr r3, =0x40000000
str r3, [r2, #0xac]
/* Configure DDR pad */
ldr r0, =0x40ad0000
ldr r1, =0x00040000
str r1, [r0, #0x128]
ldr r1, =0x0
str r1, [r0, #0xf8]
ldr r1, =0x00000180
str r1, [r0, #0xd8]
ldr r1, =0x00000180
str r1, [r0, #0x108]
ldr r1, =0x00000180
str r1, [r0, #0x104]
ldr r1, =0x00010000
str r1, [r0, #0x124]
ldr r1, =0x0000018C
str r1, [r0, #0x80]
ldr r1, =0x0000018C
str r1, [r0, #0x84]
ldr r1, =0x0000018C
str r1, [r0, #0x88]
ldr r1, =0x0000018C
str r1, [r0, #0x8c]
ldr r1, =0x00010000
str r1, [r0, #0x120]
ldr r1, =0x00000180
str r1, [r0, #0x10c]
ldr r1, =0x00000180
str r1, [r0, #0x110]
ldr r1, =0x00000180
str r1, [r0, #0x114]
ldr r1, =0x00000180
str r1, [r0, #0x118]
ldr r1, =0x00000180
str r1, [r0, #0x90]
ldr r1, =0x00000180
str r1, [r0, #0x94]
ldr r1, =0x00000180
str r1, [r0, #0x98]
ldr r1, =0x00000180
str r1, [r0, #0x9c]
ldr r1, =0x00040000
str r1, [r0, #0xe0]
ldr r1, =0x00040000
str r1, [r0, #0xe4]
ldr r0, =0x40ab0000
ldr r1, =0x00008000
str r1, [r0, #0x1c]
ldr r1, =0xA1390003
str r1, [r0, #0x800]
ldr r1, =0x0D3900A0
str r1, [r0, #0x85c]
ldr r1, =0x00400000
str r1, [r0, #0x890]
ldr r1, =0x40404040
str r1, [r0, #0x848]
ldr r1, =0x40404040
str r1, [r0, #0x850]
ldr r1, =0x33333333
str r1, [r0, #0x81c]
ldr r1, =0x33333333
str r1, [r0, #0x820]
ldr r1, =0x33333333
str r1, [r0, #0x824]
ldr r1, =0x33333333
str r1, [r0, #0x828]
ldr r1, =0xf3333333
str r1, [r0, #0x82c]
ldr r1, =0xf3333333
str r1, [r0, #0x830]
ldr r1, =0xf3333333
str r1, [r0, #0x834]
ldr r1, =0xf3333333
str r1, [r0, #0x838]
ldr r1, =0x24922492
str r1, [r0, #0x8c0]
ldr r1, =0x00000800
str r1, [r0, #0x8b8]
ldr r1, =0x00020052
str r1, [r0, #0x4]
ldr r1, =0x292C42F3
str r1, [r0, #0xc]
ldr r1, =0x00100A22
str r1, [r0, #0x10]
ldr r1, =0x00120556
str r1, [r0, #0x38]
ldr r1, =0x00C700DB
str r1, [r0, #0x14]
ldr r1, =0x00211718
str r1, [r0, #0x18]
ldr r1, =0x0F9F26D2
str r1, [r0, #0x2c]
ldr r1, =0x009F0E10
str r1, [r0, #0x30]
ldr r1, =0x0000003F
str r1, [r0, #0x40]
ldr r1, =0xC3190000
str r1, [r0, #0x0]
ldr r1, =0x00008050
str r1, [r0, #0x1c]
ldr r1, =0x00008058
str r1, [r0, #0x1c]
ldr r1, =0x003F8030
str r1, [r0, #0x1c]
ldr r1, =0x003F8038
str r1, [r0, #0x1c]
ldr r1, =0xFF0A8030
str r1, [r0, #0x1c]
ldr r1, =0xFF0A8038
str r1, [r0, #0x1c]
ldr r1, =0x04028030
str r1, [r0, #0x1c]
ldr r1, =0x04028038
str r1, [r0, #0x1c]
ldr r1, =0x83018030
str r1, [r0, #0x1c]
ldr r1, =0x83018038
str r1, [r0, #0x1c]
ldr r1, =0x01038030
str r1, [r0, #0x1c]
ldr r1, =0x01038038
str r1, [r0, #0x1c]
ldr r1, =0x20000000
str r1, [r0, #0x83c]
ldr r1, =0x00001800
str r1, [r0, #0x20]
ldr r1, =0xA1310000
str r1, [r0, #0x800]
ldr r1, =0x00020052
str r1, [r0, #0x4]
ldr r1, =0x00011006
str r1, [r0, #0x404]
ldr r1, =0x00000000
str r1, [r0, #0x1c]
.endm
.macro imx7ulp_clock_gating
.endm
.macro imx7ulp_qos_setting
.endm
.macro imx7ulp_ddr_setting
imx7ulp_evk_ddr_setting
.endm
/* include the common plugin code here */
#include <asm/arch/mx7ulp_plugin.S>

3
board/freescale/vf610twr/Kconfig
View File

@ -6,9 +6,6 @@ config SYS_BOARD
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "vf610"
config SYS_CONFIG_NAME
default "vf610twr"

17
board/gateworks/gw_ventana/README
View File

@ -30,7 +30,12 @@ will build the following artifacts from U-Boot source:
To build U-Boot for the Gateworks Ventana product family:
make gwventana_config
For NAND FLASH based boards:
make gwventana_nand_config
make
For EMMC FLASH based boards:
make gwventana_emmc_config
make
@ -99,11 +104,11 @@ This information is taken from:
More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
3.1. boot from micro-SD
-----------------------
3.1. boot from MMC (eMMC/microSD)
---------------------------------
When the IMX6 eFUSE settings have been factory programmed to boot from
micro-SD the SPL will be loaded from offset 0x400 (1KB). Once the SPL is
MMC the SPL will be loaded from offset 0x400 (1KB). Once the SPL is
booted, it will load and execute U-Boot (u-boot.img) from offset 69KB
on the micro-SD (defined by CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR).
@ -111,11 +116,11 @@ While it is technically possible to enable the SPL to be able to load
U-Boot from a file on a FAT/EXT filesystem on the micro-SD, we chose to
use raw micro-SD access to keep the code-size and boot time of the SPL down.
For these reasons a micro-SD that will be used as an IMX6 primary boot
For these reasons an MMC device that will be used as an IMX6 primary boot
device must be carefully partitioned and prepared.
The following shell commands are executed on a Linux host (adjust DEV to the
block storage device of your micro-SD):
block storage device of your MMC, ie /dev/mmcblk0):
DEV=/dev/sdc
# zero out 1MB of device

83
board/gateworks/gw_ventana/common.c
View File

@ -6,10 +6,12 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <fsl_esdhc.h>
#include <hwconfig.h>
#include <power/pmic.h>
#include <power/ltc3676_pmic.h>
@ -35,6 +37,17 @@ void setup_iomux_uart(void)
SETUP_IOMUX_PADS(uart2_pads);
}
/* MMC */
static iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
/* I2C1: GSC */
static struct i2c_pads_info mx6q_i2c_pad_info0 = {
.scl = {
@ -130,12 +143,6 @@ void setup_ventana_i2c(void)
* Baseboard specific GPIO
*/
/* common to add baseboards */
static iomux_v3_cfg_t const gw_gpio_pads[] = {
/* SD3_VSELECT */
IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
};
/* prototype */
static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
/* RS232_EN# */
@ -183,6 +190,8 @@ static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
};
static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
/* SD3_VSELECT */
IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
/* RS232_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
/* MSATA_EN */
@ -216,6 +225,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
};
static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
/* SD3_VSELECT */
IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
/* RS232_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
/* MSATA_EN */
@ -249,6 +260,8 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
};
static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
/* SD3_VSELECT */
IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
/* RS232_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
/* MSATA_EN */
@ -325,11 +338,12 @@ static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
};
static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
/* SD3_VSELECT */
IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
/* PANLEDG# */
IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
/* PANLEDR# */
IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 | DIO_PAD_CFG),
/* VID_PWR */
IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
/* PCI_RST# */
@ -573,6 +587,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.rs485en = IMX_GPIO_NR(3, 24),
.dioi2c_en = IMX_GPIO_NR(4, 5),
.pcie_sson = IMX_GPIO_NR(1, 20),
.otgpwr_en = IMX_GPIO_NR(3, 22),
},
/* GW51xx */
@ -591,6 +606,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.gps_shdn = IMX_GPIO_NR(1, 2),
.vidin_en = IMX_GPIO_NR(5, 20),
.wdis = IMX_GPIO_NR(7, 12),
.otgpwr_en = IMX_GPIO_NR(3, 22),
},
/* GW52xx */
@ -613,6 +629,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.wdis = IMX_GPIO_NR(7, 12),
.msata_en = GP_MSATA_SEL,
.rs232_en = GP_RS232_EN,
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
},
/* GW53xx */
@ -634,6 +652,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.wdis = IMX_GPIO_NR(7, 12),
.msata_en = GP_MSATA_SEL,
.rs232_en = GP_RS232_EN,
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
},
/* GW54xx */
@ -657,6 +677,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.wdis = IMX_GPIO_NR(5, 17),
.msata_en = GP_MSATA_SEL,
.rs232_en = GP_RS232_EN,
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
},
/* GW551x */
@ -702,6 +724,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.pcie_rst = IMX_GPIO_NR(1, 0),
.vidin_en = IMX_GPIO_NR(5, 20),
.wdis = IMX_GPIO_NR(7, 12),
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
},
};
@ -709,13 +733,6 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
{
int i;
/* iomux common to all Ventana boards */
SETUP_IOMUX_PADS(gw_gpio_pads);
/* OTG power off */
gpio_request(GP_USB_OTG_PWR, "usbotg_pwr");
gpio_direction_output(GP_USB_OTG_PWR, 0);
if (board >= GW_UNKNOWN)
return;
@ -725,7 +742,7 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
/* RS232_EN# */
if (gpio_cfg[board].rs232_en) {
gpio_request(gpio_cfg[board].rs232_en, "rs232_en");
gpio_request(gpio_cfg[board].rs232_en, "rs232_en#");
gpio_direction_output(gpio_cfg[board].rs232_en, 0);
}
@ -805,10 +822,18 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
gpio_direction_output(gpio_cfg[board].wdis, 1);
}
/* OTG power off */
if (gpio_cfg[board].otgpwr_en) {
gpio_request(gpio_cfg[board].otgpwr_en, "usbotg_pwr");
gpio_direction_output(gpio_cfg[board].otgpwr_en, 0);
}
/* sense vselect pin to see if we support uhs-i */
gpio_request(GP_SD3_VSELECT, "sd3_vselect");
gpio_direction_input(GP_SD3_VSELECT);
gpio_cfg[board].usd_vsel = !gpio_get_value(GP_SD3_VSELECT);
if (gpio_cfg[board].vsel_pin) {
gpio_request(gpio_cfg[board].vsel_pin, "sd3_vselect");
gpio_direction_input(gpio_cfg[board].vsel_pin);
gpio_cfg[board].usd_vsel = !gpio_get_value(gpio_cfg[board].vsel_pin);
}
}
/* setup GPIO pinmux and default configuration per baseboard and env */
@ -964,3 +989,25 @@ void setup_pmic(void)
}
}
}
#ifdef CONFIG_FSL_ESDHC
static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
int board_mmc_init(bd_t *bis)
{
/* Only one USDHC controller on Ventana */
SETUP_IOMUX_PADS(usdhc3_pads);
usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg.max_bus_width = 4;
return fsl_esdhc_initialize(bis, &usdhc_cfg);
}
int board_mmc_getcd(struct mmc *mmc)
{
/* Card Detect */
gpio_request(GP_SD3_CD, "sd_cd");
gpio_direction_input(GP_SD3_CD);
return !gpio_get_value(GP_SD3_CD);
}
#endif /* CONFIG_FSL_ESDHC */

4
board/gateworks/gw_ventana/common.h
View File

@ -13,11 +13,9 @@
/* GPIO's common to all baseboards */
#define GP_PHY_RST IMX_GPIO_NR(1, 30)
#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
#define GP_SD3_CD IMX_GPIO_NR(7, 0)
#define GP_RS232_EN IMX_GPIO_NR(2, 11)
#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
#define GP_SD3_VSELECT IMX_GPIO_NR(6, 14)
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
@ -79,6 +77,8 @@ struct ventana {
int wdis;
int msata_en;
int rs232_en;
int otgpwr_en;
int vsel_pin;
/* various features */
bool usd_vsel;
};

43
board/gateworks/gw_ventana/gw_ventana.c
View File

@ -52,17 +52,6 @@ struct ventana_board_info ventana_info;
static int board_type;
/* MMC */
static iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
/* ENET */
static iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
@ -186,35 +175,15 @@ int board_ehci_hcd_init(int port)
int board_ehci_power(int port, int on)
{
if (port)
return 0;
gpio_set_value(GP_USB_OTG_PWR, on);
/* enable OTG VBUS */
if (!port && board_type < GW_UNKNOWN) {
if (gpio_cfg[board_type].otgpwr_en)
gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
}
return 0;
}
#endif /* CONFIG_USB_EHCI_MX6 */
#ifdef CONFIG_FSL_ESDHC
static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
int board_mmc_getcd(struct mmc *mmc)
{
/* Card Detect */
gpio_request(GP_SD3_CD, "sd_cd");
gpio_direction_input(GP_SD3_CD);
return !gpio_get_value(GP_SD3_CD);
}
int board_mmc_init(bd_t *bis)
{
/* Only one USDHC controller on Ventana */
SETUP_IOMUX_PADS(usdhc3_pads);
usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg.max_bus_width = 4;
return fsl_esdhc_initialize(bis, &usdhc_cfg);
}
#endif /* CONFIG_FSL_ESDHC */
#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */
@ -772,7 +741,7 @@ int misc_init_r(void)
/* Set a non-initialized hwconfig based on board configuration */
if (!strcmp(getenv("hwconfig"), "_UNKNOWN_")) {
sprintf(buf, "hwconfig=");
buf[0] = 0;
if (gpio_cfg[board_type].rs232_en)
strcat(buf, "rs232;");
for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {

45
board/gateworks/gw_ventana/gw_ventana_spl.c
View File

@ -355,6 +355,25 @@ static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
.p1_mpwrdlctl = 0X40304239,
};
static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x0048004A,
.p0_mpwldectrl1 = 0x003F004A,
.p1_mpwldectrl0 = 0x001E0028,
.p1_mpwldectrl1 = 0x002C0043,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x02250219,
.p0_mpdgctrl1 = 0x01790202,
.p1_mpdgctrl0 = 0x02080208,
.p1_mpdgctrl1 = 0x016C0175,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x4A4C4D4C,
.p1_mprddlctl = 0x494C4A48,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0x403F3437,
.p1_mpwrdlctl = 0x383A3930,
};
static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x002A0025,
@ -368,6 +387,25 @@ static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
.p0_mpwrdlctl = 0x303E3C36,
};
static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x00230020,
.p0_mpwldectrl1 = 0x002F002A,
.p1_mpwldectrl0 = 0x001D0027,
.p1_mpwldectrl1 = 0x00100023,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x03250339,
.p0_mpdgctrl1 = 0x031C0316,
.p1_mpdgctrl0 = 0x03210331,
.p1_mpdgctrl1 = 0x031C025A,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x40373C40,
.p1_mprddlctl = 0x3A373646,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0x2E353933,
.p1_mpwrdlctl = 0x3C2F3F35,
};
static void spl_dram_init(int width, int size_mb, int board_model)
{
struct mx6_ddr3_cfg *mem = NULL;
@ -468,7 +506,14 @@ static void spl_dram_init(int width, int size_mb, int board_model)
mem = &mt41k256m16ha_125;
if (is_cpu_type(MXC_CPU_MX6Q))
calib = &mx6dq_256x64_mmdc_calib;
else
calib = &mx6sdl_256x64_mmdc_calib;
debug("4gB density\n");
} else if (width == 64 && size_mb == 4096) {
mem = &mt41k512m16ha_125;
if (is_cpu_type(MXC_CPU_MX6Q))
calib = &mx6dq_512x64_mmdc_calib;
debug("8gB density\n");
}
if (!(mem && calib)) {

6
board/phytec/pcm052/Kconfig
View File

@ -6,9 +6,6 @@ config SYS_BOARD
config SYS_VENDOR
default "phytec"
config SYS_SOC
default "vf610"
config SYS_CONFIG_NAME
default "pcm052"
@ -26,9 +23,6 @@ config SYS_BOARD
config SYS_VENDOR
default "phytec"
config SYS_SOC
default "vf610"
config SYS_CONFIG_NAME
default "bk4r1"

57
board/toradex/colibri_imx7/colibri_imx7.c
View File

@ -16,13 +16,17 @@
#include <common.h>
#include <dm.h>
#include <dm/platform_data/serial_mxc.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>
#include <jffs2/load_kernel.h>
#include <linux/sizes.h>
#include <mmc.h>
#include <miiphy.h>
#include <mtd_node.h>
#include <netdev.h>
#include <power/pmic.h>
#include <power/rn5t567_pmic.h>
#include <usb.h>
#include <usb/ehci-ci.h>
#include "../common/tdx-common.h"
@ -46,6 +50,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
#define USB_CDET_GPIO IMX_GPIO_NR(7, 14)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@ -71,6 +77,12 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#ifdef CONFIG_USB_EHCI_MX7
static iomux_v3_cfg_t const usb_cdet_pads[] = {
MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#endif
#ifdef CONFIG_NAND_MXS
static iomux_v3_cfg_t const gpmi_pads[] = {
MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
@ -319,6 +331,11 @@ int board_init(void)
setup_lcd();
#endif
#ifdef CONFIG_USB_EHCI_MX7
imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
#endif
return 0;
}
@ -359,6 +376,22 @@ int power_init_board(void)
/* set judge and press timer of N_OE to minimal values */
pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
/* configure sleep slot for 3.3V Ethernet */
reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
reg = (reg & 0xf0) | reg >> 4;
pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
/* disable DCDC2 discharge to avoid backfeeding through VFB2 */
pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
/* configure sleep slot for ARM rail */
reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
reg = (reg & 0xf0) | reg >> 4;
pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
/* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
return 0;
}
@ -391,6 +424,16 @@ int checkboard(void)
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
static struct node_info nodes[] = {
{ "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
};
/* Update partition nodes using info from mtdparts env var */
puts(" Updating MTD partitions...\n");
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif
return ft_common_board_setup(blob, bd);
}
#endif
@ -417,4 +460,18 @@ int board_ehci_hcd_init(int port)
}
return 0;
}
int board_usb_phy_mode(int port)
{
switch (port) {
case 0:
if (gpio_get_value(USB_CDET_GPIO))
return USB_INIT_DEVICE;
else
return USB_INIT_HOST;
case 1:
default:
return USB_INIT_HOST;
}
}
#endif

6
board/toradex/colibri_vf/Kconfig
View File

@ -1,17 +1,11 @@
if TARGET_COLIBRI_VF
config SYS_CPU
default "armv7"
config SYS_BOARD
default "colibri_vf"
config SYS_VENDOR
default "toradex"
config SYS_SOC
default "vf610"
config SYS_CONFIG_NAME
default "colibri_vf"

7
board/tqc/tqma6/Kconfig
View File

@ -22,6 +22,12 @@ config TQMA6Q
help
select TQMa6Q / TQMa6D with i.MX6Q/D and 1GiB DRAM
config TQMA6DL
bool "TQMa6DL"
select MX6DL
help
select TQMa6DL with i.MX6DL and 1GiB DRAM
config TQMA6S
bool "TQMa6S"
select MX6S
@ -70,6 +76,7 @@ endchoice
config IMX_CONFIG
default "board/tqc/tqma6/tqma6q.cfg" if TQMA6Q
default "board/tqc/tqma6/tqma6dl.cfg" if TQMA6DL
default "board/tqc/tqma6/tqma6s.cfg" if TQMA6S
endif

3
board/tqc/tqma6/README
View File

@ -21,6 +21,7 @@ To build U-Boot for the TQ Systems TQMa6 modules:
x is a placeholder for the CPU variant
q - means i.MX6Q/D: TQMa6Q (i.MX6Q) and TQMa6D (i.MX6D)
dl - means i.MX6DL: TQMa6DL (i.MX6DL)
s - means i.MX6S: TQMa6S (i.MX6S)
baseboard is a placeholder for the boot device
@ -31,5 +32,7 @@ This gives the following configurations:
tqma6q_mba6_mmc_config
tqma6q_mba6_spi_config
tqma6dl_mba6_mmc_config
tqma6dl_mba6_spi_config
tqma6s_mba6_mmc_config
tqma6s_mba6_spi_config

31
board/tqc/tqma6/tqma6.c
View File

@ -47,7 +47,7 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
int dram_init(void)
@ -232,25 +232,27 @@ static const char *tqma6_get_boardname(void)
};
}
int board_late_init(void)
/* setup board specific PMIC */
int power_init_board(void)
{
struct pmic *p;
u32 reg;
u32 reg, rev;
setenv("board_name", tqma6_get_boardname());
/*
* configure PFUZE100 PMIC:
* TODO: should go to power_init_board if bus switching is
* fixed in generic power code
*/
power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
p = pmic_get("PFUZE100");
if (p && !pmic_probe(p)) {
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
pmic_reg_read(p, PFUZE100_REVID, &rev);
printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev);
}
return 0;
}
int board_late_init(void)
{
setenv("board_name", tqma6_get_boardname());
tqma6_bb_board_late_init();
return 0;
@ -267,8 +269,15 @@ int checkboard(void)
* Device Tree Support
*/
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
#define MODELSTRLEN 32u
int ft_board_setup(void *blob, bd_t *bd)
{
char modelstr[MODELSTRLEN];
snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(),
tqma6_bb_get_boardname());
do_fixup_by_path_string(blob, "/", "model", modelstr);
fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size);
/* bring in eMMC dsr settings */
do_fixup_by_path_u32(blob,
"/soc/aips-bus@02100000/usdhc@02198000",

47
board/tqc/tqma6/tqma6_mba6.c
View File

@ -51,22 +51,22 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#if defined(CONFIG_MX6Q)
#if defined(CONFIG_TQMA6Q)
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790
#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac
#elif defined(CONFIG_MX6S)
#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768
#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788
#else
#error "need to define target CPU"
#error "need to select module"
#endif
@ -114,6 +114,11 @@ static iomux_v3_cfg_t const mba6_enet_pads[] = {
static void mba6_setup_iomuxc_enet(void)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* clear gpr1[ENET_CLK_SEL] for externel clock */
clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
__raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
(void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
__raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
@ -125,7 +130,7 @@ static void mba6_setup_iomuxc_enet(void)
/* Reset PHY */
gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
/* Need delay 10ms after power on according to KSZ9031 spec */
udelay(1000 * 10);
mdelay(10);
gpio_set_value(ENET_PHY_RESET_GPIO, 1);
/*
* KSZ9031 manual: 100 usec wait time after reset before communication
@ -133,7 +138,7 @@ static void mba6_setup_iomuxc_enet(void)
* BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on
* reset before the phy sees a high level
*/
udelay(200);
mdelay(15);
}
static iomux_v3_cfg_t const mba6_uart2_pads[] = {
@ -234,39 +239,20 @@ static void mba6_setup_i2c(void)
printf("setup I2C1 failed: %d\n", ret);
}
static iomux_v3_cfg_t const mba6_ecspi1_pads[] = {
NEW_PAD_CTRL(MX6_PAD_EIM_D24__GPIO3_IO24, SPI_PAD_CTRL),
NEW_PAD_CTRL(MX6_PAD_EIM_D25__GPIO3_IO25, SPI_PAD_CTRL),
};
static unsigned const mba6_ecspi1_cs[] = {
IMX_GPIO_NR(3, 24),
IMX_GPIO_NR(3, 25),
};
static void mba6_setup_iomuxc_spi(void)
{
unsigned i;
for (i = 0; i < ARRAY_SIZE(mba6_ecspi1_cs); ++i)
gpio_direction_output(mba6_ecspi1_cs[i], 1);
imx_iomux_v3_setup_multiple_pads(mba6_ecspi1_pads,
ARRAY_SIZE(mba6_ecspi1_pads));
}
int board_phy_config(struct phy_device *phydev)
{
/*
* optimized pad skew values depends on CPU variant on the TQMa6x module:
* i.MX6Q/D or i.MX6DL/S
* CONFIG_TQMA6Q: i.MX6Q/D
* CONFIG_TQMA6S: i.MX6S
* CONFIG_TQMA6DL: i.MX6DL
*/
#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q)
#if defined(CONFIG_TQMA6Q)
#define MBA6X_KSZ9031_CTRL_SKEW 0x0032
#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
#define MBA6X_KSZ9031_RX_SKEW 0x3333
#define MBA6X_KSZ9031_TX_SKEW 0x2036
#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
#define MBA6X_KSZ9031_CTRL_SKEW 0x0030
#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
#define MBA6X_KSZ9031_RX_SKEW 0x3333
@ -341,7 +327,6 @@ int tqma6_bb_board_early_init_f(void)
int tqma6_bb_board_init(void)
{
mba6_setup_i2c();
mba6_setup_iomuxc_spi();
/* do it here - to have reset completed */
mba6_setup_iomuxc_enet();

125
board/tqc/tqma6/tqma6dl.cfg Normal file
View File

@ -0,0 +1,125 @@
/*
* Copyright (C) 2014 - 2015 Markus Niebel <Markus.Niebel@tq-group.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
#define __ASSEMBLY__
#include <config.h>
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
#if defined(CONFIG_TQMA6X_MMC_BOOT)
BOOT_FROM sd
#elif defined(CONFIG_TQMA6X_SPI_BOOT)
BOOT_FROM spi
#endif
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
/* TQMa6DL DDR config Rev. 0100E */
/* IOMUX configuration */
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
/* memory interface calibration values */
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00440048
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x003D003F
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0029002D
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x002B0043
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x424C0250
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02300234
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4234023C
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0224022C
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x48484C4C
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4C4E4E4C
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36382C36
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x34343630
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
/* configure memory interface */
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333
DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
DATA 4, MX6_MMDC_P0_MDSCR, 0x00408032
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D
DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
#include "clocks.cfg"

3
configs/apalis_imx6_defconfig
View File

@ -46,6 +46,7 @@ CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Toradex"
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0x4020
CONFIG_G_DNL_PRODUCT_NUM=0x4000
CONFIG_OF_LIBFDT=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set

7
configs/apalis_t30_defconfig
View File

@ -41,6 +41,7 @@ CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="NVIDIA"
CONFIG_G_DNL_VENDOR_NUM=0x0955
CONFIG_G_DNL_PRODUCT_NUM=0x701a
CONFIG_G_DNL_MANUFACTURER="Toradex"
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0x4000
CONFIG_OF_LIBFDT_OVERLAY=y

1
configs/bk4r1_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_VF610=y
CONFIG_TARGET_BK4R1=y
CONFIG_DEFAULT_DEVICE_TREE="bk4r1"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND"

3
configs/colibri_imx6_defconfig
View File

@ -46,6 +46,7 @@ CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Toradex"
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0x4020
CONFIG_G_DNL_PRODUCT_NUM=0x4000
CONFIG_OF_LIBFDT=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set

2
configs/colibri_imx6_nospl_defconfig
View File

@ -39,6 +39,6 @@ CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Toradex"
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0x4020
CONFIG_G_DNL_PRODUCT_NUM=0x4000
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set

4
configs/colibri_imx7_defconfig
View File

@ -54,4 +54,6 @@ CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Toradex"
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0x4020
CONFIG_G_DNL_PRODUCT_NUM=0x4000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_FDT_FIXUP_PARTITIONS=y

7
configs/colibri_t20_defconfig
View File

@ -46,9 +46,10 @@ CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="NVIDIA"
CONFIG_G_DNL_VENDOR_NUM=0x0955
CONFIG_G_DNL_PRODUCT_NUM=0x701a
CONFIG_G_DNL_MANUFACTURER="Toradex"
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0x4000
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_OF_LIBFDT_OVERLAY=y

7
configs/colibri_t30_defconfig
View File

@ -36,6 +36,7 @@ CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="NVIDIA"
CONFIG_G_DNL_VENDOR_NUM=0x0955
CONFIG_G_DNL_PRODUCT_NUM=0x701a
CONFIG_G_DNL_MANUFACTURER="Toradex"
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0x4000
CONFIG_OF_LIBFDT_OVERLAY=y

4
configs/colibri_vf_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_VF610=y
CONFIG_TARGET_COLIBRI_VF=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
@ -49,4 +50,5 @@ CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Toradex"
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0x0016
CONFIG_G_DNL_PRODUCT_NUM=0x4000
CONFIG_OF_LIBFDT_OVERLAY=y

63
configs/gwventana_emmc_defconfig Normal file
View File

@ -0,0 +1,63 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_GW_VENTANA=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Gateworks"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y

6
configs/gwventana_defconfig → configs/gwventana_nand_defconfig
View File

@ -4,11 +4,12 @@ CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_GW_VENTANA=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_FIT=y
@ -22,7 +23,6 @@ CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "

1
configs/imx6dl_icore_rqs_mmc_defconfig
View File

@ -38,3 +38,4 @@ CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_BOARD_LATE_INIT=y

1
configs/imx6q_icore_rqs_mmc_defconfig
View File

@ -38,3 +38,4 @@ CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_BOARD_LATE_INIT=y

40
configs/imx6ul_isiot_emmc_defconfig Normal file
View File

@ -0,0 +1,40 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6UL_ISIOT=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-emmc"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6ul-isiot-emmc.dtb"
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_BOARD_LATE_INIT=y

42
configs/imx6ul_isiot_mmc_defconfig Normal file
View File

@ -0,0 +1,42 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6UL_ISIOT=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-mmc"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6ul-isiot-emmc.dtb"
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_BOARD_LATE_INIT=y

43
configs/imx6ul_isiot_nand_defconfig Normal file
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CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6UL_ISIOT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-nand"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6ul-isiot-nand.dtb"
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_UBI=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_NAND_MXS=y
CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_SYS_I2C_MXC=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_BOARD_LATE_INIT=y

25
configs/mx7ulp_evk_defconfig Normal file
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CONFIG_ARM=y
CONFIG_ARCH_MX7ULP=y
CONFIG_TARGET_MX7ULP_EVK=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_IMX_RGPIO2P=y
CONFIG_DM_I2C=y
CONFIG_SYS_LPI2C_IMX=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7ULP=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_CMD_MMC=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
# CONFIG_BLK is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_CMD_GPIO=y

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