arm: mvebu: Add SolidRun ClearFog Armada 38x initial support
This patch adds basic support for the SolidRun ClearFog Armada 38x based board to mainline U-Boot. Supported interfaces / devices are: - DDR3 - UART - MMC - Ethernet port 0 (connected to dedicated PHY) - I2C The included DT source was taken from Russell King's ftp server: http://www.home.arm.linux.org.uk/~rmk/clearfog/ With only minor modifications, like the addition of some aliases and the "u-boot,dm-pre-reloc" property. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
This commit is contained in:
Stefan Roese
parent
8a02ec1dc6
commit
0299c90f39
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@ -828,6 +828,7 @@ source "board/siemens/draco/Kconfig"
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source "board/siemens/pxm2/Kconfig"
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source "board/siemens/rut/Kconfig"
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source "board/silica/pengwyn/Kconfig"
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source "board/solidrun/clearfog/Kconfig"
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source "board/spear/spear300/Kconfig"
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source "board/spear/spear310/Kconfig"
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source "board/spear/spear320/Kconfig"
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@ -48,6 +48,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
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tegra210-p2571.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += \
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armada-388-clearfog.dtb \
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armada-388-gp.dtb \
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armada-xp-gp.dtb \
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armada-xp-maxbcm.dtb
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@ -0,0 +1,509 @@
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/*
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* Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
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*
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* Copyright (C) 2015 Russell King
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*
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* This board is in development; the contents of this file work with
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* the A1 rev 2.0 of the board, which does not represent final
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* production board. Things will change, don't expect this file to
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* remain compatible info the future.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-388.dtsi"
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/ {
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model = "SolidRun Clearfog A1";
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compatible = "solidrun,clearfog-a1", "marvell,armada388",
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"marvell,armada385", "marvell,armada380";
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aliases {
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/* So that mvebu u-boot can update the MAC addresses */
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ethernet1 = ð0;
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ethernet2 = ð1;
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ethernet3 = ð2;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>; /* 256 MB */
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
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internal-regs {
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ethernet@30000 {
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mac-address = [00 50 43 02 02 02];
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phy-mode = "sgmii";
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status = "okay";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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ethernet@34000 {
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mac-address = [00 50 43 02 02 03];
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managed = "in-band-status";
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phy-mode = "sgmii";
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status = "okay";
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};
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ethernet@70000 {
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mac-address = [00 50 43 02 02 01];
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pinctrl-0 = <&ge0_rgmii_pins>;
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pinctrl-names = "default";
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phy = <&phy_dedicated>;
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phy-mode = "rgmii-id";
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status = "okay";
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};
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i2c@11000 {
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/* Is there anything on this? */
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clock-frequency = <100000>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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/*
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* PCA9655 GPIO expander, up to 1MHz clock.
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* 0-CON3 CLKREQ#
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* 1-CON3 PERST#
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* 2-CON2 PERST#
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* 3-CON3 W_DISABLE
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* 4-CON2 CLKREQ#
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* 5-USB3 overcurrent
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* 6-USB3 power
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* 7-CON2 W_DISABLE
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* 8-JP4 P1
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* 9-JP4 P4
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* 10-JP4 P5
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* 11-m.2 DEVSLP
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* 12-SFP_LOS
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* 13-SFP_TX_FAULT
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* 14-SFP_TX_DISABLE
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* 15-SFP_MOD_DEF0
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*/
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expander0: gpio-expander@20 {
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/*
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* This is how it should be:
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* compatible = "onnn,pca9655",
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* "nxp,pca9555";
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* but you can't do this because of
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* the way I2C works.
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*/
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compatible = "nxp,pca9555";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x20>;
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pcie1_0_clkreq {
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gpio-hog;
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gpios = <0 GPIO_ACTIVE_LOW>;
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input;
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line-name = "pcie1.0-clkreq";
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};
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pcie1_0_w_disable {
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gpio-hog;
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gpios = <3 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "pcie1.0-w-disable";
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};
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pcie2_0_clkreq {
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gpio-hog;
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gpios = <4 GPIO_ACTIVE_LOW>;
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input;
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line-name = "pcie2.0-clkreq";
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};
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pcie2_0_w_disable {
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gpio-hog;
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gpios = <7 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "pcie2.0-w-disable";
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};
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usb3_ilimit {
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gpio-hog;
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gpios = <5 GPIO_ACTIVE_LOW>;
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input;
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line-name = "usb3-current-limit";
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};
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usb3_power {
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gpio-hog;
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gpios = <6 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "usb3-power";
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};
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m2_devslp {
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gpio-hog;
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gpios = <11 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "m.2 devslp";
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};
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};
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/* The MCP3021 is 100kHz clock only */
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mikrobus_adc: mcp3021@4c {
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compatible = "microchip,mcp3021";
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reg = <0x4c>;
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};
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/* Also something at 0x64 */
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};
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i2c@11100 {
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/*
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* Routed to SFP, mikrobus, and PCIe.
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* SFP limits this to 100kHz, and requires
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* an AT24C01A/02/04 with address pins tied
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* low, which takes addresses 0x50 and 0x51.
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* Mikrobus doesn't specify beyond an I2C
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* bus being present.
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* PCIe uses ARP to assign addresses, or
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* 0x63-0x64.
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*/
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clock-frequency = <100000>;
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pinctrl-0 = <&clearfog_i2c1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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mdio@72004 {
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pinctrl-0 = <&mdio_pins>;
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pinctrl-names = "default";
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phy_dedicated: ethernet-phy@0 {
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/*
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* Annoyingly, the marvell phy driver
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* configures the LED register, rather
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* than preserving reset-loaded setting.
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* We undo that rubbish here.
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*/
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marvell,reg-init = <3 16 0 0x101e>;
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reg = <0>;
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};
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};
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pinctrl@18000 {
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clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
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marvell,pins = "mpp46";
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marvell,function = "ref";
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};
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clearfog_dsa0_pins: clearfog-dsa0-pins {
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marvell,pins = "mpp23", "mpp41";
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marvell,function = "gpio";
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};
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clearfog_i2c1_pins: i2c1-pins {
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/* SFP, PCIe, mSATA, mikrobus */
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marvell,pins = "mpp26", "mpp27";
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marvell,function = "i2c1";
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};
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clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
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marvell,pins = "mpp20";
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marvell,function = "gpio";
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};
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clearfog_sdhci_pins: clearfog-sdhci-pins {
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marvell,pins = "mpp21", "mpp28",
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"mpp37", "mpp38",
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"mpp39", "mpp40";
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marvell,function = "sd0";
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};
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clearfog_spi1_cs_pins: spi1-cs-pins {
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marvell,pins = "mpp55";
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marvell,function = "spi1";
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};
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mikro_pins: mikro-pins {
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/* int: mpp22 rst: mpp29 */
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marvell,pins = "mpp22", "mpp29";
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marvell,function = "gpio";
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};
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mikro_spi_pins: mikro-spi-pins {
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marvell,pins = "mpp43";
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marvell,function = "spi1";
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};
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mikro_uart_pins: mikro-uart-pins {
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marvell,pins = "mpp24", "mpp25";
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marvell,function = "ua1";
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};
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rear_button_pins: rear-button-pins {
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marvell,pins = "mpp34";
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marvell,function = "gpio";
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};
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};
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rtc@a3800 {
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/*
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* If the rtc doesn't work, run "date reset"
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* twice in u-boot.
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*/
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status = "okay";
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};
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sata@a8000 {
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/* pinctrl? */
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status = "okay";
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};
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sata@e0000 {
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/* pinctrl? */
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status = "okay";
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};
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sdhci@d8000 {
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bus-width = <4>;
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cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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pinctrl-0 = <&clearfog_sdhci_pins
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&clearfog_sdhci_cd_pins>;
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pinctrl-names = "default";
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status = "okay";
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vmmc = <®_3p3v>;
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wp-inverted;
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};
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serial@12000 {
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pinctrl-0 = <&uart0_pins>;
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pinctrl-names = "default";
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status = "okay";
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u-boot,dm-pre-reloc;
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};
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serial@12100 {
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/* mikrobus uart */
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pinctrl-0 = <&mikro_uart_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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spi@10680 {
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/*
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* We don't seem to have the W25Q32 on the
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* A1 Rev 2.0 boards, so disable SPI.
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* CS0: W25Q32 (doesn't appear to be present)
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* CS1:
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* CS2: mikrobus
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*/
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pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
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pinctrl-names = "default";
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "w25q32", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <3000000>;
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status = "disabled";
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};
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};
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usb3@f8000 {
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status = "okay";
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};
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};
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pcie-controller {
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status = "okay";
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/*
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* The two PCIe units are accessible through
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* the mini-PCIe connectors on the board.
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*/
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pcie@2,0 {
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/* Port 1, Lane 0. CONN3, nearest power. */
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reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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pcie@3,0 {
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/* Port 2, Lane 0. CONN2, nearest CPU. */
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reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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};
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};
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sfp: sfp {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
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moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
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sfp,ethernet = <ð2>;
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tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
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};
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dsa@0 {
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compatible = "marvell,dsa";
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dsa,ethernet = <ð1>;
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dsa,mii-bus = <&mdio>;
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pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
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pinctrl-names = "default";
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#address-cells = <2>;
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#size-cells = <0>;
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switch@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4 0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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};
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port@4 {
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reg = <4>;
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label = "lan5";
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};
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port@5 {
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reg = <5>;
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label = "cpu";
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};
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port@6 {
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/* 88E1512 external phy */
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reg = <6>;
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label = "lan6";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&rear_button_pins>;
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pinctrl-names = "default";
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button_0 {
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/* The rear SW3 button */
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label = "Rear Button";
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gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
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linux,can-disable;
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linux,code = <BTN_0>;
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};
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};
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};
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/*
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+#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
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MPP18: gpio ? (pca9655 int?)
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MPP19: gpio ? (clkreq?)
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MPP20: gpio ? (sd0 detect)
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MPP21: sd0:cmd x sd0
|
||||
MPP22: gpio x mikro int
|
||||
MPP23: gpio x switch irq
|
||||
+#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333
|
||||
MPP24: ua1:rxd x mikro rx
|
||||
MPP25: ua1:txd x mikro tx
|
||||
MPP26: i2c1:sck x mikro sck
|
||||
MPP27: i2c1:sda x mikro sda
|
||||
MPP28: sd0:clk x sd0
|
||||
MPP29: gpio x mikro rst
|
||||
MPP30: ge1:txd2 ? (config)
|
||||
MPP31: ge1:txd3 ? (config)
|
||||
+#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002
|
||||
MPP32: ge1:txctl ? (unused)
|
||||
MPP33: gpio ? (pic_com0)
|
||||
MPP34: gpio x rear button (pic_com1)
|
||||
MPP35: gpio ? (pic_com2)
|
||||
MPP36: gpio ? (unused)
|
||||
MPP37: sd0:d3 x sd0
|
||||
MPP38: sd0:d0 x sd0
|
||||
MPP39: sd0:d1 x sd0
|
||||
+#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004
|
||||
MPP40: sd0:d2 x sd0
|
||||
MPP41: gpio x switch reset
|
||||
MPP42: gpio ? sw1-1
|
||||
MPP43: spi1:cs2 x mikro cs
|
||||
MPP44: sata3:prsnt ? (unused)
|
||||
MPP45: ref:clk_out0 ?
|
||||
MPP46: ref:clk_out1 x switch clk
|
||||
MPP47: 4 ? (unused)
|
||||
+#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333
|
||||
MPP48: tdm:pclk
|
||||
MPP49: tdm:fsync
|
||||
MPP50: tdm:drx
|
||||
MPP51: tdm:dtx
|
||||
MPP52: tdm:int
|
||||
MPP53: tdm:rst
|
||||
MPP54: gpio ? (pwm)
|
||||
MPP55: spi1:cs1 x slic
|
||||
+#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444
|
||||
MPP56: spi1:mosi x mikro mosi
|
||||
MPP57: spi1:sck x mikro sck
|
||||
MPP58: spi1:miso x mikro miso
|
||||
MPP59: spi1:cs0 x w25q32
|
||||
*/
|
||||
|
|
@ -4,6 +4,9 @@ choice
|
|||
prompt "Marvell MVEBU (Armada XP/38x) board select"
|
||||
optional
|
||||
|
||||
config TARGET_CLEARFOG
|
||||
bool "Support ClearFog"
|
||||
|
||||
config TARGET_DB_88F6820_GP
|
||||
bool "Support DB-88F6820-GP"
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,12 @@
|
|||
if TARGET_CLEARFOG
|
||||
|
||||
config SYS_BOARD
|
||||
default "clearfog"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "solidrun"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "clearfog"
|
||||
|
||||
endif
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
CLEARFOG BOARD
|
||||
M: Stefan Roese <sr@denx.de>
|
||||
S: Maintained
|
||||
F: board/soldrun/clearfog/
|
||||
F: include/configs/clearfog.h
|
||||
F: configs/clearfog_defconfig
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#
|
||||
# Copyright (C) 2015 Stefan Roese <sr@denx.de>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := clearfog.o
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
Update from original Marvell U-Boot to mainline U-Boot:
|
||||
-------------------------------------------------------
|
||||
|
||||
Generate the U-Boot image with these commands:
|
||||
|
||||
$ make clearfog_defconfig
|
||||
$ make
|
||||
|
||||
The resulting image including the SPL binary with the
|
||||
full DDR setup is "u-boot-spl.kwb".
|
||||
|
||||
Now all you need to do is copy this image on a SD card.
|
||||
For example with this command:
|
||||
|
||||
$ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1
|
||||
|
||||
Please use the correct device node for your setup instead
|
||||
of "/dev/sdX" here!
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
|
||||
#include <../serdes/a38x/high_speed_env_spec.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define ETH_PHY_CTRL_REG 0
|
||||
#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
|
||||
#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
|
||||
|
||||
/*
|
||||
* Those values and defines are taken from the Marvell U-Boot version
|
||||
* "u-boot-2013.01-15t1-clearfog"
|
||||
*/
|
||||
#define BOARD_GPP_OUT_ENA_LOW 0xffffffff
|
||||
#define BOARD_GPP_OUT_ENA_MID 0xffffffff
|
||||
|
||||
#define BOARD_GPP_OUT_VAL_LOW 0x0
|
||||
#define BOARD_GPP_OUT_VAL_MID 0x0
|
||||
#define BOARD_GPP_POL_LOW 0x0
|
||||
#define BOARD_GPP_POL_MID 0x0
|
||||
|
||||
/* IO expander on Marvell GP board includes e.g. fan enabling */
|
||||
struct marvell_io_exp {
|
||||
u8 chip;
|
||||
u8 addr;
|
||||
u8 val;
|
||||
};
|
||||
|
||||
static struct marvell_io_exp io_exp[] = {
|
||||
{ 0x20, 2, 0x40 }, /* Deassert both mini pcie reset signals */
|
||||
{ 0x20, 6, 0xf9 },
|
||||
{ 0x20, 2, 0x46 }, /* rst signals and ena USB3 current limiter */
|
||||
{ 0x20, 6, 0xb9 },
|
||||
{ 0x20, 3, 0x00 }, /* Set SFP_TX_DIS to zero */
|
||||
{ 0x20, 7, 0xbf }, /* Drive SFP_TX_DIS to zero */
|
||||
};
|
||||
|
||||
static struct serdes_map board_serdes_map[] = {
|
||||
{SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
|
||||
{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
|
||||
{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
};
|
||||
|
||||
int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
|
||||
{
|
||||
*serdes_map_array = board_serdes_map;
|
||||
*count = ARRAY_SIZE(board_serdes_map);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Define the DDR layout / topology here in the board file. This will
|
||||
* be used by the DDR3 init code in the SPL U-Boot version to configure
|
||||
* the DDR3 controller.
|
||||
*/
|
||||
static struct hws_topology_map board_topology_map = {
|
||||
0x1, /* active interfaces */
|
||||
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
|
||||
{ { { {0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0} },
|
||||
SPEED_BIN_DDR_1600K, /* speed_bin */
|
||||
BUS_WIDTH_16, /* memory_width */
|
||||
MEM_4G, /* mem_size */
|
||||
DDR_FREQ_800, /* frequency */
|
||||
0, 0, /* cas_l cas_wl */
|
||||
HWS_TEMP_LOW} }, /* temperature */
|
||||
5, /* Num Of Bus Per Interface*/
|
||||
BUS_MASK_32BIT /* Busses mask */
|
||||
};
|
||||
|
||||
struct hws_topology_map *ddr3_get_topology_map(void)
|
||||
{
|
||||
/* Return the board topology as defined in the board code */
|
||||
return &board_topology_map;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* Configure MPP */
|
||||
writel(0x11111111, MVEBU_MPP_BASE + 0x00);
|
||||
writel(0x11111111, MVEBU_MPP_BASE + 0x04);
|
||||
writel(0x10400011, MVEBU_MPP_BASE + 0x08);
|
||||
writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
|
||||
writel(0x44400002, MVEBU_MPP_BASE + 0x10);
|
||||
writel(0x41144004, MVEBU_MPP_BASE + 0x14);
|
||||
writel(0x40333333, MVEBU_MPP_BASE + 0x18);
|
||||
writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
|
||||
|
||||
/* Set GPP Out value */
|
||||
writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
|
||||
writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
|
||||
|
||||
/* Set GPP Polarity */
|
||||
writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
|
||||
writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
|
||||
|
||||
/* Set GPP Out Enable */
|
||||
writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
|
||||
writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Address of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
/* Toggle GPIO41 to reset onboard switch and phy */
|
||||
clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
|
||||
clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
|
||||
mdelay(1);
|
||||
setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
|
||||
mdelay(10);
|
||||
|
||||
/* Init I2C IO expanders */
|
||||
for (i = 0; i < ARRAY_SIZE(io_exp); i++)
|
||||
i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: SolidRun ClearFog\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
cpu_eth_init(bis); /* Built in controller(s) come first */
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
#
|
||||
# Copyright (C) 2015 Stefan Roese <sr@denx.de>
|
||||
#
|
||||
|
||||
# Armada XP uses version 1 image format
|
||||
VERSION 1
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM sdio
|
||||
|
||||
# Binary Header (bin_hdr) with DDR3 training code
|
||||
BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MVEBU=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_TARGET_CLEARFOG=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
|
||||
CONFIG_SPL=y
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DEBUG_UART_BASE=0xd0012000
|
||||
CONFIG_DEBUG_UART_CLOCK=250000000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _CONFIG_CLEARFOG_H
|
||||
#define _CONFIG_CLEARFOG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
#define CONFIG_ARMADA_XP /* SOC Family Name */
|
||||
#define CONFIG_ARMADA_38X
|
||||
#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */
|
||||
|
||||
#define CONFIG_DISPLAY_BOARDINFO_LATE
|
||||
|
||||
/*
|
||||
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
|
||||
* for DDR ECC byte filling in the SPL before loading the main
|
||||
* U-Boot into it.
|
||||
*/
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00800000
|
||||
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
|
||||
|
||||
/*
|
||||
* Commands configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ENV
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_EXT4
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_FS_GENERIC
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_CMD_TFTPPUT
|
||||
#define CONFIG_CMD_TIME
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MVTWSI
|
||||
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x0
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
/* SPI NOR flash default params, used by sf commands */
|
||||
#define CONFIG_SF_DEFAULT_SPEED 1000000
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
|
||||
/*
|
||||
* SDIO/MMC Card Configuration
|
||||
*/
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_MMC_SDMA
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_SDHCI
|
||||
#define CONFIG_MV_SDHCI
|
||||
#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
|
||||
|
||||
/* Partition support */
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_EFI_PARTITION
|
||||
|
||||
/* Additional FS support/configuration */
|
||||
#define CONFIG_SUPPORT_VFAT
|
||||
|
||||
/* USB/EHCI configuration */
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
|
||||
#define CONFIG_ENV_MIN_ENTRIES 128
|
||||
|
||||
/* Environment in MMC */
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#define CONFIG_ENV_SECT_SIZE 0x200
|
||||
#define CONFIG_ENV_SIZE 0x10000
|
||||
/*
|
||||
* For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC
|
||||
* boot image starts @ LBA-0.
|
||||
* As result in MMC/eMMC case it will be a 1 sector gap between u-boot
|
||||
* image and environment
|
||||
*/
|
||||
#define CONFIG_ENV_OFFSET 0xf0000
|
||||
#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
|
||||
|
||||
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
|
||||
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
|
||||
|
||||
/* PCIe support */
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_PCI_MVEBU
|
||||
#define CONFIG_PCI_PNP
|
||||
#define CONFIG_PCI_SCAN_SHOW
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
|
||||
/* Keep device tree and initrd in lower memory so the kernel can access them */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"fdt_high=0x10000000\0" \
|
||||
"initrd_high=0x10000000\0"
|
||||
|
||||
/* SPL */
|
||||
/*
|
||||
* Select the boot device here
|
||||
*
|
||||
* Currently supported are:
|
||||
* SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
|
||||
* SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
|
||||
*/
|
||||
#define SPL_BOOT_SPI_NOR_FLASH 1
|
||||
#define SPL_BOOT_SDIO_MMC_CARD 2
|
||||
#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_SIZE (140 << 10)
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40000030
|
||||
#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
|
||||
|
||||
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SYS_MALLOC_SIMPLE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
|
||||
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
|
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_I2C_SUPPORT
|
||||
|
||||
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
|
||||
/* SPL related SPI defines */
|
||||
#define CONFIG_SPL_SPI_SUPPORT
|
||||
#define CONFIG_SPL_SPI_FLASH_SUPPORT
|
||||
#define CONFIG_SPL_SPI_LOAD
|
||||
#define CONFIG_SPL_SPI_BUS 0
|
||||
#define CONFIG_SPL_SPI_CS 0
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
|
||||
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
|
||||
#endif
|
||||
|
||||
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
|
||||
/* SPL related MMC defines */
|
||||
#define CONFIG_SPL_MMC_SUPPORT
|
||||
#define CONFIG_SPL_LIBDISK_SUPPORT
|
||||
#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
|
||||
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR ((CONFIG_SYS_U_BOOT_OFFS / 512)\
|
||||
+ 1)
|
||||
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
|
||||
#define CONFIG_SYS_MVEBU_DDR_A38X
|
||||
#define CONFIG_DDR3
|
||||
|
||||
/*
|
||||
* mv-common.h should be defined after CMD configs since it used them
|
||||
* to enable certain macros
|
||||
*/
|
||||
#include "mv-common.h"
|
||||
|
||||
#endif /* _CONFIG_CLEARFOG_H */
|
||||
Loading…
Reference in New Issue