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ColdFire: Modules header files cleanup 

Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG,
MDHA, SKHA, INTC, and FlexBus structures and
definitions in immap_5xxx.h to more unify modules
header files. Append DSPI support for m547x_8x.
SSI cleanup. Remove USB Host structure from immap_539.h.
Apply changes to use FlexBus structures in mcf52x2's
cpu_init.c and platform configuration files.

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
This commit is contained in:
TsiChung Liew 2008-10-21 10:03:07 +00:00 committed by John Rigby
parent ac2331aee9
commit 012522fef3
41 changed files with 1496 additions and 2782 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

271
cpu/mcf52x2/cpu_init.c
View File

@ -36,6 +36,65 @@
#include <watchdog.h>
#include <asm/immap.h>
#ifndef CONFIG_M5272
/* Only 5272 Flexbus chipselect is different from the rest */
void init_fbcs(void)
{
volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
&& defined(CONFIG_SYS_CS0_CTRL))
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#else
#warning "Chip Select 0 are not initialized/used"
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
&& defined(CONFIG_SYS_CS1_CTRL))
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
&& defined(CONFIG_SYS_CS2_CTRL))
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
&& defined(CONFIG_SYS_CS3_CTRL))
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
&& defined(CONFIG_SYS_CS5_CTRL))
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
#endif
#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
&& defined(CONFIG_SYS_CS6_CTRL))
fbcs->csar6 = CONFIG_SYS_CS6_BASE;
fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
#endif
#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
&& defined(CONFIG_SYS_CS7_CTRL))
fbcs->csar7 = CONFIG_SYS_CS7_BASE;
fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
#endif
}
#endif
#if defined(CONFIG_M5253)
/*
* Breath some life into the CPU...
@ -66,22 +125,14 @@ void cpu_init_f(void)
mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); *//* Enable a 1 cycle pre-drive cycle on CS1 */
/*
* Setup chip selects...
*/
mbar_writeShort(MCFSIM_CSAR1, CONFIG_SYS_CSAR1);
mbar_writeShort(MCFSIM_CSCR1, CONFIG_SYS_CSCR1);
mbar_writeLong(MCFSIM_CSMR1, CONFIG_SYS_CSMR1);
mbar_writeShort(MCFSIM_CSAR0, CONFIG_SYS_CSAR0);
mbar_writeShort(MCFSIM_CSCR0, CONFIG_SYS_CSCR0);
mbar_writeLong(MCFSIM_CSMR0, CONFIG_SYS_CSMR0);
/* FlexBus Chipselect */
init_fbcs();
#ifdef CONFIG_FSL_I2C
CONFIG_SYS_I2C_PINMUX_REG = CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG =
CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
#ifdef CONFIG_SYS_I2C2_OFFSET
CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
@ -121,6 +172,9 @@ void cpu_init_f(void)
mbar_writeShort(MCF_WTM_WCR, 0);
#endif
/* FlexBus Chipselect */
init_fbcs();
/* Set clockspeed to 100MHz */
mbar_writeShort(MCF_FMPLL_SYNCR,
MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
@ -268,66 +322,20 @@ void uart_port_conf(void)
*/
void cpu_init_f(void)
{
/* if we come from RAM we assume the CPU is
/*
* if we come from RAM we assume the CPU is
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);
volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
/* Kill watchdog so we can initialize the PLL */
wdog_reg->wcr = 0;
/* Memory Controller: */
/* Flash */
csctrl_reg->ar0 = CONFIG_SYS_AR0_PRELIM;
csctrl_reg->cr0 = CONFIG_SYS_CR0_PRELIM;
csctrl_reg->mr0 = CONFIG_SYS_MR0_PRELIM;
#if (defined(CONFIG_SYS_AR1_PRELIM) && defined(CONFIG_SYS_CR1_PRELIM) && defined(CONFIG_SYS_MR1_PRELIM))
csctrl_reg->ar1 = CONFIG_SYS_AR1_PRELIM;
csctrl_reg->cr1 = CONFIG_SYS_CR1_PRELIM;
csctrl_reg->mr1 = CONFIG_SYS_MR1_PRELIM;
#endif
#if (defined(CONFIG_SYS_AR2_PRELIM) && defined(CONFIG_SYS_CR2_PRELIM) && defined(CONFIG_SYS_MR2_PRELIM))
csctrl_reg->ar2 = CONFIG_SYS_AR2_PRELIM;
csctrl_reg->cr2 = CONFIG_SYS_CR2_PRELIM;
csctrl_reg->mr2 = CONFIG_SYS_MR2_PRELIM;
#endif
#if (defined(CONFIG_SYS_AR3_PRELIM) && defined(CONFIG_SYS_CR3_PRELIM) && defined(CONFIG_SYS_MR3_PRELIM))
csctrl_reg->ar3 = CONFIG_SYS_AR3_PRELIM;
csctrl_reg->cr3 = CONFIG_SYS_CR3_PRELIM;
csctrl_reg->mr3 = CONFIG_SYS_MR3_PRELIM;
#endif
#if (defined(CONFIG_SYS_AR4_PRELIM) && defined(CONFIG_SYS_CR4_PRELIM) && defined(CONFIG_SYS_MR4_PRELIM))
csctrl_reg->ar4 = CONFIG_SYS_AR4_PRELIM;
csctrl_reg->cr4 = CONFIG_SYS_CR4_PRELIM;
csctrl_reg->mr4 = CONFIG_SYS_MR4_PRELIM;
#endif
#if (defined(CONFIG_SYS_AR5_PRELIM) && defined(CONFIG_SYS_CR5_PRELIM) && defined(CONFIG_SYS_MR5_PRELIM))
csctrl_reg->ar5 = CONFIG_SYS_AR5_PRELIM;
csctrl_reg->cr5 = CONFIG_SYS_CR5_PRELIM;
csctrl_reg->mr5 = CONFIG_SYS_MR5_PRELIM;
#endif
#if (defined(CONFIG_SYS_AR6_PRELIM) && defined(CONFIG_SYS_CR6_PRELIM) && defined(CONFIG_SYS_MR6_PRELIM))
csctrl_reg->ar6 = CONFIG_SYS_AR6_PRELIM;
csctrl_reg->cr6 = CONFIG_SYS_CR6_PRELIM;
csctrl_reg->mr6 = CONFIG_SYS_MR6_PRELIM;
#endif
#if (defined(CONFIG_SYS_AR7_PRELIM) && defined(CONFIG_SYS_CR7_PRELIM) && defined(CONFIG_SYS_MR7_PRELIM))
csctrl_reg->ar7 = CONFIG_SYS_AR7_PRELIM;
csctrl_reg->cr7 = CONFIG_SYS_CR7_PRELIM;
csctrl_reg->mr7 = CONFIG_SYS_MR7_PRELIM;
#endif
/* FlexBus Chipselect */
init_fbcs();
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#ifdef CONFIG_FSL_I2C
@ -349,7 +357,7 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (CONFIG_SYS_UART_PORT) {
@ -384,7 +392,8 @@ void cpu_init_f(void)
#ifndef CONFIG_MONITOR_IS_IN_RAM
/* Set speed /PLL */
MCFCLOCK_SYNCR =
MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) | MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
MCFGPIO_PBCDPAR = 0xc0;
@ -425,119 +434,8 @@ void cpu_init_f(void)
MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
#endif
/* This is probably a bad place to setup chip selects, but everyone
else is doing it! */
#if defined(CONFIG_SYS_CS0_BASE) & defined(CONFIG_SYS_CS0_SIZE) & \
defined(CONFIG_SYS_CS0_WIDTH) & defined(CONFIG_SYS_CS0_WS)
MCFCSM_CSAR0 = (CONFIG_SYS_CS0_BASE >> 16) & 0xFFFF;
#if (CONFIG_SYS_CS0_WIDTH == 8)
#define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_8
#elif (CONFIG_SYS_CS0_WIDTH == 16)
#define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_16
#elif (CONFIG_SYS_CS0_WIDTH == 32)
#define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_32
#else
#error "CONFIG_SYS_CS0_WIDTH: Fault - wrong bus with for CS0"
#endif
MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CONFIG_SYS_CS0_WS)
| CONFIG_SYS_CS0_PS | MCFCSM_CSCR_AA;
#if (CONFIG_SYS_CS0_RO != 0)
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS0_SIZE - 1)
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS0_SIZE - 1) | MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 0 are not initialized/used"
#endif
#if defined(CONFIG_SYS_CS1_BASE) & defined(CONFIG_SYS_CS1_SIZE) & \
defined(CONFIG_SYS_CS1_WIDTH) & defined(CONFIG_SYS_CS1_WS)
MCFCSM_CSAR1 = (CONFIG_SYS_CS1_BASE >> 16) & 0xFFFF;
#if (CONFIG_SYS_CS1_WIDTH == 8)
#define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_8
#elif (CONFIG_SYS_CS1_WIDTH == 16)
#define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_16
#elif (CONFIG_SYS_CS1_WIDTH == 32)
#define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_32
#else
#error "CONFIG_SYS_CS1_WIDTH: Fault - wrong bus with for CS1"
#endif
MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CONFIG_SYS_CS1_WS)
| CONFIG_SYS_CS1_PS | MCFCSM_CSCR_AA;
#if (CONFIG_SYS_CS1_RO != 0)
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS1_SIZE - 1)
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS1_SIZE - 1)
| MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 1 are not initialized/used"
#endif
#if defined(CONFIG_SYS_CS2_BASE) & defined(CONFIG_SYS_CS2_SIZE) & \
defined(CONFIG_SYS_CS2_WIDTH) & defined(CONFIG_SYS_CS2_WS)
MCFCSM_CSAR2 = (CONFIG_SYS_CS2_BASE >> 16) & 0xFFFF;
#if (CONFIG_SYS_CS2_WIDTH == 8)
#define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_8
#elif (CONFIG_SYS_CS2_WIDTH == 16)
#define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_16
#elif (CONFIG_SYS_CS2_WIDTH == 32)
#define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_32
#else
#error "CONFIG_SYS_CS2_WIDTH: Fault - wrong bus with for CS2"
#endif
MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CONFIG_SYS_CS2_WS)
| CONFIG_SYS_CS2_PS | MCFCSM_CSCR_AA;
#if (CONFIG_SYS_CS2_RO != 0)
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS2_SIZE - 1)
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS2_SIZE - 1)
| MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 2 are not initialized/used"
#endif
#if defined(CONFIG_SYS_CS3_BASE) & defined(CONFIG_SYS_CS3_SIZE) & \
defined(CONFIG_SYS_CS3_WIDTH) & defined(CONFIG_SYS_CS3_WS)
MCFCSM_CSAR3 = (CONFIG_SYS_CS3_BASE >> 16) & 0xFFFF;
#if (CONFIG_SYS_CS3_WIDTH == 8)
#define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_8
#elif (CONFIG_SYS_CS3_WIDTH == 16)
#define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_16
#elif (CONFIG_SYS_CS3_WIDTH == 32)
#define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_32
#else
#error "CONFIG_SYS_CS3_WIDTH: Fault - wrong bus with for CS1"
#endif
MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CONFIG_SYS_CS3_WS)
| CONFIG_SYS_CS3_PS | MCFCSM_CSCR_AA;
#if (CONFIG_SYS_CS3_RO != 0)
MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS3_SIZE - 1)
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS3_SIZE - 1)
| MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 3 are not initialized/used"
#endif
/* FlexBus Chipselect */
init_fbcs();
#endif /* CONFIG_MONITOR_IS_IN_RAM */
@ -632,17 +530,8 @@ void cpu_init_f(void)
mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
/*
* Setup chip selects...
*/
mbar_writeShort(MCFSIM_CSAR1, CONFIG_SYS_CSAR1);
mbar_writeShort(MCFSIM_CSCR1, CONFIG_SYS_CSCR1);
mbar_writeLong(MCFSIM_CSMR1, CONFIG_SYS_CSMR1);
mbar_writeShort(MCFSIM_CSAR0, CONFIG_SYS_CSAR0);
mbar_writeShort(MCFSIM_CSCR0, CONFIG_SYS_CSCR0);
mbar_writeLong(MCFSIM_CSMR0, CONFIG_SYS_CSMR0);
/* FlexBus Chipselect */
init_fbcs();
/* enable instruction cache now */
icache_enable();

79
include/asm-m68k/coldfire/ata.h Normal file
View File

@ -0,0 +1,79 @@
/*
* ATA Internal Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ATA_H__
#define __ATA_H__
/* ATA */
typedef struct atac {
/* PIO */
u8 toff; /* 0x00 */
u8 ton; /* 0x01 */
u8 t1; /* 0x02 */
u8 t2w; /* 0x03 */
u8 t2r; /* 0x04 */
u8 ta; /* 0x05 */
u8 trd; /* 0x06 */
u8 t4; /* 0x07 */
u8 t9; /* 0x08 */
/* DMA */
u8 tm; /* 0x09 */
u8 tn; /* 0x0A */
u8 td; /* 0x0B */
u8 tk; /* 0x0C */
u8 tack; /* 0x0D */
u8 tenv; /* 0x0E */
u8 trp; /* 0x0F */
u8 tzah; /* 0x10 */
u8 tmli; /* 0x11 */
u8 tdvh; /* 0x12 */
u8 tdzfs; /* 0x13 */
u8 tdvs; /* 0x14 */
u8 tcvh; /* 0x15 */
u8 tss; /* 0x16 */
u8 tcyc; /* 0x17 */
/* FIFO */
u32 fifo32; /* 0x18 */
u16 fifo16; /* 0x1C */
u8 rsvd0[2];
u8 ffill; /* 0x20 */
u8 rsvd1[3];
/* ATA */
u8 cr; /* 0x24 */
u8 rsvd2[3];
u8 isr; /* 0x28 */
u8 rsvd3[3];
u8 ier; /* 0x2C */
u8 rsvd4[3];
u8 icr; /* 0x30 */
u8 rsvd5[3];
u8 falarm; /* 0x34 */
u8 rsvd6[106];
} atac_t;
#endif /* __ATA_H__ */

15
include/asm-m68k/coldfire/dspi.h
View File

@ -46,15 +46,14 @@ typedef struct dspi {
u32 dirsr;
u32 dtfr;
u32 drfr;
u32 dtfdr0;
u32 dtfdr1;
u32 dtfdr2;
u32 dtfdr3;
#ifdef CONFIG_MCF547x_8x
u32 dtfdr[4];
u8 resv1[0x30];
u32 drfdr0;
u32 drfdr1;
u32 drfdr2;
u32 drfdr3;
u32 drfdr[4];
#else
u32 dtfdr[16];
u32 drfdr[16];
#endif
} dspi_t;
/* Bit definitions and macros for DMCR */

139
include/asm-m68k/coldfire/eport.h Normal file
View File

@ -0,0 +1,139 @@
/*
* Edge Port Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __EPORT_H__
#define __EPORT_H__
/* Edge Port Module (EPORT) */
typedef struct eport {
#ifdef CONFIG_MCF547x_8x
u16 par; /* 0x00 */
u16 res0; /* 0x02 */
u8 ddr; /* 0x04 */
u8 ier; /* 0x05 */
u16 res1; /* 0x06 */
u8 dr; /* 0x08 */
u8 pdr; /* 0x09 */
u16 res2; /* 0x0A */
u8 fr; /* 0x0C */
u8 res3[3]; /* 0x0D */
#else
u16 par; /* 0x00 Pin Assignment */
u8 ddr; /* 0x02 Data Direction */
u8 ier; /* 0x03 Interrupt Enable */
u8 dr; /* 0x04 Data */
u8 pdr; /* 0x05 Pin Data */
u8 fr; /* 0x06 Flag */
u8 res0;
#endif
} eport_t;
/* EPPAR */
#define EPORT_PAR_EPPA1(x) (((x)&0x0003)<<2)
#define EPORT_PAR_EPPA2(x) (((x)&0x0003)<<4)
#define EPORT_PAR_EPPA3(x) (((x)&0x0003)<<6)
#define EPORT_PAR_EPPA4(x) (((x)&0x0003)<<8)
#define EPORT_PAR_EPPA5(x) (((x)&0x0003)<<10)
#define EPORT_PAR_EPPA6(x) (((x)&0x0003)<<12)
#define EPORT_PAR_EPPA7(x) (((x)&0x0003)<<14)
#define EPORT_PAR_LEVEL (0)
#define EPORT_PAR_RISING (1)
#define EPORT_PAR_FALLING (2)
#define EPORT_PAR_BOTH (3)
#define EPORT_PAR_EPPA7_LEVEL (0x0000)
#define EPORT_PAR_EPPA7_RISING (0x4000)
#define EPORT_PAR_EPPA7_FALLING (0x8000)
#define EPORT_PAR_EPPA7_BOTH (0xC000)
#define EPORT_PAR_EPPA6_LEVEL (0x0000)
#define EPORT_PAR_EPPA6_RISING (0x1000)
#define EPORT_PAR_EPPA6_FALLING (0x2000)
#define EPORT_PAR_EPPA6_BOTH (0x3000)
#define EPORT_PAR_EPPA5_LEVEL (0x0000)
#define EPORT_PAR_EPPA5_RISING (0x0400)
#define EPORT_PAR_EPPA5_FALLING (0x0800)
#define EPORT_PAR_EPPA5_BOTH (0x0C00)
#define EPORT_PAR_EPPA4_LEVEL (0x0000)
#define EPORT_PAR_EPPA4_RISING (0x0100)
#define EPORT_PAR_EPPA4_FALLING (0x0200)
#define EPORT_PAR_EPPA4_BOTH (0x0300)
#define EPORT_PAR_EPPA3_LEVEL (0x0000)
#define EPORT_PAR_EPPA3_RISING (0x0040)
#define EPORT_PAR_EPPA3_FALLING (0x0080)
#define EPORT_PAR_EPPA3_BOTH (0x00C0)
#define EPORT_PAR_EPPA2_LEVEL (0x0000)
#define EPORT_PAR_EPPA2_RISING (0x0010)
#define EPORT_PAR_EPPA2_FALLING (0x0020)
#define EPORT_PAR_EPPA2_BOTH (0x0030)
#define EPORT_PAR_EPPA1_LEVEL (0x0000)
#define EPORT_PAR_EPPA1_RISING (0x0004)
#define EPORT_PAR_EPPA1_FALLING (0x0008)
#define EPORT_PAR_EPPA1_BOTH (0x000C)
/* EPDDR */
#define EPORT_DDR_EPDD1 (0x02)
#define EPORT_DDR_EPDD2 (0x04)
#define EPORT_DDR_EPDD3 (0x08)
#define EPORT_DDR_EPDD4 (0x10)
#define EPORT_DDR_EPDD5 (0x20)
#define EPORT_DDR_EPDD6 (0x40)
#define EPORT_DDR_EPDD7 (0x80)
/* EPIER */
#define EPORT_IER_EPIE1 (0x02)
#define EPORT_IER_EPIE2 (0x04)
#define EPORT_IER_EPIE3 (0x08)
#define EPORT_IER_EPIE4 (0x10)
#define EPORT_IER_EPIE5 (0x20)
#define EPORT_IER_EPIE6 (0x40)
#define EPORT_IER_EPIE7 (0x80)
/* EPDR */
#define EPORT_DR_EPD1 (0x02)
#define EPORT_DR_EPD2 (0x04)
#define EPORT_DR_EPD3 (0x08)
#define EPORT_DR_EPD4 (0x10)
#define EPORT_DR_EPD5 (0x20)
#define EPORT_DR_EPD6 (0x40)
#define EPORT_DR_EPD7 (0x80)
/* EPPDR */
#define EPORT_PDR_EPPD1 (0x02)
#define EPORT_PDR_EPPD2 (0x04)
#define EPORT_PDR_EPPD3 (0x08)
#define EPORT_PDR_EPPD4 (0x10)
#define EPORT_PDR_EPPD5 (0x20)
#define EPORT_PDR_EPPD6 (0x40)
#define EPORT_PDR_EPPD7 (0x80)
/* EPFR */
#define EPORT_FR_EPF1 (0x02)
#define EPORT_FR_EPF2 (0x04)
#define EPORT_FR_EPF3 (0x08)
#define EPORT_FR_EPF4 (0x10)
#define EPORT_FR_EPF5 (0x20)
#define EPORT_FR_EPF6 (0x40)
#define EPORT_FR_EPF7 (0x80)
#endif /* __EPORT_H__ */

96
include/asm-m68k/coldfire/flexbus.h
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@ -31,33 +31,36 @@
*********************************************************************/
typedef struct fbcs {
u32 csar0; /* Chip-select Address Register */
u32 csmr0; /* Chip-select Mask Register */
u32 cscr0; /* Chip-select Control Register */
u32 csar1; /* Chip-select Address Register */
u32 csmr1; /* Chip-select Mask Register */
u32 cscr1; /* Chip-select Control Register */
u32 csar2; /* Chip-select Address Register */
u32 csmr2; /* Chip-select Mask Register */
u32 cscr2; /* Chip-select Control Register */
u32 csar3; /* Chip-select Address Register */
u32 csmr3; /* Chip-select Mask Register */
u32 cscr3; /* Chip-select Control Register */
u32 csar4; /* Chip-select Address Register */
u32 csmr4; /* Chip-select Mask Register */
u32 cscr4; /* Chip-select Control Register */
u32 csar5; /* Chip-select Address Register */
u32 csmr5; /* Chip-select Mask Register */
u32 cscr5; /* Chip-select Control Register */
u32 csar0; /* Chip-select Address */
u32 csmr0; /* Chip-select Mask */
u32 cscr0; /* Chip-select Control */
u32 csar1;
u32 csmr1;
u32 cscr1;
u32 csar2;
u32 csmr2;
u32 cscr2;
u32 csar3;
u32 csmr3;
u32 cscr3;
u32 csar4;
u32 csmr4;
u32 cscr4;
u32 csar5;
u32 csmr5;
u32 cscr5;
u32 csar6;
u32 csmr6;
u32 cscr6;
u32 csar7;
u32 csmr7;
u32 cscr7;
} fbcs_t;
/* Bit definitions and macros for CSAR group */
#define FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
#define FBCS_CSAR_BA(x) ((x) & 0xFFFF0000)
/* Bit definitions and macros for CSMR group */
#define FBCS_CSMR_V (0x00000001) /* Valid bit */
#define FBCS_CSMR_WP (0x00000100) /* Write protect */
#define FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
#define FBCS_CSMR_BAM(x) (((x) & 0xFFFF) << 16)
#define FBCS_CSMR_BAM_MASK (0x0000FFFF)
#define FBCS_CSMR_BAM_4G (0xFFFF0000)
#define FBCS_CSMR_BAM_2G (0x7FFF0000)
#define FBCS_CSMR_BAM_1G (0x3FFF0000)
@ -78,21 +81,40 @@ typedef struct fbcs {
#define FBCS_CSMR_BAM_128K (0x00010000)
#define FBCS_CSMR_BAM_64K (0x00000000)
/* Bit definitions and macros for CSCR group */
#define FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */
#define FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */
#define FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */
#define FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */
#define FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */
#define FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
#define FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
#define FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
#define FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
#define FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */
#define FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
#ifdef CONFIG_M5249
#define FBCS_CSMR_WP (0x00000080)
#define FBCS_CSMR_AM (0x00000040)
#define FBCS_CSMR_CI (0x00000020)
#define FBCS_CSMR_SC (0x00000010)
#define FBCS_CSMR_SD (0x00000008)
#define FBCS_CSMR_UC (0x00000004)
#define FBCS_CSMR_UD (0x00000002)
#else
#define FBCS_CSMR_WP (0x00000100)
#endif
#define FBCS_CSMR_V (0x00000001) /* Valid bit */
#define FBCS_CSCR_SWS(x) (((x) & 0x3F) << 26)
#define FBCS_CSCR_SWS_MASK (0x03FFFFFF)
#define FBCS_CSCR_SWSEN (0x00800000)
#define FBCS_CSCR_ASET(x) (((x) & 0x03) << 20)
#define FBCS_CSCR_ASET_MASK (0xFFCFFFFF)
#define FBCS_CSCR_RDAH(x) (((x) & 0x03) << 18)
#define FBCS_CSCR_RDAH_MASK (0xFFF3FFFF)
#define FBCS_CSCR_WRAH(x) (((x) & 0x03) << 16)
#define FBCS_CSCR_WRAH_MASK (0xFFFCFFFF)
#define FBCS_CSCR_WS(x) (((x) & 0x3F) << 10)
#define FBCS_CSCR_WS_MASK (0xFFFF03FF)
#define FBCS_CSCR_SBM (0x00000200)
#define FBCS_CSCR_AA (0x00000100)
#define FBCS_CSCR_PS(x) (((x) & 0x03) << 6)
#define FBCS_CSCR_PS_MASK (0xFFFFFF3F)
#define FBCS_CSCR_BEM (0x00000020)
#define FBCS_CSCR_BSTR (0x00000010)
#define FBCS_CSCR_BSTW (0x00000008)
#define FBCS_CSCR_PS_8 (0x00000040)
#define FBCS_CSCR_PS_16 (0x00000080)
#define FBCS_CSCR_PS_8 (0x00000040)
#define FBCS_CSCR_PS_32 (0x00000000)
#endif /* __FLEXBUS_H */

219
include/asm-m68k/coldfire/flexcan.h Normal file
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@ -0,0 +1,219 @@
/*
* Flex CAN Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __FLEXCAN_H__
#define __FLEXCAN_H__
/* FlexCan Message Buffer */
typedef struct can_msgbuf_ctrl {
#ifdef CONFIG_M5282
u8 tmstamp; /* 0x00 Timestamp */
u8 ctrl; /* 0x01 Control */
u16 idh; /* 0x02 ID High */
u16 idl; /* 0x04 ID High */
u8 data[8]; /* 0x06 8 Byte Data Field */
u16 res; /* 0x0E */
#else
u16 ctrl; /* 0x00 Control/Status */
u16 tmstamp; /* 0x02 Timestamp */
u32 id; /* 0x04 Identifier */
u8 data[8]; /* 0x08 8 Byte Data Field */
#endif
} can_msg_t;
#ifdef CONFIG_M5282
/* MSGBUF CTRL */
#define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x0F) << 4)
#define CAN_MSGBUF_CTRL_CODE_MASK (0x0F)
#define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x0F)
#define CAN_MSGBUF_CTRL_LEN_MASK (0xF0)
/* MSGBUF ID */
#define CAN_MSGBUF_IDH_STD(x) (((x) & 0x07FF) << 5)
#define CAN_MSGBUF_IDH_STD_MASK (0xE003FFFF)
#define CAN_MSGBUF_IDH_SRR (0x0010)
#define CAN_MSGBUF_IDH_IDE (0x0080)
#define CAN_MSGBUF_IDH_EXTH(x) ((x) & 0x07)
#define CAN_MSGBUF_IDH_EXTH_MASK (0xFFF8)
#define CAN_MSGBUF_IDL_EXTL(x) (((x) & 0x7FFF) << 1)
#define CAN_MSGBUF_IDL_EXTL_MASK (0xFFFE)
#define CAN_MSGBUF_IDL_RTR (0x0001)
#else
/* MSGBUF CTRL */
#define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x000F) << 8)
#define CAN_MSGBUF_CTRL_CODE_MASK (0xF0FF)
#define CAN_MSGBUF_CTRL_SRR (0x0040)
#define CAN_MSGBUF_CTRL_IDE (0x0020)
#define CAN_MSGBUF_CTRL_RTR (0x0010)
#define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x000F)
#define CAN_MSGBUF_CTRL_LEN_MASK (0xFFF0)
/* MSGBUF ID */
#define CAN_MSGBUF_ID_STD(x) (((x) & 0x000007FF) << 18)
#define CAN_MSGBUF_ID_STD_MASK (0xE003FFFF)
#define CAN_MSGBUF_ID_EXT(x) ((x) & 0x0003FFFF)
#define CAN_MSGBUF_ID_EXT_MASK (0xFFFC0000)
#endif
/* FlexCan module */
typedef struct can_ctrl {
u32 mcr; /* 0x00 Module Configuration */
u32 ctrl; /* 0x04 Control */
u32 timer; /* 0x08 Free Running Timer */
u32 res1; /* 0x0C */
u32 rxgmsk; /* 0x10 Rx Global Mask */
u32 rx14msk; /* 0x14 RxBuffer 14 Mask */
u32 rx15msk; /* 0x18 RxBuffer 15 Mask */
#ifdef CONFIG_M5282
u32 res2; /* 0x1C */
u16 errstat; /* 0x20 Error and status */
u16 imsk; /* 0x22 Interrupt Mask */
u16 iflag; /* 0x24 Interrupt Flag */
u16 errcnt; /* 0x26 Error Counter */
u32 res3[3]; /* 0x28 - 0x33 */
#else
u16 res2; /* 0x1C */
u16 errcnt; /* 0x1E Error Counter */
u16 res3; /* 0x20 */
u16 errstat; /* 0x22 Error and status */
u32 res4; /* 0x24 */
u32 imsk; /* 0x28 Interrupt Mask */
u32 res5; /* 0x2C */
u16 iflag; /* 0x30 Interrupt Flag */
#endif
u32 res6[19]; /* 0x34 - 0x7F */
void *msgbuf; /* 0x80 Message Buffer 0-15 */
} can_t;
/* MCR */
#define CAN_MCR_MDIS (0x80000000)
#define CAN_MCR_FRZ (0x40000000)
#define CAN_MCR_HALT (0x10000000)
#define CAN_MCR_NORDY (0x08000000)
#define CAN_MCF_WAKEMSK (0x04000000) /* 5282 */
#define CAN_MCR_SOFTRST (0x02000000)
#define CAN_MCR_FRZACK (0x01000000)
#define CAN_MCR_SUPV (0x00800000)
#define CAN_MCR_SELFWAKE (0x00400000) /* 5282 */
#define CAN_MCR_APS (0x00200000) /* 5282 */
#define CAN_MCR_LPMACK (0x00100000)
#define CAN_MCF_BCC (0x00010000)
#define CAN_MCR_MAXMB(x) ((x) & 0x0F)
#define CAN_MCR_MAXMB_MASK (0xFFFFFFF0)
/* CTRL */
#define CAN_CTRL_PRESDIV(x) (((x) & 0xFF) << 24)
#define CAN_CTRL_PRESDIV_MASK (0x00FFFFFF)
#define CAN_CTRL_RJW(x) (((x) & 0x03) << 22)
#define CAN_CTRL_RJW_MASK (0xFF3FFFFF)
#define CAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
#define CAN_CTRL_PSEG1_MASK (0xFFC7FFFF)
#define CAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
#define CAN_CTRL_PSEG2_MASK (0xFFF8FFFF)
#define CAN_CTRL_BOFFMSK (0x00008000)
#define CAN_CTRL_ERRMSK (0x00004000)
#define CAN_CTRL_CLKSRC (0x00002000)
#define CAN_CTRL_LPB (0x00001000)
#define CAN_CTRL_RXMODE (0x00000400) /* 5282 */
#define CAN_CTRL_TXMODE(x) (((x) & 0x03) << 8) /* 5282 */
#define CAN_CTRL_TXMODE_MASK (0xFFFFFCFF) /* 5282 */
#define CAN_CTRL_TXMODE_CAN0 (0x00000000) /* 5282 */
#define CAN_CTRL_TXMODE_CAN1 (0x00000100) /* 5282 */
#define CAN_CTRL_TXMODE_OPEN (0x00000200) /* 5282 */
#define CAN_CTRL_SMP (0x00000080)
#define CAN_CTRL_BOFFREC (0x00000040)
#define CAN_CTRL_TSYNC (0x00000020)
#define CAN_CTRL_LBUF (0x00000010)
#define CAN_CTRL_LOM (0x00000008)
#define CAN_CTRL_PROPSEG(x) ((x) & 0x07)
#define CAN_CTRL_PROPSEG_MASK (0xFFFFFFF8)
/* TIMER */
/* Note: PRESDIV, RJW, PSG1, and PSG2 are part of timer in 5282 */
#define CAN_TIMER(x) ((x) & 0xFFFF)
#define CAN_TIMER_MASK (0xFFFF0000)
/* RXGMASK */
#ifdef CONFIG_M5282
#define CAN_RXGMSK_MI_STD(x) (((x) & 0x000007FF) << 21)
#define CAN_RXGMSK_MI_STD_MASK (0x001FFFFF)
#define CAN_RXGMSK_MI_EXT(x) (((x) & 0x0003FFFF) << 1)
#define CAN_RXGMSK_MI_EXT_MASK (0xFFF80001)
#else
#define CAN_RXGMSK_MI_STD(x) (((x) & 0x000007FF) << 18)
#define CAN_RXGMSK_MI_STD_MASK (0xE003FFFF)
#define CAN_RXGMSK_MI_EXT(x) ((x) & 0x0003FFFF)
#define CAN_RXGMSK_MI_EXT_MASK (0xFFFC0000)
#endif
/* ERRCNT */
#define CAN_ERRCNT_RXECTR(x) (((x) & 0xFF) << 8)
#define CAN_ERRCNT_RXECTR_MASK (0x00FF)
#define CAN_ERRCNT_TXECTR(x) ((x) & 0xFF)
#define CAN_ERRCNT_TXECTR_MASK (0xFF00)
/* ERRSTAT */
#define CAN_ERRSTAT_BITERR1 (0x8000)
#define CAN_ERRSTAT_BITERR0 (0x4000)
#define CAN_ERRSTAT_ACKERR (0x2000)
#define CAN_ERRSTAT_CRCERR (0x1000)
#define CAN_ERRSTAT_FRMERR (0x0800)
#define CAN_ERRSTAT_STFERR (0x0400)
#define CAN_ERRSTAT_TXWRN (0x0200)
#define CAN_ERRSTAT_RXWRN (0x0100)
#define CAN_ERRSTAT_IDLE (0x0080)
#define CAN_ERRSTAT_TXRX (0x0040)
#define CAN_ERRSTAT_FLT_MASK (0xFFCF)
#define CAN_ERRSTAT_FLT_BUSOFF (0x0020)
#define CAN_ERRSTAT_FLT_PASSIVE (0x0010)
#define CAN_ERRSTAT_FLT_ACTIVE (0x0000)
#ifdef CONFIG_M5282
#define CAN_ERRSTAT_BOFFINT (0x0004)
#define CAN_ERRSTAT_ERRINT (0x0002)
#else
#define CAN_ERRSTAT_ERRINT (0x0004)
#define CAN_ERRSTAT_BOFFINT (0x0002)
#define CAN_ERRSTAT_WAKEINT (0x0001)
#endif
/* IMASK */
#ifdef CONFIG_M5253
#define CAN_IMASK_BUFnM(x) (1 << (x & 0xFFFFFFFF))
#define CAN_IMASK_BUFnM_MASKBIT(x) ~CAN_IMASK_BUFnM(x)
#else
#define CAN_IMASK_BUFnM(x) (1 << (x & 0xFFFF))
#define CAN_IMASK_BUFnM_MASKBIT(x) ~CAN_IMASK_BUFnM(x)
#endif
/* IFLAG */
#ifdef CONFIG_M5253
#define CAN_IFLAG_BUFnM(x) (1 << (x & 0xFFFFFFFF))
#define CAN_IFLAG_BUFnM_MASKBIT(x) ~CAN_IFLAG_BUFnM(x)
#else
#define CAN_IFLAG_BUFnM(x) (1 << (x & 0xFFFF))
#define CAN_IFLAG_BUFnM_MASKBIT(x) ~CAN_IFLAG_BUFnM(x)
#endif
#endif /* __FLEXCAN_H__ */

246
include/asm-m68k/coldfire/intctrl.h Normal file
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@ -0,0 +1,246 @@
/*
* Interrupt Controller Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __INTCTRL_H__
#define __INTCTRL_H__
#if defined(CONFIG_M5235) || defined(CONFIG_M5271) || \
defined(CONFIG_M5275) || defined(CONFIG_M5282) || \
defined(CONFIG_M547x) || defined(CONFIG_M548x)
# define CONFIG_SYS_CF_INTC_REG1
#endif
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending High */
u32 iprl0; /* 0x04 Pending Low */
u32 imrh0; /* 0x08 Mask High */
u32 imrl0; /* 0x0C Mask Low */
u32 frch0; /* 0x10 Force High */
u32 frcl0; /* 0x14 Force Low */
#if defined(CONFIG_SYS_CF_INTC_REG1)
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
#else
u16 res1; /* 0x18 - 0x19 */
u16 icfg0; /* 0x1A Configuration */
u8 simr0; /* 0x1C Set Interrupt Mask */
u8 cimr0; /* 0x1D Clear Interrupt Mask */
u8 clmask0; /* 0x1E Current Level Mask */
u8 slmask; /* 0x1F Saved Level Mask */
u32 res2[8]; /* 0x20 - 0x3F */
#endif
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt ack */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 L1iack0; /* 0xE4 Level n interrupt ack */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 L2iack0; /* 0xE8 Level n interrupt ack */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 L3iack0; /* 0xEC Level n interrupt ack */
u8 res7[3]; /* 0xED - 0xEF */
u8 L4iack0; /* 0xF0 Level n interrupt ack */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 L5iack0; /* 0xF4 Level n interrupt ack */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 L6iack0; /* 0xF8 Level n interrupt ack */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 L7iack0; /* 0xFC Level n interrupt ack */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending High */
u32 iprl1; /* 0x04 Pending Low */
u32 imrh1; /* 0x08 Mask High */
u32 imrl1; /* 0x0C Mask Low */
u32 frch1; /* 0x10 Force High */
u32 frcl1; /* 0x14 Force Low */
#if defined(CONFIG_SYS_CF_INTC_REG1)
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
#else
u16 res1; /* 0x18 */
u16 icfg1; /* 0x1A Configuration */
u8 simr1; /* 0x1C Set Interrupt Mask */
u8 cimr1; /* 0x1D Clear Interrupt Mask */
u16 res2; /* 0x1E - 0x1F */
u32 res3[8]; /* 0x20 - 0x3F */
#endif
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt ack */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 L1iack1; /* 0xE4 Level n interrupt ack */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 L2iack1; /* 0xE8 Level n interrupt ack */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 L3iack1; /* 0xEC Level n interrupt ack */
u8 res8[3]; /* 0xED - 0xEF */
u8 L4iack1; /* 0xF0 Level n interrupt ack */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 L5iack1; /* 0xF4 Level n interrupt ack */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 L6iack1; /* 0xF8 Level n interrupt ack */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 L7iack1; /* 0xFC Level n interrupt ack */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
typedef struct intgack_ctrl1 {
/* Global IACK Registers */
u8 swiack; /* 0x00 Global Software Interrupt ack */
u8 res0[0x3];
u8 gl1iack; /* 0x04 */
u8 resv1[0x3];
u8 gl2iack; /* 0x08 */
u8 res2[0x3];
u8 gl3iack; /* 0x0C */
u8 res3[0x3];
u8 gl4iack; /* 0x10 */
u8 res4[0x3];
u8 gl5iack; /* 0x14 */
u8 res5[0x3];
u8 gl6iack; /* 0x18 */
u8 res6[0x3];
u8 gl7iack; /* 0x1C */
u8 res7[0x3];
} intgack_t;
#define INTC_IPRH_INT63 (0x80000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT32 (0x00000001)
#define INTC_IPRL_INT31 (0x80000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT0 (0x00000001)
#define INTC_IMRLn_MASKALL (0x00000001)
#define INTC_IRLR(x) (((x) & 0x7F) << 1)
#define INTC_IRLR_MASK (0x01)
#define INTC_IACKLPR_LVL(x) (((x) & 0x07) << 4)
#define INTC_IACKLPR_LVL_MASK (0x8F)
#define INTC_IACKLPR_PRI(x) ((x) & 0x0F)
#define INTC_IACKLPR_PRI_MASK (0xF0)
#if defined(CONFIG_SYS_CF_INTC_REG1)
#define INTC_ICR_IL(x) (((x) & 0x07) << 3)
#define INTC_ICR_IL_MASK (0xC7)
#define INTC_ICR_IP(x) ((x) & 0x07)
#define INTC_ICR_IP_MASK (0xF8)
#else
#define INTC_ICR_IL(x) ((x) & 0x07)
#define INTC_ICR_IL_MASK (0xF8)
#endif
#define INTC_ICONFIG_ELVLPRI_MASK (0x01FF)
#define INTC_ICONFIG_ELVLPRI7 (0x8000)
#define INTC_ICONFIG_ELVLPRI6 (0x4000)
#define INTC_ICONFIG_ELVLPRI5 (0x2000)
#define INTC_ICONFIG_ELVLPRI4 (0x1000)
#define INTC_ICONFIG_ELVLPRI3 (0x0800)
#define INTC_ICONFIG_ELVLPRI2 (0x0400)
#define INTC_ICONFIG_ELVLPRI1 (0x0200)
#define INTC_ICONFIG_EMASK (0x0020)
#define INTC_SIMR_ALL (0x40)
#define INTC_SIMR(x) ((x) & 0x3F)
#define INTC_SIMR_MASK (0x80)
#define INTC_CIMR_ALL (0x40)
#define INTC_CIMR(x) ((x) & 0x3F)
#define INTC_CIMR_MASK (0x80)
#define INTC_CLMASK(x) ((x) & 0x0F)
#define INTC_CLMASK_MASK (0xF0)
#define INTC_SLMASK(x) ((x) & 0x0F)
#define INTC_SLMASK_MASK (0xF0)
#endif /* __INTCTRL_H__ */

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/*
* Message Digest Hardware Accelerator Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MDHA_H__
#define __MDHA_H__
/* Message Digest Hardware Accelerator */
typedef struct mdha_ctrl {
u32 mr; /* 0x00 MDHA Mode */
u32 cr; /* 0x04 Control */
u32 cmd; /* 0x08 Command */
u32 sr; /* 0x0C Status */
u32 isr; /* 0x10 Interrupt Status */
u32 imr; /* 0x14 Interrupt Mask */
u32 dsz; /* 0x1C Data Size */
u32 inp; /* 0x20 Input FIFO */
u32 res1[3]; /* 0x24 - 0x2F */
u32 mda0; /* 0x30 Message Digest AO */
u32 mdb0; /* 0x34 Message Digest BO */
u32 mdc0; /* 0x38 Message Digest CO */
u32 mdd0; /* 0x3C Message Digest DO */
u32 mde0; /* 0x40 Message Digest EO */
u32 mdsz; /* 0x44 Message Data Size */
u32 res[10]; /* 0x48 - 0x6F */
u32 mda1; /* 0x70 Message Digest A1 */
u32 mdb1; /* 0x74 Message Digest B1 */
u32 mdc1; /* 0x78 Message Digest C1 */
u32 mdd1; /* 0x7C Message Digest D1 */
u32 mde1; /* 0x80 Message Digest E1 */
} mdha_t;
#define MDHA_MR_SSL (0x00000400)
#define MDHA_MR_MACFUL (0x00000200)
#define MDHA_MR_SWAP (0x00000100)
#define MDHA_MR_OPAD (0x00000080)
#define MDHA_MR_IPAD (0x00000040)
#define MDHA_MR_INIT (0x00000020)
#define MDHA_MR_MAC(x) (((x) & 0x03) << 3)
#define MDHA_MR_MAC_MASK (0xFFFFFFE7)
#define MDHA_MR_MAC_EHMAC (0x00000010)
#define MDHA_MR_MAC_HMAC (0x00000008)
#define MDHA_MR_MAC_NONE (0x00000000)
#define MDHA_MR_PDATA (0x00000004)
#define MDHA_MR_ALG (0x00000001)
#define MDHA_CR_DMAL(x) (((x) & 0x1F) << 16) /* 532x */
#define MDHA_CR_DMAL_MASK (0xFFE0FFFF) /* 532x */
#define MDHA_CR_END (0x00000004) /* 532x */
#define MDHA_CR_DMA (0x00000002) /* 532x */
#define MDHA_CR_IE (0x00000001)
#define MDHA_CMD_GO (0x00000008)
#define MDHA_CMD_CI (0x00000004)
#define MDHA_CMD_RI (0x00000001)
#define MDHA_CMD_SWR (0x00000001)
#define MDHA_SR_IFL(x) (((x) & 0xFF) << 16)
#define MDHA_SR_IFL_MASK (0xFF00FFFF)
#define MDHA_SR_APD(x) (((x) & 0x7) << 13)
#define MDHA_SR_APD_MASK (0xFFFF1FFF)
#define MDHA_SR_FS(x) (((x) & 0x7) << 8)
#define MDHA_SR_FS_MASK (0xFFFFF8FF)
#define MDHA_SR_GNW (0x00000080)
#define MDHA_SR_HSH (0x00000040)
#define MDHA_SR_BUSY (0x00000010)
#define MDHA_SR_RD (0x00000008)
#define MDHA_SR_ERR (0x00000004)
#define MDHA_SR_DONE (0x00000002)
#define MDHA_SR_INT (0x00000001)
#define MDHA_ISR_DRL (0x00000400) /* 532x */
#define MDHA_ISR_GTDS (0x00000200)
#define MDHA_ISR_ERE (0x00000100)
#define MDHA_ISR_RMDP (0x00000080)
#define MDHA_ISR_DSE (0x00000020)
#define MDHA_ISR_IME (0x00000010)
#define MDHA_ISR_NEIF (0x00000004)
#define MDHA_ISR_IFO (0x00000001)
#endif /* __MDHA_H__ */

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/*
* Pulse Width Modulation Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ATA_H__
#define __ATA_H__
/* Pulse Width Modulation (PWM) */
typedef struct pwm_ctrl {
#ifdef CONFIG_M5272
u8 cr0;
u8 res1[3];
u8 cr1;
u8 res2[3];
u8 cr2;
u8 res3[7];
u8 pwr0;
u8 res4[3];
u8 pwr1;
u8 res5[3];
u8 pwr2;
u8 res6[7];
#else
u8 en; /* 0x00 PWM Enable */
u8 pol; /* 0x01 Polarity */
u8 clk; /* 0x02 Clock Select */
u8 prclk; /* 0x03 Prescale Clock Select */
u8 cae; /* 0x04 Center Align Enable */
u8 ctl; /* 0x05 Control */
u16 res1; /* 0x06 - 0x07 */
u8 scla; /* 0x08 Scale A */
u8 sclb; /* 0x09 Scale B */
u16 res2; /* 0x0A - 0x0B */
#ifdef CONFIG_M5275
u8 cnt[4]; /* 0x0C Channel n Counter */
u16 res3; /* 0x10 - 0x11 */
u8 per[4]; /* 0x14 Channel n Period */
u16 res4; /* 0x16 - 0x17 */
u8 dty[4]; /* 0x18 Channel n Duty */
#else
u8 cnt[8]; /* 0x0C Channel n Counter */
u8 per[8]; /* 0x14 Channel n Period */
u8 dty[8]; /* 0x1C Channel n Duty */
u8 sdn; /* 0x24 Shutdown */
u8 res3[3]; /* 0x25 - 0x27 */
#endif /* CONFIG_M5275 */
#endif /* CONFIG_M5272 */
} pwm_t;
#ifdef CONFIG_M5272
#define PWM_CR_EN (0x80)
#define PWM_CR_FRC1 (0x40)
#define PWM_CR_LVL (0x20)
#define PWM_CR_CLKSEL(x) ((x) & 0x0F)
#define PWM_CR_CLKSEL_MASK (0xF0)
#else
#define PWM_EN_PWMEn(x) (1 << ((x) & 0x07))
#define PWM_EN_PWMEn_MASK (0xF0)
#define PWM_POL_PPOLn(x) (1 << ((x) & 0x07))
#define PWM_POL_PPOLn_MASK (0xF0)
#define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07))
#define PWM_CLK_PCLKn_MASK (0xF0)
#define PWM_PRCLK_PCKB(x) (((x) & 0x07) << 4)
#define PWM_PRCLK_PCKB_MASK (0x8F)
#define PWM_PRCLK_PCKA(x) ((x) & 0x07)
#define PWM_PRCLK_PCKA_MASK (0xF8)
#define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07))
#define PWM_CLK_PCLKn_MASK (0xF0)
#define PWM_CTL_CON67 (0x80)
#define PWM_CTL_CON45 (0x40)
#define PWM_CTL_CON23 (0x20)
#define PWM_CTL_CON01 (0x10)
#define PWM_CTL_PSWAR (0x08)
#define PWM_CTL_PFRZ (0x04)
#define PWM_SDN_IF (0x80)
#define PWM_SDN_IE (0x40)
#define PWM_SDN_RESTART (0x20)
#define PWM_SDN_LVL (0x10)
#define PWM_SDN_PWM7IN (0x04)
#define PWM_SDN_PWM7IL (0x02)
#define PWM_SDN_SDNEN (0x01)
#endif /* CONFIG_M5272 */
#endif /* __ATA_H__ */

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include/asm-m68k/coldfire/qspi.h Normal file
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/*
* Queue Serial Peripheral Interface Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __QSPI_H__
#define __QSPI_H__
/* QSPI module registers */
typedef struct qspi_ctrl {
u16 mr; /* 0x00 Mode */
u16 res1;
u16 dlyr; /* 0x04 Delay */
u16 res2;
u16 wr; /* 0x08 Wrap */
u16 res3;
u16 ir; /* 0x0C Interrupt */
u16 res4;
u16 ar; /* 0x10 Address */
u16 res5;
u16 dr; /* 0x14 Data */
u16 res6;
} qspi_t;
/* MR */
#define QSPI_QMR_MSTR (0x8000)
#define QSPI_QMR_DOHIE (0x4000)
#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
#define QSPI_QMR_BITS_MASK (0xC3FF)
#define QSPI_QMR_BITS_8 (0x2000)
#define QSPI_QMR_BITS_9 (0x2400)
#define QSPI_QMR_BITS_10 (0x2800)
#define QSPI_QMR_BITS_11 (0x2C00)
#define QSPI_QMR_BITS_12 (0x3000)
#define QSPI_QMR_BITS_13 (0x3400)
#define QSPI_QMR_BITS_14 (0x3800)
#define QSPI_QMR_BITS_15 (0x3C00)
#define QSPI_QMR_BITS_16 (0x0000)
#define QSPI_QMR_CPOL (0x0200)
#define QSPI_QMR_CPHA (0x0100)
#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
#define QSPI_QMR_BAUD_MASK (0xFF00)
/* DLYR */
#define QSPI_QDLYR_SPE (0x8000)
#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
#define QSPI_QDLYR_QCD_MASK (0x80FF)
#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
#define QSPI_QDLYR_DTL_MASK (0xFF00)
/* WR */
#define QSPI_QWR_HALT (0x8000)
#define QSPI_QWR_WREN (0x4000)
#define QSPI_QWR_WRTO (0x2000)
#define QSPI_QWR_CSIV (0x1000)
#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
#define QSPI_QWR_ENDQP_MASK (0xF0FF)
#define QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4)
#define QSPI_QWR_CPTQP_MASK (0xFF0F)
#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
#define QSPI_QWR_NEWQP_MASK (0xFFF0)
/* IR */
#define QSPI_QIR_WCEFB (0x8000)
#define QSPI_QIR_ABRTB (0x4000)
#define QSPI_QIR_ABRTL (0x1000)
#define QSPI_QIR_WCEFE (0x0800)
#define QSPI_QIR_ABRTE (0x0400)
#define QSPI_QIR_SPIFE (0x0100)
#define QSPI_QIR_WCEF (0x0008)
#define QSPI_QIR_ABRT (0x0004)
#define QSPI_QIR_SPIF (0x0001)
/* AR */
#define QSPI_QAR_ADDR(x) ((x)&0x003F)
#define QSPI_QAR_ADDR_MASK (0xFFC0)
#define QSPI_QAR_TRANS (0x0000)
#define QSPI_QAR_RECV (0x0010)
#define QSPI_QAR_CMD (0x0020)
/* DR */
#define QSPI_QDR_CONT (0x8000)
#define QSPI_QDR_BITSE (0x4000)
#define QSPI_QDR_DT (0x2000)
#define QSPI_QDR_DSCK (0x1000)
#define QSPI_QDR_QSPI_CS3 (0x0800)
#define QSPI_QDR_QSPI_CS2 (0x0400)
#define QSPI_QDR_QSPI_CS1 (0x0200)
#define QSPI_QDR_QSPI_CS0 (0x0100)
#endif /* __QSPI_H__ */

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/*
* RNG Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __RNG_H__
#define __RNG_H__
/* Random Number Generator */
typedef struct rng_ctrl {
u32 cr; /* 0x00 Control */
u32 sr; /* 0x04 Status */
u32 er; /* 0x08 Entropy */
u32 out; /* 0x0C Output FIFO */
} rng_t;
#define RNG_CR_SLM (0x00000010) /* Sleep mode - 5445x */
#define RNG_CR_CI (0x00000008) /* Clear interrupt */
#define RNG_CR_IM (0x00000004) /* Interrupt mask */
#define RNG_CR_HA (0x00000002) /* High assurance */
#define RNG_CR_GO (0x00000001) /* Go bit */
#define RNG_SR_OFS(x) (((x) & 0x000000FF) << 16)
#define RNG_SR_OFS_MASK (0xFF00FFFF)
#define RNG_SR_OFL(x) (((x) & 0x000000FF) << 8)
#define RNG_SR_OFL_MASK (0xFFFF00FF)
#define RNG_SR_EI (0x00000008)
#define RNG_SR_FUF (0x00000004)
#define RNG_SR_LRS (0x00000002)
#define RNG_SR_SV (0x00000001)
#endif /* __RNG_H__ */

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/*
* Symmetric Key Hardware Accelerator Memory Map
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __SKHA_H__
#define __SKHA_H__
typedef struct skha_ctrl {
u32 mr; /* 0x00 Mode */
u32 cr; /* 0x04 Control */
u32 cmr; /* 0x08 Command */
u32 sr; /* 0x0C Status */
u32 esr; /* 0x10 Error Status */
u32 emr; /* 0x14 Error Status Mask Register) */
u32 ksr; /* 0x18 Key Size */
u32 dsr; /* 0x1C Data Size */
u32 in; /* 0x20 Input FIFO */
u32 out; /* 0x24 Output FIFO */
u32 res1[2]; /* 0x28 - 0x2F */
u32 kdr1; /* 0x30 Key Data 1 */
u32 kdr2; /* 0x34 Key Data 2 */
u32 kdr3; /* 0x38 Key Data 3 */
u32 kdr4; /* 0x3C Key Data 4 */
u32 kdr5; /* 0x40 Key Data 5 */
u32 kdr6; /* 0x44 Key Data 6 */
u32 res2[10]; /* 0x48 - 0x6F */
u32 c1; /* 0x70 Context 1 */
u32 c2; /* 0x74 Context 2 */
u32 c3; /* 0x78 Context 3 */
u32 c4; /* 0x7C Context 4 */
u32 c5; /* 0x80 Context 5 */
u32 c6; /* 0x84 Context 6 */
u32 c7; /* 0x88 Context 7 */
u32 c8; /* 0x8C Context 8 */
u32 c9; /* 0x90 Context 9 */
u32 c10; /* 0x94 Context 10 */
u32 c11; /* 0x98 Context 11 */
u32 c12; /* 0x9C Context 12 - 5235, 5271, 5272 */
} skha_t;
#ifdef CONFIG_MCF532x
#define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 9)
#define SKHA_MODE_CTRM_MASK (0xFFFFE1FF)
#define SKHA_MODE_DKP (0x00000100)
#else
#define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 8)
#define SKHA_MODE_CTRM_MASK (0xFFFFF0FF)
#define SKHA_MODE_DKP (0x00000080)
#endif
#define SKHA_MODE_CM(x) (((x) & 0x03) << 3)
#define SKHA_MODE_CM_MASK (0xFFFFFFE7)
#define SKHA_MODE_DIR (0x00000004)
#define SKHA_MODE_ALG(x) ((x) & 0x03)
#define SKHA_MODE_ALG_MASK (0xFFFFFFFC)
#define SHKA_CR_ODMAL(x) (((x) & 0x3F) << 24)
#define SHKA_CR_ODMAL_MASK (0xC0FFFFFF)
#define SHKA_CR_IDMAL(x) (((x) & 0x3F) << 16)
#define SHKA_CR_IDMAL_MASK (0xFFC0FFFF)
#define SHKA_CR_END (0x00000008)
#define SHKA_CR_ODMA (0x00000004)
#define SHKA_CR_IDMA (0x00000002)
#define SKHA_CR_IE (0x00000001)
#define SKHA_CMR_GO (0x00000008)
#define SKHA_CMR_CI (0x00000004)
#define SKHA_CMR_RI (0x00000002)
#define SKHA_CMR_SWR (0x00000001)
#define SKHA_SR_OFL(x) (((x) & 0xFF) << 24)
#define SKHA_SR_OFL_MASK (0x00FFFFFF)
#define SKHA_SR_IFL(x) (((x) & 0xFF) << 16)
#define SKHA_SR_IFL_MASK (0xFF00FFFF)
#define SKHA_SR_AESES(x) (((x) & 0x1F) << 11)
#define SKHA_SR_AESES_MASK (0xFFFF07FF)
#define SKHA_SR_DESES(x) (((x) & 0x7) << 8)
#define SKHA_SR_DESES_MASK (0xFFFFF8FF)
#define SKHA_SR_BUSY (0x00000010)
#define SKHA_SR_RD (0x00000008)
#define SKHA_SR_ERR (0x00000004)
#define SKHA_SR_DONE (0x00000002)
#define SKHA_SR_INT (0x00000001)
#define SHKA_ESE_DRL (0x00000800)
#define SKHA_ESR_KRE (0x00000400)
#define SKHA_ESR_KPE (0x00000200)
#define SKHA_ESR_ERE (0x00000100)
#define SKHA_ESR_RMDP (0x00000080)
#define SKHA_ESR_KSE (0x00000040)
#define SKHA_ESR_DSE (0x00000020)
#define SKHA_ESR_IME (0x00000010)
#define SKHA_ESR_NEOF (0x00000008)
#define SKHA_ESR_NEIF (0x00000004)
#define SKHA_ESR_OFU (0x00000002)
#define SKHA_ESR_IFO (0x00000001)
#define SKHA_KSR_SZ(x) ((x) & 0x3F)
#define SKHA_KSR_SZ_MASK (0xFFFFFFC0)
#endif /* __SKHA_H__ */

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@ -26,10 +26,6 @@
#ifndef __SSI_H__
#define __SSI_H__
/*********************************************************************
* Synchronous Serial Interface (SSI)
*********************************************************************/
typedef struct ssi {
u32 tx0;
u32 tx1;
@ -52,14 +48,10 @@ typedef struct ssi {
u32 rmask;
} ssi_t;
/*********************************************************************
* Synchronous Serial Interface (SSI)
*********************************************************************/
/* Bit definitions and macros for SSI_CR */
#define SSI_CR_CIS (0x00000200)
#define SSI_CR_TCH (0x00000100)
#define SSI_CR_MCE (0x00000080)
#define SSI_CR_I2S_MASK (0xFFFFFF9F)
#define SSI_CR_I2S_SLAVE (0x00000040)
#define SSI_CR_I2S_MASTER (0x00000020)
#define SSI_CR_I2S_NORMAL (0x00000000)
@ -69,7 +61,6 @@ typedef struct ssi {
#define SSI_CR_TE (0x00000002)
#define SSI_CR_SSI_EN (0x00000001)
/* Bit definitions and macros for SSI_ISR */
#define SSI_ISR_CMDAU (0x00040000)
#define SSI_ISR_CMDDU (0x00020000)
#define SSI_ISR_RXT (0x00010000)
@ -90,7 +81,6 @@ typedef struct ssi {
#define SSI_ISR_TFE1 (0x00000002)
#define SSI_ISR_TFE0 (0x00000001)
/* Bit definitions and macros for SSI_IER */
#define SSI_IER_RDMAE (0x00400000)
#define SSI_IER_RIE (0x00200000)
#define SSI_IER_TDMAE (0x00100000)
@ -115,7 +105,6 @@ typedef struct ssi {
#define SSI_IER_TFE1 (0x00000002)
#define SSI_IER_TFE0 (0x00000001)
/* Bit definitions and macros for SSI_TCR */
#define SSI_TCR_TXBIT0 (0x00000200)
#define SSI_TCR_TFEN1 (0x00000100)
#define SSI_TCR_TFEN0 (0x00000080)
@ -127,7 +116,6 @@ typedef struct ssi {
#define SSI_TCR_TFSL (0x00000002)
#define SSI_TCR_TEFS (0x00000001)
/* Bit definitions and macros for SSI_RCR */
#define SSI_RCR_RXEXT (0x00000400)
#define SSI_RCR_RXBIT0 (0x00000200)
#define SSI_RCR_RFEN1 (0x00000100)
@ -138,38 +126,44 @@ typedef struct ssi {
#define SSI_RCR_RFSL (0x00000002)
#define SSI_RCR_REFS (0x00000001)
/* Bit definitions and macros for SSI_CCR */
#define SSI_CCR_DIV2 (0x00040000)
#define SSI_CCR_PSR (0x00020000)
#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
#define SSI_CCR_PM(x) ((x)&0x000000FF)
#define SSI_CCR_WL(x) (((x) & 0x0F) << 13)
#define SSI_CCR_WL_MASK (0xFFFE1FFF)
#define SSI_CCR_DC(x) (((x)& 0x1F) << 8)
#define SSI_CCR_DC_MASK (0xFFFFE0FF)
#define SSI_CCR_PM(x) ((x) & 0xFF)
#define SSI_CCR_PM_MASK (0xFFFFFF00)
/* Bit definitions and macros for SSI_FCSR */
#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
#define SSI_FCSR_TFWM0(x) ((x)&0x0000000F)
#define SSI_FCSR_RFCNT1(x) (((x) & 0x0F) << 28)
#define SSI_FCSR_RFCNT1_MASK (0x0FFFFFFF)
#define SSI_FCSR_TFCNT1(x) (((x) & 0x0F) << 24)
#define SSI_FCSR_TFCNT1_MASK (0xF0FFFFFF)
#define SSI_FCSR_RFWM1(x) (((x) & 0x0F) << 20)
#define SSI_FCSR_RFWM1_MASK (0xFF0FFFFF)
#define SSI_FCSR_TFWM1(x) (((x) & 0x0F) << 16)
#define SSI_FCSR_TFWM1_MASK (0xFFF0FFFF)
#define SSI_FCSR_RFCNT0(x) (((x) & 0x0F) << 12)
#define SSI_FCSR_RFCNT0_MASK (0xFFFF0FFF)
#define SSI_FCSR_TFCNT0(x) (((x) & 0x0F) << 8)
#define SSI_FCSR_TFCNT0_MASK (0xFFFFF0FF)
#define SSI_FCSR_RFWM0(x) (((x) & 0x0F) << 4)
#define SSI_FCSR_RFWM0_MASK (0xFFFFFF0F)
#define SSI_FCSR_TFWM0(x) ((x) & 0x0F)
#define SSI_FCSR_TFWM0_MASK (0xFFFFFFF0)
/* Bit definitions and macros for SSI_ACR */
#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
#define SSI_ACR_FRDIV(x) (((x) & 0x3F) << 5)
#define SSI_ACR_FRDIV_MASK (0xFFFFF81F)
#define SSI_ACR_WR (0x00000010)
#define SSI_ACR_RD (0x00000008)
#define SSI_ACR_TIF (0x00000004)
#define SSI_ACR_FV (0x00000002)
#define SSI_ACR_AC97EN (0x00000001)
/* Bit definitions and macros for SSI_ACADD */
#define SSI_ACADD_SSI_ACADD(x) ((x)&0x0007FFFF)
#define SSI_ACADD_SSI_ACADD(x) ((x) & 0x0007FFFF)
/* Bit definitions and macros for SSI_ACDAT */
#define SSI_ACDAT_SSI_ACDAT(x) ((x)&0x0007FFFF)
#define SSI_ACDAT_SSI_ACDAT(x) ((x) & 0x0007FFFF)
/* Bit definitions and macros for SSI_ATAG */
#define SSI_ATAG_DDI_ATAG(x) ((x)&0x0000FFFF)
#define SSI_ATAG_DDI_ATAG(x) ((x) & 0x0000FFFF)
#endif /* __SSI_H__ */

109
include/asm-m68k/immap_5227x.h
View File

@ -69,109 +69,14 @@
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/lcd.h>
#include <asm/coldfire/pwm.h>
#include <asm/coldfire/ssi.h>
/* Interrupt Controller (INTC) */
typedef struct int0_ctrl {
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u16 res1; /* 0x18 - 0x19 */
u16 icfg0; /* 0x1A Configuration Register */
u8 simr0; /* 0x1C Set Interrupt Mask */
u8 cimr0; /* 0x1D Clear Interrupt Mask */
u8 clmask0; /* 0x1E Current Level Mask */
u8 slmask; /* 0x1F Saved Level Mask */
u32 res2[8]; /* 0x20 - 0x3F */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt ack */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt ack */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt ack */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt ack */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt ack */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt ack */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt ack */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt ack */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u16 res1; /* 0x18 */
u16 icfg1; /* 0x1A Configuration Register */
u8 simr1; /* 0x1C Set Interrupt Mask */
u8 cimr1; /* 0x1D Clear Interrupt Mask */
u16 res2; /* 0x1E - 0x1F */
u32 res3[8]; /* 0x20 - 0x3F */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt ack */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt ack */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt ack */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt ack */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt ack */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt ack */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt ack */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt ack */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
/* Global Interrupt Acknowledge (IACK) */
typedef struct iack {
u8 resv0[0xE0];
u8 gswiack;
u8 resv1[0x3];
u8 gl1iack;
u8 resv2[0x3];
u8 gl2iack;
u8 resv3[0x3];
u8 gl3iack;
u8 resv4[0x3];
u8 gl4iack;
u8 resv5[0x3];
u8 gl5iack;
u8 resv6[0x3];
u8 gl6iack;
u8 resv7[0x3];
u8 gl7iack;
} iack_t;
/* Edge Port Module (EPORT) */
typedef struct eport {
u16 eppar;
u8 epddr;
u8 epier;
u8 epdr;
u8 eppdr;
u8 epfr;
} eport_t;
/* Reset Controller Module (RCM) */
typedef struct rcm {
u8 rcr;
@ -193,6 +98,12 @@ typedef struct ccm {
u16 sbfcr; /* Serial Boot Control */
} ccm_t;
typedef struct canex_ctrl {
can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
u32 res0[0x700]; /* 0x100 */
can_msg_t rxim[16]; /* 0x800 Rx Individual Mask 0-15 */
} canex_t;
/* General Purpose I/O Module (GPIO) */
typedef struct gpio {
/* Port Output Data Registers */

166
include/asm-m68k/immap_5235.h
View File

@ -63,6 +63,15 @@
#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000)
#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/mdha.h>
#include <asm/coldfire/qspi.h>
#include <asm/coldfire/rng.h>
#include <asm/coldfire/skha.h>
/* System Control Module register */
typedef struct scm_ctrl {
u32 ipsbar; /* 0x00 - MBAR */
@ -104,141 +113,9 @@ typedef struct sdram_ctrl {
u32 dmr1; /* 0x14 mask register block 1 */
} sdram_t;
/* Flexbus module Chip select registers */
typedef struct fbcs_ctrl {
u16 csar0; /* 0x00 Chip-Select Address Register 0 */
u16 res0;
u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
u16 res1; /* 0x08 */
u16 cscr0; /* 0x0A Chip-Select Control Register 0 */
u16 csar1; /* 0x0C Chip-Select Address Register 1 */
u16 res2;
u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
u16 res3; /* 0x14 */
u16 cscr1; /* 0x16 Chip-Select Control Register 1 */
u16 csar2; /* 0x18 Chip-Select Address Register 2 */
u16 res4;
u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
u16 res5; /* 0x20 */
u16 cscr2; /* 0x22 Chip-Select Control Register 2 */
u16 csar3; /* 0x24 Chip-Select Address Register 3 */
u16 res6;
u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
u16 res7; /* 0x2C */
u16 cscr3; /* 0x2E Chip-Select Control Register 3 */
u16 csar4; /* 0x30 Chip-Select Address Register 4 */
u16 res8;
u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
u16 res9; /* 0x38 */
u16 cscr4; /* 0x3A Chip-Select Control Register 4 */
u16 csar5; /* 0x3C Chip-Select Address Register 5 */
u16 res10;
u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
u16 res11; /* 0x44 */
u16 cscr5; /* 0x46 Chip-Select Control Register 5 */
u16 csar6; /* 0x48 Chip-Select Address Register 5 */
u16 res12;
u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */
u16 res13; /* 0x50 */
u16 cscr6; /* 0x52 Chip-Select Control Register 5 */
u16 csar7; /* 0x54 Chip-Select Address Register 5 */
u16 res14;
u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */
u16 res15; /* 0x5C */
u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
} fbcs_t;
/* QSPI module registers */
typedef struct qspi_ctrl {
u16 qmr; /* Mode register */
u16 res1;
u16 qdlyr; /* Delay register */
u16 res2;
u16 qwr; /* Wrap register */
u16 res3;
u16 qir; /* Interrupt register */
u16 res4;
u16 qar; /* Address register */
u16 res5;
u16 qdr; /* Data register */
u16 res6;
} qspi_t;
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
typedef struct intgack_ctrl1 {
/* Global IACK Registers */
u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */
u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
} intgack_t;
typedef struct canex_ctrl {
can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
} canex_t;
/* GPIO port registers */
typedef struct gpio_ctrl {
@ -356,23 +233,4 @@ typedef struct wdog_ctrl {
u16 sr; /* 0x06 Service register */
} wdog_t;
/* FlexCan module registers */
typedef struct can_ctrl {
u32 mcr; /* 0x00 Module Configuration register */
u32 ctrl; /* 0x04 Control register */
u32 timer; /* 0x08 Free Running Timer */
u32 res1; /* 0x0C */
u32 rxgmask; /* 0x10 Rx Global Mask */
u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
u32 errcnt; /* 0x1C Error Counter Register */
u32 errstat; /* 0x20 Error and status Register */
u32 res2; /* 0x24 */
u32 imask; /* 0x28 Interrupt Mask Register */
u32 res3; /* 0x2C */
u32 iflag; /* 0x30 Interrupt Flag Register */
u32 res4[19]; /* 0x34 - 0x7F */
u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
} can_t;
#endif /* __IMMAP_5235__ */

4
include/asm-m68k/immap_5249.h
View File

@ -26,10 +26,14 @@
#define __IMMAP_5249__
#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400)
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/qspi.h>
#endif /* __IMMAP_5249__ */

65
include/asm-m68k/immap_5253.h
View File

@ -23,10 +23,11 @@
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5249__
#define __IMMAP_5249__
#ifndef __IMMAP_5253__
#define __IMMAP_5253__
#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
@ -39,57 +40,13 @@
#define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440)
#define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00)
/*********************************************************************
* ATA Module (ATAC)
*********************************************************************/
#include <asm/coldfire/ata.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/qspi.h>
/* Register read/write struct */
typedef struct atac {
/* PIO */
u8 toff; /* 0x00 */
u8 ton; /* 0x01 */
u8 t1; /* 0x02 */
u8 t2w; /* 0x03 */
u8 t2r; /* 0x04 */
u8 ta; /* 0x05 */
u8 trd; /* 0x06 */
u8 t4; /* 0x07 */
u8 t9; /* 0x08 */
typedef struct canex_ctrl {
can_msg_t msg[32]; /* 0x80 Message Buffer 0-31 */
} canex_t;
/* DMA */
u8 tm; /* 0x09 */
u8 tn; /* 0x0A */
u8 td; /* 0x0B */
u8 tk; /* 0x0C */
u8 tack; /* 0x0D */
u8 tenv; /* 0x0E */
u8 trp; /* 0x0F */
u8 tzah; /* 0x10 */
u8 tmli; /* 0x11 */
u8 tdvh; /* 0x12 */
u8 tdzfs; /* 0x13 */
u8 tdvs; /* 0x14 */
u8 tcvh; /* 0x15 */
u8 tss; /* 0x16 */
u8 tcyc; /* 0x17 */
/* FIFO */
u32 fifo32; /* 0x18 */
u16 fifo16; /* 0x1C */
u8 rsvd0[2];
u8 ffill; /* 0x20 */
u8 rsvd1[3];
/* ATA */
u8 cr; /* 0x24 */
u8 rsvd2[3];
u8 isr; /* 0x28 */
u8 rsvd3[3];
u8 ier; /* 0x2C */
u8 rsvd4[3];
u8 icr; /* 0x30 */
u8 rsvd5[3];
u8 falarm; /* 0x34 */
} atac_t;
#endif /* __IMMAP_5249__ */
#endif /* __IMMAP_5253__ */

39
include/asm-m68k/immap_5271.h
View File

@ -63,36 +63,13 @@
#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000)
#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000)
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/mdha.h>
#include <asm/coldfire/qspi.h>
#include <asm/coldfire/rng.h>
#include <asm/coldfire/skha.h>
#endif /* __IMMAP_5271__ */

34
include/asm-m68k/immap_5272.h
View File

@ -44,6 +44,8 @@
#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00000840)
#define MMAP_USB (CONFIG_SYS_MBAR + 0x00001000)
#include <asm/coldfire/pwm.h>
/* System configuration registers */
typedef struct sys_ctrl {
uint sc_mbar;
@ -104,38 +106,6 @@ typedef struct gpio_ctrl {
uchar res2[4];
} gpio_t;
/* QSPI module registers */
typedef struct qspi_ctrl {
ushort qspi_qmr;
uchar res1[2];
ushort qspi_qdlyr;
uchar res2[2];
ushort qspi_qwr;
uchar res3[2];
ushort qspi_qir;
uchar res4[2];
ushort qspi_qar;
uchar res5[2];
ushort qspi_qdr;
uchar res6[10];
} qspi_t;
/* PWM module registers */
typedef struct pwm_ctrl {
uchar pwm_pwcr0;
uchar res1[3];
uchar pwm_pwcr1;
uchar res2[3];
uchar pwm_pwcr2;
uchar res3[7];
uchar pwm_pwwd0;
uchar res4[3];
uchar pwm_pwwd1;
uchar res5[3];
uchar pwm_pwwd2;
uchar res6[7];
} pwm_t;
/* DMA module registers */
typedef struct dma_ctrl {
ulong dma_dmr;

120
include/asm-m68k/immap_5275.h
View File

@ -66,6 +66,15 @@
#define MMAP_USB (CONFIG_SYS_MBAR + 0x001C0000)
#define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/mdha.h>
#include <asm/coldfire/pwm.h>
#include <asm/coldfire/qspi.h>
#include <asm/coldfire/rng.h>
#include <asm/coldfire/skha.h>
/* System configuration registers
*/
typedef struct sys_ctrl {
@ -109,51 +118,6 @@ typedef struct sdram_ctrl {
u32 sdbmr1;
} sdramctrl_t;
/* Chip select module registers, offset: 0x080
*/
typedef struct cs_ctlr {
u16 ar0;
u16 res1;
u32 mr0;
u16 res2;
u16 cr0;
u16 ar1;
u16 res3;
u32 mr1;
u16 res4;
u16 cr1;
u16 ar2;
u16 res5;
u32 mr2;
u16 res6;
u16 cr2;
u16 ar3;
u16 res7;
u32 mr3;
u16 res8;
u16 cr3;
u16 ar4;
u16 res9;
u32 mr4;
u16 res10;
u16 cr4;
u16 ar5;
u16 res11;
u32 mr5;
u16 res12;
u16 cr5;
u16 ar6;
u16 res13;
u32 mr6;
u16 res14;
u16 cr6;
u16 ar7;
u16 res15;
u32 mr7;
u16 res16;
u16 cr7;
} csctrl_t;
/* DMA module registers, offset 0x100
*/
typedef struct dma_ctrl {
@ -163,55 +127,6 @@ typedef struct dma_ctrl {
u32 dcr;
} dma_t;
/* QSPI module registers, offset 0x340
*/
typedef struct qspi_ctrl {
u16 qmr;
u8 res1[2];
u16 qdlyr;
u8 res2[2];
u16 qwr;
u8 res3[2];
u16 qir;
u8 res4[2];
u16 qar;
u8 res5[2];
u16 qdr;
u8 res6[2];
} qspi_t;
/* Interrupt module registers, offset 0xc00
*/
typedef struct int_ctrl {
u32 iprh0;
u32 iprl0;
u32 imrh0;
u32 imrl0;
u32 frch0;
u32 frcl0;
u8 irlr;
u8 iacklpr;
u8 res1[0x26];
u8 icr0[64]; /* No ICR0, done this way for readability */
u8 res2[0x60];
u8 swiack0;
u8 res3[3];
u8 Lniack0_1;
u8 res4[3];
u8 Lniack0_2;
u8 res5[3];
u8 Lniack0_3;
u8 res6[3];
u8 Lniack0_4;
u8 res7[3];
u8 Lniack0_5;
u8 res8[3];
u8 Lniack0_6;
u8 res9[3];
u8 Lniack0_7;
u8 res10[3];
} int0_t;
/* GPIO port registers
*/
typedef struct gpio_ctrl {
@ -325,23 +240,6 @@ typedef struct gpio_ctrl {
} gpio_t;
/* PWM module registers
*/
typedef struct pwm_ctrl {
u8 pwcr0;
u8 res1[3];
u8 pwcr1;
u8 res2[3];
u8 pwcr2;
u8 res3[7];
u8 pwwd0;
u8 res4[3];
u8 pwwd1;
u8 res5[3];
u8 pwwd2;
u8 res6[7];
} pwm_t;
/* Watchdog registers
*/
typedef struct wdog_ctrl {

91
include/asm-m68k/immap_5282.h
View File

@ -62,6 +62,12 @@
#define MMAP_CFMC (CONFIG_SYS_MBAR + 0x001D0000)
#define MMAP_CFMMEM (CONFIG_SYS_MBAR + 0x04000000)
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/qspi.h>
/* System Control Module */
typedef struct scm_ctrl {
u32 ipsbar;
@ -92,88 +98,9 @@ typedef struct scm_ctrl {
u16 res8;
} scm_t;
/* Flexbus module Chip select registers */
typedef struct fbcs_ctrl {
u16 csar0; /* 0x00 Chip-Select Address Register 0 */
u16 res0;
u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
u16 res1; /* 0x08 */
u16 cscr0; /* 0x0A Chip-Select Control Register 0 */
u16 csar1; /* 0x0C Chip-Select Address Register 1 */
u16 res2;
u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
u16 res3; /* 0x14 */
u16 cscr1; /* 0x16 Chip-Select Control Register 1 */
u16 csar2; /* 0x18 Chip-Select Address Register 2 */
u16 res4;
u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
u16 res5; /* 0x20 */
u16 cscr2; /* 0x22 Chip-Select Control Register 2 */
u16 csar3; /* 0x24 Chip-Select Address Register 3 */
u16 res6;
u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
u16 res7; /* 0x2C */
u16 cscr3; /* 0x2E Chip-Select Control Register 3 */
u16 csar4; /* 0x30 Chip-Select Address Register 4 */
u16 res8;
u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
u16 res9; /* 0x38 */
u16 cscr4; /* 0x3A Chip-Select Control Register 4 */
u16 csar5; /* 0x3C Chip-Select Address Register 5 */
u16 res10;
u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
u16 res11; /* 0x44 */
u16 cscr5; /* 0x46 Chip-Select Control Register 5 */
u16 csar6; /* 0x48 Chip-Select Address Register 5 */
u16 res12;
u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */
u16 res13; /* 0x50 */
u16 cscr6; /* 0x52 Chip-Select Control Register 5 */
u16 csar7; /* 0x54 Chip-Select Address Register 5 */
u16 res14;
u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */
u16 res15; /* 0x5C */
u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
} fbcs_t;
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct canex_ctrl {
can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
} canex_t;
/* Clock Module registers */
typedef struct pll_ctrl {

284
include/asm-m68k/immap_5329.h
View File

@ -70,9 +70,16 @@
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/qspi.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/lcd.h>
#include <asm/coldfire/mdha.h>
#include <asm/coldfire/pwm.h>
#include <asm/coldfire/ssi.h>
#include <asm/coldfire/skha.h>
/* System control module registers */
typedef struct scm1_ctrl {
@ -83,72 +90,6 @@ typedef struct scm1_ctrl {
u32 bmt0; /*0x54 Bus Monitor Timeout 0 */
} scm1_t;
/* Message Digest Hardware Accelerator */
typedef struct mdha_ctrl {
u32 mdmr; /* 0x00 MDHA Mode Register */
u32 mdcr; /* 0x04 Control register */
u32 mdcmr; /* 0x08 Command Register */
u32 mdsr; /* 0x0C Status Register */
u32 mdisr; /* 0x10 Interrupt Status Register */
u32 mdimr; /* 0x14 Interrupt Mask Register */
u32 mddsr; /* 0x1C Data Size Register */
u32 mdin; /* 0x20 Input FIFO */
u32 res1[3]; /* 0x24 - 0x2F */
u32 mdao; /* 0x30 Message Digest AO Register */
u32 mdbo; /* 0x34 Message Digest BO Register */
u32 mdco; /* 0x38 Message Digest CO Register */
u32 mddo; /* 0x3C Message Digest DO Register */
u32 mdeo; /* 0x40 Message Digest EO Register */
u32 mdmds; /* 0x44 Message Data Size Register */
u32 res[10]; /* 0x48 - 0x6F */
u32 mda1; /* 0x70 Message Digest A1 Register */
u32 mdb1; /* 0x74 Message Digest B1 Register */
u32 mdc1; /* 0x78 Message Digest C1 Register */
u32 mdd1; /* 0x7C Message Digest D1 Register */
u32 mde1; /* 0x80 Message Digest E1 Register */
} mdha_t;
/* Symmetric Key Hardware Accelerator */
typedef struct skha_ctrl {
u32 mr; /* 0x00 Mode Register */
u32 cr; /* 0x04 Control Register */
u32 cmr; /* 0x08 Command Register */
u32 sr; /* 0x0C Status Register */
u32 esr; /* 0x10 Error Status Register */
u32 emr; /* 0x14 Error Status Mask Register) */
u32 ksr; /* 0x18 Key Size Register */
u32 dsr; /* 0x1C Data Size Register */
u32 in; /* 0x20 Input FIFO */
u32 out; /* 0x24 Output FIFO */
u32 res1[2]; /* 0x28 - 0x2F */
u32 kdr1; /* 0x30 Key Data Register 1 */
u32 kdr2; /* 0x34 Key Data Register 2 */
u32 kdr3; /* 0x38 Key Data Register 3 */
u32 kdr4; /* 0x3C Key Data Register 4 */
u32 kdr5; /* 0x40 Key Data Register 5 */
u32 kdr6; /* 0x44 Key Data Register 6 */
u32 res2[10]; /* 0x48 - 0x6F */
u32 c1; /* 0x70 Context 1 */
u32 c2; /* 0x74 Context 2 */
u32 c3; /* 0x78 Context 3 */
u32 c4; /* 0x7C Context 4 */
u32 c5; /* 0x80 Context 5 */
u32 c6; /* 0x84 Context 6 */
u32 c7; /* 0x88 Context 7 */
u32 c8; /* 0x8C Context 8 */
u32 c9; /* 0x90 Context 9 */
u32 c10; /* 0x94 Context 10 */
u32 c11; /* 0x98 Context 11 */
} skha_t;
/* Random Number Generator */
typedef struct rng_ctrl {
u32 rngcr; /* 0x00 RNG Control Register */
u32 rngsr; /* 0x04 RNG Status Register */
u32 rnger; /* 0x08 RNG Entropy Register */
u32 rngout; /* 0x0C RNG Output FIFO */
} rng_t;
/* System control module registers 2 */
typedef struct scm2_ctrl {
u32 mpr1; /* 0x00 Master Privilege Register */
@ -165,25 +106,6 @@ typedef struct scm2_ctrl {
u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */
} scm2_t;
/* FlexCan module registers */
typedef struct can_ctrl {
u32 mcr; /* 0x00 Module Configuration register */
u32 ctrl; /* 0x04 Control register */
u32 timer; /* 0x08 Free Running Timer */
u32 res1; /* 0x0C */
u32 rxgmask; /* 0x10 Rx Global Mask */
u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
u32 errcnt; /* 0x1C Error Counter Register */
u32 errstat; /* 0x20 Error and status Register */
u32 res2; /* 0x24 */
u32 imask; /* 0x28 Interrupt Mask Register */
u32 res3; /* 0x2C */
u32 iflag; /* 0x30 Interrupt Flag Register */
u32 res4[19]; /* 0x34 - 0x7F */
u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
} can_t;
/* System Control Module register 3 */
typedef struct scm3_ctrl {
u8 res1[19]; /* 0x00 - 0x12 */
@ -206,148 +128,9 @@ typedef struct scm3_ctrl {
u32 cfdtr; /* 0x7C Core Fault Data Register */
} scm3_t;
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u16 res1; /* 0x18 - 0x19 */
u16 icfg0; /* 0x1A Configuration Register */
u8 simr0; /* 0x1C Set Interrupt Mask */
u8 cimr0; /* 0x1D Clear Interrupt Mask */
u8 clmask0; /* 0x1E Current Level Mask */
u8 slmask; /* 0x1F Saved Level Mask */
u32 res2[8]; /* 0x20 - 0x3F */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u16 res1; /* 0x18 */
u16 icfg1; /* 0x1A Configuration Register */
u8 simr1; /* 0x1C Set Interrupt Mask */
u8 cimr1; /* 0x1D Clear Interrupt Mask */
u16 res2; /* 0x1E - 0x1F */
u32 res3[8]; /* 0x20 - 0x3F */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
typedef struct intgack_ctrl1 {
/* Global IACK Registers */
u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */
u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
} intgack_t;
/* QSPI module registers */
typedef struct qspi_ctrl {
u16 qmr; /* Mode register */
u16 res1;
u16 qdlyr; /* Delay register */
u16 res2;
u16 qwr; /* Wrap register */
u16 res3;
u16 qir; /* Interrupt register */
u16 res4;
u16 qar; /* Address register */
u16 res5;
u16 qdr; /* Data register */
u16 res6;
} qspi_t;
/* PWM module registers */
typedef struct pwm_ctrl {
u8 en; /* 0x00 PWM Enable Register */
u8 pol; /* 0x01 Polarity Register */
u8 clk; /* 0x02 Clock Select Register */
u8 prclk; /* 0x03 Prescale Clock Select Register */
u8 cae; /* 0x04 Center Align Enable Register */
u8 ctl; /* 0x05 Control Register */
u8 res1[2]; /* 0x06 - 0x07 */
u8 scla; /* 0x08 Scale A register */
u8 sclb; /* 0x09 Scale B register */
u8 res2[2]; /* 0x0A - 0x0B */
u8 cnt0; /* 0x0C Channel 0 Counter register */
u8 cnt1; /* 0x0D Channel 1 Counter register */
u8 cnt2; /* 0x0E Channel 2 Counter register */
u8 cnt3; /* 0x0F Channel 3 Counter register */
u8 cnt4; /* 0x10 Channel 4 Counter register */
u8 cnt5; /* 0x11 Channel 5 Counter register */
u8 cnt6; /* 0x12 Channel 6 Counter register */
u8 cnt7; /* 0x13 Channel 7 Counter register */
u8 per0; /* 0x14 Channel 0 Period register */
u8 per1; /* 0x15 Channel 1 Period register */
u8 per2; /* 0x16 Channel 2 Period register */
u8 per3; /* 0x17 Channel 3 Period register */
u8 per4; /* 0x18 Channel 4 Period register */
u8 per5; /* 0x19 Channel 5 Period register */
u8 per6; /* 0x1A Channel 6 Period register */
u8 per7; /* 0x1B Channel 7 Period register */
u8 dty0; /* 0x1C Channel 0 Duty register */
u8 dty1; /* 0x1D Channel 1 Duty register */
u8 dty2; /* 0x1E Channel 2 Duty register */
u8 dty3; /* 0x1F Channel 3 Duty register */
u8 dty4; /* 0x20 Channel 4 Duty register */
u8 dty5; /* 0x21 Channel 5 Duty register */
u8 dty6; /* 0x22 Channel 6 Duty register */
u8 dty7; /* 0x23 Channel 7 Duty register */
u8 sdn; /* 0x24 Shutdown register */
u8 res3[3]; /* 0x25 - 0x27 */
} pwm_t;
/* Edge Port module registers */
typedef struct eport_ctrl {
u16 par; /* 0x00 Pin Assignment Register */
u8 ddar; /* 0x02 Data Direction Register */
u8 ier; /* 0x03 Interrupt Enable Register */
u8 dr; /* 0x04 Data Register */
u8 pdr; /* 0x05 Pin Data Register */
u8 fr; /* 0x06 Flag_Register */
u8 res1;
} eport_t;
typedef struct canex_ctrl {
can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
} canex_t;
/* Watchdog registers */
typedef struct wdog_ctrl {
@ -593,53 +376,6 @@ typedef struct usb_otg {
u32 eptctrl3; /* 0x1CC Endpoint control 3 */
} usbotg_t;
/* USB Host module registers */
typedef struct usb_host {
u32 id; /* 0x000 Identification Register */
u32 hwgeneral; /* 0x004 General HW Parameters */
u32 hwhost; /* 0x008 Host HW Parameters */
u32 res1; /* 0x0C */
u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */
u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */
u32 res2[58]; /* 0x18 - 0xFF */
/* Host Controller Capability Register */
u8 caplength; /* 0x100 Capability Register Length */
u8 res3; /* 0x101 */
u16 hciver; /* 0x102 Host Interface Version Number */
u32 hcsparams; /* 0x104 Host Structural Parameters */
u32 hccparams; /* 0x108 Host Capability Parameters */
u32 res4[13]; /* 0x10C - 0x13F */
/* Host Controller Operational Register */
u32 cmd; /* 0x140 USB Command */
u32 sts; /* 0x144 USB Status */
u32 intr; /* 0x148 USB Interrupt Enable */
u32 frindex; /* 0x14C USB Frame Index */
u32 res5; /* 0x150 (ctrl segment register in EHCI spec) */
u32 prdlst; /* 0x154 Periodic Frame List Base Address */
u32 aynclst; /* 0x158 Current Asynchronous List Address */
u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control (non-ehci) */
u32 burstsize; /* 0x160 Master Interface Data Burst Size (non-ehci) */
u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control (non-ehci) */
u32 res6[6]; /* 0x168 - 0x17F */
u32 cfgflag; /* 0x180 Configure Flag Register */
u32 portsc1; /* 0x184 Port Status/Control */
u32 res7[8]; /* 0x188 - 0x1A7 */
/* non-ehci registers */
u32 mode; /* 0x1A8 USB mode register */
u32 eptsetstat; /* 0x1AC Endpoint Setup status */
u32 eptprime; /* 0x1B0 Endpoint initialization */
u32 eptflush; /* 0x1B4 Endpoint de-initialize */
u32 eptstat; /* 0x1B8 Endpoint status */
u32 eptcomplete; /* 0x1BC Endpoint Complete */
u32 eptctrl0; /* 0x1C0 Endpoint control 0 */
u32 eptctrl1; /* 0x1C4 Endpoint control 1 */
u32 eptctrl2; /* 0x1C8 Endpoint control 2 */
u32 eptctrl3; /* 0x1CC Endpoint control 3 */
} usbhost_t;
/* SDRAM controller registers */
typedef struct sdram_ctrl {
u32 mode; /* 0x00 Mode/Extended Mode register */

160
include/asm-m68k/immap_5445x.h
View File

@ -69,161 +69,15 @@
#define MMAP_USBEHCI 0xFC0B0140
#define MMAP_USBOTG 0xFC0B01A0
#include <asm/coldfire/ata.h>
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/ssi.h>
/* ATA */
typedef struct atac {
/* PIO */
u8 toff; /* 0x00 */
u8 ton; /* 0x01 */
u8 t1; /* 0x02 */
u8 t2w; /* 0x03 */
u8 t2r; /* 0x04 */
u8 ta; /* 0x05 */
u8 trd; /* 0x06 */
u8 t4; /* 0x07 */
u8 t9; /* 0x08 */
/* DMA */
u8 tm; /* 0x09 */
u8 tn; /* 0x0A */
u8 td; /* 0x0B */
u8 tk; /* 0x0C */
u8 tack; /* 0x0D */
u8 tenv; /* 0x0E */
u8 trp; /* 0x0F */
u8 tzah; /* 0x10 */
u8 tmli; /* 0x11 */
u8 tdvh; /* 0x12 */
u8 tdzfs; /* 0x13 */
u8 tdvs; /* 0x14 */
u8 tcvh; /* 0x15 */
u8 tss; /* 0x16 */
u8 tcyc; /* 0x17 */
/* FIFO */
u32 fifo32; /* 0x18 */
u16 fifo16; /* 0x1C */
u8 rsvd0[2];
u8 ffill; /* 0x20 */
u8 rsvd1[3];
/* ATA */
u8 cr; /* 0x24 */
u8 rsvd2[3];
u8 isr; /* 0x28 */
u8 rsvd3[3];
u8 ier; /* 0x2C */
u8 rsvd4[3];
u8 icr; /* 0x30 */
u8 rsvd5[3];
u8 falarm; /* 0x34 */
u8 rsvd6[106];
} atac_t;
/* Interrupt Controller (INTC) */
typedef struct int0_ctrl {
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u16 res1; /* 0x18 - 0x19 */
u16 icfg0; /* 0x1A Configuration Register */
u8 simr0; /* 0x1C Set Interrupt Mask */
u8 cimr0; /* 0x1D Clear Interrupt Mask */
u8 clmask0; /* 0x1E Current Level Mask */
u8 slmask; /* 0x1F Saved Level Mask */
u32 res2[8]; /* 0x20 - 0x3F */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u16 res1; /* 0x18 */
u16 icfg1; /* 0x1A Configuration Register */
u8 simr1; /* 0x1C Set Interrupt Mask */
u8 cimr1; /* 0x1D Clear Interrupt Mask */
u16 res2; /* 0x1E - 0x1F */
u32 res3[8]; /* 0x20 - 0x3F */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
/* Global Interrupt Acknowledge (IACK) */
typedef struct iack {
u8 resv0[0xE0];
u8 gswiack;
u8 resv1[0x3];
u8 gl1iack;
u8 resv2[0x3];
u8 gl2iack;
u8 resv3[0x3];
u8 gl3iack;
u8 resv4[0x3];
u8 gl4iack;
u8 resv5[0x3];
u8 gl5iack;
u8 resv6[0x3];
u8 gl6iack;
u8 resv7[0x3];
u8 gl7iack;
} iack_t;
/* Edge Port Module (EPORT) */
typedef struct eport {
u16 eppar;
u8 epddr;
u8 epier;
u8 epdr;
u8 eppdr;
u8 epfr;
} eport_t;
/* Watchdog Timer Modules (WTM) */
typedef struct wtm {
u16 wcr;
@ -387,14 +241,6 @@ typedef struct gpio {
u8 dscr_ata; /* ATA Drive Strength Control Register */
} gpio_t;
/* Random Number Generator (RNG) */
typedef struct rng {
u32 rngcr;
u32 rngsr;
u32 rnger;
u32 rngout;
} rng_t;
/* SDRAM Controller (SDRAMC) */
typedef struct sdramc {
u32 sdmr; /* SDRAM Mode/Extended Mode Register */

40
include/asm-m68k/immap_547x_8x.h
View File

@ -57,7 +57,11 @@
#define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001FF00)
#define MMAP_SEC (CONFIG_SYS_MBAR + 0x00020000)
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
typedef struct siu {
u32 mbar; /* 0x00 */
@ -98,37 +102,6 @@ typedef struct xlb_arb {
u32 pri; /* 0x268 */
} xlbarb_t;
typedef struct int0_ctrl {
u32 iprh0; /* 0x00 */
u32 iprl0; /* 0x04 */
u32 imrh0; /* 0x08 */
u32 imrl0; /* 0x0C */
u32 frch0; /* 0x10 */
u32 frcl0; /* 0x14 */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1; /* 0x1A - 0x1B */
u32 res2[9]; /* 0x1C - 0x3F */
u8 icr0[64]; /* 0x40 - 0x7F */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct gptmr {
u8 ocpw;
u8 octict;
@ -147,6 +120,11 @@ typedef struct gptmr {
u8 intr; /* Interrupts */
} gptmr_t;
typedef struct canex_ctrl {
can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
} canex_t;
typedef struct slt {
u32 tcnt; /* 0x00 */
u32 cr; /* 0x04 */

233
include/asm-m68k/m5227x.h
View File

@ -26,9 +26,7 @@
#ifndef __MCF5227X__
#define __MCF5227X__
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
/* Interrupt Controller (INTC) */
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT4 (4)
@ -98,235 +96,6 @@
#define INT1_HI_TOUCH_ADC (61)
#define INT1_HI_PLL_LOCKS (62)
/* Bit definitions and macros for IPRH */
#define INTC_IPRH_INT32 (0x00000001)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT63 (0x80000000)
/* Bit definitions and macros for IPRL */
#define INTC_IPRL_INT0 (0x00000001)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT31 (0x80000000)
/* Bit definitions and macros for IMRH */
#define INTC_IMRH_INT_MASK32 (0x00000001)
#define INTC_IMRH_INT_MASK33 (0x00000002)
#define INTC_IMRH_INT_MASK34 (0x00000004)
#define INTC_IMRH_INT_MASK35 (0x00000008)
#define INTC_IMRH_INT_MASK36 (0x00000010)
#define INTC_IMRH_INT_MASK37 (0x00000020)
#define INTC_IMRH_INT_MASK38 (0x00000040)
#define INTC_IMRH_INT_MASK39 (0x00000080)
#define INTC_IMRH_INT_MASK40 (0x00000100)
#define INTC_IMRH_INT_MASK41 (0x00000200)
#define INTC_IMRH_INT_MASK42 (0x00000400)
#define INTC_IMRH_INT_MASK43 (0x00000800)
#define INTC_IMRH_INT_MASK44 (0x00001000)
#define INTC_IMRH_INT_MASK45 (0x00002000)
#define INTC_IMRH_INT_MASK46 (0x00004000)
#define INTC_IMRH_INT_MASK47 (0x00008000)
#define INTC_IMRH_INT_MASK48 (0x00010000)
#define INTC_IMRH_INT_MASK49 (0x00020000)
#define INTC_IMRH_INT_MASK50 (0x00040000)
#define INTC_IMRH_INT_MASK51 (0x00080000)
#define INTC_IMRH_INT_MASK52 (0x00100000)
#define INTC_IMRH_INT_MASK53 (0x00200000)
#define INTC_IMRH_INT_MASK54 (0x00400000)
#define INTC_IMRH_INT_MASK55 (0x00800000)
#define INTC_IMRH_INT_MASK56 (0x01000000)
#define INTC_IMRH_INT_MASK57 (0x02000000)
#define INTC_IMRH_INT_MASK58 (0x04000000)
#define INTC_IMRH_INT_MASK59 (0x08000000)
#define INTC_IMRH_INT_MASK60 (0x10000000)
#define INTC_IMRH_INT_MASK61 (0x20000000)
#define INTC_IMRH_INT_MASK62 (0x40000000)
#define INTC_IMRH_INT_MASK63 (0x80000000)
/* Bit definitions and macros for IMRL */
#define INTC_IMRL_INT_MASK0 (0x00000001)
#define INTC_IMRL_INT_MASK1 (0x00000002)
#define INTC_IMRL_INT_MASK2 (0x00000004)
#define INTC_IMRL_INT_MASK3 (0x00000008)
#define INTC_IMRL_INT_MASK4 (0x00000010)
#define INTC_IMRL_INT_MASK5 (0x00000020)
#define INTC_IMRL_INT_MASK6 (0x00000040)
#define INTC_IMRL_INT_MASK7 (0x00000080)
#define INTC_IMRL_INT_MASK8 (0x00000100)
#define INTC_IMRL_INT_MASK9 (0x00000200)
#define INTC_IMRL_INT_MASK10 (0x00000400)
#define INTC_IMRL_INT_MASK11 (0x00000800)
#define INTC_IMRL_INT_MASK12 (0x00001000)
#define INTC_IMRL_INT_MASK13 (0x00002000)
#define INTC_IMRL_INT_MASK14 (0x00004000)
#define INTC_IMRL_INT_MASK15 (0x00008000)
#define INTC_IMRL_INT_MASK16 (0x00010000)
#define INTC_IMRL_INT_MASK17 (0x00020000)
#define INTC_IMRL_INT_MASK18 (0x00040000)
#define INTC_IMRL_INT_MASK19 (0x00080000)
#define INTC_IMRL_INT_MASK20 (0x00100000)
#define INTC_IMRL_INT_MASK21 (0x00200000)
#define INTC_IMRL_INT_MASK22 (0x00400000)
#define INTC_IMRL_INT_MASK23 (0x00800000)
#define INTC_IMRL_INT_MASK24 (0x01000000)
#define INTC_IMRL_INT_MASK25 (0x02000000)
#define INTC_IMRL_INT_MASK26 (0x04000000)
#define INTC_IMRL_INT_MASK27 (0x08000000)
#define INTC_IMRL_INT_MASK28 (0x10000000)
#define INTC_IMRL_INT_MASK29 (0x20000000)
#define INTC_IMRL_INT_MASK30 (0x40000000)
#define INTC_IMRL_INT_MASK31 (0x80000000)
/* Bit definitions and macros for INTFRCH */
#define INTC_INTFRCH_INTFRC32 (0x00000001)
#define INTC_INTFRCH_INTFRC33 (0x00000002)
#define INTC_INTFRCH_INTFRC34 (0x00000004)
#define INTC_INTFRCH_INTFRC35 (0x00000008)
#define INTC_INTFRCH_INTFRC36 (0x00000010)
#define INTC_INTFRCH_INTFRC37 (0x00000020)
#define INTC_INTFRCH_INTFRC38 (0x00000040)
#define INTC_INTFRCH_INTFRC39 (0x00000080)
#define INTC_INTFRCH_INTFRC40 (0x00000100)
#define INTC_INTFRCH_INTFRC41 (0x00000200)
#define INTC_INTFRCH_INTFRC42 (0x00000400)
#define INTC_INTFRCH_INTFRC43 (0x00000800)
#define INTC_INTFRCH_INTFRC44 (0x00001000)
#define INTC_INTFRCH_INTFRC45 (0x00002000)
#define INTC_INTFRCH_INTFRC46 (0x00004000)
#define INTC_INTFRCH_INTFRC47 (0x00008000)
#define INTC_INTFRCH_INTFRC48 (0x00010000)
#define INTC_INTFRCH_INTFRC49 (0x00020000)
#define INTC_INTFRCH_INTFRC50 (0x00040000)
#define INTC_INTFRCH_INTFRC51 (0x00080000)
#define INTC_INTFRCH_INTFRC52 (0x00100000)
#define INTC_INTFRCH_INTFRC53 (0x00200000)
#define INTC_INTFRCH_INTFRC54 (0x00400000)
#define INTC_INTFRCH_INTFRC55 (0x00800000)
#define INTC_INTFRCH_INTFRC56 (0x01000000)
#define INTC_INTFRCH_INTFRC57 (0x02000000)
#define INTC_INTFRCH_INTFRC58 (0x04000000)
#define INTC_INTFRCH_INTFRC59 (0x08000000)
#define INTC_INTFRCH_INTFRC60 (0x10000000)
#define INTC_INTFRCH_INTFRC61 (0x20000000)
#define INTC_INTFRCH_INTFRC62 (0x40000000)
#define INTC_INTFRCH_INTFRC63 (0x80000000)
/* Bit definitions and macros for INTFRCL */
#define INTC_INTFRCL_INTFRC0 (0x00000001)
#define INTC_INTFRCL_INTFRC1 (0x00000002)
#define INTC_INTFRCL_INTFRC2 (0x00000004)
#define INTC_INTFRCL_INTFRC3 (0x00000008)
#define INTC_INTFRCL_INTFRC4 (0x00000010)
#define INTC_INTFRCL_INTFRC5 (0x00000020)
#define INTC_INTFRCL_INTFRC6 (0x00000040)
#define INTC_INTFRCL_INTFRC7 (0x00000080)
#define INTC_INTFRCL_INTFRC8 (0x00000100)
#define INTC_INTFRCL_INTFRC9 (0x00000200)
#define INTC_INTFRCL_INTFRC10 (0x00000400)
#define INTC_INTFRCL_INTFRC11 (0x00000800)
#define INTC_INTFRCL_INTFRC12 (0x00001000)
#define INTC_INTFRCL_INTFRC13 (0x00002000)
#define INTC_INTFRCL_INTFRC14 (0x00004000)
#define INTC_INTFRCL_INTFRC15 (0x00008000)
#define INTC_INTFRCL_INTFRC16 (0x00010000)
#define INTC_INTFRCL_INTFRC17 (0x00020000)
#define INTC_INTFRCL_INTFRC18 (0x00040000)
#define INTC_INTFRCL_INTFRC19 (0x00080000)
#define INTC_INTFRCL_INTFRC20 (0x00100000)
#define INTC_INTFRCL_INTFRC21 (0x00200000)
#define INTC_INTFRCL_INTFRC22 (0x00400000)
#define INTC_INTFRCL_INTFRC23 (0x00800000)
#define INTC_INTFRCL_INTFRC24 (0x01000000)
#define INTC_INTFRCL_INTFRC25 (0x02000000)
#define INTC_INTFRCL_INTFRC26 (0x04000000)
#define INTC_INTFRCL_INTFRC27 (0x08000000)
#define INTC_INTFRCL_INTFRC28 (0x10000000)
#define INTC_INTFRCL_INTFRC29 (0x20000000)
#define INTC_INTFRCL_INTFRC30 (0x40000000)
#define INTC_INTFRCL_INTFRC31 (0x80000000)
/* Bit definitions and macros for ICONFIG */
#define INTC_ICONFIG_EMASK (0x0020)
#define INTC_ICONFIG_ELVLPRI1 (0x0200)
#define INTC_ICONFIG_ELVLPRI2 (0x0400)
#define INTC_ICONFIG_ELVLPRI3 (0x0800)
#define INTC_ICONFIG_ELVLPRI4 (0x1000)
#define INTC_ICONFIG_ELVLPRI5 (0x2000)
#define INTC_ICONFIG_ELVLPRI6 (0x4000)
#define INTC_ICONFIG_ELVLPRI7 (0x8000)
/* Bit definitions and macros for SIMR */
#define INTC_SIMR_SIMR(x) (((x)&0x7F))
/* Bit definitions and macros for CIMR */
#define INTC_CIMR_CIMR(x) (((x)&0x7F))
/* Bit definitions and macros for CLMASK */
#define INTC_CLMASK_CLMASK(x) (((x)&0x0F))
/* Bit definitions and macros for SLMASK */
#define INTC_SLMASK_SLMASK(x) (((x)&0x0F))
/* Bit definitions and macros for ICR group */
#define INTC_ICR_IL(x) (((x)&0x07))
/*********************************************************************
* Reset Controller Module (RCM)
*********************************************************************/

303
include/asm-m68k/m5235.h
View File

@ -162,94 +162,6 @@
#define SDRAMC_DMRn_WP (0x00000100)
#define SDRAMC_DMRn_V (0x00000001)
/*********************************************************************
* FlexBus Chip Selects (FBCS)
*********************************************************************/
/* Bit definitions and macros for FBCS_CSMR */
#define FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<16)
#define FBCS_CSMR_BAM_4G (0xFFFF0000)
#define FBCS_CSMR_BAM_2G (0x7FFF0000)
#define FBCS_CSMR_BAM_1G (0x3FFF0000)
#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
#define FBCS_CSMR_BAM_512M (0x1FFF0000)
#define FBCS_CSMR_BAM_256M (0x0FFF0000)
#define FBCS_CSMR_BAM_128M (0x07FF0000)
#define FBCS_CSMR_BAM_64M (0x03FF0000)
#define FBCS_CSMR_BAM_32M (0x01FF0000)
#define FBCS_CSMR_BAM_16M (0x00FF0000)
#define FBCS_CSMR_BAM_8M (0x007F0000)
#define FBCS_CSMR_BAM_4M (0x003F0000)
#define FBCS_CSMR_BAM_2M (0x001F0000)
#define FBCS_CSMR_BAM_1M (0x000F0000)
#define FBCS_CSMR_BAM_1024K (0x000F0000)
#define FBCS_CSMR_BAM_512K (0x00070000)
#define FBCS_CSMR_BAM_256K (0x00030000)
#define FBCS_CSMR_BAM_128K (0x00010000)
#define FBCS_CSMR_BAM_64K (0x00000000)
#define FBCS_CSMR_WP (0x00000100)
#define FBCS_CSMR_V (0x00000001)
/* Bit definitions and macros for FBCS_CSCR */
#define FBCS_CSCR_SRWS(x) (((x)&0x03)<<14)
#define FBCS_CSCR_IWS(x) (((x)&0x0F)<<10)
#define FBCS_CSCR_AA (0x0100)
#define FBCS_CSCR_PS_MASK (0x00C0)
#define FBCS_CSCR_PS_32 (0x0000)
#define FBCS_CSCR_PS_16 (0x0080)
#define FBCS_CSCR_PS_8 (0x0040)
#define FBCS_CSCR_BEM (0x0020)
#define FBCS_CSCR_BSTR (0x0010)
#define FBCS_CSCR_BSTW (0x0008)
#define FBCS_CSCR_SWWS(x) ((x)&0x07)
/*********************************************************************
* Queued Serial Peripheral Interface (QSPI)
*********************************************************************/
/* Bit definitions and macros for QSPI_QMR */
#define QSPI_QMR_MSTR (0x8000)
#define QSPI_QMR_DOHIE (0x4000)
#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
#define QSPI_QMR_CPOL (0x0200)
#define QSPI_QMR_CPHA (0x0100)
#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
/* Bit definitions and macros for QSPI_QDLYR */
#define QSPI_QDLYR_SPE (0x8000)
#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
/* Bit definitions and macros for QSPI_QWR */
#define QSPI_QWR_HALT (0x8000)
#define QSPI_QWR_WREN (0x4000)
#define QSPI_QWR_WRTO (0x2000)
#define QSPI_QWR_CSIV (0x1000)
#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
/* Bit definitions and macros for QSPI_QIR */
#define QSPI_QIR_WCEFB (0x8000)
#define QSPI_QIR_ABRTB (0x4000)
#define QSPI_QIR_ABRTL (0x1000)
#define QSPI_QIR_WCEFE (0x0800)
#define QSPI_QIR_ABRTE (0x0400)
#define QSPI_QIR_SPIFE (0x0100)
#define QSPI_QIR_WCEF (0x0008)
#define QSPI_QIR_ABRT (0x0004)
#define QSPI_QIR_SPIF (0x0001)
/* Bit definitions and macros for QSPI_QAR */
#define QSPI_QAR_ADDR(x) ((x)&0x003F)
/* Bit definitions and macros for QSPI_QDR */
#define QSPI_QDR_CONT (0x8000)
#define QSPI_QDR_BITSE (0x4000)
#define QSPI_QDR_DT (0x2000)
#define QSPI_QDR_DSCK (0x1000)
#define QSPI_QDR_QSPI_CS3 (0x0800)
#define QSPI_QDR_QSPI_CS2 (0x0400)
#define QSPI_QDR_QSPI_CS1 (0x0200)
#define QSPI_QDR_QSPI_CS0 (0x0100)
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
@ -370,85 +282,6 @@
#define INT1_HI_ETPU_TC31F (58)
#define INT1_HI_ETPU_TGIF (59)
/* Bit definitions and macros for INTC_IPRH */
#define INTC_IPRH_INT63 (0x80000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT32 (0x00000001)
/* Bit definitions and macros for INTC_IPRL */
#define INTC_IPRL_INT31 (0x80000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT0 (0x00000001)
/* Bit definitions and macros for INTC_IRLR */
#define INTC_IRLRn(x) (((x)&0x7F)<<1)
/* Bit definitions and macros for INTC_IACKLPRn */
#define INTC_IACKLPRn_LEVEL(x) (((x)&0x07)<<4)
#define INTC_IACKLPRn_PRI(x) ((x)&0x0F)
/* Bit definitions and macros for INTC_ICRnx */
#define INTC_ICRnx_IL(x) (((x)&0x07)<<3)
#define INTC_ICRnx_IP(x) ((x)&0x07)
/*********************************************************************
* General Purpose I/O (GPIO)
*********************************************************************/
@ -757,49 +590,6 @@
#define PLL_SYNSR_CALDONE (0x00000002)
#define PLL_SYNSR_CALPASS (0x00000001)
/*********************************************************************
* Edge Port
*********************************************************************/
#define EPORT_EPPAR_EPPA7(x) (((x)&0x03)<<14)
#define EPORT_EPPAR_EPPA6(x) (((x)&0x03)<<12)
#define EPORT_EPPAR_EPPA5(x) (((x)&0x03)<<10)
#define EPORT_EPPAR_EPPA4(x) (((x)&0x03)<<8)
#define EPORT_EPPAR_EPPA3(x) (((x)&0x03)<<6)
#define EPORT_EPPAR_EPPA2(x) (((x)&0x03)<<4)
#define EPORT_EPPAR_EPPA1(x) (((x)&0x03)<<2)
#define EPORT_EPDDR_EPDD7(x) EPORT_EPPAR_EPPA7(x)
#define EPORT_EPDDR_EPDD6(x) EPORT_EPPAR_EPPA6(x)
#define EPORT_EPDDR_EPDD5(x) EPORT_EPPAR_EPPA5(x)
#define EPORT_EPDDR_EPDD4(x) EPORT_EPPAR_EPPA4(x)
#define EPORT_EPDDR_EPDD3(x) EPORT_EPPAR_EPPA3(x)
#define EPORT_EPDDR_EPDD2(x) EPORT_EPPAR_EPPA2(x)
#define EPORT_EPDDR_EPDD1(x) EPORT_EPPAR_EPPA1(x)
#define EPORT_EPIER_EPIE7 (0x80)
#define EPORT_EPIER_EPIE6 (0x40)
#define EPORT_EPIER_EPIE5 (0x20)
#define EPORT_EPIER_EPIE4 (0x10)
#define EPORT_EPIER_EPIE3 (0x08)
#define EPORT_EPIER_EPIE2 (0x04)
#define EPORT_EPIER_EPIE1 (0x02)
#define EPORT_EPDR_EPDR7 EPORT_EPIER_EPIE7
#define EPORT_EPDR_EPDR6 EPORT_EPIER_EPIE6
#define EPORT_EPDR_EPDR5 EPORT_EPIER_EPIE5
#define EPORT_EPDR_EPDR4 EPORT_EPIER_EPIE4
#define EPORT_EPDR_EPDR3 EPORT_EPIER_EPIE3
#define EPORT_EPDR_EPDR2 EPORT_EPIER_EPIE2
#define EPORT_EPDR_EPDR1 EPORT_EPIER_EPIE1
#define EPORT_EPPDR_EPPDR7 EPORT_EPIER_EPIE7
#define EPORT_EPPDR_EPPDR6 EPORT_EPIER_EPIE6
#define EPORT_EPPDR_EPPDR5 EPORT_EPIER_EPIE5
#define EPORT_EPPDR_EPPDR4 EPORT_EPIER_EPIE4
#define EPORT_EPPDR_EPPDR3 EPORT_EPIER_EPIE3
#define EPORT_EPPDR_EPPDR2 EPORT_EPIER_EPIE2
#define EPORT_EPPDR_EPPDR1 EPORT_EPIER_EPIE1
/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/
@ -809,97 +599,4 @@
#define WTM_WCR_HALTED (0x0002)
#define WTM_WCR_EN (0x0001)
/*********************************************************************
* FlexCAN Module (CAN)
*********************************************************************/
/* Bit definitions and macros for CAN_CANMCR */
#define CANMCR_MDIS (0x80000000)
#define CANMCR_FRZ (0x40000000)
#define CANMCR_HALT (0x10000000)
#define CANMCR_NORDY (0x08000000)
#define CANMCR_SOFTRST (0x02000000)
#define CANMCR_FRZACK (0x01000000)
#define CANMCR_SUPV (0x00800000)
#define CANMCR_LPMACK (0x00100000)
#define CANMCR_MAXMB(x) (((x)&0x0F))
/* Bit definitions and macros for CAN_CANCTRL */
#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
#define CANCTRL_RJW(x) (((x)&0x03)<<22)
#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
#define CANCTRL_BOFFMSK (0x00008000)
#define CANCTRL_ERRMSK (0x00004000)
#define CANCTRL_CLKSRC (0x00002000)
#define CANCTRL_LPB (0x00001000)
#define CANCTRL_SMP (0x00000080)
#define CANCTRL_BOFFREC (0x00000040)
#define CANCTRL_TSYNC (0x00000020)
#define CANCTRL_LBUF (0x00000010)
#define CANCTRL_LOM (0x00000008)
#define CANCTRL_PROPSEG(x) (((x)&0x07))
/* Bit definitions and macros for CAN_TIMER */
#define TIMER_TIMER(x) ((x)&0xFFFF)
/* Bit definitions and macros for CAN_RXGMASK */
#define RXGMASK_MI(x) ((x)&0x1FFFFFFF)
/* Bit definitions and macros for CAN_ERRCNT */
#define ERRCNT_TXECTR(x) (((x)&0xFF))
#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
/* Bit definitions and macros for CAN_ERRSTAT */
#define ERRSTAT_BITERR1 (0x00008000)
#define ERRSTAT_BITERR0 (0x00004000)
#define ERRSTAT_ACKERR (0x00002000)
#define ERRSTAT_CRCERR (0x00001000)
#define ERRSTAT_FRMERR (0x00000800)
#define ERRSTAT_STFERR (0x00000400)
#define ERRSTAT_TXWRN (0x00000200)
#define ERRSTAT_RXWRN (0x00000100)
#define ERRSTAT_IDLE (0x00000080)
#define ERRSTAT_TXRX (0x00000040)
#define ERRSTAT_FLT_BUSOFF (0x00000020)
#define ERRSTAT_FLT_PASSIVE (0x00000010)
#define ERRSTAT_FLT_ACTIVE (0x00000000)
#define ERRSTAT_BOFFINT (0x00000004)
#define ERRSTAT_ERRINT (0x00000002)
/* Bit definitions and macros for CAN_IMASK */
#define IMASK_BUF15M (0x00008000)
#define IMASK_BUF14M (0x00004000)
#define IMASK_BUF13M (0x00002000)
#define IMASK_BUF12M (0x00001000)
#define IMASK_BUF11M (0x00000800)
#define IMASK_BUF10M (0x00000400)
#define IMASK_BUF9M (0x00000200)
#define IMASK_BUF8M (0x00000100)
#define IMASK_BUF7M (0x00000080)
#define IMASK_BUF6M (0x00000040)
#define IMASK_BUF5M (0x00000020)
#define IMASK_BUF4M (0x00000010)
#define IMASK_BUF3M (0x00000008)
#define IMASK_BUF2M (0x00000004)
#define IMASK_BUF1M (0x00000002)
#define IMASK_BUF0M (0x00000001)
/* Bit definitions and macros for CAN_IFLAG */
#define IFLAG_BUF15I (0x00008000)
#define IFLAG_BUF14I (0x00004000)
#define IFLAG_BUF13I (0x00002000)
#define IFLAG_BUF12I (0x00001000)
#define IFLAG_BUF11I (0x00000800)
#define IFLAG_BUF10I (0x00000400)
#define IFLAG_BUF9I (0x00000200)
#define IFLAG_BUF8I (0x00000100)
#define IFLAG_BUF7I (0x00000080)
#define IFLAG_BUF6I (0x00000040)
#define IFLAG_BUF5I (0x00000020)
#define IFLAG_BUF4I (0x00000010)
#define IFLAG_BUF3I (0x00000008)
#define IFLAG_BUF2I (0x00000004)
#define IFLAG_BUF1I (0x00000002)
#define IFLAG_BUF0I (0x00000001)
#endif /* mcf5235_h */

13
include/asm-m68k/m5249.h
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@ -77,19 +77,6 @@
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */

38
include/asm-m68k/m5271.h
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@ -116,9 +116,7 @@
#define MCFSIM_ICR1 0x000C41
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
/* Interrupt Controller (INTC) */
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
@ -182,38 +180,4 @@
#define INT0_HI_CAN1_BOFFINT (60)
/* 60-63 Reserved */
/* Bit definitions and macros for INTC_IPRL */
#define INTC_IPRL_INT31 (0x80000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT0 (0x00000001)
#endif /* _MCF5271_H_ */

46
include/asm-m68k/m5275.h
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@ -30,18 +30,6 @@
* Define the 5275 SIM register set addresses. These are similar,
* but not quite identical to the 5282 registers and offsets.
*/
#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
#define MCFINTC_IRLR 0x18 /* */
#define MCFINTC_IACKL 0x19 /* */
#define MCFINTC_ICR0 0x40 /* Base ICR register */
#define MCF_GPIO_PAR_UART 0x10007c
#define UART0_ENABLE_MASK 0x000f
#define UART1_ENABLE_MASK 0x00f0
@ -198,40 +186,6 @@
#define INT1_HI_FEC1_BABR (35)
/* 36-63 Reserved */
/* Bit definitions and macros for INTC_IPRL */
#define INTC_IPRL_INT31 (0x80000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT0 (0x00000001)
/* Bit definitions and macros for RCR */
#define RCM_RCR_FRCRSTOUT (0x40)
#define RCM_RCR_SOFTRST (0x80)

23
include/asm-m68k/m5282.h
View File

@ -440,29 +440,6 @@
#define MCFWTM_WCNTR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140004))
#define MCFWTM_WSR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140006))
/* Chip SELECT Module CSM */
#define MCFCSM_CSAR0 (*(vu_short *)(CONFIG_SYS_MBAR+0x00000080))
#define MCFCSM_CSMR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000084))
#define MCFCSM_CSCR0 (*(vu_short *)(CONFIG_SYS_MBAR+0x0000008a))
#define MCFCSM_CSAR1 (*(vu_short *)(CONFIG_SYS_MBAR+0x0000008C))
#define MCFCSM_CSMR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000090))
#define MCFCSM_CSCR1 (*(vu_short *)(CONFIG_SYS_MBAR+0x00000096))
#define MCFCSM_CSAR2 (*(vu_short *)(CONFIG_SYS_MBAR+0x00000098))
#define MCFCSM_CSMR2 (*(vu_long *) (CONFIG_SYS_MBAR+0x0000009C))
#define MCFCSM_CSCR2 (*(vu_short *)(CONFIG_SYS_MBAR+0x000000A2))
#define MCFCSM_CSAR3 (*(vu_short *)(CONFIG_SYS_MBAR+0x000000A4))
#define MCFCSM_CSMR3 (*(vu_long *) (CONFIG_SYS_MBAR+0x000000A8))
#define MCFCSM_CSCR3 (*(vu_short *)(CONFIG_SYS_MBAR+0x000000AE))
#define MCFCSM_CSMR_BAM(x) ((x) & 0xFFFF0000)
#define MCFCSM_CSMR_WP (1<<8)
#define MCFCSM_CSMR_V (0x01)
#define MCFCSM_CSCR_WS(x) ((x & 0x0F)<<10)
#define MCFCSM_CSCR_AA (0x0100)
#define MCFCSM_CSCR_PS_32 (0x0000)
#define MCFCSM_CSCR_PS_8 (0x0040)
#define MCFCSM_CSCR_PS_16 (0x0080)
/*********************************************************************
* General Purpose Timer (GPT) Module
*********************************************************************/

347
include/asm-m68k/m5329.h
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@ -186,65 +186,6 @@
#define CFATR_MODE (0x02)
#define CFATR_TYPE (0x01)
/*********************************************************************
* FlexBus Chip Selects (FBCS)
*********************************************************************/
/* Bit definitions and macros for FBCS_CSAR */
#define CSAR_BA(x) (((x)&0xFFFF)<<16)
/* Bit definitions and macros for FBCS_CSMR */
#define CSMR_BAM(x) (((x)&0xFFFF)<<16)
#define CSMR_BAM_4G (0xFFFF0000)
#define CSMR_BAM_2G (0x7FFF0000)
#define CSMR_BAM_1G (0x3FFF0000)
#define CSMR_BAM_1024M (0x3FFF0000)
#define CSMR_BAM_512M (0x1FFF0000)
#define CSMR_BAM_256M (0x0FFF0000)
#define CSMR_BAM_128M (0x07FF0000)
#define CSMR_BAM_64M (0x03FF0000)
#define CSMR_BAM_32M (0x01FF0000)
#define CSMR_BAM_16M (0x00FF0000)
#define CSMR_BAM_8M (0x007F0000)
#define CSMR_BAM_4M (0x003F0000)
#define CSMR_BAM_2M (0x001F0000)
#define CSMR_BAM_1M (0x000F0000)
#define CSMR_BAM_1024K (0x000F0000)
#define CSMR_BAM_512K (0x00070000)
#define CSMR_BAM_256K (0x00030000)
#define CSMR_BAM_128K (0x00010000)
#define CSMR_BAM_64K (0x00000000)
#define CSMR_WP (0x00000100)
#define CSMR_V (0x00000001)
/* Bit definitions and macros for FBCS_CSCR */
#define CSCR_SWS(x) (((x)&0x3F)<<26)
#define CSCR_ASET(x) (((x)&0x03)<<20)
#define CSCR_SWSEN (0x00800000)
#define CSCR_ASET_4CLK (0x00300000)
#define CSCR_ASET_3CLK (0x00200000)
#define CSCR_ASET_2CLK (0x00100000)
#define CSCR_ASET_1CLK (0x00000000)
#define CSCR_RDAH(x) (((x)&0x03)<<18)
#define CSCR_RDAH_4CYC (0x000C0000)
#define CSCR_RDAH_3CYC (0x00080000)
#define CSCR_RDAH_2CYC (0x00040000)
#define CSCR_RDAH_1CYC (0x00000000)
#define CSCR_WRAH(x) (((x)&0x03)<<16)
#define CSCR_WDAH_4CYC (0x00003000)
#define CSCR_WDAH_3CYC (0x00002000)
#define CSCR_WDAH_2CYC (0x00001000)
#define CSCR_WDAH_1CYC (0x00000000)
#define CSCR_WS(x) (((x)&0x3F)<<10)
#define CSCR_SBM (0x00000200)
#define CSCR_AA (0x00000100)
#define CSCR_PS_MASK (0x000000C0)
#define CSCR_PS_32 (0x00000000)
#define CSCR_PS_16 (0x00000080)
#define CSCR_PS_8 (0x00000040)
#define CSCR_BEM (0x00000020)
#define CSCR_BSTR (0x00000010)
#define CSCR_BSTW (0x00000008)
/*********************************************************************
* Reset Controller Module (RCM)
*********************************************************************/
@ -260,100 +201,6 @@
#define RCM_RSR_POR (0x08)
#define RCM_RSR_SOFT (0x20)
/*********************************************************************
* FlexCAN Module (CAN)
*********************************************************************/
/* Bit definitions and macros for CAN_CANMCR */
#define CANMCR_MDIS (0x80000000)
#define CANMCR_FRZ (0x40000000)
#define CANMCR_HALT (0x10000000)
#define CANMCR_NORDY (0x08000000)
#define CANMCR_SOFTRST (0x02000000)
#define CANMCR_FRZACK (0x01000000)
#define CANMCR_SUPV (0x00800000)
#define CANMCR_LPMACK (0x00100000)
#define CANMCR_MAXMB(x) (((x)&0x0F))
/* Bit definitions and macros for CAN_CANCTRL */
#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
#define CANCTRL_RJW(x) (((x)&0x03)<<22)
#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
#define CANCTRL_BOFFMSK (0x00008000)
#define CANCTRL_ERRMSK (0x00004000)
#define CANCTRL_CLKSRC (0x00002000)
#define CANCTRL_LPB (0x00001000)
#define CANCTRL_SMP (0x00000080)
#define CANCTRL_BOFFREC (0x00000040)
#define CANCTRL_TSYNC (0x00000020)
#define CANCTRL_LBUF (0x00000010)
#define CANCTRL_LOM (0x00000008)
#define CANCTRL_PROPSEG(x) (((x)&0x07))
/* Bit definitions and macros for CAN_TIMER */
#define TIMER_TIMER(x) ((x)&0xFFFF)
/* Bit definitions and macros for CAN_RXGMASK */
#define RXGMASK_MI(x) ((x)&0x1FFFFFFF)
/* Bit definitions and macros for CAN_ERRCNT */
#define ERRCNT_TXECTR(x) (((x)&0xFF))
#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
/* Bit definitions and macros for CAN_ERRSTAT */
#define ERRSTAT_BITERR1 (0x00008000)
#define ERRSTAT_BITERR0 (0x00004000)
#define ERRSTAT_ACKERR (0x00002000)
#define ERRSTAT_CRCERR (0x00001000)
#define ERRSTAT_FRMERR (0x00000800)
#define ERRSTAT_STFERR (0x00000400)
#define ERRSTAT_TXWRN (0x00000200)
#define ERRSTAT_RXWRN (0x00000100)
#define ERRSTAT_IDLE (0x00000080)
#define ERRSTAT_TXRX (0x00000040)
#define ERRSTAT_FLT_BUSOFF (0x00000020)
#define ERRSTAT_FLT_PASSIVE (0x00000010)
#define ERRSTAT_FLT_ACTIVE (0x00000000)
#define ERRSTAT_BOFFINT (0x00000004)
#define ERRSTAT_ERRINT (0x00000002)
#define ERRSTAT_WAKINT (0x00000001)
/* Bit definitions and macros for CAN_IMASK */
#define IMASK_BUF15M (0x00008000)
#define IMASK_BUF14M (0x00004000)
#define IMASK_BUF13M (0x00002000)
#define IMASK_BUF12M (0x00001000)
#define IMASK_BUF11M (0x00000800)
#define IMASK_BUF10M (0x00000400)
#define IMASK_BUF9M (0x00000200)
#define IMASK_BUF8M (0x00000100)
#define IMASK_BUF7M (0x00000080)
#define IMASK_BUF6M (0x00000040)
#define IMASK_BUF5M (0x00000020)
#define IMASK_BUF4M (0x00000010)
#define IMASK_BUF3M (0x00000008)
#define IMASK_BUF2M (0x00000004)
#define IMASK_BUF1M (0x00000002)
#define IMASK_BUF0M (0x00000001)
/* Bit definitions and macros for CAN_IFLAG */
#define IFLAG_BUF15I (0x00008000)
#define IFLAG_BUF14I (0x00004000)
#define IFLAG_BUF13I (0x00002000)
#define IFLAG_BUF12I (0x00001000)
#define IFLAG_BUF11I (0x00000800)
#define IFLAG_BUF10I (0x00000400)
#define IFLAG_BUF9I (0x00000200)
#define IFLAG_BUF8I (0x00000100)
#define IFLAG_BUF7I (0x00000080)
#define IFLAG_BUF6I (0x00000040)
#define IFLAG_BUF5I (0x00000020)
#define IFLAG_BUF4I (0x00000010)
#define IFLAG_BUF3I (0x00000008)
#define IFLAG_BUF2I (0x00000004)
#define IFLAG_BUF1I (0x00000002)
#define IFLAG_BUF0I (0x00000001)
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
@ -411,200 +258,6 @@
/* 49 - 61 Reserved */
#define INT0_HI_SCM (62)
/* Bit definitions and macros for INTC_IPRH */
#define INTC_IPRH_INT63 (0x80000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT32 (0x00000001)
/* Bit definitions and macros for INTC_IPRL */
#define INTC_IPRL_INT31 (0x80000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT0 (0x00000001)
/* Bit definitions and macros for INTC_ICONFIG */
#define INTC_ICFG_ELVLPRI7 (0x8000)
#define INTC_ICFG_ELVLPRI6 (0x4000)
#define INTC_ICFG_ELVLPRI5 (0x2000)
#define INTC_ICFG_ELVLPRI4 (0x1000)
#define INTC_ICFG_ELVLPRI3 (0x0800)
#define INTC_ICFG_ELVLPRI2 (0x0400)
#define INTC_ICFG_ELVLPRI1 (0x0200)
#define INTC_ICFG_EMASK (0x0020)
/* Bit definitions and macros for INTC_SIMR */
#define INTC_SIMR_SALL (0x40)
#define INTC_SIMR_SIMR(x) ((x)&0x3F)
/* Bit definitions and macros for INTC_CIMR */
#define INTC_CIMR_CALL (0x40)
#define INTC_CIMR_CIMR(x) ((x)&0x3F)
/* Bit definitions and macros for INTC_CLMASK */
#define INTC_CLMASK_CLMASK(x) ((x)&0x0F)
/* Bit definitions and macros for INTC_SLMASK */
#define INTC_SLMASK_SLMASK(x) ((x)&0x0F)
/* Bit definitions and macros for INTC_ICR */
#define INTC_ICR_IL(x) ((x)&0x07)
/*********************************************************************
* Queued Serial Peripheral Interface (QSPI)
*********************************************************************/
/* Bit definitions and macros for QSPI_QMR */
#define QSPI_QMR_MSTR (0x8000)
#define QSPI_QMR_DOHIE (0x4000)
#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
#define QSPI_QMR_CPOL (0x0200)
#define QSPI_QMR_CPHA (0x0100)
#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
/* Bit definitions and macros for QSPI_QDLYR */
#define QSPI_QDLYR_SPE (0x8000)
#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
/* Bit definitions and macros for QSPI_QWR */
#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
#define QSPI_QWR_CSIV (0x1000)
#define QSPI_QWR_WRTO (0x2000)
#define QSPI_QWR_WREN (0x4000)
#define QSPI_QWR_HALT (0x8000)
/* Bit definitions and macros for QSPI_QIR */
#define QSPI_QIR_WCEFB (0x8000)
#define QSPI_QIR_ABRTB (0x4000)
#define QSPI_QIR_ABRTL (0x1000)
#define QSPI_QIR_WCEFE (0x0800)
#define QSPI_QIR_ABRTE (0x0400)
#define QSPI_QIR_SPIFE (0x0100)
#define QSPI_QIR_WCEF (0x0008)
#define QSPI_QIR_ABRT (0x0004)
#define QSPI_QIR_SPIF (0x0001)
/* Bit definitions and macros for QSPI_QAR */
#define QSPI_QAR_ADDR(x) ((x)&0x003F)
#define QSPI_QAR_TRANS (0x0000)
#define QSPI_QAR_RECV (0x0010)
#define QSPI_QAR_CMD (0x0020)
/* Bit definitions and macros for QSPI_QDR */
#define QSPI_QDR_CONT (0x8000)
#define QSPI_QDR_BITSE (0x4000)
#define QSPI_QDR_DT (0x2000)
#define QSPI_QDR_DSCK (0x1000)
#define QSPI_QDR_QSPI_CS3 (0x0800)
#define QSPI_QDR_QSPI_CS2 (0x0400)
#define QSPI_QDR_QSPI_CS1 (0x0200)
#define QSPI_QDR_QSPI_CS0 (0x0100)
/*********************************************************************
* Pulse Width Modulation (PWM)
*********************************************************************/
/* Bit definitions and macros for PWM_E */
#define PWM_EN_PWME7 (0x80)
#define PWM_EN_PWME5 (0x20)
#define PWM_EN_PWME3 (0x08)
#define PWM_EN_PWME1 (0x02)
/* Bit definitions and macros for PWM_POL */
#define PWM_POL_PPOL7 (0x80)
#define PWM_POL_PPOL5 (0x20)
#define PWM_POL_PPOL3 (0x08)
#define PWM_POL_PPOL1 (0x02)
/* Bit definitions and macros for PWM_CLK */
#define PWM_CLK_PCLK7 (0x80)
#define PWM_CLK_PCLK5 (0x20)
#define PWM_CLK_PCLK3 (0x08)
#define PWM_CLK_PCLK1 (0x02)
/* Bit definitions and macros for PWM_PRCLK */
#define PWM_PRCLK_PCKB(x) (((x)&0x07)<<4)
#define PWM_PRCLK_PCKA(x) ((x)&0x07)
/* Bit definitions and macros for PWM_CAE */
#define PWM_CAE_CAE7 (0x80)
#define PWM_CAE_CAE5 (0x20)
#define PWM_CAE_CAE3 (0x08)
#define PWM_CAE_CAE1 (0x02)
/* Bit definitions and macros for PWM_CTL */
#define PWM_CTL_CON67 (0x80)
#define PWM_CTL_CON45 (0x40)
#define PWM_CTL_CON23 (0x20)
#define PWM_CTL_CON01 (0x10)
#define PWM_CTL_PSWAR (0x08)
#define PWM_CTL_PFRZ (0x04)
/* Bit definitions and macros for PWM_SDN */
#define PWM_SDN_IF (0x80)
#define PWM_SDN_IE (0x40)
#define PWM_SDN_RESTART (0x20)
#define PWM_SDN_LVL (0x10)
#define PWM_SDN_PWM7IN (0x04)
#define PWM_SDN_PWM7IL (0x02)
#define PWM_SDN_SDNEN (0x01)
/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/

337
include/asm-m68k/m5445x.h
View File

@ -114,325 +114,6 @@
#define INT1_HI_PCI_ASR (56)
#define INT1_HI_PLL_LOCKS (57)
/* Bit definitions and macros for IPRH */
#define INTC_IPRH_INT32 (0x00000001)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT63 (0x80000000)
/* Bit definitions and macros for IPRL */
#define INTC_IPRL_INT0 (0x00000001)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT31 (0x80000000)
/* Bit definitions and macros for IMRH */
#define INTC_IMRH_INT_MASK32 (0x00000001)
#define INTC_IMRH_INT_MASK33 (0x00000002)
#define INTC_IMRH_INT_MASK34 (0x00000004)
#define INTC_IMRH_INT_MASK35 (0x00000008)
#define INTC_IMRH_INT_MASK36 (0x00000010)
#define INTC_IMRH_INT_MASK37 (0x00000020)
#define INTC_IMRH_INT_MASK38 (0x00000040)
#define INTC_IMRH_INT_MASK39 (0x00000080)
#define INTC_IMRH_INT_MASK40 (0x00000100)
#define INTC_IMRH_INT_MASK41 (0x00000200)
#define INTC_IMRH_INT_MASK42 (0x00000400)
#define INTC_IMRH_INT_MASK43 (0x00000800)
#define INTC_IMRH_INT_MASK44 (0x00001000)
#define INTC_IMRH_INT_MASK45 (0x00002000)
#define INTC_IMRH_INT_MASK46 (0x00004000)
#define INTC_IMRH_INT_MASK47 (0x00008000)
#define INTC_IMRH_INT_MASK48 (0x00010000)
#define INTC_IMRH_INT_MASK49 (0x00020000)
#define INTC_IMRH_INT_MASK50 (0x00040000)
#define INTC_IMRH_INT_MASK51 (0x00080000)
#define INTC_IMRH_INT_MASK52 (0x00100000)
#define INTC_IMRH_INT_MASK53 (0x00200000)
#define INTC_IMRH_INT_MASK54 (0x00400000)
#define INTC_IMRH_INT_MASK55 (0x00800000)
#define INTC_IMRH_INT_MASK56 (0x01000000)
#define INTC_IMRH_INT_MASK57 (0x02000000)
#define INTC_IMRH_INT_MASK58 (0x04000000)
#define INTC_IMRH_INT_MASK59 (0x08000000)
#define INTC_IMRH_INT_MASK60 (0x10000000)
#define INTC_IMRH_INT_MASK61 (0x20000000)
#define INTC_IMRH_INT_MASK62 (0x40000000)
#define INTC_IMRH_INT_MASK63 (0x80000000)
/* Bit definitions and macros for IMRL */
#define INTC_IMRL_INT_MASK0 (0x00000001)
#define INTC_IMRL_INT_MASK1 (0x00000002)
#define INTC_IMRL_INT_MASK2 (0x00000004)
#define INTC_IMRL_INT_MASK3 (0x00000008)
#define INTC_IMRL_INT_MASK4 (0x00000010)
#define INTC_IMRL_INT_MASK5 (0x00000020)
#define INTC_IMRL_INT_MASK6 (0x00000040)
#define INTC_IMRL_INT_MASK7 (0x00000080)
#define INTC_IMRL_INT_MASK8 (0x00000100)
#define INTC_IMRL_INT_MASK9 (0x00000200)
#define INTC_IMRL_INT_MASK10 (0x00000400)
#define INTC_IMRL_INT_MASK11 (0x00000800)
#define INTC_IMRL_INT_MASK12 (0x00001000)
#define INTC_IMRL_INT_MASK13 (0x00002000)
#define INTC_IMRL_INT_MASK14 (0x00004000)
#define INTC_IMRL_INT_MASK15 (0x00008000)
#define INTC_IMRL_INT_MASK16 (0x00010000)
#define INTC_IMRL_INT_MASK17 (0x00020000)
#define INTC_IMRL_INT_MASK18 (0x00040000)
#define INTC_IMRL_INT_MASK19 (0x00080000)
#define INTC_IMRL_INT_MASK20 (0x00100000)
#define INTC_IMRL_INT_MASK21 (0x00200000)
#define INTC_IMRL_INT_MASK22 (0x00400000)
#define INTC_IMRL_INT_MASK23 (0x00800000)
#define INTC_IMRL_INT_MASK24 (0x01000000)
#define INTC_IMRL_INT_MASK25 (0x02000000)
#define INTC_IMRL_INT_MASK26 (0x04000000)
#define INTC_IMRL_INT_MASK27 (0x08000000)
#define INTC_IMRL_INT_MASK28 (0x10000000)
#define INTC_IMRL_INT_MASK29 (0x20000000)
#define INTC_IMRL_INT_MASK30 (0x40000000)
#define INTC_IMRL_INT_MASK31 (0x80000000)
/* Bit definitions and macros for INTFRCH */
#define INTC_INTFRCH_INTFRC32 (0x00000001)
#define INTC_INTFRCH_INTFRC33 (0x00000002)
#define INTC_INTFRCH_INTFRC34 (0x00000004)
#define INTC_INTFRCH_INTFRC35 (0x00000008)
#define INTC_INTFRCH_INTFRC36 (0x00000010)
#define INTC_INTFRCH_INTFRC37 (0x00000020)
#define INTC_INTFRCH_INTFRC38 (0x00000040)
#define INTC_INTFRCH_INTFRC39 (0x00000080)
#define INTC_INTFRCH_INTFRC40 (0x00000100)
#define INTC_INTFRCH_INTFRC41 (0x00000200)
#define INTC_INTFRCH_INTFRC42 (0x00000400)
#define INTC_INTFRCH_INTFRC43 (0x00000800)
#define INTC_INTFRCH_INTFRC44 (0x00001000)
#define INTC_INTFRCH_INTFRC45 (0x00002000)
#define INTC_INTFRCH_INTFRC46 (0x00004000)
#define INTC_INTFRCH_INTFRC47 (0x00008000)
#define INTC_INTFRCH_INTFRC48 (0x00010000)
#define INTC_INTFRCH_INTFRC49 (0x00020000)
#define INTC_INTFRCH_INTFRC50 (0x00040000)
#define INTC_INTFRCH_INTFRC51 (0x00080000)
#define INTC_INTFRCH_INTFRC52 (0x00100000)
#define INTC_INTFRCH_INTFRC53 (0x00200000)
#define INTC_INTFRCH_INTFRC54 (0x00400000)
#define INTC_INTFRCH_INTFRC55 (0x00800000)
#define INTC_INTFRCH_INTFRC56 (0x01000000)
#define INTC_INTFRCH_INTFRC57 (0x02000000)
#define INTC_INTFRCH_INTFRC58 (0x04000000)
#define INTC_INTFRCH_INTFRC59 (0x08000000)
#define INTC_INTFRCH_INTFRC60 (0x10000000)
#define INTC_INTFRCH_INTFRC61 (0x20000000)
#define INTC_INTFRCH_INTFRC62 (0x40000000)
#define INTC_INTFRCH_INTFRC63 (0x80000000)
/* Bit definitions and macros for INTFRCL */
#define INTC_INTFRCL_INTFRC0 (0x00000001)
#define INTC_INTFRCL_INTFRC1 (0x00000002)
#define INTC_INTFRCL_INTFRC2 (0x00000004)
#define INTC_INTFRCL_INTFRC3 (0x00000008)
#define INTC_INTFRCL_INTFRC4 (0x00000010)
#define INTC_INTFRCL_INTFRC5 (0x00000020)
#define INTC_INTFRCL_INTFRC6 (0x00000040)
#define INTC_INTFRCL_INTFRC7 (0x00000080)
#define INTC_INTFRCL_INTFRC8 (0x00000100)
#define INTC_INTFRCL_INTFRC9 (0x00000200)
#define INTC_INTFRCL_INTFRC10 (0x00000400)
#define INTC_INTFRCL_INTFRC11 (0x00000800)
#define INTC_INTFRCL_INTFRC12 (0x00001000)
#define INTC_INTFRCL_INTFRC13 (0x00002000)
#define INTC_INTFRCL_INTFRC14 (0x00004000)
#define INTC_INTFRCL_INTFRC15 (0x00008000)
#define INTC_INTFRCL_INTFRC16 (0x00010000)
#define INTC_INTFRCL_INTFRC17 (0x00020000)
#define INTC_INTFRCL_INTFRC18 (0x00040000)
#define INTC_INTFRCL_INTFRC19 (0x00080000)
#define INTC_INTFRCL_INTFRC20 (0x00100000)
#define INTC_INTFRCL_INTFRC21 (0x00200000)
#define INTC_INTFRCL_INTFRC22 (0x00400000)
#define INTC_INTFRCL_INTFRC23 (0x00800000)
#define INTC_INTFRCL_INTFRC24 (0x01000000)
#define INTC_INTFRCL_INTFRC25 (0x02000000)
#define INTC_INTFRCL_INTFRC26 (0x04000000)
#define INTC_INTFRCL_INTFRC27 (0x08000000)
#define INTC_INTFRCL_INTFRC28 (0x10000000)
#define INTC_INTFRCL_INTFRC29 (0x20000000)
#define INTC_INTFRCL_INTFRC30 (0x40000000)
#define INTC_INTFRCL_INTFRC31 (0x80000000)
/* Bit definitions and macros for ICONFIG */
#define INTC_ICONFIG_EMASK (0x0020)
#define INTC_ICONFIG_ELVLPRI1 (0x0200)
#define INTC_ICONFIG_ELVLPRI2 (0x0400)
#define INTC_ICONFIG_ELVLPRI3 (0x0800)
#define INTC_ICONFIG_ELVLPRI4 (0x1000)
#define INTC_ICONFIG_ELVLPRI5 (0x2000)
#define INTC_ICONFIG_ELVLPRI6 (0x4000)
#define INTC_ICONFIG_ELVLPRI7 (0x8000)
/* Bit definitions and macros for SIMR */
#define INTC_SIMR_SIMR(x) (((x)&0x7F))
/* Bit definitions and macros for CIMR */
#define INTC_CIMR_CIMR(x) (((x)&0x7F))
/* Bit definitions and macros for CLMASK */
#define INTC_CLMASK_CLMASK(x) (((x)&0x0F))
/* Bit definitions and macros for SLMASK */
#define INTC_SLMASK_SLMASK(x) (((x)&0x0F))
/* Bit definitions and macros for ICR group */
#define INTC_ICR_IL(x) (((x)&0x07))
/*********************************************************************
* Edge Port Module (EPORT)
*********************************************************************/
/* Bit definitions and macros for EPPAR */
#define EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
#define EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
#define EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
#define EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
#define EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
#define EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
#define EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
#define EPORT_EPPAR_LEVEL (0)
#define EPORT_EPPAR_RISING (1)
#define EPORT_EPPAR_FALLING (2)
#define EPORT_EPPAR_BOTH (3)
#define EPORT_EPPAR_EPPA7_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA7_RISING (0x4000)
#define EPORT_EPPAR_EPPA7_FALLING (0x8000)
#define EPORT_EPPAR_EPPA7_BOTH (0xC000)
#define EPORT_EPPAR_EPPA6_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA6_RISING (0x1000)
#define EPORT_EPPAR_EPPA6_FALLING (0x2000)
#define EPORT_EPPAR_EPPA6_BOTH (0x3000)
#define EPORT_EPPAR_EPPA5_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA5_RISING (0x0400)
#define EPORT_EPPAR_EPPA5_FALLING (0x0800)
#define EPORT_EPPAR_EPPA5_BOTH (0x0C00)
#define EPORT_EPPAR_EPPA4_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA4_RISING (0x0100)
#define EPORT_EPPAR_EPPA4_FALLING (0x0200)
#define EPORT_EPPAR_EPPA4_BOTH (0x0300)
#define EPORT_EPPAR_EPPA3_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA3_RISING (0x0040)
#define EPORT_EPPAR_EPPA3_FALLING (0x0080)
#define EPORT_EPPAR_EPPA3_BOTH (0x00C0)
#define EPORT_EPPAR_EPPA2_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA2_RISING (0x0010)
#define EPORT_EPPAR_EPPA2_FALLING (0x0020)
#define EPORT_EPPAR_EPPA2_BOTH (0x0030)
#define EPORT_EPPAR_EPPA1_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA1_RISING (0x0004)
#define EPORT_EPPAR_EPPA1_FALLING (0x0008)
#define EPORT_EPPAR_EPPA1_BOTH (0x000C)
/* Bit definitions and macros for EPDDR */
#define EPORT_EPDDR_EPDD1 (0x02)
#define EPORT_EPDDR_EPDD2 (0x04)
#define EPORT_EPDDR_EPDD3 (0x08)
#define EPORT_EPDDR_EPDD4 (0x10)
#define EPORT_EPDDR_EPDD5 (0x20)
#define EPORT_EPDDR_EPDD6 (0x40)
#define EPORT_EPDDR_EPDD7 (0x80)
/* Bit definitions and macros for EPIER */
#define EPORT_EPIER_EPIE1 (0x02)
#define EPORT_EPIER_EPIE2 (0x04)
#define EPORT_EPIER_EPIE3 (0x08)
#define EPORT_EPIER_EPIE4 (0x10)
#define EPORT_EPIER_EPIE5 (0x20)
#define EPORT_EPIER_EPIE6 (0x40)
#define EPORT_EPIER_EPIE7 (0x80)
/* Bit definitions and macros for EPDR */
#define EPORT_EPDR_EPD1 (0x02)
#define EPORT_EPDR_EPD2 (0x04)
#define EPORT_EPDR_EPD3 (0x08)
#define EPORT_EPDR_EPD4 (0x10)
#define EPORT_EPDR_EPD5 (0x20)
#define EPORT_EPDR_EPD6 (0x40)
#define EPORT_EPDR_EPD7 (0x80)
/* Bit definitions and macros for EPPDR */
#define EPORT_EPPDR_EPPD1 (0x02)
#define EPORT_EPPDR_EPPD2 (0x04)
#define EPORT_EPPDR_EPPD3 (0x08)
#define EPORT_EPPDR_EPPD4 (0x10)
#define EPORT_EPPDR_EPPD5 (0x20)
#define EPORT_EPPDR_EPPD6 (0x40)
#define EPORT_EPPDR_EPPD7 (0x80)
/* Bit definitions and macros for EPFR */
#define EPORT_EPFR_EPF1 (0x02)
#define EPORT_EPFR_EPF2 (0x04)
#define EPORT_EPFR_EPF3 (0x08)
#define EPORT_EPFR_EPF4 (0x10)
#define EPORT_EPFR_EPF5 (0x20)
#define EPORT_EPFR_EPF6 (0x40)
#define EPORT_EPFR_EPF7 (0x80)
/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/
@ -1039,24 +720,6 @@
#define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01)
#define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00)
/*********************************************************************
* Random Number Generator (RNG)
*********************************************************************/
/* Bit definitions and macros for RNGCR */
#define RNG_RNGCR_GO (0x00000001)
#define RNG_RNGCR_HA (0x00000002)
#define RNG_RNGCR_IM (0x00000004)
#define RNG_RNGCR_CI (0x00000008)
/* Bit definitions and macros for RNGSR */
#define RNG_RNGSR_SV (0x00000001)
#define RNG_RNGSR_LRS (0x00000002)
#define RNG_RNGSR_FUF (0x00000004)
#define RNG_RNGSR_EI (0x00000008)
#define RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8)
#define RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16)
/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/

68
include/asm-m68k/m547x_8x.h
View File

@ -305,74 +305,6 @@
#define INT0_HI_GPT1 (61)
#define INT0_HI_GPT0 (62)
/* Bit definitions and macros for IPRH */
#define INTC_IPRH_INT32 (0x00000001)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT63 (0x80000000)
/* Bit definitions and macros for IPRL */
#define INTC_IPRL_INT0 (0x00000001)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT31 (0x80000000)
/*********************************************************************
* General Purpose Timers (GPTMR)
*********************************************************************/

16
include/configs/EB+MCF-EV123.h
View File

@ -178,7 +178,7 @@
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE1
#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE1
#define CONFIG_SYS_FLASH_BASE 0xFFE00000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
@ -218,17 +218,13 @@
* Memory bank definitions
*/
#define CONFIG_SYS_CS0_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE 2*1024*1024
#define CONFIG_SYS_CS0_WIDTH 16
#define CONFIG_SYS_CS0_RO 0
#define CONFIG_SYS_CS0_WS 6
#define CONFIG_SYS_CS0_BASE 0xFFE00000
#define CONFIG_SYS_CS0_CTRL 0x00001980
#define CONFIG_SYS_CS0_MASK 0x001F0001
#define CONFIG_SYS_CS3_BASE 0xE0000000
#define CONFIG_SYS_CS3_SIZE 1*1024*1024
#define CONFIG_SYS_CS3_WIDTH 16
#define CONFIG_SYS_CS3_RO 0
#define CONFIG_SYS_CS3_WS 6
#define CONFIG_SYS_CS0_CTRL 0x00001980
#define CONFIG_SYS_CS3_MASK 0x000F0001
/*-----------------------------------------------------------------------
* Port configuration

10
include/configs/M5235EVB.h
View File

@ -215,7 +215,7 @@
# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#endif
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE << 16)
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@ -251,13 +251,13 @@
* CS7 - Available
*/
#ifdef NORFLASH_PS32BIT
# define CONFIG_SYS_CS0_BASE 0xFFC0
# define CONFIG_SYS_CS0_BASE 0xFFC00000
# define CONFIG_SYS_CS0_MASK 0x003f0001
# define CONFIG_SYS_CS0_CTRL 0x1D00
# define CONFIG_SYS_CS0_CTRL 0x00001D00
#else
# define CONFIG_SYS_CS0_BASE 0xFFE0
# define CONFIG_SYS_CS0_BASE 0xFFE00000
# define CONFIG_SYS_CS0_MASK 0x001f0001
# define CONFIG_SYS_CS0_CTRL 0x1D80
# define CONFIG_SYS_CS0_CTRL 0x00001D80
#endif
#endif /* _M5329EVB_H */

14
include/configs/M5249EVB.h
View File

@ -125,7 +125,7 @@
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CSAR0 << 16)
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
#if 0 /* test-only */
#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
@ -170,15 +170,15 @@
*/
/* CS0 - AMD Flash, address 0xffc00000 */
#define CONFIG_SYS_CSAR0 0xffe0
#define CONFIG_SYS_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */
#define CONFIG_SYS_CS0_BASE 0xffe00000
#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
#define CONFIG_SYS_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
/* CS1 - FPGA, address 0xe0000000 */
#define CONFIG_SYS_CSAR1 0xe000
#define CONFIG_SYS_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */
#define CONFIG_SYS_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
#define CONFIG_SYS_CS1_BASE 0xe0000000
#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
/*-----------------------------------------------------------------------
* Port configuration

24
include/configs/M5253DEMO.h
View File

@ -90,7 +90,7 @@
#define CONFIG_DRIVER_DM9000
#ifdef CONFIG_DRIVER_DM9000
# define CONFIG_DM9000_BASE ((CONFIG_SYS_CSAR1 << 16) | 0x300)
# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
# define DM9000_IO CONFIG_DM9000_BASE
# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
# undef CONFIG_DM9000_DEBUG
@ -202,7 +202,7 @@
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CSAR0 << 16)
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
@ -233,21 +233,13 @@
/* Port configuration */
#define CONFIG_SYS_FECI2C 0xF0
#define CONFIG_SYS_CSAR0 0xFF80
#define CONFIG_SYS_CSMR0 0x007F0021
#define CONFIG_SYS_CSCR0 0x1D80
#define CONFIG_SYS_CS0_BASE 0xFF800000
#define CONFIG_SYS_CS0_MASK 0x007F0021
#define CONFIG_SYS_CS0_CTRL 0x00001D80
#define CONFIG_SYS_CSAR1 0xE000
#define CONFIG_SYS_CSMR1 0x00000001
#define CONFIG_SYS_CSCR1 0x3DD8
#define CONFIG_SYS_CSAR2 0
#define CONFIG_SYS_CSMR2 0
#define CONFIG_SYS_CSCR2 0
#define CONFIG_SYS_CSAR3 0
#define CONFIG_SYS_CSMR3 0
#define CONFIG_SYS_CSCR3 0
#define CONFIG_SYS_CS1_BASE 0xE0000000
#define CONFIG_SYS_CS1_MASK 0x00000001
#define CONFIG_SYS_CS1_CTRL 0x00003DD8
/*-----------------------------------------------------------------------
* Port configuration

20
include/configs/M5253EVBE.h
View File

@ -166,7 +166,7 @@
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE 0xffe00000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
@ -182,21 +182,9 @@
/* Port configuration */
#define CONFIG_SYS_FECI2C 0xF0
#define CONFIG_SYS_CSAR0 0xFFE0
#define CONFIG_SYS_CSMR0 0x001F0021
#define CONFIG_SYS_CSCR0 0x1D80
#define CONFIG_SYS_CSAR1 0
#define CONFIG_SYS_CSMR1 0
#define CONFIG_SYS_CSCR1 0
#define CONFIG_SYS_CSAR2 0
#define CONFIG_SYS_CSMR2 0
#define CONFIG_SYS_CSCR2 0
#define CONFIG_SYS_CSAR3 0
#define CONFIG_SYS_CSMR3 0
#define CONFIG_SYS_CSCR3 0
#define CONFIG_SYS_CS0_BASE 0xFFE00000
#define CONFIG_SYS_CS0_MASK 0x001F0021
#define CONFIG_SYS_CS0_CTRL 0x00001D80
/*-----------------------------------------------------------------------
* Port configuration

14
include/configs/M5275EVB.h
View File

@ -173,7 +173,7 @@
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE 0xffe00000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE 0x20000
@ -211,13 +211,13 @@
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
#define CONFIG_SYS_AR0_PRELIM (CONFIG_SYS_FLASH_BASE >> 16)
#define CONFIG_SYS_CR0_PRELIM 0x1980
#define CONFIG_SYS_MR0_PRELIM 0x001F0001
#define CONFIG_SYS_CS0_BASE 0xffe00000
#define CONFIG_SYS_CS0_CTRL 0x00001980
#define CONFIG_SYS_CS0_MASK 0x001F0001
#define CONFIG_SYS_AR1_PRELIM 0x3000
#define CONFIG_SYS_CR1_PRELIM 0x1900
#define CONFIG_SYS_MR1_PRELIM 0x00070001
#define CONFIG_SYS_CS1_BASE 0x30000000
#define CONFIG_SYS_CS1_CTRL 0x00001900
#define CONFIG_SYS_CS1_MASK 0x00070001
/*-----------------------------------------------------------------------
* Port configuration

18
include/configs/M5282EVB.h
View File

@ -165,7 +165,7 @@
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE 0xffe00000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
@ -212,18 +212,10 @@
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
#define CONFIG_SYS_CS0_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE 2*1024*1024
#define CONFIG_SYS_CS0_WIDTH 16
#define CONFIG_SYS_CS0_RO 0
#define CONFIG_SYS_CS0_WS 6
/*
#define CONFIG_SYS_CS3_BASE 0xE0000000
#define CONFIG_SYS_CS3_SIZE 1*1024*1024
#define CONFIG_SYS_CS3_WIDTH 16
#define CONFIG_SYS_CS3_RO 0
#define CONFIG_SYS_CS3_WS 6
*/
#define CONFIG_SYS_CS0_BASE 0xFFE00000
#define CONFIG_SYS_CS0_CTRL 0x00001980
#define CONFIG_SYS_CS0_MASK 0x001F0001
/*-----------------------------------------------------------------------
* Port configuration
*/

14
include/configs/TASREG.h
View File

@ -206,7 +206,7 @@
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE 0xffc00000
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#if 0 /* test-only */
#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
@ -257,15 +257,15 @@
*/
/* CS0 - AMD Flash, address 0xffc00000 */
#define CONFIG_SYS_CSAR0 0xffc0
#define CONFIG_SYS_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */
#define CONFIG_SYS_CS0_BASE 0xffc00000
#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
#define CONFIG_SYS_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
/* CS1 - FPGA, address 0xe0000000 */
#define CONFIG_SYS_CSAR1 0xe000
#define CONFIG_SYS_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */
#define CONFIG_SYS_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
#define CONFIG_SYS_CS1_BASE 0xe0000000
#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
/*-----------------------------------------------------------------------
* Port configuration