2014-10-21 12:29:11 +00:00
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#include <config.h>
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include "ar7240_soc.h"
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#include "ag7240.h"
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#include "ag7240_phy.h"
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#if (CONFIG_COMMANDS & CFG_CMD_MII)
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#include <miiphy.h>
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#endif
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#define ag7240_unit2mac(_unit) ag7240_macs[(_unit)]
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#define ag7240_name2mac(name) strcmp(name,"eth0") ? ag7240_unit2mac(1) : ag7240_unit2mac(0)
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uint16_t ag7240_miiphy_read(char *devname, uint32_t phaddr,
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uint8_t reg);
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void ag7240_miiphy_write(char *devname, uint32_t phaddr,
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uint8_t reg, uint16_t data);
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ag7240_mac_t *ag7240_macs[CFG_AG7240_NMACS];
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extern void ar7240_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq);
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#ifdef CFG_ATHRS26_PHY
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extern int athrs26_phy_setup(int unit);
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extern int athrs26_phy_is_up(int unit);
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extern int athrs26_phy_is_fdx(int unit);
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extern int athrs26_phy_speed(int unit);
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extern void athrs26_reg_init(void);
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extern void athrs26_reg_init_lan(void);
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extern int athrs26_mdc_check(void);
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#endif
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#ifdef CFG_ATHRS27_PHY
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extern int athrs27_phy_setup(int unit);
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extern int athrs27_phy_is_up(int unit);
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extern int athrs27_phy_is_fdx(int unit);
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extern int athrs27_phy_speed(int unit);
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extern void athrs27_reg_init(void);
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extern void athrs27_reg_init_lan(void);
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extern int athrs27_mdc_check(void);
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#endif
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#ifdef CONFIG_F1E_PHY
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extern int athr_phy_setup(int unit);
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extern int athr_phy_is_up(int unit);
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extern int athr_phy_is_fdx(int unit);
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extern int athr_phy_speed(int unit);
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extern void athr_reg_init(void);
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#endif
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static int
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ag7240_send(struct eth_device *dev, volatile void *packet, int length)
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{
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int i;
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ag7240_mac_t *mac = (ag7240_mac_t *)dev->priv;
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ag7240_desc_t *f = mac->fifo_tx[mac->next_tx];
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f->pkt_size = length;
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f->res1 = 0;
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f->pkt_start_addr = virt_to_phys(packet);
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ag7240_tx_give_to_dma(f);
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flush_cache((u32) packet, length);
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ag7240_reg_wr(mac, AG7240_DMA_TX_DESC, virt_to_phys(f));
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ag7240_reg_wr(mac, AG7240_DMA_TX_CTRL, AG7240_TXE);
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for (i = 0; i < MAX_WAIT; i++) {
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udelay(10);
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if (!ag7240_tx_owned_by_dma(f))
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break;
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}
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if (i == MAX_WAIT)
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printf("Tx Timed out\n");
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f->pkt_start_addr = 0;
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f->pkt_size = 0;
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if (++mac->next_tx >= NO_OF_TX_FIFOS)
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mac->next_tx = 0;
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return (0);
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}
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static int ag7240_recv(struct eth_device *dev)
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{
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int length;
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ag7240_desc_t *f;
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ag7240_mac_t *mac;
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mac = (ag7240_mac_t *)dev->priv;
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for (;;) {
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f = mac->fifo_rx[mac->next_rx];
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if (ag7240_rx_owned_by_dma(f))
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break;
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length = f->pkt_size;
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NetReceive(NetRxPackets[mac->next_rx] , length - 4);
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flush_cache((u32) NetRxPackets[mac->next_rx] , PKTSIZE_ALIGN);
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ag7240_rx_give_to_dma(f);
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if (++mac->next_rx >= NO_OF_RX_FIFOS)
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mac->next_rx = 0;
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}
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if (!(ag7240_reg_rd(mac, AG7240_DMA_RX_CTRL))) {
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ag7240_reg_wr(mac, AG7240_DMA_RX_DESC, virt_to_phys(f));
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ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, 1);
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}
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return (0);
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}
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void ag7240_mii_setup(ag7240_mac_t *mac)
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{
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u32 mgmt_cfg_val;
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u32 cpu_freq,ddr_freq,ahb_freq;
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u32 check_cnt,revid_val;
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#ifdef CFG_ATHRS27_PHY
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if (is_wasp()) {
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printf("WASP ----> S27 PHY \n");
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mgmt_cfg_val = 2;
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ar7240_reg_wr(0xb8050024, 0x271); // 25MHz ref clock
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//ar7240_reg_wr(0xb8050024, 0x570); // 40MHz ref clock
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ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
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ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
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return;
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}
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#endif
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#ifdef CONFIG_AR7242_S16_PHY
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if (is_wasp()) {
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printf("WASP ----> S16 PHY *\n");
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mgmt_cfg_val = 4;
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if(mac->mac_unit == 0)
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ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
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ar7240_reg_rmw_clear(AG7240_ETH_SWITCH_CLK_SPARE, (1 << 6));
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ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
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ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
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return;
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}
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#endif
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#ifdef CONFIG_F1E_PHY
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if (is_wasp()) {
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printf("WASP ----> F1 PHY *\n");
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mgmt_cfg_val = 6;
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if(mac->mac_unit == 0)
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ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
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ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
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ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
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return;
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}
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#endif
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if ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_2) {
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mgmt_cfg_val = 0x2;
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if (mac->mac_unit == 0) {
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ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
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ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
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}
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}
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else {
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ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);
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switch (ahb_freq/1000000) {
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case 150:
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mgmt_cfg_val = 0x7;
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break;
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case 175:
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mgmt_cfg_val = 0x5;
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break;
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case 200:
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mgmt_cfg_val = 0x4;
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break;
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case 210:
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mgmt_cfg_val = 0x9;
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break;
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case 220:
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mgmt_cfg_val = 0x9;
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break;
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default:
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mgmt_cfg_val = 0x7;
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}
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if ((is_ar7241() || is_ar7242())) {
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/* External MII mode */
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if (mac->mac_unit == 0 && is_ar7242()) {
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mgmt_cfg_val = 0x6;
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ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
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ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
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ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
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}
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/* Virian */
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mgmt_cfg_val = 0x4;
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ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
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ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
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printf("Virian MDC CFG Value ==> %x\n",mgmt_cfg_val);
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}
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else if(is_ar933x()){
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//GE0 receives Rx/Tx clock, and use S26 phy
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ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_MII_GE0_SLAVE);
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mgmt_cfg_val = 0xF;
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if (mac->mac_unit == 1) {
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check_cnt = 0;
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while (check_cnt++ < 10) {
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ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
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ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
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#ifdef CFG_ATHRS26_PHY
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if(athrs26_mdc_check() == 0)
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break;
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#endif
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}
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if(check_cnt == 11)
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printf("%s: MDC check failed\n", __func__);
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}
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}
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else { /* Python 1.0 & 1.1 */
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if (mac->mac_unit == 0) {
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check_cnt = 0;
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while (check_cnt++ < 10) {
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ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
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ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
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#ifdef CFG_ATHRS26_PHY
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if(athrs26_mdc_check() == 0)
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break;
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#endif
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}
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if(check_cnt == 11)
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printf("%s: MDC check failed\n", __func__);
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}
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}
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}
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}
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static void ag7240_hw_start(ag7240_mac_t *mac)
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{
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if(mac->mac_unit)
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{
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ag7240_reg_wr(mac, AG7240_MAC_CFG1, (AG7240_MAC_CFG1_RX_EN |
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AG7240_MAC_CFG1_TX_EN));
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ag7240_reg_rmw_set(mac, AG7240_MAC_CFG2, (AG7240_MAC_CFG2_PAD_CRC_EN |
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AG7240_MAC_CFG2_LEN_CHECK | AG7240_MAC_CFG2_IF_1000));
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}
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else {
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ag7240_reg_wr(mac, AG7240_MAC_CFG1, (AG7240_MAC_CFG1_RX_EN |
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AG7240_MAC_CFG1_TX_EN));
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ag7240_reg_rmw_set(mac, AG7240_MAC_CFG2, (AG7240_MAC_CFG2_PAD_CRC_EN |
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AG7240_MAC_CFG2_LEN_CHECK | AG7240_MAC_CFG2_IF_10_100));
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}
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ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_0, 0x1f00);
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ag7240_mii_setup(mac);
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ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_1, 0x10ffff);
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ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_2, 0xAAA0555);
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ag7240_reg_rmw_set(mac, AG7240_MAC_FIFO_CFG_4, 0x3ffff);
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/*
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* Setting Drop CRC Errors, Pause Frames,Length Error frames
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* and Multi/Broad cast frames.
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*/
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#ifdef AG7240_BROADCAST_ENABLE
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ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_5, 0xe6be2);
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#else
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ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_5, 0x7eccf);
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#endif
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ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_3, 0x1f00140);
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debug(": cfg1 %#x cfg2 %#x\n", ag7240_reg_rd(mac, AG7240_MAC_CFG1),
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ag7240_reg_rd(mac, AG7240_MAC_CFG2));
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}
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static int ag7240_check_link(ag7240_mac_t *mac)
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{
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u32 link, duplex, speed, fdx;
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ag7240_phy_link(mac->mac_unit, &link);
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ag7240_phy_duplex(mac->mac_unit, &duplex);
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ag7240_phy_speed(mac->mac_unit, &speed);
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mac->link = link;
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#ifdef SUPPORT_PLC
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if(strcmp(mac->dev->name, "eth0") == 0) {
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debug("ag7240_check_link: %s link forced down\n",mac->dev->name);
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return 0;
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}
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#endif
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if(!mac->link) {
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debug("%s link down\n",mac->dev->name);
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return 0;
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}
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switch (speed)
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{
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case _1000BASET:
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ag7240_set_mac_if(mac, 1);
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ag7240_reg_rmw_set(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
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if (is_ar7242() && (mac->mac_unit == 0)) {
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ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x1c000000);
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}
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#ifdef CONFIG_F1E_PHY
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if (is_wasp() && (mac->mac_unit == 0)) {
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ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x0e000000);
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}
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#else
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if (is_wasp() && (mac->mac_unit == 0)) {
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ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x06000000);
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}
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#endif
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break;
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case _100BASET:
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ag7240_set_mac_if(mac, 0);
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ag7240_set_mac_speed(mac, 1);
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ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
|
|
|
|
if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0))
|
|
|
|
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x0101);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case _10BASET:
|
|
|
|
ag7240_set_mac_if(mac, 0);
|
|
|
|
ag7240_set_mac_speed(mac, 0);
|
|
|
|
ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
|
|
|
|
if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0))
|
|
|
|
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x1616);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
debug("Invalid speed detected\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (mac->link && (duplex == mac->duplex) && (speed == mac->speed))
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
mac->duplex = duplex;
|
|
|
|
mac->speed = speed;
|
|
|
|
|
|
|
|
debug("dup %d speed %d\n", duplex, speed);
|
|
|
|
|
|
|
|
ag7240_set_mac_duplex(mac,duplex);
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* For every command we re-setup the ring and start with clean h/w rx state
|
|
|
|
*/
|
|
|
|
static int ag7240_clean_rx(struct eth_device *dev, bd_t * bd)
|
|
|
|
{
|
|
|
|
|
|
|
|
int i;
|
|
|
|
ag7240_desc_t *fr;
|
|
|
|
ag7240_mac_t *mac = (ag7240_mac_t*)dev->priv;
|
|
|
|
|
|
|
|
if (!ag7240_check_link(mac))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
mac->next_rx = 0;
|
|
|
|
for (i = 0; i < NO_OF_RX_FIFOS; i++) {
|
|
|
|
fr = mac->fifo_rx[i];
|
|
|
|
fr->pkt_start_addr = virt_to_phys(NetRxPackets[i]);
|
|
|
|
flush_cache((u32) NetRxPackets[i], PKTSIZE_ALIGN);
|
|
|
|
ag7240_rx_give_to_dma(fr);
|
|
|
|
}
|
|
|
|
|
|
|
|
ag7240_reg_wr(mac, AG7240_DMA_RX_DESC, virt_to_phys(mac->fifo_rx[0]));
|
|
|
|
ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, AG7240_RXE); /* rx start */
|
|
|
|
if(!is_ar933x())
|
|
|
|
udelay(1000 * 1000);
|
|
|
|
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ag7240_alloc_fifo(int ndesc, ag7240_desc_t ** fifo)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
u32 size;
|
|
|
|
uchar *p = NULL;
|
|
|
|
|
|
|
|
size = sizeof(ag7240_desc_t) * ndesc;
|
|
|
|
size += CFG_CACHELINE_SIZE - 1;
|
|
|
|
|
|
|
|
if ((p = malloc(size)) == NULL) {
|
|
|
|
printf("Cant allocate fifos\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
p = (uchar *) (((u32) p + CFG_CACHELINE_SIZE - 1) &
|
|
|
|
~(CFG_CACHELINE_SIZE - 1));
|
|
|
|
p = UNCACHED_SDRAM(p);
|
|
|
|
|
|
|
|
for (i = 0; i < ndesc; i++)
|
|
|
|
fifo[i] = (ag7240_desc_t *) p + i;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ag7240_setup_fifos(ag7240_mac_t *mac)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (ag7240_alloc_fifo(NO_OF_TX_FIFOS, mac->fifo_tx))
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
for (i = 0; i < NO_OF_TX_FIFOS; i++) {
|
|
|
|
mac->fifo_tx[i]->next_desc = (i == NO_OF_TX_FIFOS - 1) ?
|
|
|
|
virt_to_phys(mac->fifo_tx[0]) : virt_to_phys(mac->fifo_tx[i + 1]);
|
|
|
|
ag7240_tx_own(mac->fifo_tx[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ag7240_alloc_fifo(NO_OF_RX_FIFOS, mac->fifo_rx))
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
for (i = 0; i < NO_OF_RX_FIFOS; i++) {
|
|
|
|
mac->fifo_rx[i]->next_desc = (i == NO_OF_RX_FIFOS - 1) ?
|
|
|
|
virt_to_phys(mac->fifo_rx[0]) : virt_to_phys(mac->fifo_rx[i + 1]);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ag7240_halt(struct eth_device *dev)
|
|
|
|
{
|
|
|
|
ag7240_mac_t *mac = (ag7240_mac_t *)dev->priv;
|
|
|
|
ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, 0);
|
|
|
|
while (ag7240_reg_rd(mac, AG7240_DMA_RX_CTRL));
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned char *
|
|
|
|
ag7240_mac_addr_loc(void)
|
|
|
|
{
|
|
|
|
extern flash_info_t flash_info[];
|
|
|
|
|
|
|
|
#ifdef BOARDCAL
|
|
|
|
/*
|
|
|
|
** BOARDCAL environmental variable has the address of the cal sector
|
|
|
|
*/
|
|
|
|
|
|
|
|
return ((unsigned char *)BOARDCAL);
|
|
|
|
|
|
|
|
#else
|
|
|
|
/* MAC address is store in the 2nd 4k of last sector */
|
|
|
|
return ((unsigned char *)
|
|
|
|
(KSEG1ADDR(AR7240_SPI_BASE) + (4 * 1024) +
|
|
|
|
flash_info[0].size - (64 * 1024) /* sector_size */ ));
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ag7240_get_ethaddr(struct eth_device *dev)
|
|
|
|
{
|
|
|
|
unsigned char *eeprom;
|
|
|
|
unsigned char *mac = dev->enetaddr;
|
|
|
|
#ifndef CONFIG_AR7240_EMU
|
|
|
|
eeprom = ag7240_mac_addr_loc();
|
|
|
|
|
|
|
|
if (strcmp(dev->name, "eth0") == 0) {
|
|
|
|
memcpy(mac, eeprom, 6);
|
|
|
|
} else if (strcmp(dev->name, "eth1") == 0) {
|
|
|
|
eeprom += 6;
|
|
|
|
memcpy(mac, eeprom, 6);
|
|
|
|
} else {
|
|
|
|
printf("%s: unknown ethernet device %s\n", __func__, dev->name);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
/* Use fixed address if the above address is invalid */
|
2015-03-10 13:46:45 +00:00
|
|
|
if ((mac[0] == 0xff) ||
|
2014-10-21 12:29:11 +00:00
|
|
|
(mac[1] == 0x00 && mac[2] == 0x00 &&
|
|
|
|
mac[3] == 0x00 && mac[4] == 0x00)) {
|
|
|
|
#else
|
|
|
|
if (1) {
|
|
|
|
#endif
|
|
|
|
mac[0] = 0x00;
|
|
|
|
mac[1] = 0x03;
|
|
|
|
mac[2] = 0x7f;
|
|
|
|
mac[3] = 0x09;
|
|
|
|
mac[4] = 0x0b;
|
|
|
|
mac[5] = 0xad;
|
|
|
|
debug("No valid address in Flash. Using fixed address\n");
|
|
|
|
} else {
|
|
|
|
debug("Fetching MAC Address from 0x%p\n", __func__, eeprom);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int ag7240_enet_initialize(bd_t * bis)
|
|
|
|
{
|
|
|
|
struct eth_device *dev[CFG_AG7240_NMACS];
|
|
|
|
u32 mask, mac_h, mac_l;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
debug("ag7240_enet_initialize...\n");
|
|
|
|
|
|
|
|
if(is_ar933x() ) {
|
|
|
|
u32 rd = 0x0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* To get s26 out of reset, we have to...
|
|
|
|
* bit0~bit3: has to be deasserted
|
|
|
|
* bit4: has to be asserted
|
|
|
|
*/
|
|
|
|
rd = ar7240_reg_rd(AR7240_S26_CLK_CTRL_OFFSET) & ~(0x1f);
|
|
|
|
rd |= 0x10;
|
|
|
|
ar7240_reg_wr(AR7240_S26_CLK_CTRL_OFFSET, rd);
|
|
|
|
|
|
|
|
if(ar7240_reg_rd(AR7240_RESET)!=0)
|
|
|
|
ar7240_reg_wr(AR7240_RESET,0);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0;i < CFG_AG7240_NMACS;i++) {
|
|
|
|
|
|
|
|
if ((dev[i] = (struct eth_device *) malloc(sizeof (struct eth_device))) == NULL) {
|
|
|
|
puts("malloc failed\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((ag7240_macs[i] = (ag7240_mac_t *) malloc(sizeof (ag7240_mac_t))) == NULL) {
|
|
|
|
puts("malloc failed\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i]));
|
|
|
|
memset(dev[i], 0, sizeof(dev[i]));
|
|
|
|
|
|
|
|
sprintf(dev[i]->name, "eth%d", i);
|
|
|
|
ag7240_get_ethaddr(dev[i]);
|
|
|
|
|
|
|
|
ag7240_macs[i]->mac_unit = i;
|
|
|
|
ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE ;
|
|
|
|
ag7240_macs[i]->dev = dev[i];
|
|
|
|
|
|
|
|
dev[i]->iobase = 0;
|
|
|
|
dev[i]->init = ag7240_clean_rx;
|
|
|
|
dev[i]->halt = ag7240_halt;
|
|
|
|
dev[i]->send = ag7240_send;
|
|
|
|
dev[i]->recv = ag7240_recv;
|
|
|
|
dev[i]->priv = (void *)ag7240_macs[i];
|
|
|
|
}
|
|
|
|
for (i = 0;i < CFG_AG7240_NMACS;i++) {
|
|
|
|
eth_register(dev[i]);
|
|
|
|
#if(CONFIG_COMMANDS & CFG_CMD_MII)
|
|
|
|
miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST
|
|
|
|
| AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST);
|
|
|
|
|
|
|
|
if(!i) {
|
|
|
|
mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE0_PHY |
|
|
|
|
AR7240_RESET_GE1_MAC | AR7240_RESET_GE1_PHY);
|
|
|
|
|
|
|
|
if (is_ar7241() || is_ar7242() || is_wasp()) {
|
|
|
|
mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO;
|
|
|
|
printf(" wasp reset mask:%x \n",mask);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
ar7240_reg_rmw_set(AR7240_RESET, mask);
|
|
|
|
if(!is_ar933x())
|
|
|
|
udelay(1000 * 100);
|
|
|
|
|
|
|
|
ar7240_reg_rmw_clear(AR7240_RESET, mask);
|
|
|
|
if(!is_ar933x())
|
|
|
|
udelay(1000 * 100);
|
|
|
|
|
|
|
|
if(!is_ar933x())
|
|
|
|
udelay(10 * 1000);
|
|
|
|
}
|
|
|
|
|
|
|
|
ag7240_hw_start(ag7240_macs[i]);
|
|
|
|
ag7240_setup_fifos(ag7240_macs[i]);
|
|
|
|
|
|
|
|
if(!is_ar933x())
|
|
|
|
udelay(100 * 1000);
|
|
|
|
|
|
|
|
{
|
|
|
|
unsigned char *mac = dev[i]->enetaddr;
|
|
|
|
|
|
|
|
debug("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev[i]->name,
|
|
|
|
mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff,
|
|
|
|
mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff);
|
|
|
|
}
|
|
|
|
mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]);
|
|
|
|
mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) |
|
|
|
|
(dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0);
|
|
|
|
|
|
|
|
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l);
|
|
|
|
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h);
|
|
|
|
|
|
|
|
/* if using header for register configuration, we have to */
|
|
|
|
/* configure s26 register after frame transmission is enabled */
|
|
|
|
|
|
|
|
if (ag7240_macs[i]->mac_unit == 0) { /* WAN Phy */
|
|
|
|
#ifdef CONFIG_AR7242_S16_PHY
|
|
|
|
if (is_ar7242() || is_wasp()) {
|
|
|
|
athrs16_reg_init();
|
|
|
|
} else
|
|
|
|
#endif
|
|
|
|
{
|
|
|
|
#ifdef CFG_ATHRS26_PHY
|
|
|
|
athrs26_reg_init();
|
|
|
|
#endif
|
|
|
|
#ifdef CFG_ATHRS27_PHY
|
|
|
|
debug("s27 reg init \n");
|
|
|
|
athrs27_reg_init();
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_F1E_PHY
|
|
|
|
debug("F1Phy reg init \n");
|
|
|
|
athr_reg_init();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
#ifdef CFG_ATHRS26_PHY
|
|
|
|
debug("athrs26_reg_init_lan\n");
|
|
|
|
athrs26_reg_init_lan();
|
|
|
|
#endif
|
|
|
|
#ifdef CFG_ATHRS27_PHY
|
|
|
|
debug("s27 reg init lan \n");
|
|
|
|
athrs27_reg_init_lan();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
ag7240_phy_setup(ag7240_macs[i]->mac_unit);
|
|
|
|
debug("%s up\n",dev[i]->name);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if (CONFIG_COMMANDS & CFG_CMD_MII)
|
|
|
|
uint16_t
|
|
|
|
ag7240_miiphy_read(char *devname, uint32_t phy_addr, uint8_t reg)
|
|
|
|
{
|
|
|
|
ag7240_mac_t *mac = ag7240_name2mac(devname);
|
|
|
|
uint16_t addr = (phy_addr << AG7240_ADDR_SHIFT) | reg, val;
|
|
|
|
volatile int rddata;
|
|
|
|
uint16_t ii = 0xFFFF;
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check for previous transactions are complete. Added to avoid
|
|
|
|
* race condition while running at higher frequencies.
|
|
|
|
*/
|
|
|
|
do
|
|
|
|
{
|
|
|
|
udelay(5);
|
|
|
|
rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;
|
|
|
|
}while(rddata && --ii);
|
|
|
|
|
|
|
|
if (ii == 0)
|
|
|
|
printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__);
|
|
|
|
|
|
|
|
|
|
|
|
ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0);
|
|
|
|
ag7240_reg_wr(mac, AG7240_MII_MGMT_ADDRESS, addr);
|
|
|
|
ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, AG7240_MGMT_CMD_READ);
|
|
|
|
|
|
|
|
do
|
|
|
|
{
|
|
|
|
udelay(5);
|
|
|
|
rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;
|
|
|
|
}while(rddata && --ii);
|
|
|
|
|
|
|
|
if(ii==0)
|
|
|
|
printf("Error!!! Leave ag7240_miiphy_read without polling correct status!\n");
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val = ag7240_reg_rd(mac, AG7240_MII_MGMT_STATUS);
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ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0);
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return val;
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}
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void
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ag7240_miiphy_write(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t data)
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|
{
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ag7240_mac_t *mac = ag7240_name2mac(devname);
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uint16_t addr = (phy_addr << AG7240_ADDR_SHIFT) | reg;
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|
|
volatile int rddata;
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|
|
|
uint16_t ii = 0xFFFF;
|
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|
|
|
|
|
|
/*
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|
|
|
* Check for previous transactions are complete. Added to avoid
|
|
|
|
* race condition while running at higher frequencies.
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|
|
|
*/
|
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|
do
|
|
|
|
{
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|
|
|
udelay(5);
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|
|
|
rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;
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|
|
}while(rddata && --ii);
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|
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|
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|
|
if (ii == 0)
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|
|
|
printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__);
|
|
|
|
|
|
|
|
ag7240_reg_wr(mac, AG7240_MII_MGMT_ADDRESS, addr);
|
|
|
|
ag7240_reg_wr(mac, AG7240_MII_MGMT_CTRL, data);
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|
|
|
|
|
|
|
do
|
|
|
|
{
|
|
|
|
rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;
|
|
|
|
}while(rddata && --ii);
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|
|
|
|
|
|
|
if(ii==0)
|
|
|
|
printf("Error!!! Leave ag7240_miiphy_write without polling correct status!\n");
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_COMMANDS & CFG_CMD_MII */
|