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In addition to a slew of minor fixes and cleanups these patches refactors how we deal with remoteprocs that will be auto-booting themselves, this in itself do clean up the remote resource handling but opens for additional work to clarify responsibilities and life cycles of resources. We also revise how module locking of remoteproc drivers work, so that they are locked as we hand out references to them to third parties, rather than only when booted by anyone. In addition to this we also introduce the Qualcomm Wireless Subsystem remoteproc driver. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJX9Xl0AAoJEAsfOT8Nma3FwsMP/R44bOoIgKPF1ph9FfGn5gHC 1mgdSDBkWQgFeWE/hiDvL9YjPUwBZz9yhxzKw9aOuG21a6/53Hx164glC7Jumwgj 39dDtge4SRqJn83PbbRxMJdjFqrtjV1E2MWQXWYG76IS5CSH6xh884cInaoQZMk/ kL8eFOCzWIrE+PcntZh1LJ4+sOrDLAxeVEDT0V6KgefRs8/Ecn0BpUQChNS2hxpf cBduZBFYhaSLcsJsu75IQRJmSG1dcVDSfdheV+CylXd0ETcuQaYgEglx9S739dvS J0sr/4LZf9vUkM8gDRZoF9ZFkR8gj2lm6d7rLFijSdK65cvjiEF4I/0FCUyadjxU SQYa+7Q9sFAXbBaDrUdI1KTjaEgudlpl+AMb220Ulko6r2NRrfmyQNGmk9htbo1A DrWqMG176pcWus/GSBPVNvuBdUvS6qsCtTZCg87W6mZvdTxaoFPYppjfpuhm6D3v 3k6m5usFh7N9gF3QVoaA775qEbOsFGp8GX+/BvxFKgThQs4OQ6DXzi9qDTOs6W2Q iW8yMtv7PEncX/u4UvF8bFRD/Gy/1vTfm8DLuT4MBWkhu7q615m50bqX0godI0s6 5pqV0TPn9M93cOrWAqpdoLouypRHsEfh8ZE+Yuji6A1I2wAqM1HeLP4gvjau99nS Mqzqw/IE4jD4/EkELEli =nREP -----END PGP SIGNATURE----- Merge tag 'rproc-v4.9' of git://github.com/andersson/remoteproc Pull remoteproc updates from Bjorn Andersson: "In addition to a slew of minor fixes and cleanups these patches refactor how we deal with remoteprocs that will be auto-booting themselves. That does clean up the remote resource handling but makes for additional work to clarify responsibilities and life cycles of resources. We also revise how module locking of remoteproc drivers work, so that they are locked as we hand out references to them to third parties, rather than only when booted by anyone. In addition to that we also introduce the Qualcomm Wireless Subsystem remoteproc driver" * tag 'rproc-v4.9' of git://github.com/andersson/remoteproc: (26 commits) remoteproc: Refactor rproc module locking remoteproc: Split driver and consumer dereferencing remoteproc: Correct resource handling upon boot failure remoteproc: Drop unnecessary NULL check remoteproc: core: transform struct fw_rsc_vdev_vring reserved field in pa remoteproc: Modify FW_RSC_ADDR_ANY definition remoteproc: qcom: wcnss: Fix return value check in wcnss_probe() remoteproc: qcom: Introduce WCNSS peripheral image loader dt-binding: remoteproc: Introduce Qualcomm WCNSS loader binding remoteproc: Only update table_ptr if we have a loaded table remoteproc: Move handling of cached table to boot/shutdown remoteproc: Move vdev handling to boot/shutdown remoteproc: Calculate max_notifyid during load remoteproc: Introduce auto-boot flag remoteproc/omap: revise a minor error trace message remoteproc/omap: fix various code formatting issues remoteproc: print hex numbers with a leading 0x format remoteproc: align code with open parenthesis remoteproc: fix bare unsigned type usage remoteproc: use variable names for sizeof() operator ...master
Linus Torvalds
5 years ago
20 changed files with 1168 additions and 205 deletions
@ -0,0 +1,132 @@ |
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Qualcomm WCNSS Peripheral Image Loader |
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|
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This document defines the binding for a component that loads and boots firmware |
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on the Qualcomm WCNSS core. |
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|
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- compatible: |
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Usage: required |
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Value type: <string> |
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Definition: must be one of: |
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"qcom,riva-pil", |
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"qcom,pronto-v1-pil", |
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"qcom,pronto-v2-pil" |
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|
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- reg: |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: must specify the base address and size of the CCU, DXE and |
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PMU register blocks |
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|
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- reg-names: |
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Usage: required |
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Value type: <stringlist> |
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Definition: must be "ccu", "dxe", "pmu" |
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|
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- interrupts-extended: |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: must list the watchdog and fatal IRQs and may specify the |
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ready, handover and stop-ack IRQs |
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|
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- interrupt-names: |
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Usage: required |
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Value type: <stringlist> |
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Definition: should be "wdog", "fatal", optionally followed by "ready", |
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"handover", "stop-ack" |
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|
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- vddmx-supply: |
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- vddcx-supply: |
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- vddpx-supply: |
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Usage: required |
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Value type: <phandle> |
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Definition: reference to the regulators to be held on behalf of the |
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booting of the WCNSS core |
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|
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- qcom,smem-states: |
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Usage: optional |
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Value type: <prop-encoded-array> |
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Definition: reference to the SMEM state used to indicate to WCNSS that |
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it should shut down |
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|
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- qcom,smem-state-names: |
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Usage: optional |
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Value type: <stringlist> |
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Definition: should be "stop" |
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|
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- memory-region: |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: reference to reserved-memory node for the remote processor |
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see ../reserved-memory/reserved-memory.txt |
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|
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= SUBNODES |
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A single subnode of the WCNSS PIL describes the attached rf module and its |
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resource dependencies. |
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|
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- compatible: |
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Usage: required |
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Value type: <string> |
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Definition: must be one of: |
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"qcom,wcn3620", |
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"qcom,wcn3660", |
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"qcom,wcn3680" |
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|
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- clocks: |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: should specify the xo clock and optionally the rf clock |
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|
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- clock-names: |
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Usage: required |
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Value type: <stringlist> |
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Definition: should be "xo", optionally followed by "rf" |
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|
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- vddxo-supply: |
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- vddrfa-supply: |
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- vddpa-supply: |
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- vdddig-supply: |
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Usage: required |
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Value type: <phandle> |
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Definition: reference to the regulators to be held on behalf of the |
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booting of the WCNSS core |
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|
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= EXAMPLE |
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The following example describes the resources needed to boot control the WCNSS, |
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with attached WCN3680, as it is commonly found on MSM8974 boards. |
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|
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pronto@fb204000 { |
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compatible = "qcom,pronto-v2-pil"; |
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reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; |
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reg-names = "ccu", "dxe", "pmu"; |
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|
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interrupts-extended = <&intc 0 149 1>, |
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<&wcnss_smp2p_slave 0 0>, |
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<&wcnss_smp2p_slave 1 0>, |
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<&wcnss_smp2p_slave 2 0>, |
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<&wcnss_smp2p_slave 3 0>; |
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interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; |
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|
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vddmx-supply = <&pm8841_s1>; |
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vddcx-supply = <&pm8841_s2>; |
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vddpx-supply = <&pm8941_s3>; |
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|
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qcom,smem-states = <&wcnss_smp2p_out 0>; |
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qcom,smem-state-names = "stop"; |
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|
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memory-region = <&wcnss_region>; |
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|
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pinctrl-names = "default"; |
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pinctrl-0 = <&wcnss_pin_a>; |
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|
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iris { |
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compatible = "qcom,wcn3680"; |
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|
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clocks = <&rpmcc RPM_CXO_CLK_SRC>, <&rpmcc RPM_CXO_A2>; |
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clock-names = "xo", "rf"; |
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|
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vddxo-supply = <&pm8941_l6>; |
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vddrfa-supply = <&pm8941_l11>; |
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vddpa-supply = <&pm8941_l19>; |
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vdddig-supply = <&pm8941_s3>; |
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}; |
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}; |
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@ -0,0 +1,624 @@ |
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/*
|
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* Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader |
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* |
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* Copyright (C) 2016 Linaro Ltd |
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* Copyright (C) 2014 Sony Mobile Communications AB |
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* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* version 2 as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/firmware.h> |
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#include <linux/interrupt.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/io.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/qcom_scm.h> |
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#include <linux/regulator/consumer.h> |
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#include <linux/remoteproc.h> |
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#include <linux/soc/qcom/smem.h> |
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#include <linux/soc/qcom/smem_state.h> |
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|
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#include "qcom_mdt_loader.h" |
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#include "remoteproc_internal.h" |
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#include "qcom_wcnss.h" |
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|
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#define WCNSS_CRASH_REASON_SMEM 422 |
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#define WCNSS_FIRMWARE_NAME "wcnss.mdt" |
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#define WCNSS_PAS_ID 6 |
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|
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#define WCNSS_SPARE_NVBIN_DLND BIT(25) |
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|
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#define WCNSS_PMU_IRIS_XO_CFG BIT(3) |
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#define WCNSS_PMU_IRIS_XO_EN BIT(4) |
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#define WCNSS_PMU_GC_BUS_MUX_SEL_TOP BIT(5) |
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#define WCNSS_PMU_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */ |
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|
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#define WCNSS_PMU_IRIS_RESET BIT(7) |
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#define WCNSS_PMU_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */ |
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#define WCNSS_PMU_IRIS_XO_READ BIT(9) |
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#define WCNSS_PMU_IRIS_XO_READ_STS BIT(10) |
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|
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#define WCNSS_PMU_XO_MODE_MASK GENMASK(2, 1) |
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#define WCNSS_PMU_XO_MODE_19p2 0 |
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#define WCNSS_PMU_XO_MODE_48 3 |
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|
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struct wcnss_data { |
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size_t pmu_offset; |
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size_t spare_offset; |
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|
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const struct wcnss_vreg_info *vregs; |
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size_t num_vregs; |
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}; |
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|
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struct qcom_wcnss { |
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struct device *dev; |
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struct rproc *rproc; |
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|
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void __iomem *pmu_cfg; |
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void __iomem *spare_out; |
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|
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bool use_48mhz_xo; |
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|
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int wdog_irq; |
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int fatal_irq; |
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int ready_irq; |
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int handover_irq; |
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int stop_ack_irq; |
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|
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struct qcom_smem_state *state; |
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unsigned stop_bit; |
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|
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struct mutex iris_lock; |
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struct qcom_iris *iris; |
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|
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struct regulator_bulk_data *vregs; |
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size_t num_vregs; |
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|
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struct completion start_done; |
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struct completion stop_done; |
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|
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phys_addr_t mem_phys; |
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phys_addr_t mem_reloc; |
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void *mem_region; |
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size_t mem_size; |
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}; |
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|
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static const struct wcnss_data riva_data = { |
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.pmu_offset = 0x28, |
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.spare_offset = 0xb4, |
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|
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.vregs = (struct wcnss_vreg_info[]) { |
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{ "vddmx", 1050000, 1150000, 0 }, |
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{ "vddcx", 1050000, 1150000, 0 }, |
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{ "vddpx", 1800000, 1800000, 0 }, |
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}, |
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.num_vregs = 3, |
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}; |
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|
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static const struct wcnss_data pronto_v1_data = { |
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.pmu_offset = 0x1004, |
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.spare_offset = 0x1088, |
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|
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.vregs = (struct wcnss_vreg_info[]) { |
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{ "vddmx", 950000, 1150000, 0 }, |
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{ "vddcx", .super_turbo = true}, |
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{ "vddpx", 1800000, 1800000, 0 }, |
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}, |
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.num_vregs = 3, |
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}; |
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|
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static const struct wcnss_data pronto_v2_data = { |
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.pmu_offset = 0x1004, |
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.spare_offset = 0x1088, |
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|
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.vregs = (struct wcnss_vreg_info[]) { |
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{ "vddmx", 1287500, 1287500, 0 }, |
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{ "vddcx", .super_turbo = true }, |
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{ "vddpx", 1800000, 1800000, 0 }, |
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}, |
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.num_vregs = 3, |
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}; |
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|
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void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss, |
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struct qcom_iris *iris, |
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bool use_48mhz_xo) |
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{ |
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mutex_lock(&wcnss->iris_lock); |
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wcnss->iris = iris; |
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wcnss->use_48mhz_xo = use_48mhz_xo; |
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|
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mutex_unlock(&wcnss->iris_lock); |
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} |
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EXPORT_SYMBOL_GPL(qcom_wcnss_assign_iris); |
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|
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static int wcnss_load(struct rproc *rproc, const struct firmware *fw) |
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{ |
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struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; |
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phys_addr_t fw_addr; |
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size_t fw_size; |
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bool relocate; |
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int ret; |
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|
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ret = qcom_scm_pas_init_image(WCNSS_PAS_ID, fw->data, fw->size); |
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if (ret) { |
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dev_err(&rproc->dev, "invalid firmware metadata\n"); |
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return ret; |
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} |
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|
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ret = qcom_mdt_parse(fw, &fw_addr, &fw_size, &relocate); |
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if (ret) { |
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dev_err(&rproc->dev, "failed to parse mdt header\n"); |
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return ret; |
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} |
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|
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if (relocate) { |
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wcnss->mem_reloc = fw_addr; |
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|
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ret = qcom_scm_pas_mem_setup(WCNSS_PAS_ID, wcnss->mem_phys, fw_size); |
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if (ret) { |
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dev_err(&rproc->dev, "unable to setup memory for image\n"); |
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return ret; |
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} |
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} |
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|
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return qcom_mdt_load(rproc, fw, rproc->firmware); |
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} |
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|
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static const struct rproc_fw_ops wcnss_fw_ops = { |
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.find_rsc_table = qcom_mdt_find_rsc_table, |
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.load = wcnss_load, |
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}; |
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|
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static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss) |
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{ |
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u32 val; |
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|
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/* Indicate NV download capability */ |
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val = readl(wcnss->spare_out); |
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val |= WCNSS_SPARE_NVBIN_DLND; |
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writel(val, wcnss->spare_out); |
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} |
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|
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static void wcnss_configure_iris(struct qcom_wcnss *wcnss) |
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{ |
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u32 val; |
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|
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/* Clear PMU cfg register */ |
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writel(0, wcnss->pmu_cfg); |
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val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN; |
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writel(val, wcnss->pmu_cfg); |
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|
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/* Clear XO_MODE */ |
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val &= ~WCNSS_PMU_XO_MODE_MASK; |
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if (wcnss->use_48mhz_xo) |
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val |= WCNSS_PMU_XO_MODE_48 << 1; |
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else |
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val |= WCNSS_PMU_XO_MODE_19p2 << 1; |
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writel(val, wcnss->pmu_cfg); |
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|
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/* Reset IRIS */ |
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val |= WCNSS_PMU_IRIS_RESET; |
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writel(val, wcnss->pmu_cfg); |
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|
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/* Wait for PMU.iris_reg_reset_sts */ |
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while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS) |
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cpu_relax(); |
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|
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/* Clear IRIS reset */ |
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val &= ~WCNSS_PMU_IRIS_RESET; |
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writel(val, wcnss->pmu_cfg); |
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|
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/* Start IRIS XO configuration */ |
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val |= WCNSS_PMU_IRIS_XO_CFG; |
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writel(val, wcnss->pmu_cfg); |
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|
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/* Wait for XO configuration to finish */ |
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while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS) |
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cpu_relax(); |
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|
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/* Stop IRIS XO configuration */ |
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val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP; |
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val &= ~WCNSS_PMU_IRIS_XO_CFG; |
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writel(val, wcnss->pmu_cfg); |
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|
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/* Add some delay for XO to settle */ |
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msleep(20); |
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} |
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|
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static int wcnss_start(struct rproc *rproc) |
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{ |
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struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; |
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int ret; |
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|
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mutex_lock(&wcnss->iris_lock); |
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if (!wcnss->iris) { |
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dev_err(wcnss->dev, "no iris registered\n"); |
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ret = -EINVAL; |
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goto release_iris_lock; |
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} |
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|
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ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs); |
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if (ret) |
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goto release_iris_lock; |
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|
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ret = qcom_iris_enable(wcnss->iris); |
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if (ret) |
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goto disable_regulators; |
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|
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wcnss_indicate_nv_download(wcnss); |
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wcnss_configure_iris(wcnss); |
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|
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ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID); |
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if (ret) { |
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dev_err(wcnss->dev, |
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"failed to authenticate image and release reset\n"); |
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goto disable_iris; |
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} |
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|
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ret = wait_for_completion_timeout(&wcnss->start_done, |
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msecs_to_jiffies(5000)); |
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if (wcnss->ready_irq > 0 && ret == 0) { |
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/* We have a ready_irq, but it didn't fire in time. */ |
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dev_err(wcnss->dev, "start timed out\n"); |
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qcom_scm_pas_shutdown(WCNSS_PAS_ID); |
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ret = -ETIMEDOUT; |
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goto disable_iris; |
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} |
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|
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ret = 0; |
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|
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disable_iris: |
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qcom_iris_disable(wcnss->iris); |
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disable_regulators: |
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regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs); |
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release_iris_lock: |
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mutex_unlock(&wcnss->iris_lock); |
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|
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return ret; |
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} |
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|
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static int wcnss_stop(struct rproc *rproc) |
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{ |
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struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; |
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int ret; |
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|
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if (wcnss->state) { |
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qcom_smem_state_update_bits(wcnss->state, |
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BIT(wcnss->stop_bit), |
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BIT(wcnss->stop_bit)); |
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|
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ret = wait_for_completion_timeout(&wcnss->stop_done, |
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msecs_to_jiffies(5000)); |
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if (ret == 0) |
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dev_err(wcnss->dev, "timed out on wait\n"); |
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|
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qcom_smem_state_update_bits(wcnss->state, |
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BIT(wcnss->stop_bit), |
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0); |
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} |
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|
|||
ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID); |
|||
if (ret) |
|||
dev_err(wcnss->dev, "failed to shutdown: %d\n", ret); |
|||
|
|||
return ret; |
|||
} |
|||
|
|||
static void *wcnss_da_to_va(struct rproc *rproc, u64 da, int len) |
|||
{ |
|||
struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; |
|||
int offset; |
|||
|
|||
offset = da - wcnss->mem_reloc; |
|||
if (offset < 0 || offset + len > wcnss->mem_size) |
|||
return NULL; |
|||
|
|||
return wcnss->mem_region + offset; |
|||
} |
|||
|
|||
static const struct rproc_ops wcnss_ops = { |
|||
.start = wcnss_start, |
|||
.stop = wcnss_stop, |
|||
.da_to_va = wcnss_da_to_va, |
|||
}; |
|||
|
|||
static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev) |
|||
{ |
|||
struct qcom_wcnss *wcnss = dev; |
|||
|
|||
rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG); |
|||
|
|||
return IRQ_HANDLED; |
|||
} |
|||
|
|||
static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev) |
|||
{ |
|||
struct qcom_wcnss *wcnss = dev; |
|||
size_t len; |
|||
char *msg; |
|||
|
|||
msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len); |
|||
if (!IS_ERR(msg) && len > 0 && msg[0]) |
|||
dev_err(wcnss->dev, "fatal error received: %s\n", msg); |
|||
|
|||
rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR); |
|||
|
|||
if (!IS_ERR(msg)) |
|||
msg[0] = '\0'; |
|||
|
|||
return IRQ_HANDLED; |
|||
} |
|||
|
|||
static irqreturn_t wcnss_ready_interrupt(int irq, void *dev) |
|||
{ |
|||
struct qcom_wcnss *wcnss = dev; |
|||
|
|||
complete(&wcnss->start_done); |
|||
|
|||
return IRQ_HANDLED; |
|||
} |
|||
|
|||
static irqreturn_t wcnss_handover_interrupt(int irq, void *dev) |
|||
{ |
|||
/*
|
|||
* XXX: At this point we're supposed to release the resources that we |
|||
* have been holding on behalf of the WCNSS. Unfortunately this |
|||
* interrupt comes way before the other side seems to be done. |
|||
* |
|||
* So we're currently relying on the ready interrupt firing later then |
|||
* this and we just disable the resources at the end of wcnss_start(). |
|||
*/ |
|||
|
|||
return IRQ_HANDLED; |
|||
} |
|||
|
|||
static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev) |
|||
{ |
|||
struct qcom_wcnss *wcnss = dev; |
|||
|
|||
complete(&wcnss->stop_done); |
|||
|
|||
return IRQ_HANDLED; |
|||
} |
|||
|
|||
static int wcnss_init_regulators(struct qcom_wcnss *wcnss, |
|||
const struct wcnss_vreg_info *info, |
|||
int num_vregs) |
|||
{ |
|||
struct regulator_bulk_data *bulk; |
|||
int ret; |
|||
int i; |
|||
|
|||
bulk = devm_kcalloc(wcnss->dev, |
|||
num_vregs, sizeof(struct regulator_bulk_data), |
|||
GFP_KERNEL); |
|||
if (!bulk) |
|||
return -ENOMEM; |
|||
|
|||
for (i = 0; i < num_vregs; i++) |
|||
bulk[i].supply = info[i].name; |
|||
|
|||
ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk); |
|||
if (ret) |
|||
return ret; |
|||
|
|||
for (i = 0; i < num_vregs; i++) { |
|||
if (info[i].max_voltage) |
|||
regulator_set_voltage(bulk[i].consumer, |
|||
info[i].min_voltage, |
|||
info[i].max_voltage); |
|||
|
|||
if (info[i].load_uA) |
|||
regulator_set_load(bulk[i].consumer, info[i].load_uA); |
|||
} |
|||
|
|||
wcnss->vregs = bulk; |
|||
wcnss->num_vregs = num_vregs; |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
static int wcnss_request_irq(struct qcom_wcnss *wcnss, |
|||
struct platform_device *pdev, |
|||
const char *name, |
|||
bool optional, |
|||
irq_handler_t thread_fn) |
|||
{ |
|||
int ret; |
|||
|
|||
ret = platform_get_irq_byname(pdev, name); |
|||
if (ret < 0 && optional) { |
|||
dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name); |
|||
return 0; |
|||
} else if (ret < 0) { |
|||
dev_err(&pdev->dev, "no %s IRQ defined\n", name); |
|||
return ret; |
|||
} |
|||
|
|||
ret = devm_request_threaded_irq(&pdev->dev, ret, |
|||
NULL, thread_fn, |
|||
IRQF_TRIGGER_RISING | IRQF_ONESHOT, |
|||
"wcnss", wcnss); |
|||
if (ret) |
|||
dev_err(&pdev->dev, "request %s IRQ failed\n", name); |
|||
|
|||
return ret; |
|||
} |
|||
|
|||
static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss) |
|||
{ |
|||
struct device_node *node; |
|||
struct resource r; |
|||
int ret; |
|||
|
|||
node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0); |
|||
if (!node) { |
|||
dev_err(wcnss->dev, "no memory-region specified\n"); |
|||
return -EINVAL; |
|||
} |
|||
|
|||
ret = of_address_to_resource(node, 0, &r); |
|||
if (ret) |
|||
return ret; |
|||
|
|||
wcnss->mem_phys = wcnss->mem_reloc = r.start; |
|||
wcnss->mem_size = resource_size(&r); |
|||
wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size); |
|||
if (!wcnss->mem_region) { |
|||
dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n", |
|||
&r.start, wcnss->mem_size); |
|||
return -EBUSY; |
|||
} |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
static int wcnss_probe(struct platform_device *pdev) |
|||
{ |
|||
const struct wcnss_data *data; |
|||
struct qcom_wcnss *wcnss; |
|||
struct resource *res; |
|||
struct rproc *rproc; |
|||
void __iomem *mmio; |
|||
int ret; |
|||
|
|||
data = of_device_get_match_data(&pdev->dev); |
|||
|
|||
if (!qcom_scm_is_available()) |
|||
return -EPROBE_DEFER; |
|||
|
|||
if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) { |
|||
dev_err(&pdev->dev, "PAS is not available for WCNSS\n"); |
|||
return -ENXIO; |
|||
} |
|||
|
|||
rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops, |
|||
WCNSS_FIRMWARE_NAME, sizeof(*wcnss)); |
|||
if (!rproc) { |
|||
dev_err(&pdev->dev, "unable to allocate remoteproc\n"); |
|||
return -ENOMEM; |
|||
} |
|||
|
|||
rproc->fw_ops = &wcnss_fw_ops; |
|||
|
|||
wcnss = (struct qcom_wcnss *)rproc->priv; |
|||
wcnss->dev = &pdev->dev; |
|||
wcnss->rproc = rproc; |
|||
platform_set_drvdata(pdev, wcnss); |
|||
|
|||
init_completion(&wcnss->start_done); |
|||
init_completion(&wcnss->stop_done); |
|||
|
|||
mutex_init(&wcnss->iris_lock); |
|||
|
|||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu"); |
|||
mmio = devm_ioremap_resource(&pdev->dev, res); |
|||
if (IS_ERR(mmio)) { |
|||
ret = PTR_ERR(mmio); |
|||
goto free_rproc; |
|||
}; |
|||
|
|||
ret = wcnss_alloc_memory_region(wcnss); |
|||
if (ret) |
|||
goto free_rproc; |
|||
|
|||
wcnss->pmu_cfg = mmio + data->pmu_offset; |
|||
wcnss->spare_out = mmio + data->spare_offset; |
|||
|
|||
ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs); |
|||
if (ret) |
|||
goto free_rproc; |
|||
|
|||
ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt); |
|||
if (ret < 0) |
|||
goto free_rproc; |
|||
wcnss->wdog_irq = ret; |
|||
|
|||
ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt); |
|||
if (ret < 0) |
|||
goto free_rproc; |
|||
wcnss->fatal_irq = ret; |
|||
|
|||
ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt); |
|||
if (ret < 0) |
|||
goto free_rproc; |
|||
wcnss->ready_irq = ret; |
|||
|
|||
ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt); |
|||
if (ret < 0) |
|||
goto free_rproc; |
|||
wcnss->handover_irq = ret; |
|||
|
|||
ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt); |
|||
if (ret < 0) |
|||
goto free_rproc; |
|||
wcnss->stop_ack_irq = ret; |
|||
|
|||
if (wcnss->stop_ack_irq) { |
|||
wcnss->state = qcom_smem_state_get(&pdev->dev, "stop", |
|||
&wcnss->stop_bit); |
|||
if (IS_ERR(wcnss->state)) { |
|||
ret = PTR_ERR(wcnss->state); |
|||
goto free_rproc; |
|||
} |
|||
} |
|||
|
|||
ret = rproc_add(rproc); |
|||
if (ret) |
|||
goto free_rproc; |
|||
|
|||
return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); |
|||
|
|||
free_rproc: |
|||
rproc_free(rproc); |
|||
|
|||
return ret; |
|||
} |
|||
|
|||
static int wcnss_remove(struct platform_device *pdev) |
|||
{ |
|||
struct qcom_wcnss *wcnss = platform_get_drvdata(pdev); |
|||
|
|||
of_platform_depopulate(&pdev->dev); |
|||
|
|||
qcom_smem_state_put(wcnss->state); |
|||
rproc_del(wcnss->rproc); |
|||
rproc_free(wcnss->rproc); |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
static const struct of_device_id wcnss_of_match[] = { |
|||
{ .compatible = "qcom,riva-pil", &riva_data }, |
|||
{ .compatible = "qcom,pronto-v1-pil", &pronto_v1_data }, |
|||
{ .compatible = "qcom,pronto-v2-pil", &pronto_v2_data }, |
|||
{ }, |
|||
}; |
|||
|
|||
static struct platform_driver wcnss_driver = { |
|||
.probe = wcnss_probe, |
|||
.remove = wcnss_remove, |
|||
.driver = { |
|||
.name = "qcom-wcnss-pil", |
|||
.of_match_table = wcnss_of_match, |
|||
}, |
|||
}; |
|||
|
|||
module_platform_driver(wcnss_driver); |
|||
MODULE_DESCRIPTION("Qualcomm Peripherial Image Loader for Wireless Subsystem"); |
|||
MODULE_LICENSE("GPL v2"); |
|||
@ -0,0 +1,22 @@ |
|||
#ifndef __QCOM_WNCSS_H__ |
|||
#define __QCOM_WNCSS_H__ |
|||
|
|||
struct qcom_iris; |
|||
struct qcom_wcnss; |
|||
|
|||
struct wcnss_vreg_info { |
|||
const char * const name; |
|||
int min_voltage; |
|||
int max_voltage; |
|||
|
|||
int load_uA; |
|||
|
|||
bool super_turbo; |
|||
}; |
|||
|
|||
int qcom_iris_enable(struct qcom_iris *iris); |
|||
void qcom_iris_disable(struct qcom_iris *iris); |
|||
|
|||
void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss, struct qcom_iris *iris, bool use_48mhz_xo); |
|||
|
|||
#endif |
|||
@ -0,0 +1,188 @@ |
|||
/*
|
|||
* Qualcomm Wireless Connectivity Subsystem Iris driver |
|||
* |
|||
* Copyright (C) 2016 Linaro Ltd |
|||
* Copyright (C) 2014 Sony Mobile Communications AB |
|||
* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
|||
* |
|||
* This program is free software; you can redistribute it and/or |
|||
* modify it under the terms of the GNU General Public License |
|||
* version 2 as published by the Free Software Foundation. |
|||
* |
|||
* This program is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU General Public License for more details. |
|||
*/ |
|||
|
|||
#include <linux/clk.h> |
|||
#include <linux/kernel.h> |
|||
#include <linux/module.h> |
|||
#include <linux/of_device.h> |
|||
#include <linux/platform_device.h> |
|||
#include <linux/regulator/consumer.h> |
|||
|
|||
#include "qcom_wcnss.h" |
|||
|
|||
struct qcom_iris { |
|||
struct device *dev; |
|||
|
|||
struct clk *xo_clk; |
|||
|
|||
struct regulator_bulk_data *vregs; |
|||
size_t num_vregs; |
|||
}; |
|||
|
|||
struct iris_data { |
|||
const struct wcnss_vreg_info *vregs; |
|||
size_t num_vregs; |
|||
|
|||
bool use_48mhz_xo; |
|||
}; |
|||
|
|||
static const struct iris_data wcn3620_data = { |
|||
.vregs = (struct wcnss_vreg_info[]) { |
|||
{ "vddxo", 1800000, 1800000, 10000 }, |
|||
{ "vddrfa", 1300000, 1300000, 100000 }, |
|||
{ "vddpa", 3300000, 3300000, 515000 }, |
|||
{ "vdddig", 1800000, 1800000, 10000 }, |
|||
}, |
|||
.num_vregs = 4, |
|||
.use_48mhz_xo = false, |
|||
}; |
|||
|
|||
static const struct iris_data wcn3660_data = { |
|||
.vregs = (struct wcnss_vreg_info[]) { |
|||
{ "vddxo", 1800000, 1800000, 10000 }, |
|||
{ "vddrfa", 1300000, 1300000, 100000 }, |
|||
{ "vddpa", 2900000, 3000000, 515000 }, |
|||
{ "vdddig", 1200000, 1225000, 10000 }, |
|||
}, |
|||
.num_vregs = 4, |
|||
.use_48mhz_xo = true, |
|||
}; |
|||
|
|||
static const struct iris_data wcn3680_data = { |
|||
.vregs = (struct wcnss_vreg_info[]) { |
|||
{ "vddxo", 1800000, 1800000, 10000 }, |
|||
{ "vddrfa", 1300000, 1300000, 100000 }, |
|||
{ "vddpa", 3300000, 3300000, 515000 }, |
|||
{ "vdddig", 1800000, 1800000, 10000 }, |
|||
}, |
|||
.num_vregs = 4, |
|||
.use_48mhz_xo = true, |
|||
}; |
|||
|
|||
int qcom_iris_enable(struct qcom_iris *iris) |
|||
{ |
|||
int ret; |
|||
|
|||
ret = regulator_bulk_enable(iris->num_vregs, iris->vregs); |
|||
if (ret) |
|||
return ret; |
|||
|
|||
ret = clk_prepare_enable(iris->xo_clk); |
|||
if (ret) { |
|||
dev_err(iris->dev, "failed to enable xo clk\n"); |
|||
goto disable_regulators; |
|||
} |
|||
|
|||
return 0; |
|||
|
|||
disable_regulators: |
|||
regulator_bulk_disable(iris->num_vregs, iris->vregs); |
|||
|
|||
return ret; |
|||
} |
|||
EXPORT_SYMBOL_GPL(qcom_iris_enable); |
|||
|
|||
void qcom_iris_disable(struct qcom_iris *iris) |
|||
{ |
|||
clk_disable_unprepare(iris->xo_clk); |
|||
regulator_bulk_disable(iris->num_vregs, iris->vregs); |
|||
} |
|||
EXPORT_SYMBOL_GPL(qcom_iris_disable); |
|||
|
|||
static int qcom_iris_probe(struct platform_device *pdev) |
|||
{ |
|||
const struct iris_data *data; |
|||
struct qcom_wcnss *wcnss; |
|||
struct qcom_iris *iris; |
|||
int ret; |
|||
int i; |
|||
|
|||
iris = devm_kzalloc(&pdev->dev, sizeof(struct qcom_iris), GFP_KERNEL); |
|||
if (!iris) |
|||
return -ENOMEM; |
|||
|
|||
data = of_device_get_match_data(&pdev->dev); |
|||
wcnss = dev_get_drvdata(pdev->dev.parent); |
|||
|
|||
iris->xo_clk = devm_clk_get(&pdev->dev, "xo"); |
|||
if (IS_ERR(iris->xo_clk)) { |
|||
if (PTR_ERR(iris->xo_clk) != -EPROBE_DEFER) |
|||
dev_err(&pdev->dev, "failed to acquire xo clk\n"); |
|||
return PTR_ERR(iris->xo_clk); |
|||
} |
|||
|
|||
iris->num_vregs = data->num_vregs; |
|||
iris->vregs = devm_kcalloc(&pdev->dev, |
|||
iris->num_vregs, |
|||
sizeof(struct regulator_bulk_data), |
|||
GFP_KERNEL); |
|||
if (!iris->vregs) |
|||
return -ENOMEM; |
|||
|
|||
for (i = 0; i < iris->num_vregs; i++) |
|||
iris->vregs[i].supply = data->vregs[i].name; |
|||
|
|||
ret = devm_regulator_bulk_get(&pdev->dev, iris->num_vregs, iris->vregs); |
|||
if (ret) { |
|||
dev_err(&pdev->dev, "failed to get regulators\n"); |
|||
return ret; |
|||
} |
|||
|
|||
for (i = 0; i < iris->num_vregs; i++) { |
|||
if (data->vregs[i].max_voltage) |
|||
regulator_set_voltage(iris->vregs[i].consumer, |
|||
data->vregs[i].min_voltage, |
|||
data->vregs[i].max_voltage); |
|||
|
|||
if (data->vregs[i].load_uA) |
|||
regulator_set_load(iris->vregs[i].consumer, |
|||
data->vregs[i].load_uA); |
|||
} |
|||
|
|||
qcom_wcnss_assign_iris(wcnss, iris, data->use_48mhz_xo); |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
static int qcom_iris_remove(struct platform_device *pdev) |
|||
{ |
|||
struct qcom_wcnss *wcnss = dev_get_drvdata(pdev->dev.parent); |
|||
|
|||
qcom_wcnss_assign_iris(wcnss, NULL, false); |
|||
|
|||
return 0; |
|||
} |
|||
|
|||
static const struct of_device_id iris_of_match[] = { |
|||
{ .compatible = "qcom,wcn3620", .data = &wcn3620_data }, |
|||
{ .compatible = "qcom,wcn3660", .data = &wcn3660_data }, |
|||
{ .compatible = "qcom,wcn3680", .data = &wcn3680_data }, |
|||
{} |
|||
}; |
|||
|
|||
static struct platform_driver wcnss_driver = { |
|||
.probe = qcom_iris_probe, |
|||
.remove = qcom_iris_remove, |
|||
.driver = { |
|||
.name = "qcom-iris", |
|||
.of_match_table = iris_of_match, |
|||
}, |
|||
}; |
|||
|
|||
module_platform_driver(wcnss_driver); |
|||
MODULE_DESCRIPTION("Qualcomm Wireless Subsystem Iris driver"); |
|||
MODULE_LICENSE("GPL v2"); |
|||