Browse Source

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "This is the main MIPS pull request for 4.9:

  MIPS core arch code:
   - traps: 64bit kernels should read CP0_EBase 64bit
   - traps: Convert ebase to KSEG0
   - c-r4k: Drop bc_wback_inv() from icache flush
   - c-r4k: Split user/kernel flush_icache_range()
   - cacheflush: Use __flush_icache_user_range()
   - uprobes: Flush icache via kernel address
   - KVM: Use __local_flush_icache_user_range()
   - c-r4k: Fix flush_icache_range() for EVA
   - Fix -mabi=64 build of vdso.lds
   - VDSO: Drop duplicated -I*/-E* aflags
   - tracing: move insn_has_delay_slot to a shared header
   - tracing: disable uprobe/kprobe on compact branch instructions
   - ptrace: Fix regs_return_value for kernel context
   - Squash lines for simple wrapper functions
   - Move identification of VP(E) into proc.c from smp-mt.c
   - Add definitions of SYNC barrierstype values
   - traps: Ensure full EBase is written
   - tlb-r4k: If there are wired entries, don't use TLBINVF
   - Sanitise coherentio semantics
   - dma-default: Don't check hw_coherentio if device is non-coherent
   - Support per-device DMA coherence
   - Adjust MIPS64 CAC_BASE to reflect Config.K0
   - Support generating Flattened Image Trees (.itb)
   - generic: Introduce generic DT-based board support
   - generic: Convert SEAD-3 to a generic board
   - Enable hardened usercopy
   - Don't specify STACKPROTECTOR in defconfigs

  Octeon:
   - Delete dead code and files across the platform.
   - Change to use all memory into use by default.
   - Rename upper case variables in setup code to lowercase.
   - Delete legacy hack for broken bootloaders.
   - Leave maintaining the link state to the actual ethernet/PHY drivers.
   - Add DTS for D-Link DSR-500N.
   - Fix PCI interrupt routing on D-Link DSR-500N.

  Pistachio:
   - Remove ANDROID_TIMED_OUTPUT from defconfig

  TX39xx:
   - Move GPIO setup from .mem_setup() to .arch_init()
   - Convert to Common Clock Framework

  TX49xx:
   - Move GPIO setup from .mem_setup() to .arch_init()
   - Convert to Common Clock Framework

  txx9wdt:
   - Add missing clock (un)prepare calls for CCF

  BMIPS:
   - Add PW, GPIO SDHCI and NAND device node names
   - Support APPENDED_DTB
   - Add missing bcm97435svmb to DT_NONE
   - Rename bcm96358nb4ser to bcm6358-neufbox4-sercom
   - Add DT examples for BCM63268, BCM3368 and BCM6362
   - Add support for BCM3368 and BCM6362

  PCI
   - Reduce stack frame usage
   - Use struct list_head lists
   - Support for CONFIG_PCI_DOMAINS_GENERIC
   - Make pcibios_set_cache_line_size an initcall
   - Inline pcibios_assign_all_busses
   - Split pci.c into pci.c & pci-legacy.c
   - Introduce CONFIG_PCI_DRIVERS_LEGACY
   - Support generic drivers

  CPC
   - Convert bare 'unsigned' to 'unsigned int'
   - Avoid lock when MIPS CM >= 3 is present

  GIC:
   - Delete unused file smp-gic.c

  mt7620:
   - Delete unnecessary assignment for the field "owner" from PCI

  BCM63xx:
   - Let clk_disable() return immediately if clk is NULL

  pm-cps:
   - Change FSB workaround to CPU blacklist
   - Update comments on barrier instructions
   - Use MIPS standard lightweight ordering barrier
   - Use MIPS standard completion barrier
   - Remove selection of sync types
   - Add MIPSr6 CPU support
   - Support CM3 changes to Coherence Enable Register

  SMP:
   - Wrap call to mips_cpc_lock_other in mips_cm_lock_other
   - Introduce mechanism for freeing and allocating IPIs

  cpuidle:
   - cpuidle-cps: Enable use with MIPSr6 CPUs.

  SEAD3:
   - Rewrite to use DT and generic kernel feature.

  USB:
   - host: ehci-sead3: Remove SEAD-3 EHCI code

  FBDEV:
   - cobalt_lcdfb: Drop SEAD3 support

  dt-bindings:
   -  Document a binding for simple ASCII LCDs

  auxdisplay:
   - img-ascii-lcd: driver for simple ASCII LCD displays

  irqchip i8259:
   - i8259: Add domain before mapping parent irq
   - i8259: Allow platforms to override poll function
   - i8259: Remove unused i8259A_irq_pending

  Malta:
   - Rewrite to use DT

  of/platform:
   - Probe "isa" busses by default

  CM:
   - Print CM error reports upon bus errors

  Module:
   - Migrate exception table users off module.h and onto extable.h
   - Make various drivers explicitly non-modular:
   - Audit and remove any unnecessary uses of module.h

  mailmap:
   - Canonicalize to Qais' current email address.

  Documentation:
   - MIPS supports HAVE_REGS_AND_STACK_ACCESS_API

  Loongson1C:
   - Add CPU support for Loongson1C
   - Add board support
   - Add defconfig
   - Add RTC support for Loongson1C board

  All this except one Documentation fix has sat in linux-next and has
  survived Imagination's automated build test system"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (127 commits)
  Documentation: MIPS supports HAVE_REGS_AND_STACK_ACCESS_API
  MIPS: ptrace: Fix regs_return_value for kernel context
  MIPS: VDSO: Drop duplicated -I*/-E* aflags
  MIPS: Fix -mabi=64 build of vdso.lds
  MIPS: Enable hardened usercopy
  MIPS: generic: Convert SEAD-3 to a generic board
  MIPS: generic: Introduce generic DT-based board support
  MIPS: Support generating Flattened Image Trees (.itb)
  MIPS: Adjust MIPS64 CAC_BASE to reflect Config.K0
  MIPS: Print CM error reports upon bus errors
  MIPS: Support per-device DMA coherence
  MIPS: dma-default: Don't check hw_coherentio if device is non-coherent
  MIPS: Sanitise coherentio semantics
  MIPS: PCI: Support generic drivers
  MIPS: PCI: Introduce CONFIG_PCI_DRIVERS_LEGACY
  MIPS: PCI: Split pci.c into pci.c & pci-legacy.c
  MIPS: PCI: Inline pcibios_assign_all_busses
  MIPS: PCI: Make pcibios_set_cache_line_size an initcall
  MIPS: PCI: Support for CONFIG_PCI_DOMAINS_GENERIC
  MIPS: PCI: Use struct list_head lists
  ...
master
Linus Torvalds 5 years ago
parent
commit
133d970e0d
  1. 1
      .mailmap
  2. 17
      Documentation/devicetree/bindings/auxdisplay/img-ascii-lcd.txt
  3. 4
      Documentation/devicetree/bindings/mips/brcm/soc.txt
  4. 2
      Documentation/features/perf/kprobes-event/arch-support.txt
  5. 6
      MAINTAINERS
  6. 2
      arch/mips/Kbuild.platforms
  7. 121
      arch/mips/Kconfig
  8. 77
      arch/mips/Makefile
  9. 6
      arch/mips/alchemy/common/setup.c
  10. 11
      arch/mips/bcm47xx/serial.c
  11. 3
      arch/mips/bcm63xx/clk.c
  12. 20
      arch/mips/bmips/Kconfig
  13. 12
      arch/mips/bmips/setup.c
  14. 66
      arch/mips/boot/Makefile
  15. 36
      arch/mips/boot/dts/brcm/Makefile
  16. 22
      arch/mips/boot/dts/brcm/bcm3368-netgear-cvg834g.dts
  17. 101
      arch/mips/boot/dts/brcm/bcm3368.dtsi
  18. 108
      arch/mips/boot/dts/brcm/bcm63268-comtrend-vr-3032u.dts
  19. 134
      arch/mips/boot/dts/brcm/bcm63268.dtsi
  20. 1
      arch/mips/boot/dts/brcm/bcm6358-neufbox4-sercomm.dts
  21. 22
      arch/mips/boot/dts/brcm/bcm6362-neufbox6-sercomm.dts
  22. 134
      arch/mips/boot/dts/brcm/bcm6362.dtsi
  23. 34
      arch/mips/boot/dts/brcm/bcm7125.dtsi
  24. 97
      arch/mips/boot/dts/brcm/bcm7346.dtsi
  25. 89
      arch/mips/boot/dts/brcm/bcm7358.dtsi
  26. 89
      arch/mips/boot/dts/brcm/bcm7360.dtsi
  27. 89
      arch/mips/boot/dts/brcm/bcm7362.dtsi
  28. 42
      arch/mips/boot/dts/brcm/bcm7420.dtsi
  29. 109
      arch/mips/boot/dts/brcm/bcm7425.dtsi
  30. 109
      arch/mips/boot/dts/brcm/bcm7435.dtsi
  31. 4
      arch/mips/boot/dts/brcm/bcm97125cbmb.dts
  32. 17
      arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
  33. 13
      arch/mips/boot/dts/brcm/bcm97358svmb.dts
  34. 8
      arch/mips/boot/dts/brcm/bcm97360svmb.dts
  35. 13
      arch/mips/boot/dts/brcm/bcm97362svmb.dts
  36. 8
      arch/mips/boot/dts/brcm/bcm97420c.dts
  37. 21
      arch/mips/boot/dts/brcm/bcm97425svmb.dts
  38. 21
      arch/mips/boot/dts/brcm/bcm97435svmb.dts
  39. 25
      arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch24.dtsi
  40. 25
      arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch4.dtsi
  41. 45
      arch/mips/boot/dts/cavium-octeon/dlink_dsr-1000n.dts
  42. 58
      arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n-1000n.dtsi
  43. 40
      arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n.dts
  44. 2
      arch/mips/boot/dts/mti/Makefile
  45. 99
      arch/mips/boot/dts/mti/malta.dts
  46. 238
      arch/mips/boot/dts/mti/sead3.dts
  47. 337
      arch/mips/cavium-octeon/executive/cvmx-helper-board.c
  48. 5
      arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
  49. 1
      arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
  50. 2
      arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
  51. 10
      arch/mips/cavium-octeon/executive/cvmx-helper.c
  52. 38
      arch/mips/cavium-octeon/setup.c
  53. 2
      arch/mips/configs/generic/32r1.config
  54. 3
      arch/mips/configs/generic/32r2.config
  55. 2
      arch/mips/configs/generic/32r6.config
  56. 4
      arch/mips/configs/generic/64r1.config
  57. 5
      arch/mips/configs/generic/64r2.config
  58. 4
      arch/mips/configs/generic/64r6.config
  59. 32
      arch/mips/configs/generic/board-sead-3.config
  60. 1
      arch/mips/configs/generic/eb.config
  61. 1
      arch/mips/configs/generic/el.config
  62. 4
      arch/mips/configs/generic/micro32r2.config
  63. 96
      arch/mips/configs/generic_defconfig
  64. 126
      arch/mips/configs/loongson1c_defconfig
  65. 4
      arch/mips/configs/malta_defconfig
  66. 4
      arch/mips/configs/malta_kvm_defconfig
  67. 4
      arch/mips/configs/malta_kvm_guest_defconfig
  68. 2
      arch/mips/configs/malta_qemu_32r6_defconfig
  69. 2
      arch/mips/configs/maltaaprp_defconfig
  70. 2
      arch/mips/configs/maltasmvp_defconfig
  71. 2
      arch/mips/configs/maltasmvp_eva_defconfig
  72. 2
      arch/mips/configs/maltaup_defconfig
  73. 4
      arch/mips/configs/maltaup_xpa_defconfig
  74. 2
      arch/mips/configs/pistachio_defconfig
  75. 121
      arch/mips/configs/sead3_defconfig
  76. 122
      arch/mips/configs/sead3micro_defconfig
  77. 19
      arch/mips/generic/Kconfig
  78. 15
      arch/mips/generic/Makefile
  79. 14
      arch/mips/generic/Platform
  80. 376
      arch/mips/generic/board-sead3.c
  81. 176
      arch/mips/generic/init.c
  82. 64
      arch/mips/generic/irq.c
  83. 29
      arch/mips/generic/proc.c
  84. 31
      arch/mips/generic/vmlinux.its.S
  85. 3
      arch/mips/include/asm/addrspace.h
  86. 96
      arch/mips/include/asm/barrier.h
  87. 5
      arch/mips/include/asm/cacheflush.h
  88. 3
      arch/mips/include/asm/cpu-type.h
  89. 1
      arch/mips/include/asm/cpu.h
  90. 5
      arch/mips/include/asm/device.h
  91. 16
      arch/mips/include/asm/dma-coherence.h
  92. 10
      arch/mips/include/asm/dma-mapping.h
  93. 12
      arch/mips/include/asm/i8259.h
  94. 14
      arch/mips/include/asm/mach-generic/dma-coherence.h
  95. 6
      arch/mips/include/asm/mach-generic/floppy.h
  96. 8
      arch/mips/include/asm/mach-generic/spaces.h
  97. 1
      arch/mips/include/asm/mach-ip27/spaces.h
  98. 41
      arch/mips/include/asm/mach-loongson32/irq.h
  99. 5
      arch/mips/include/asm/mach-loongson32/loongson1.h
  100. 1
      arch/mips/include/asm/mach-loongson32/platform.h

1
.mailmap

@ -127,6 +127,7 @@ Peter Oruba <peter@oruba.de>
Peter Oruba <peter.oruba@amd.com>
Pratyush Anand <pratyush.anand@gmail.com> <pratyush.anand@st.com>
Praveen BP <praveenbp@ti.com>
Qais Yousef <qsyousef@gmail.com> <qais.yousef@imgtec.com>
Rajesh Shah <rajesh.shah@intel.com>
Ralf Baechle <ralf@linux-mips.org>
Ralf Wildenhues <Ralf.Wildenhues@gmx.de>

17
Documentation/devicetree/bindings/auxdisplay/img-ascii-lcd.txt

@ -0,0 +1,17 @@
Binding for ASCII LCD displays on Imagination Technologies boards
Required properties:
- compatible : should be one of:
"img,boston-lcd"
"mti,malta-lcd"
"mti,sead3-lcd"
Required properties for "img,boston-lcd":
- reg : memory region locating the device registers
Required properties for "mti,malta-lcd" or "mti,sead3-lcd":
- regmap: phandle of the system controller containing the LCD registers
- offset: offset in bytes to the LCD registers within the system controller
The layout of the registers & properties of the display are determined
from the compatible string, making this binding somewhat trivial.

4
Documentation/devicetree/bindings/mips/brcm/soc.txt

@ -2,9 +2,9 @@
Required properties:
- compatible: "brcm,bcm3384", "brcm,bcm33843"
- compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
"brcm,bcm3384-viper", "brcm,bcm33843-viper"
"brcm,bcm6328", "brcm,bcm6358", "brcm,bcm6368",
"brcm,bcm6328", "brcm,bcm6358", "brcm,bcm6362", "brcm,bcm6368",
"brcm,bcm63168", "brcm,bcm63268",
"brcm,bcm7125", "brcm,bcm7346", "brcm,bcm7358", "brcm,bcm7360",
"brcm,bcm7362", "brcm,bcm7420", "brcm,bcm7425"

2
Documentation/features/perf/kprobes-event/arch-support.txt

@ -22,7 +22,7 @@
| m68k: | TODO |
| metag: | TODO |
| microblaze: | TODO |
| mips: | TODO |
| mips: | ok |
| mn10300: | TODO |
| nios2: | TODO |
| openrisc: | TODO |

6
MAINTAINERS

@ -6131,6 +6131,12 @@ M: Stanislaw Gruszka <stf_xl@wp.pl>
S: Maintained
F: drivers/usb/atm/ueagle-atm.c
IMGTEC ASCII LCD DRIVER
M: Paul Burton <paul.burton@imgtec.com>
S: Maintained
F: Documentation/devicetree/bindings/auxdisplay/img-ascii-lcd.txt
F: drivers/auxdisplay/img-ascii-lcd.c
INA209 HARDWARE MONITOR DRIVER
M: Guenter Roeck <linux@roeck-us.net>
L: linux-hwmon@vger.kernel.org

2
arch/mips/Kbuild.platforms

@ -11,6 +11,7 @@ platforms += cavium-octeon
platforms += cobalt
platforms += dec
platforms += emma
platforms += generic
platforms += jazz
platforms += jz4740
platforms += lantiq
@ -18,7 +19,6 @@ platforms += lasat
platforms += loongson32
platforms += loongson64
platforms += mti-malta
platforms += mti-sead3
platforms += netlogic
platforms += paravirt
platforms += pic32

121
arch/mips/Kconfig

@ -65,6 +65,7 @@ config MIPS
select HANDLE_DOMAIN_IRQ
select HAVE_EXIT_THREAD
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_ARCH_HARDENED_USERCOPY
menu "Machine selection"
@ -72,6 +73,57 @@ choice
prompt "System type"
default SGI_IP22
config MIPS_GENERIC
bool "Generic board-agnostic MIPS kernel"
select BOOT_RAW
select BUILTIN_DTB
select CEVT_R4K
select CLKSRC_MIPS_GIC
select COMMON_CLK
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
select CSRC_R4K
select DMA_PERDEV_COHERENT
select HW_HAS_PCI
select IRQ_MIPS_CPU
select LIBFDT
select MIPS_CPU_SCACHE
select MIPS_GIC
select MIPS_L1_CACHE_SHIFT_7
select NO_EXCEPT_FILL
select PCI_DRIVERS_GENERIC
select PINCTRL
select SMP_UP if SMP
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_HAS_CPU_MIPS32_R6
select SYS_HAS_CPU_MIPS64_R1
select SYS_HAS_CPU_MIPS64_R2
select SYS_HAS_CPU_MIPS64_R6
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_MICROMIPS
select SYS_SUPPORTS_MIPS_CPS
select SYS_SUPPORTS_MIPS16
select SYS_SUPPORTS_MULTITHREADING
select SYS_SUPPORTS_RELOCATABLE
select SYS_SUPPORTS_SMARTMIPS
select USB_EHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
select USB_EHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
select USB_OHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
select USB_OHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
select USB_UHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
select USB_UHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
select USE_OF
help
Select this to build a kernel which aims to support multiple boards,
generally using a flattened device tree passed from the bootloader
using the boot protocol defined in the UHI (Unified Hosting
Interface) specification.
config MIPS_ALCHEMY
bool "Alchemy processor based machines"
select ARCH_PHYS_ADDR_T_64BIT
@ -478,6 +530,7 @@ config MIPS_MALTA
select SYS_SUPPORTS_ZBOOT
select SYS_SUPPORTS_RELOCATABLE
select USE_OF
select LIBFDT
select ZONE_DMA32 if 64BIT
select BUILTIN_DTB
select LIBFDT
@ -493,42 +546,6 @@ config MACH_PIC32
Microchip PIC32 is a family of general-purpose 32 bit MIPS core
microcontrollers.
config MIPS_SEAD3
bool "MIPS SEAD3 board"
select BOOT_ELF32
select BOOT_RAW
select BUILTIN_DTB
select CEVT_R4K
select CSRC_R4K
select CLKSRC_MIPS_GIC
select COMMON_CLK
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
select DMA_NONCOHERENT
select IRQ_MIPS_CPU
select MIPS_GIC
select LIBFDT
select MIPS_MSC
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_HAS_CPU_MIPS32_R6
select SYS_HAS_CPU_MIPS64_R1
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_SMARTMIPS
select SYS_SUPPORTS_MICROMIPS
select SYS_SUPPORTS_MIPS16
select SYS_SUPPORTS_RELOCATABLE
select USB_EHCI_BIG_ENDIAN_DESC
select USB_EHCI_BIG_ENDIAN_MMIO
select USE_OF
help
This enables support for the MIPS Technologies SEAD3 evaluation
board.
config NEC_MARKEINS
bool "NEC EMMA2RH Mark-eins board"
select SOC_EMMA2RH
@ -988,6 +1005,7 @@ source "arch/mips/ath79/Kconfig"
source "arch/mips/bcm47xx/Kconfig"
source "arch/mips/bcm63xx/Kconfig"
source "arch/mips/bmips/Kconfig"
source "arch/mips/generic/Kconfig"
source "arch/mips/jazz/Kconfig"
source "arch/mips/jz4740/Kconfig"
source "arch/mips/lantiq/Kconfig"
@ -1098,6 +1116,10 @@ config DMA_MAYBE_COHERENT
select DMA_NONCOHERENT
bool
config DMA_PERDEV_COHERENT
bool
select DMA_MAYBE_COHERENT
config DMA_COHERENT
bool
@ -1401,6 +1423,16 @@ config CPU_LOONGSON1B
The Loongson 1B is a 32-bit SoC, which implements the MIPS32
release 2 instruction set.
config CPU_LOONGSON1C
bool "Loongson 1C"
depends on SYS_HAS_CPU_LOONGSON1C
select CPU_LOONGSON1
select ARCH_WANT_OPTIONAL_GPIOLIB
select LEDS_GPIO_REGISTER
help
The Loongson 1C is a 32-bit SoC, which implements the MIPS32
release 2 instruction set.
config CPU_MIPS32_R1
bool "MIPS32 Release 1"
depends on SYS_HAS_CPU_MIPS32_R1
@ -1850,6 +1882,9 @@ config SYS_HAS_CPU_LOONGSON2F
config SYS_HAS_CPU_LOONGSON1B
bool
config SYS_HAS_CPU_LOONGSON1C
bool
config SYS_HAS_CPU_MIPS32_R1
bool
@ -2906,7 +2941,7 @@ endchoice
choice
prompt "Kernel command line type" if !CMDLINE_OVERRIDE
default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
!MIPS_MALTA && !MIPS_SEAD3 && \
!MIPS_MALTA && \
!CAVIUM_OCTEON_SOC
default MIPS_CMDLINE_FROM_BOOTLOADER
@ -2960,7 +2995,6 @@ config PCI
bool "Support for PCI controller"
depends on HW_HAS_PCI
select PCI_DOMAINS
select NO_GENERIC_PCI_IOPORT_MAP
help
Find out whether you have a PCI motherboard. PCI is the name of a
bus system, i.e. the way the CPU talks to the other stuff inside
@ -2981,6 +3015,17 @@ config HT_PCI
config PCI_DOMAINS
bool
config PCI_DOMAINS_GENERIC
bool
config PCI_DRIVERS_GENERIC
select PCI_DOMAINS_GENERIC if PCI_DOMAINS
bool
config PCI_DRIVERS_LEGACY
def_bool !PCI_DRIVERS_GENERIC
select NO_GENERIC_PCI_IOPORT_MAP
source "drivers/pci/Kconfig"
#

77
arch/mips/Makefile

@ -262,7 +262,14 @@ KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y)
KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)
bootvars-y = VMLINUX_LOAD_ADDRESS=$(load-y) \
VMLINUX_ENTRY_ADDRESS=$(entry-y)
VMLINUX_ENTRY_ADDRESS=$(entry-y) \
PLATFORM=$(platform-y)
ifdef CONFIG_32BIT
bootvars-y += ADDR_BITS=32
endif
ifdef CONFIG_64BIT
bootvars-y += ADDR_BITS=64
endif
LDFLAGS += -m $(ld-emul)
@ -302,6 +309,11 @@ boot-y += uImage.gz
boot-y += uImage.lzma
boot-y += uImage.lzo
endif
boot-y += vmlinux.itb
boot-y += vmlinux.gz.itb
boot-y += vmlinux.bz2.itb
boot-y += vmlinux.lzma.itb
boot-y += vmlinux.lzo.itb
# compressed boot image targets (arch/mips/boot/compressed/)
bootz-y := vmlinuz
@ -425,4 +437,67 @@ define archhelp
echo ' dtbs_install - Install dtbs to $(INSTALL_DTBS_PATH)'
echo
echo ' These will be default as appropriate for a configured platform.'
echo
echo ' If you are targeting a system supported by generic kernels you may'
echo ' configure the kernel for a given architecture target like so:'
echo
echo ' {micro32,32,64}{r1,r2,r6}{el,}_defconfig <BOARDS="list of boards">'
echo
echo ' Otherwise, the following default configurations are available:'
endef
generic_config_dir = $(srctree)/arch/$(ARCH)/configs/generic
generic_defconfigs :=
#
# If the user generates a generic kernel configuration without specifying a
# list of boards to include the config fragments for, default to including all
# available board config fragments.
#
ifeq ($(BOARDS),)
BOARDS = $(patsubst board-%.config,%,$(notdir $(wildcard $(generic_config_dir)/board-*.config)))
endif
#
# Generic kernel configurations which merge generic_defconfig with the
# appropriate config fragments from arch/mips/configs/generic/, resulting in
# the ability to easily configure the kernel for a given architecture,
# endianness & set of boards without duplicating the needed configuration in
# hundreds of defconfig files.
#
define gen_generic_defconfigs
$(foreach bits,$(1),$(foreach rev,$(2),$(foreach endian,$(3),
target := $(bits)$(rev)$(filter el,$(endian))_defconfig
generic_defconfigs += $$(target)
$$(target): $(generic_config_dir)/$(bits)$(rev).config
$$(target): $(generic_config_dir)/$(endian).config
)))
endef
$(eval $(call gen_generic_defconfigs,32 64,r1 r2 r6,eb el))
$(eval $(call gen_generic_defconfigs,micro32,r2,eb el))
.PHONY: $(generic_defconfigs)
$(generic_defconfigs):
$(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh \
-m -O $(objtree) $(srctree)/arch/$(ARCH)/configs/generic_defconfig $^ \
$(foreach board,$(BOARDS),$(generic_config_dir)/board-$(board).config)
$(Q)$(MAKE) olddefconfig
#
# Prevent generic merge_config rules attempting to merge single fragments
#
$(generic_config_dir)/%.config: ;
#
# Legacy defconfig compatibility - these targets used to be real defconfigs but
# now that the boards have been converted to use the generic kernel they are
# wrappers around the generic rules above.
#
.PHONY: sead3_defconfig
sead3_defconfig:
$(Q)$(MAKE) 32r2el_defconfig BOARDS=sead-3
.PHONY: sead3micro_defconfig
sead3micro_defconfig:
$(Q)$(MAKE) micro32r2el_defconfig BOARDS=sead-3

6
arch/mips/alchemy/common/setup.c

@ -48,17 +48,17 @@ void __init plat_mem_setup(void)
clear_c0_config(1 << 19); /* Clear Config[OD] */
hw_coherentio = 0;
coherentio = 1;
coherentio = IO_COHERENCE_ENABLED;
switch (alchemy_get_cputype()) {
case ALCHEMY_CPU_AU1000:
case ALCHEMY_CPU_AU1500:
case ALCHEMY_CPU_AU1100:
coherentio = 0;
coherentio = IO_COHERENCE_DISABLED;
break;
case ALCHEMY_CPU_AU1200:
/* Au1200 AB USB does not support coherent memory */
if (0 == (read_c0_prid() & PRID_REV_MASK))
coherentio = 0;
coherentio = IO_COHERENCE_DISABLED;
break;
}

11
arch/mips/bcm47xx/serial.c

@ -1,4 +1,7 @@
/*
* 8250 UART probe driver for the BCM47XX platforms
* Author: Aurelien Jarno
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
@ -6,7 +9,6 @@
* Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
@ -88,9 +90,4 @@ static int __init uart8250_init(void)
}
return -EINVAL;
}
module_init(uart8250_init);
MODULE_AUTHOR("Aurelien Jarno <aurelien@aurel32.net>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("8250 UART probe driver for the BCM47XX platforms");
device_initcall(uart8250_init);

3
arch/mips/bcm63xx/clk.c

@ -326,6 +326,9 @@ EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
if (!clk)
return;
mutex_lock(&clocks_mutex);
clk_disable_unlocked(clk);
mutex_unlock(&clocks_mutex);

20
arch/mips/bmips/Kconfig

@ -21,10 +21,6 @@ config DT_BCM93384WVG_VIPER
bool "BCM93384WVG Viper CPU (EXPERIMENTAL)"
select BUILTIN_DTB
config DT_BCM96358NB4SER
bool "BCM96358NB4SER"
select BUILTIN_DTB
config DT_BCM96368MVWG
bool "BCM96368MVWG"
select BUILTIN_DTB
@ -65,6 +61,22 @@ config DT_BCM97435SVMB
bool "BCM97435SVMB"
select BUILTIN_DTB
config DT_COMTREND_VR3032U
bool "Comtrend VR-3032u"
select BUILTIN_DTB
config DT_NETGEAR_CVG834G
bool "NETGEAR CVG834G"
select BUILTIN_DTB
config DT_SFR_NEUFBOX4_SERCOMM
bool "SFR Neufbox 4 (Sercomm)"
select BUILTIN_DTB
config DT_SFR_NEUFBOX6_SERCOMM
bool "SFR Neufbox 6 (Sercomm)"
select BUILTIN_DTB
endchoice
endif

12
arch/mips/bmips/setup.c

@ -17,6 +17,7 @@
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/of_platform.h>
#include <linux/libfdt.h>
#include <linux/smp.h>
#include <asm/addrspace.h>
#include <asm/bmips.h>
@ -98,7 +99,7 @@ static void bcm6328_quirks(void)
static void bcm6358_quirks(void)
{
/*
* BCM6358 needs special handling for its shared TLB, so
* BCM3368/BCM6358 need special handling for their shared TLB, so
* disable SMP for now
*/
bmips_smp_enabled = 0;
@ -110,10 +111,12 @@ static void bcm6368_quirks(void)
}
static const struct bmips_quirk bmips_quirk_list[] = {
{ "brcm,bcm3368", &bcm6358_quirks },
{ "brcm,bcm3384-viper", &bcm3384_viper_quirks },
{ "brcm,bcm33843-viper", &bcm3384_viper_quirks },
{ "brcm,bcm6328", &bcm6328_quirks },
{ "brcm,bcm6358", &bcm6358_quirks },
{ "brcm,bcm6362", &bcm6368_quirks },
{ "brcm,bcm6368", &bcm6368_quirks },
{ "brcm,bcm63168", &bcm6368_quirks },
{ "brcm,bcm63268", &bcm6368_quirks },
@ -150,6 +153,8 @@ void __init plat_time_init(void)
mips_hpt_frequency = freq;
}
extern const char __appended_dtb;
void __init plat_mem_setup(void)
{
void *dtb;
@ -159,6 +164,11 @@ void __init plat_mem_setup(void)
ioport_resource.start = 0;
ioport_resource.end = ~0;
#ifdef CONFIG_MIPS_ELF_APPENDED_DTB
if (!fdt_check_header(&__appended_dtb))
dtb = (void *)&__appended_dtb;
else
#endif
/* intended to somewhat resemble ARM; see Documentation/arm/Booting */
if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
dtb = phys_to_virt(fw_arg2);

66
arch/mips/boot/Makefile

@ -100,3 +100,69 @@ $(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo FORCE
$(obj)/uImage: $(obj)/uImage.$(suffix-y)
@ln -sf $(notdir $<) $@
@echo ' Image $@ is ready'
#
# Flattened Image Tree (.itb) images
#
targets += vmlinux.itb
targets += vmlinux.gz.itb
targets += vmlinux.bz2.itb
targets += vmlinux.lzma.itb
targets += vmlinux.lzo.itb
ifeq ($(ADDR_BITS),32)
itb_addr_cells = 1
endif
ifeq ($(ADDR_BITS),64)
itb_addr_cells = 2
endif
quiet_cmd_cpp_its_S = ITS $@
cmd_cpp_its_S = $(CPP) $(cpp_flags) -P -C -o $@ $< \
-DKERNEL_NAME="\"Linux $(KERNELRELEASE)\"" \
-DVMLINUX_BINARY="\"$(3)\"" \
-DVMLINUX_COMPRESSION="\"$(2)\"" \
-DVMLINUX_LOAD_ADDRESS=$(VMLINUX_LOAD_ADDRESS) \
-DVMLINUX_ENTRY_ADDRESS=$(VMLINUX_ENTRY_ADDRESS) \
-DADDR_BITS=$(ADDR_BITS) \
-DADDR_CELLS=$(itb_addr_cells)
$(obj)/vmlinux.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S FORCE
$(call if_changed_dep,cpp_its_S,none,vmlinux.bin)
$(obj)/vmlinux.gz.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S FORCE
$(call if_changed_dep,cpp_its_S,gzip,vmlinux.bin.gz)
$(obj)/vmlinux.bz2.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S FORCE
$(call if_changed_dep,cpp_its_S,bzip2,vmlinux.bin.bz2)
$(obj)/vmlinux.lzma.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S FORCE
$(call if_changed_dep,cpp_its_S,lzma,vmlinux.bin.lzma)
$(obj)/vmlinux.lzo.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S FORCE
$(call if_changed_dep,cpp_its_S,lzo,vmlinux.bin.lzo)
quiet_cmd_itb-image = ITB $@
cmd_itb-image = \
env PATH="$(objtree)/scripts/dtc:$(PATH)" \
$(CONFIG_SHELL) $(MKIMAGE) \
-D "-I dts -O dtb -p 500 \
--include $(objtree)/arch/mips \
--warning no-unit_address_vs_reg" \
-f $(2) $@
$(obj)/vmlinux.itb: $(obj)/vmlinux.its $(obj)/vmlinux.bin FORCE
$(call if_changed,itb-image,$<)
$(obj)/vmlinux.gz.itb: $(obj)/vmlinux.gz.its $(obj)/vmlinux.bin.gz FORCE
$(call if_changed,itb-image,$<)
$(obj)/vmlinux.bz2.itb: $(obj)/vmlinux.bz2.its $(obj)/vmlinux.bin.bz2 FORCE
$(call if_changed,itb-image,$<)
$(obj)/vmlinux.lzma.itb: $(obj)/vmlinux.lzma.its $(obj)/vmlinux.bin.lzma FORCE
$(call if_changed,itb-image,$<)
$(obj)/vmlinux.lzo.itb: $(obj)/vmlinux.lzo.its $(obj)/vmlinux.bin.lzo FORCE
$(call if_changed,itb-image,$<)

36
arch/mips/boot/dts/brcm/Makefile

@ -1,6 +1,5 @@
dtb-$(CONFIG_DT_BCM93384WVG) += bcm93384wvg.dtb
dtb-$(CONFIG_DT_BCM93384WVG_VIPER) += bcm93384wvg_viper.dtb
dtb-$(CONFIG_DT_BCM96358NB4SER) += bcm96358nb4ser.dtb
dtb-$(CONFIG_DT_BCM96368MVWG) += bcm96368mvwg.dtb
dtb-$(CONFIG_DT_BCM9EJTAGPRB) += bcm9ejtagprb.dtb
dtb-$(CONFIG_DT_BCM97125CBMB) += bcm97125cbmb.dtb
@ -11,20 +10,29 @@ dtb-$(CONFIG_DT_BCM97362SVMB) += bcm97362svmb.dtb
dtb-$(CONFIG_DT_BCM97420C) += bcm97420c.dtb
dtb-$(CONFIG_DT_BCM97425SVMB) += bcm97425svmb.dtb
dtb-$(CONFIG_DT_BCM97435SVMB) += bcm97435svmb.dtb
dtb-$(CONFIG_DT_COMTREND_VR3032U) += bcm63268-comtrend-vr-3032u.dtb
dtb-$(CONFIG_DT_NETGEAR_CVG834G) += bcm3368-netgear-cvg834g.dtb
dtb-$(CONFIG_DT_SFR_NEUFBOX4_SERCOMM) += bcm6358-neufbox4-sercomm.dtb
dtb-$(CONFIG_DT_SFR_NEUFBOX6_SERCOMM) += bcm6362-neufbox6-sercomm.dtb
dtb-$(CONFIG_DT_NONE) += \
bcm93384wvg.dtb \
bcm93384wvg_viper.dtb \
bcm96358nb4ser.dtb \
bcm96368mvwg.dtb \
bcm9ejtagprb.dtb \
bcm97125cbmb.dtb \
bcm97346dbsmb.dtb \
bcm97358svmb.dtb \
bcm97360svmb.dtb \
bcm97362svmb.dtb \
bcm97420c.dtb \
bcm97425svmb.dtb
dtb-$(CONFIG_DT_NONE) += \
bcm3368-netgear-cvg834g.dtb \
bcm6358-neufbox4-sercomm.dtb \
bcm6362-neufbox6-sercomm.dtb \
bcm63268-comtrend-vr-3032u.dtb \
bcm93384wvg.dtb \
bcm93384wvg_viper.dtb \
bcm96358nb4ser.dtb \
bcm96368mvwg.dtb \
bcm9ejtagprb.dtb \
bcm97125cbmb.dtb \
bcm97346dbsmb.dtb \
bcm97358svmb.dtb \
bcm97360svmb.dtb \
bcm97362svmb.dtb \
bcm97420c.dtb \
bcm97425svmb.dtb \
bcm97435svmb.dtb
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))

22
arch/mips/boot/dts/brcm/bcm3368-netgear-cvg834g.dts

@ -0,0 +1,22 @@
/dts-v1/;
/include/ "bcm3368.dtsi"
/ {
compatible = "netgear,cvg834g", "brcm,bcm3368";
model = "NETGEAR CVG834G";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x02000000>;
};
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = &uart0;
};
};
&uart0 {
status = "okay";
};

101
arch/mips/boot/dts/brcm/bcm3368.dtsi

@ -0,0 +1,101 @@
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm3368";
cpus {
#address-cells = <1>;
#size-cells = <0>;
mips-hpt-frequency = <150000000>;
cpu@0 {
compatible = "brcm,bmips4350";
device_type = "cpu";
reg = <0>;
};
cpu@1 {
compatible = "brcm,bmips4350";
device_type = "cpu";
reg = <1>;
};
};
clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
};
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
cpu_intc: interrupt-controller {
#address-cells = <0>;
compatible = "mti,cpu-interrupt-controller";
interrupt-controller;
#interrupt-cells = <1>;
};
ubus {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
periph_cntl: syscon@fff8c000 {
compatible = "syscon";
reg = <0xfff8c000 0xc>;
native-endian;
};
reboot: syscon-reboot@fff8c008 {
compatible = "syscon-reboot";
regmap = <&periph_cntl>;
offset = <0x8>;
mask = <0x1>;
};
periph_intc: interrupt-controller@fff8c00c {
compatible = "brcm,bcm6345-l1-intc";
reg = <0xfff8c00c 0x8>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>;
};
uart0: serial@fff8c100 {
compatible = "brcm,bcm6345-uart";
reg = <0xfff8c100 0x18>;
interrupt-parent = <&periph_intc>;
interrupts = <2>;
clocks = <&periph_clk>;
status = "disabled";
};
uart1: serial@fff8c120 {
compatible = "brcm,bcm6345-uart";
reg = <0xfff8c120 0x18>;
interrupt-parent = <&periph_intc>;
interrupts = <3>;
clocks = <&periph_clk>;
status = "disabled";
};
};
};

108
arch/mips/boot/dts/brcm/bcm63268-comtrend-vr-3032u.dts

@ -0,0 +1,108 @@
/dts-v1/;
/include/ "bcm63268.dtsi"
/ {
compatible = "comtrend,vr-3032u", "brcm,bcm63268";
model = "Comtrend VR-3032u";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x04000000>;
};
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = &uart0;
};
};
&leds0 {
status = "ok";
brcm,serial-leds;
brcm,serial-dat-low;
brcm,serial-shift-inv;
led@0 {
reg = <0>;
brcm,hardware-controlled;
brcm,link-signal-sources = <0>;
/* GPHY0 Speed 0 */
};
led@1 {
reg = <1>;
brcm,hardware-controlled;
brcm,link-signal-sources = <1>;
/* GPHY0 Speed 1 */
};
led@2 {
reg = <2>;
active-low;
label = "vr-3032u:red:inet";
};
led@3 {
reg = <3>;
active-low;
label = "vr-3032u:green:dsl";
};
led@4 {
reg = <4>;
active-low;
label = "vr-3032u:green:usb";
};
led@7 {
reg = <7>;
active-low;
label = "vr-3032u:green:wps";
};
led@8 {
reg = <8>;
active-low;
label = "vr-3032u:green:inet";
};
led@9 {
reg = <9>;
brcm,hardware-controlled;
/* EPHY0 Activity */
};
led@10 {
reg = <10>;
brcm,hardware-controlled;
/* EPHY1 Activity */
};
led@11 {
reg = <11>;
brcm,hardware-controlled;
/* EPHY2 Activity */
};
led@12 {
reg = <12>;
brcm,hardware-controlled;
/* GPHY0 Activity */
};
led@13 {
reg = <13>;
brcm,hardware-controlled;
/* EPHY0 Speed */
};
led@14 {
reg = <14>;
brcm,hardware-controlled;
/* EPHY1 Speed */
};
led@15 {
reg = <15>;
brcm,hardware-controlled;
/* EPHY2 Speed */
};
led@20 {
reg = <20>;
active-low;
label = "vr-3032u:green:power";
default-state = "on";
};
};
&uart0 {
status = "okay";
};

134
arch/mips/boot/dts/brcm/bcm63268.dtsi

@ -0,0 +1,134 @@
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm63268";
cpus {
#address-cells = <1>;
#size-cells = <0>;
mips-hpt-frequency = <200000000>;
cpu@0 {
compatible = "brcm,bmips4350";
device_type = "cpu";
reg = <0>;
};
cpu@1 {
compatible = "brcm,bmips4350";
device_type = "cpu";
reg = <1>;
};
};
clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
};
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
cpu_intc: interrupt-controller {
#address-cells = <0>;
compatible = "mti,cpu-interrupt-controller";
interrupt-controller;
#interrupt-cells = <1>;
};
ubus {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
periph_cntl: syscon@10000000 {
compatible = "syscon";
reg = <0x10000000 0x14>;
native-endian;
};
reboot: syscon-reboot@10000008 {
compatible = "syscon-reboot";
regmap = <&periph_cntl>;
offset = <0x8>;
mask = <0x1>;
};
periph_intc: interrupt-controller@10000020 {
compatible = "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x20>,
<0x10000040 0x20>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>, <3>;
};
uart0: serial@10000180 {
compatible = "brcm,bcm6345-uart";
reg = <0x10000180 0x18>;
interrupt-parent = <&periph_intc>;
interrupts = <5>;
clocks = <&periph_clk>;
status = "disabled";
};
uart1: serial@100001a0 {
compatible = "brcm,bcm6345-uart";
reg = <0x100001a0 0x18>;
interrupt-parent = <&periph_intc>;
interrupts = <34>;
clocks = <&periph_clk>;
status = "disabled";
};
leds0: led-controller@10001900 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,bcm6328-leds";
reg = <0x10001900 0x24>;
status = "disabled";
};
ehci: usb@10002500 {
compatible = "brcm,bcm63268-ehci", "generic-ehci";
reg = <0x10002500 0x100>;
big-endian;
interrupt-parent = <&periph_intc>;
interrupts = <10>;
status = "disabled";
};
ohci: usb@10002600 {
compatible = "brcm,bcm63268-ohci", "generic-ohci";
reg = <0x10002600 0x100>;
big-endian;
no-big-frame-no;
interrupt-parent = <&periph_intc>;
interrupts = <9>;
status = "disabled";
};
};
};

1
arch/mips/boot/dts/brcm/bcm96358nb4ser.dts → arch/mips/boot/dts/brcm/bcm6358-neufbox4-sercomm.dts

@ -12,6 +12,7 @@
};
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = &uart0;
};
};

22
arch/mips/boot/dts/brcm/bcm6362-neufbox6-sercomm.dts

@ -0,0 +1,22 @@
/dts-v1/;
/include/ "bcm6362.dtsi"
/ {
compatible = "sfr,nb6-ser", "brcm,bcm6362";
model = "SFR NeufBox 6 (Sercomm)";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = &uart0;
};
};
&uart0 {
status = "okay";
};

134
arch/mips/boot/dts/brcm/bcm6362.dtsi

@ -0,0 +1,134 @@
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm6362";
cpus {
#address-cells = <1>;
#size-cells = <0>;
mips-hpt-frequency = <200000000>;
cpu@0 {
compatible = "brcm,bmips4350";
device_type = "cpu";
reg = <0>;
};
cpu@1 {
compatible = "brcm,bmips4350";
device_type = "cpu";
reg = <1>;
};
};
clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
};
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
cpu_intc: interrupt-controller {
#address-cells = <0>;
compatible = "mti,cpu-interrupt-controller";
interrupt-controller;
#interrupt-cells = <1>;
};
ubus {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
periph_cntl: syscon@10000000 {
compatible = "syscon";
reg = <0x10000000 0x14>;
native-endian;
};
reboot: syscon-reboot@10000008 {
compatible = "syscon-reboot";
regmap = <&periph_cntl>;
offset = <0x8>;
mask = <0x1>;
};
periph_intc: interrupt-controller@10000020 {
compatible = "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x10>,
<0x10000030 0x10>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>, <3>;
};
uart0: serial@10000100 {
compatible = "brcm,bcm6345-uart";
reg = <0x10000100 0x18>;
interrupt-parent = <&periph_intc>;
interrupts = <3>;
clocks = <&periph_clk>;
status = "disabled";
};
uart1: serial@10000120 {
compatible = "brcm,bcm6345-uart";
reg = <0x10000120 0x18>;
interrupt-parent = <&periph_intc>;
interrupts = <4>;
clocks = <&periph_clk>;
status = "disabled";
};
leds0: led-controller@10001900 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,bcm6328-leds";
reg = <0x10001900 0x24>;
status = "disabled";
};
ehci: usb@10002500 {
compatible = "brcm,bcm6362-ehci", "generic-ehci";
reg = <0x10002500 0x100>;
big-endian;
interrupt-parent = <&periph_intc>;
interrupts = <10>;
status = "disabled";
};
ohci: usb@10002600 {
compatible = "brcm,bcm6362-ohci", "generic-ohci";
reg = <0x10002600 0x100>;
big-endian;
no-big-frame-no;
interrupt-parent = <&periph_intc>;
interrupts = <9>;
status = "disabled";
};
};
};

34
arch/mips/boot/dts/brcm/bcm7125.dtsi

@ -26,7 +26,7 @@
uart0 = &uart0;
};
cpu_intc: cpu_intc {
cpu_intc: interrupt-controller {
#address-cells = <0>;
compatible = "mti,cpu-interrupt-controller";
@ -40,6 +40,12 @@
#clock-cells = <0>;
clock-frequency = <81000000>;
};
upg_clk: upg_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
rdb {
@ -49,7 +55,7 @@
compatible = "simple-bus";
ranges = <0 0x10000000 0x01000000>;
periph_intc: periph_intc@441400 {
periph_intc: interrupt-controller@441400 {
compatible = "brcm,bcm7038-l1-intc";
reg = <0x441400 0x30>, <0x441600 0x30>;
@ -60,7 +66,7 @@
interrupts = <2>, <3>;
};
sun_l2_intc: sun_l2_intc@401800 {
sun_l2_intc: interrupt-controller@401800 {
compatible = "brcm,l2-intc";
reg = <0x401800 0x30>;
interrupt-controller;
@ -81,7 +87,7 @@
"avd_0", "jtag_0";
};
upg_irq0_intc: upg_irq0_intc@406780 {
upg_irq0_intc: interrupt-controller@406780 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x406780 0x8>;
@ -183,6 +189,26 @@
status = "disabled";
};
pwma: pwm@406580 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406580 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
upg_gio: gpio@406700 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406700 0x80>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
interrupt-parent = <&upg_irq0_intc>;
interrupts = <6>;
brcm,gpio-bank-widths = <32 32 32 18>;
};
ehci0: usb@488300 {
compatible = "brcm,bcm7125-ehci", "generic-ehci";
reg = <0x488300 0x100>;

97
arch/mips/boot/dts/brcm/bcm7346.dtsi

@ -26,7 +26,7 @@
uart0 = &uart0;
};
cpu_intc: cpu_intc {
cpu_intc: interrupt-controller {
#address-cells = <0>;
compatible = "mti,cpu-interrupt-controller";
@ -40,6 +40,12 @@
#clock-cells = <0>;
clock-frequency = <81000000>;
};
upg_clk: upg_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
rdb {
@ -49,7 +55,7 @@
compatible = "simple-bus";
ranges = <0 0x10000000 0x01000000>;
periph_intc: periph_intc@411400 {
periph_intc: interrupt-controller@411400 {
compatible = "brcm,bcm7038-l1-intc";
reg = <0x411400 0x30>, <0x411600 0x30>;
@ -60,7 +66,7 @@
interrupts = <2>, <3>;
};
sun_l2_intc: sun_l2_intc@403000 {
sun_l2_intc: interrupt-controller@403000 {
compatible = "brcm,l2-intc";
reg = <0x403000 0x30>;
interrupt-controller;
@ -81,7 +87,7 @@
"jtag_0", "svd_0";
};
upg_irq0_intc: upg_irq0_intc@406780 {
upg_irq0_intc: interrupt-controller@406780 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x406780 0x8>;
@ -96,7 +102,7 @@
interrupt-names = "upg_main", "upg_bsc";
};
upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
upg_aon_irq0_intc: interrupt-controller@408b80 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x408b80 0x8>;
@ -210,6 +216,59 @@
status = "disabled";
};
pwma: pwm@406580 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406580 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
pwmb: pwm@406800 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406800 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
aon_pm_l2_intc: interrupt-controller@408440 {
compatible = "brcm,l2-intc";
reg = <0x408440 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <53>;
brcm,irq-can-wake;
};
upg_gio: gpio@406700 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406700 0x60>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
interrupt-parent = <&upg_irq0_intc>;
interrupts = <6>;
brcm,gpio-bank-widths = <32 32 16>;
};
upg_gio_aon: gpio@408c00 {
compatible = "brcm,brcmstb-gpio";
reg = <0x408c00 0x60>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
interrupt-parent = <&upg_aon_irq0_intc>;
interrupts = <6>;
interrupts-extended = <&upg_aon_irq0_intc 6>,
<&aon_pm_l2_intc 5>;
wakeup-source;
brcm,gpio-bank-widths = <27 32 2>;
};
enet0: ethernet@430000 {
phy-mode = "internal";
phy-handle = <&phy1>;
@ -313,6 +372,26 @@
status = "disabled";
};
hif_l2_intc: interrupt-controller@411000 {
compatible = "brcm,l2-intc";
reg = <0x411000 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <30>;
};
nand: nand@412800 {
compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "nand";
reg = <0x412800 0x400>;
interrupt-parent = <&hif_l2_intc>;
interrupts = <24>;
status = "disabled";
};
sata: sata@181000 {
compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
reg-names = "ahci", "top-ctrl";
@ -352,5 +431,13 @@
#phy-cells = <0>;
};
};
sdhci0: sdhci@413500 {
compatible = "brcm,bcm7425-sdhci";
reg = <0x413500 0x100>;
interrupt-parent = <&periph_intc>;
interrupts = <85>;
status = "disabled";
};
};
};

89
arch/mips/boot/dts/brcm/bcm7358.dtsi

@ -20,7 +20,7 @@
uart0 = &uart0;
};
cpu_intc: cpu_intc {
cpu_intc: interrupt-controller {
#address-cells = <0>;
compatible = "mti,cpu-interrupt-controller";
@ -34,6 +34,12 @@
#clock-cells = <0>;
clock-frequency = <81000000>;
};
upg_clk: upg_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
rdb {
@ -43,7 +49,7 @@
compatible = "simple-bus";
ranges = <0 0x10000000 0x01000000>;
periph_intc: periph_intc@411400 {
periph_intc: interrupt-controller@411400 {
compatible = "brcm,bcm7038-l1-intc";
reg = <0x411400 0x30>;
@ -54,7 +60,7 @@
interrupts = <2>;
};
sun_l2_intc: sun_l2_intc@403000 {
sun_l2_intc: interrupt-controller@403000 {
compatible = "brcm,l2-intc";
reg = <0x403000 0x30>;
interrupt-controller;
@ -75,7 +81,7 @@
"avd_0", "jtag_0";
};
upg_irq0_intc: upg_irq0_intc@406600 {
upg_irq0_intc: interrupt-controller@406600 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x406600 0x8>;
@ -90,7 +96,7 @@
interrupt-names = "upg_main", "upg_bsc";
};
upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
upg_aon_irq0_intc: interrupt-controller@408b80 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x408b80 0x8>;
@ -194,6 +200,59 @@
status = "disabled";
};
pwma: pwm@406400 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406400 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
pwmb: pwm@406700 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406700 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
aon_pm_l2_intc: interrupt-controller@408240 {
compatible = "brcm,l2-intc";
reg = <0x408240 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <50>;
brcm,irq-can-wake;
};
upg_gio: gpio@406500 {
compatible = "brcm,brcmstb-gpio";
reg = <0x406500 0xa0>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
interrupt-parent = <&upg_irq0_intc>;
interrupts = <6>;
brcm,gpio-bank-widths = <32 32 32 29 4>;
};
upg_gio_aon: gpio@408c00 {
compatible = "brcm,brcmstb-gpio";
reg = <0x408c00 0x60>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
interrupt-parent = <&upg_aon_irq0_intc>;
interrupts = <6>;
interrupts-extended = <&upg_aon_irq0_intc 6>,
<&aon_pm_l2_intc 5>;
wakeup-source;
brcm,gpio-bank-widths = <21 32 2>;
};
enet0: ethernet@430000 {
phy-mode = "internal";
phy-handle = <&phy1>;
@ -239,5 +298,25 @@
interrupts = <66>;
status = "disabled";
};
hif_l2_intc: interrupt-controller@411000 {
compatible = "brcm,l2-intc";
reg = <0x411000 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <30>;
};
nand: nand@412800 {
compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "nand";
reg = <0x412800 0x400>;
interrupt-parent = <&hif_l2_intc>;
interrupts = <24>;
status = "disabled";
};
};
};

89
arch/mips/boot/dts/brcm/bcm7360.dtsi

@ -20,7 +20,7 @@
uart0 = &uart0;
};
cpu_intc: cpu_intc {
cpu_intc: interrupt-controller {
#address-cells = <0>;
compatible = "mti,cpu-interrupt-controller";
@ -34,6 +34,12 @@
#clock-cells = <0>;
clock-frequency = <81000000>;
};
upg_clk: upg_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
rdb {
@ -43,7 +49,7 @@
compatible = "simple-bus";
ranges = <0 0x10000000 0x01000000>;
periph_intc: periph_intc@411400 {
periph_intc: interrupt-controller@411400 {
compatible = "brcm,bcm7038-l1-intc";
reg = <0x411400 0x30>;