24 lines
905 B
Diff
24 lines
905 B
Diff
commit 930469634910fa87c21f0a7423c98b270d35d8c6
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Author: Eric Anholt <eric@anholt.net>
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Date: Mon Sep 15 13:13:34 2008 -0700
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drm: G33-class hardware has a newer 965-style MCH (no DCC register).
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Fixes bad software fallback rendering in Mesa in dual-channel configurations.
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d9a2470012588dc5313a5ac8bb2f03575af00e99
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diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
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index 0c1b3a0..6b3f1e4 100644
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--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
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+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
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@@ -96,7 +96,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
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*/
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swizzle_x = I915_BIT_6_SWIZZLE_NONE;
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swizzle_y = I915_BIT_6_SWIZZLE_NONE;
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- } else if (!IS_I965G(dev) || IS_I965GM(dev)) {
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+ } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) {
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uint32_t dcc;
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/* On 915-945 and GM965, channel interleave by the CPU is
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