425 lines
13 KiB
Diff
425 lines
13 KiB
Diff
commit 4f99970852559935b27bc634318f34c18c5fd143
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Author: Eric Anholt <eric@anholt.net>
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Date: Tue Jul 29 12:10:39 2008 -0700
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i915: Add support for MSI and interrupt mitigation.
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Previous attempts at interrupt mitigation had been foiled by i915_wait_irq's
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failure to update the sarea seqno value when the status page indicated that
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the seqno had already been passed. MSI support has been seen to cut CPU
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costs by up to 40% in some workloads by avoiding other expensive interrupt
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handlers for frequent graphics interrupts.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Dave Airlie <airlied@redhat.com>
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diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
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index 53f0e5a..61ed515 100644
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--- a/drivers/gpu/drm/drm_irq.c
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+++ b/drivers/gpu/drm/drm_irq.c
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@@ -63,7 +63,7 @@ int drm_irq_by_busid(struct drm_device *dev, void *data,
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p->devnum != PCI_SLOT(dev->pdev->devfn) || p->funcnum != PCI_FUNC(dev->pdev->devfn))
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return -EINVAL;
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- p->irq = dev->irq;
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+ p->irq = dev->pdev->irq;
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DRM_DEBUG("%d:%d:%d => IRQ %d\n", p->busnum, p->devnum, p->funcnum,
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p->irq);
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@@ -89,7 +89,7 @@ static int drm_irq_install(struct drm_device * dev)
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if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
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return -EINVAL;
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- if (dev->irq == 0)
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+ if (dev->pdev->irq == 0)
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return -EINVAL;
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mutex_lock(&dev->struct_mutex);
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@@ -107,7 +107,7 @@ static int drm_irq_install(struct drm_device * dev)
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dev->irq_enabled = 1;
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mutex_unlock(&dev->struct_mutex);
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- DRM_DEBUG("irq=%d\n", dev->irq);
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+ DRM_DEBUG("irq=%d\n", dev->pdev->irq);
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if (drm_core_check_feature(dev, DRIVER_IRQ_VBL)) {
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init_waitqueue_head(&dev->vbl_queue);
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@@ -127,8 +127,12 @@ static int drm_irq_install(struct drm_device * dev)
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if (drm_core_check_feature(dev, DRIVER_IRQ_SHARED))
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sh_flags = IRQF_SHARED;
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- ret = request_irq(dev->irq, dev->driver->irq_handler,
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+ ret = request_irq(dev->pdev->irq, dev->driver->irq_handler,
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sh_flags, dev->devname, dev);
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+ /* Expose the device irq number to drivers that want to export it for
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+ * whatever reason.
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+ */
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+ dev->irq = dev->pdev->irq;
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if (ret < 0) {
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mutex_lock(&dev->struct_mutex);
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dev->irq_enabled = 0;
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@@ -164,11 +168,11 @@ int drm_irq_uninstall(struct drm_device * dev)
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if (!irq_enabled)
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return -EINVAL;
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- DRM_DEBUG("irq=%d\n", dev->irq);
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+ DRM_DEBUG("irq=%d\n", dev->pdev->irq);
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dev->driver->irq_uninstall(dev);
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- free_irq(dev->irq, dev);
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+ free_irq(dev->pdev->irq, dev);
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dev->locked_tasklet_func = NULL;
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@@ -201,7 +205,7 @@ int drm_control(struct drm_device *dev, void *data,
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if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
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return 0;
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if (dev->if_version < DRM_IF_VERSION(1, 2) &&
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- ctl->irq != dev->irq)
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+ ctl->irq != dev->pdev->irq)
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return -EINVAL;
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return drm_irq_install(dev);
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case DRM_UNINST_HANDLER:
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@@ -239,7 +243,7 @@ int drm_wait_vblank(struct drm_device *dev, void *data, struct drm_file *file_pr
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int ret = 0;
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unsigned int flags, seq;
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- if ((!dev->irq) || (!dev->irq_enabled))
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+ if ((!dev->pdev->irq) || (!dev->irq_enabled))
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return -EINVAL;
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if (vblwait->request.type &
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diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
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index 7be580b..10bfb0c 100644
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--- a/drivers/gpu/drm/i915/i915_dma.c
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+++ b/drivers/gpu/drm/i915/i915_dma.c
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@@ -84,7 +84,7 @@ static int i915_dma_cleanup(struct drm_device * dev)
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* may not have been called from userspace and after dev_private
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* is freed, it's too late.
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*/
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- if (dev->irq)
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+ if (dev->irq_enabled)
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drm_irq_uninstall(dev);
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if (dev_priv->ring.virtual_start) {
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@@ -644,7 +644,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
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switch (param->param) {
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case I915_PARAM_IRQ_ACTIVE:
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- value = dev->irq ? 1 : 0;
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+ value = dev->irq_enabled;
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break;
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case I915_PARAM_ALLOW_BATCHBUFFER:
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value = dev_priv->allow_batchbuffer ? 1 : 0;
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@@ -763,6 +763,20 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
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_DRM_KERNEL | _DRM_DRIVER,
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&dev_priv->mmio_map);
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+
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+
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+ /* On the 945G/GM, the chipset reports the MSI capability on the
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+ * integrated graphics even though the support isn't actually there
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+ * according to the published specs. It doesn't appear to function
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+ * correctly in testing on 945G.
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+ * This may be a side effect of MSI having been made available for PEG
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+ * and the registers being closely associated.
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+ */
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+ if (!IS_I945G(dev) && !IS_I945GM(dev))
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+ pci_enable_msi(dev->pdev);
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+
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+ spin_lock_init(&dev_priv->user_irq_lock);
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+
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return ret;
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}
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@@ -770,6 +784,9 @@ int i915_driver_unload(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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+ if (dev->pdev->msi_enabled)
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+ pci_disable_msi(dev->pdev);
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+
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if (dev_priv->mmio_map)
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drm_rmmap(dev, dev_priv->mmio_map);
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diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
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index afb51a3..8daf0d8 100644
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--- a/drivers/gpu/drm/i915/i915_drv.h
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+++ b/drivers/gpu/drm/i915/i915_drv.h
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@@ -105,6 +105,12 @@ typedef struct drm_i915_private {
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wait_queue_head_t irq_queue;
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atomic_t irq_received;
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atomic_t irq_emitted;
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+ /** Protects user_irq_refcount and irq_mask_reg */
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+ spinlock_t user_irq_lock;
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+ /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
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+ int user_irq_refcount;
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+ /** Cached value of IMR to avoid reads in updating the bitfield */
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+ u32 irq_mask_reg;
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int tex_lru_log_granularity;
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int allow_batchbuffer;
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diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
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index 4a2de78..24d11ed 100644
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--- a/drivers/gpu/drm/i915/i915_irq.c
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+++ b/drivers/gpu/drm/i915/i915_irq.c
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@@ -33,6 +33,31 @@
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#define MAX_NOPID ((u32)~0)
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+/** These are the interrupts used by the driver */
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+#define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT | \
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+ I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | \
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+ I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)
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+
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+static inline void
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+i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
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+{
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+ if ((dev_priv->irq_mask_reg & mask) != 0) {
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+ dev_priv->irq_mask_reg &= ~mask;
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+ I915_WRITE(IMR, dev_priv->irq_mask_reg);
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+ (void) I915_READ(IMR);
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+ }
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+}
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+
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+static inline void
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+i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
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+{
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+ if ((dev_priv->irq_mask_reg & mask) != mask) {
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+ dev_priv->irq_mask_reg |= mask;
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+ I915_WRITE(IMR, dev_priv->irq_mask_reg);
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+ (void) I915_READ(IMR);
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+ }
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+}
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+
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/**
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* Emit blits for scheduled buffer swaps.
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*
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@@ -229,46 +254,50 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
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{
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struct drm_device *dev = (struct drm_device *) arg;
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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- u16 temp;
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u32 pipea_stats, pipeb_stats;
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+ u32 iir;
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pipea_stats = I915_READ(PIPEASTAT);
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pipeb_stats = I915_READ(PIPEBSTAT);
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- temp = I915_READ16(IIR);
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-
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- temp &= (I915_USER_INTERRUPT |
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- I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
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- I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT);
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+ if (dev->pdev->msi_enabled)
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+ I915_WRITE(IMR, ~0);
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+ iir = I915_READ(IIR);
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- DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp);
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+ DRM_DEBUG("iir=%08x\n", iir);
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- if (temp == 0)
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+ if (iir == 0) {
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+ if (dev->pdev->msi_enabled) {
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+ I915_WRITE(IMR, dev_priv->irq_mask_reg);
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+ (void) I915_READ(IMR);
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+ }
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return IRQ_NONE;
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+ }
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- I915_WRITE16(IIR, temp);
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- (void) I915_READ16(IIR);
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- DRM_READMEMORYBARRIER();
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+ I915_WRITE(IIR, iir);
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+ if (dev->pdev->msi_enabled)
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+ I915_WRITE(IMR, dev_priv->irq_mask_reg);
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+ (void) I915_READ(IIR); /* Flush posted writes */
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dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
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- if (temp & I915_USER_INTERRUPT)
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+ if (iir & I915_USER_INTERRUPT)
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DRM_WAKEUP(&dev_priv->irq_queue);
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- if (temp & (I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
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- I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)) {
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+ if (iir & (I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
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+ I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)) {
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int vblank_pipe = dev_priv->vblank_pipe;
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if ((vblank_pipe &
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(DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B))
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== (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B)) {
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- if (temp & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT)
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+ if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT)
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atomic_inc(&dev->vbl_received);
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- if (temp & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)
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+ if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)
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atomic_inc(&dev->vbl_received2);
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- } else if (((temp & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) &&
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+ } else if (((iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) &&
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(vblank_pipe & DRM_I915_VBLANK_PIPE_A)) ||
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- ((temp & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) &&
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+ ((iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) &&
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(vblank_pipe & DRM_I915_VBLANK_PIPE_B)))
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atomic_inc(&dev->vbl_received);
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@@ -314,6 +343,27 @@ static int i915_emit_irq(struct drm_device * dev)
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return dev_priv->counter;
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}
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+static void i915_user_irq_get(struct drm_device *dev)
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+{
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+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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+
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+ spin_lock(&dev_priv->user_irq_lock);
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+ if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
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+ i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
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+ spin_unlock(&dev_priv->user_irq_lock);
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+}
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+
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+static void i915_user_irq_put(struct drm_device *dev)
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+{
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+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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+
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+ spin_lock(&dev_priv->user_irq_lock);
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+ BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
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+ if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0))
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+ i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
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+ spin_unlock(&dev_priv->user_irq_lock);
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+}
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+
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static int i915_wait_irq(struct drm_device * dev, int irq_nr)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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@@ -322,13 +372,17 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr)
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DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
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READ_BREADCRUMB(dev_priv));
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- if (READ_BREADCRUMB(dev_priv) >= irq_nr)
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+ if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
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+ dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
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return 0;
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+ }
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dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
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+ i915_user_irq_get(dev);
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DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
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READ_BREADCRUMB(dev_priv) >= irq_nr);
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+ i915_user_irq_put(dev);
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if (ret == -EBUSY) {
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DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
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@@ -413,20 +467,6 @@ int i915_irq_wait(struct drm_device *dev, void *data,
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return i915_wait_irq(dev, irqwait->irq_seq);
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}
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-static void i915_enable_interrupt (struct drm_device *dev)
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-{
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- drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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- u16 flag;
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-
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- flag = 0;
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- if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
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- flag |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
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- if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
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- flag |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
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-
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- I915_WRITE16(IER, I915_USER_INTERRUPT | flag);
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-}
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-
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/* Set the vblank monitor pipe
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*/
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int i915_vblank_pipe_set(struct drm_device *dev, void *data,
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@@ -434,6 +474,7 @@ int i915_vblank_pipe_set(struct drm_device *dev, void *data,
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_i915_vblank_pipe_t *pipe = data;
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+ u32 enable_mask = 0, disable_mask = 0;
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if (!dev_priv) {
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DRM_ERROR("called with no initialization\n");
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@@ -445,9 +486,20 @@ int i915_vblank_pipe_set(struct drm_device *dev, void *data,
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return -EINVAL;
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}
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- dev_priv->vblank_pipe = pipe->pipe;
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+ if (pipe->pipe & DRM_I915_VBLANK_PIPE_A)
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+ enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
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+ else
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+ disable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
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+
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+ if (pipe->pipe & DRM_I915_VBLANK_PIPE_B)
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+ enable_mask |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
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+ else
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+ disable_mask |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
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- i915_enable_interrupt (dev);
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+ i915_enable_irq(dev_priv, enable_mask);
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+ i915_disable_irq(dev_priv, disable_mask);
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+
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+ dev_priv->vblank_pipe = pipe->pipe;
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return 0;
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}
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@@ -464,7 +516,7 @@ int i915_vblank_pipe_get(struct drm_device *dev, void *data,
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return -EINVAL;
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}
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- flag = I915_READ(IER);
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+ flag = I915_READ(IMR);
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pipe->pipe = 0;
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if (flag & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT)
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pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
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@@ -586,9 +638,9 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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- I915_WRITE16(HWSTAM, 0xfffe);
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- I915_WRITE16(IMR, 0x0);
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- I915_WRITE16(IER, 0x0);
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+ I915_WRITE(HWSTAM, 0xfffe);
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+ I915_WRITE(IMR, 0x0);
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+ I915_WRITE(IER, 0x0);
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}
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void i915_driver_irq_postinstall(struct drm_device * dev)
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@@ -601,7 +653,18 @@ void i915_driver_irq_postinstall(struct drm_device * dev)
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if (!dev_priv->vblank_pipe)
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dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
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- i915_enable_interrupt(dev);
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+
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+ /* Set initial unmasked IRQs to just the selected vblank pipes. */
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+ dev_priv->irq_mask_reg = ~0;
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+ if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
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+ dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
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+ if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
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+ dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
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+
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+ I915_WRITE(IMR, dev_priv->irq_mask_reg);
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+ I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
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+ (void) I915_READ(IER);
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+
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DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
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}
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@@ -613,10 +676,10 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
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if (!dev_priv)
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return;
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- I915_WRITE16(HWSTAM, 0xffff);
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- I915_WRITE16(IMR, 0xffff);
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- I915_WRITE16(IER, 0x0);
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+ I915_WRITE(HWSTAM, 0xffff);
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+ I915_WRITE(IMR, 0xffff);
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+ I915_WRITE(IER, 0x0);
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- temp = I915_READ16(IIR);
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- I915_WRITE16(IIR, temp);
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+ temp = I915_READ(IIR);
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+ I915_WRITE(IIR, temp);
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}
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