52 lines
1.7 KiB
Diff
52 lines
1.7 KiB
Diff
From a582b0a53d1dc8604a201348b99ca8de48784e7e Mon Sep 17 00:00:00 2001
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From: jiwang <jiwang@138bc75d-0d04-0410-961f-82ee72b054a4>
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Date: Thu, 12 May 2016 17:00:52 +0000
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Subject: [PATCH] [LRA] PR70904, relax the restriction on subreg reload for
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wide mode
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2016-05-12 Jiong Wang <jiong.wang@arm.com>
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gcc/
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PR rtl-optimization/70904
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* lra-constraint.c (process_addr_reg): Relax the restriction on
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subreg reload for wide mode.
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@236181 138bc75d-0d04-0410-961f-82ee72b054a4
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---
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Upstream-Status: Backport
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Signed-off-by: Khem Raj <raj.khem@gmail.com>
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gcc/lra-constraints.c | 16 +++++++++++++++-
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1 file changed, 15 insertions(+), 1 deletion(-)
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diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
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index f96fd458e23..73fb72a2ea5 100644
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--- a/gcc/lra-constraints.c
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+++ b/gcc/lra-constraints.c
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@@ -1326,7 +1326,21 @@ process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **aft
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subreg_p = GET_CODE (*loc) == SUBREG;
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if (subreg_p)
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- loc = &SUBREG_REG (*loc);
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+ {
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+ reg = SUBREG_REG (*loc);
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+ mode = GET_MODE (reg);
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+
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+ /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
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+ between two registers with different classes, but there normally will
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+ be "mov" which transfers element of vector register into the general
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+ register, and this normally will be a subreg which should be reloaded
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+ as a whole. This is particularly likely to be triggered when
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+ -fno-split-wide-types specified. */
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+ if (in_class_p (reg, cl, &new_class)
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+ || GET_MODE_SIZE (mode) <= GET_MODE_SIZE (ptr_mode))
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+ loc = &SUBREG_REG (*loc);
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+ }
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+
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reg = *loc;
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mode = GET_MODE (reg);
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if (! REG_P (reg))
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--
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2.14.2
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