407 lines
15 KiB
Diff
407 lines
15 KiB
Diff
Upstream-Status: Inappropriate [Backport]
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From 04688242805dcf2a1e9c8948a3d15611d88c1520 Mon Sep 17 00:00:00 2001
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From: nickc <nickc@138bc75d-0d04-0410-961f-82ee72b054a4>
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Date: Tue, 29 Mar 2011 12:27:07 +0000
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Subject: [PATCH 020/200] * config/rx/rx.h (LABEL_ALIGN_AFTER_BARRIER): Define.
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(ASM_OUTPUT_MAX_SKIP): Define.
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* config/rx/predicates.md (rx_zs_comparison_operator): Do not
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allow LT aor GE comparisons.
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* config/rx/rx-protos.h (rx_align_for_label): Prototype.
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* config/rx/rx.md: Add peepholes and patterns to combine extending
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loads with simple arithmetic instructions.
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* config/rx/rx.c (rx_is_legitimate_address): Allow QI and HI modes
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to use pre-decrement and post-increment addressing.
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(rx_is_restricted_memory_address): For REG+INT addressing, ensure
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that the INT is a valid offset.
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(rx_print_operand): Handle %R.
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Fix %Q's handling of MEMs.
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(rx_option_override): Set alignments.
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(rx_align_for_label): New function.
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(rx_max_skip_for_label): New function.
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(TARGET_ASM_JUMP_ALIGN_MAX_SKIP): Define.
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(TARGET_ASM_LOOP_ALIGN_MAX_SKIP): Define.
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(TARGET_ASM_LABEL_ALIGN_MAX_SKIP): Define.
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(TARGET_ASM_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP): Define.
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_6-branch@171659 138bc75d-0d04-0410-961f-82ee72b054a4
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index 77b3353..82cac42 100644
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--- a/gcc/config/rx/predicates.md
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+++ b/gcc/config/rx/predicates.md
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@@ -284,7 +284,7 @@
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)
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(define_predicate "rx_zs_comparison_operator"
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- (match_code "eq,ne,lt,ge")
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+ (match_code "eq,ne")
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)
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;; GT and LE omitted due to operand swap required.
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diff --git a/gcc/config/rx/rx-protos.h b/gcc/config/rx/rx-protos.h
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index a6ae416..e1ab9c2 100644
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--- a/gcc/config/rx/rx-protos.h
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+++ b/gcc/config/rx/rx-protos.h
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@@ -30,16 +30,17 @@ extern void rx_expand_prologue (void);
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extern int rx_initial_elimination_offset (int, int);
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#ifdef RTX_CODE
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+extern int rx_align_for_label (void);
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extern void rx_emit_stack_popm (rtx *, bool);
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extern void rx_emit_stack_pushm (rtx *);
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extern void rx_expand_epilogue (bool);
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extern char * rx_gen_move_template (rtx *, bool);
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extern bool rx_is_legitimate_constant (rtx);
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extern bool rx_is_restricted_memory_address (rtx, Mmode);
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+extern bool rx_match_ccmode (rtx, Mmode);
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extern void rx_notice_update_cc (rtx body, rtx insn);
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extern void rx_split_cbranch (Mmode, Rcode, rtx, rtx, rtx);
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extern Mmode rx_select_cc_mode (Rcode, rtx, rtx);
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-extern bool rx_match_ccmode (rtx, Mmode);
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#endif
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#endif /* GCC_RX_PROTOS_H */
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diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c
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index 6b179e7..ad8d0bb 100644
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--- a/gcc/config/rx/rx.c
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+++ b/gcc/config/rx/rx.c
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@@ -57,7 +57,7 @@ static void rx_print_operand (FILE *, rtx, int);
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#define CC_FLAG_Z (1 << 1)
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#define CC_FLAG_O (1 << 2)
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#define CC_FLAG_C (1 << 3)
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-#define CC_FLAG_FP (1 << 4) /* fake, to differentiate CC_Fmode */
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+#define CC_FLAG_FP (1 << 4) /* Fake, to differentiate CC_Fmode. */
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static unsigned int flags_from_mode (enum machine_mode mode);
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static unsigned int flags_from_code (enum rtx_code code);
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@@ -85,7 +85,9 @@ rx_is_legitimate_address (Mmode mode, rtx x, bool strict ATTRIBUTE_UNUSED)
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/* Register Indirect. */
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return true;
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- if (GET_MODE_SIZE (mode) == 4
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+ if ((GET_MODE_SIZE (mode) == 4
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+ || GET_MODE_SIZE (mode) == 2
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+ || GET_MODE_SIZE (mode) == 1)
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&& (GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC))
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/* Pre-decrement Register Indirect or
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Post-increment Register Indirect. */
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@@ -187,7 +189,10 @@ rx_is_restricted_memory_address (rtx mem, enum machine_mode mode)
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base = XEXP (mem, 0);
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index = XEXP (mem, 1);
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- return RX_REG_P (base) && CONST_INT_P (index);
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+ if (! RX_REG_P (base) || ! CONST_INT_P (index))
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+ return false;
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+
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+ return IN_RANGE (INTVAL (index), 0, (0x10000 * GET_MODE_SIZE (mode)) - 1);
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case SYMBOL_REF:
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/* Can happen when small data is being supported.
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@@ -386,11 +391,14 @@ rx_assemble_integer (rtx x, unsigned int size, int is_aligned)
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%L Print low part of a DImode register, integer or address.
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%N Print the negation of the immediate value.
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%Q If the operand is a MEM, then correctly generate
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- register indirect or register relative addressing. */
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+ register indirect or register relative addressing.
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+ %R Like %Q but for zero-extending loads. */
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static void
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rx_print_operand (FILE * file, rtx op, int letter)
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{
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+ bool unsigned_load = false;
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+
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switch (letter)
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{
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case 'A':
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@@ -450,6 +458,7 @@ rx_print_operand (FILE * file, rtx op, int letter)
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else
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{
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unsigned int flags = flags_from_mode (mode);
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+
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switch (code)
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{
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case LT:
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@@ -588,10 +597,15 @@ rx_print_operand (FILE * file, rtx op, int letter)
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rx_print_integer (file, - INTVAL (op));
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break;
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+ case 'R':
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+ gcc_assert (GET_MODE_SIZE (GET_MODE (op)) < 4);
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+ unsigned_load = true;
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+ /* Fall through. */
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case 'Q':
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if (MEM_P (op))
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{
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HOST_WIDE_INT offset;
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+ rtx mem = op;
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op = XEXP (op, 0);
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@@ -626,22 +640,24 @@ rx_print_operand (FILE * file, rtx op, int letter)
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rx_print_operand (file, op, 0);
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fprintf (file, "].");
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- switch (GET_MODE_SIZE (GET_MODE (op)))
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+ switch (GET_MODE_SIZE (GET_MODE (mem)))
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{
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case 1:
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- gcc_assert (offset < 65535 * 1);
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- fprintf (file, "B");
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+ gcc_assert (offset <= 65535 * 1);
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+ fprintf (file, unsigned_load ? "UB" : "B");
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break;
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case 2:
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gcc_assert (offset % 2 == 0);
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- gcc_assert (offset < 65535 * 2);
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- fprintf (file, "W");
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+ gcc_assert (offset <= 65535 * 2);
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+ fprintf (file, unsigned_load ? "UW" : "W");
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break;
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- default:
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+ case 4:
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gcc_assert (offset % 4 == 0);
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- gcc_assert (offset < 65535 * 4);
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+ gcc_assert (offset <= 65535 * 4);
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fprintf (file, "L");
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break;
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+ default:
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+ gcc_unreachable ();
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}
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break;
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}
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@@ -2336,6 +2352,13 @@ rx_option_override (void)
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flag_strict_volatile_bitfields = 1;
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rx_override_options_after_change ();
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+
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+ if (align_jumps == 0 && ! optimize_size)
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+ align_jumps = 3;
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+ if (align_loops == 0 && ! optimize_size)
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+ align_loops = 3;
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+ if (align_labels == 0 && ! optimize_size)
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+ align_labels = 3;
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}
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/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
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@@ -2728,6 +2751,45 @@ rx_match_ccmode (rtx insn, enum machine_mode cc_mode)
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}
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+int
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+rx_align_for_label (void)
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+{
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+ return optimize_size ? 1 : 3;
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+}
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+
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+static int
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+rx_max_skip_for_label (rtx lab)
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+{
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+ int opsize;
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+ rtx op;
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+
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+ if (lab == NULL_RTX)
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+ return 0;
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+ op = lab;
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+ do
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+ {
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+ op = next_nonnote_insn (op);
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+ }
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+ while (op && (LABEL_P (op)
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+ || (INSN_P (op) && GET_CODE (PATTERN (op)) == USE)));
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+ if (!op)
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+ return 0;
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+
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+ opsize = get_attr_length (op);
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+ if (opsize >= 0 && opsize < 8)
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+ return opsize - 1;
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+ return 0;
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+}
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+
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+#undef TARGET_ASM_JUMP_ALIGN_MAX_SKIP
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+#define TARGET_ASM_JUMP_ALIGN_MAX_SKIP rx_max_skip_for_label
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+#undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
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+#define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rx_max_skip_for_label
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+#undef TARGET_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP
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+#define TARGET_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP rx_max_skip_for_label
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+#undef TARGET_ASM_LABEL_ALIGN_MAX_SKIP
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+#define TARGET_ASM_LABEL_ALIGN_MAX_SKIP rx_max_skip_for_label
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+
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#undef TARGET_FUNCTION_VALUE
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#define TARGET_FUNCTION_VALUE rx_function_value
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diff --git a/gcc/config/rx/rx.h b/gcc/config/rx/rx.h
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index e3966ed..01fc23b 100644
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--- a/gcc/config/rx/rx.h
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+++ b/gcc/config/rx/rx.h
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@@ -615,4 +615,23 @@ typedef unsigned int CUMULATIVE_ARGS;
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#define BRANCH_COST(SPEED,PREDICT) 1
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#define REGISTER_MOVE_COST(MODE,FROM,TO) 2
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-#define SELECT_CC_MODE(OP,X,Y) rx_select_cc_mode(OP, X, Y)
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+#define SELECT_CC_MODE(OP,X,Y) rx_select_cc_mode((OP), (X), (Y))
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+
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+#define LABEL_ALIGN_AFTER_BARRIER(x) rx_align_for_label ()
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+
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+#define ASM_OUTPUT_MAX_SKIP_ALIGN(STREAM, LOG, MAX_SKIP) \
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+ do \
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+ { \
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+ if ((LOG) == 0 || (MAX_SKIP) == 0) \
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+ break; \
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+ if (TARGET_AS100_SYNTAX) \
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+ { \
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+ if ((LOG) >= 2) \
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+ fprintf (STREAM, "\t.ALIGN 4\t; %d alignment actually requested\n", 1 << (LOG)); \
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+ else \
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+ fprintf (STREAM, "\t.ALIGN 2\n"); \
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+ } \
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+ else \
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+ fprintf (STREAM, "\t.balign %d,3,%d\n", 1 << (LOG), (MAX_SKIP)); \
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+ } \
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+ while (0)
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diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md
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index cd5b571..641f1d4 100644
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--- a/gcc/config/rx/rx.md
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+++ b/gcc/config/rx/rx.md
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@@ -1545,6 +1545,139 @@
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(set_attr "length" "3,4,5,6,7,6")]
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)
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+;; A set of peepholes to catch extending loads followed by arithmetic operations.
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+;; We use iterators where possible to reduce the amount of typing and hence the
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+;; possibilities for typos.
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+
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+(define_code_iterator extend_types [(zero_extend "") (sign_extend "")])
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+(define_code_attr letter [(zero_extend "R") (sign_extend "Q")])
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+
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+(define_code_iterator memex_commutative [(plus "") (and "") (ior "") (xor "")])
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+(define_code_iterator memex_noncomm [(div "") (udiv "") (minus "")])
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+(define_code_iterator memex_nocc [(smax "") (smin "") (mult "")])
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+
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+(define_code_attr op [(plus "add") (and "and") (div "div") (udiv "divu") (smax "max") (smin "min") (mult "mul") (ior "or") (minus "sub") (xor "xor")])
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+
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+(define_peephole2
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+ [(set (match_operand:SI 0 "register_operand")
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+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
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+ (parallel [(set (match_operand:SI 2 "register_operand")
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+ (memex_commutative:SI (match_dup 0)
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+ (match_dup 2)))
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+ (clobber (reg:CC CC_REG))])]
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+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
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+ [(parallel [(set:SI (match_dup 2)
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+ (memex_commutative:SI (match_dup 2)
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+ (extend_types:SI (match_dup 1))))
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+ (clobber (reg:CC CC_REG))])]
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+)
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+
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+(define_peephole2
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+ [(set (match_operand:SI 0 "register_operand")
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+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
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+ (parallel [(set (match_operand:SI 2 "register_operand")
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+ (memex_commutative:SI (match_dup 2)
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+ (match_dup 0)))
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+ (clobber (reg:CC CC_REG))])]
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+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
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+ [(parallel [(set:SI (match_dup 2)
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+ (memex_commutative:SI (match_dup 2)
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+ (extend_types:SI (match_dup 1))))
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+ (clobber (reg:CC CC_REG))])]
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+)
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+
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+(define_peephole2
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+ [(set (match_operand:SI 0 "register_operand")
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+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
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+ (parallel [(set (match_operand:SI 2 "register_operand")
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+ (memex_noncomm:SI (match_dup 2)
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+ (match_dup 0)))
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+ (clobber (reg:CC CC_REG))])]
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+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
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+ [(parallel [(set:SI (match_dup 2)
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+ (memex_noncomm:SI (match_dup 2)
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+ (extend_types:SI (match_dup 1))))
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+ (clobber (reg:CC CC_REG))])]
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+)
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+
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+(define_peephole2
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+ [(set (match_operand:SI 0 "register_operand")
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+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
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+ (set (match_operand:SI 2 "register_operand")
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+ (memex_nocc:SI (match_dup 0)
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+ (match_dup 2)))]
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+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
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+ [(set:SI (match_dup 2)
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+ (memex_nocc:SI (match_dup 2)
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+ (extend_types:SI (match_dup 1))))]
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+)
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+
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+(define_peephole2
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+ [(set (match_operand:SI 0 "register_operand")
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+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
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+ (set (match_operand:SI 2 "register_operand")
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+ (memex_nocc:SI (match_dup 2)
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+ (match_dup 0)))]
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+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
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+ [(set:SI (match_dup 2)
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+ (memex_nocc:SI (match_dup 2)
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+ (extend_types:SI (match_dup 1))))]
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+)
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+
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+(define_insn "*<memex_commutative:code>si3_<extend_types:code><small_int_modes:mode>"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ (memex_commutative:SI (match_operand:SI 1 "register_operand" "%0")
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+ (extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))
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+ (clobber (reg:CC CC_REG))]
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+ ""
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+ "<memex_commutative:op>\t%<extend_types:letter>2, %0"
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+ [(set_attr "timings" "33")
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+ (set_attr "length" "5")] ;; Worst case sceanario. FIXME: If we defined separate patterns
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+) ;; rather than using iterators we could specify exact sizes.
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+
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+(define_insn "*<memex_noncomm:code>si3_<extend_types:code><small_int_modes:mode>"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ (memex_noncomm:SI (match_operand:SI 1 "register_operand" "0")
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+ (extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))
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+ (clobber (reg:CC CC_REG))]
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+ ""
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+ "<memex_noncomm:op>\t%<extend_types:letter>2, %0"
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+ [(set_attr "timings" "33")
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+ (set_attr "length" "5")] ;; Worst case sceanario. FIXME: If we defined separate patterns
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+) ;; rather than using iterators we could specify exact sizes.
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+
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+(define_insn "*<memex_nocc:code>si3_<extend_types:code><small_int_modes:mode>"
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+ [(set (match_operand:SI 0 "register_operand" "=r")
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+ (memex_nocc:SI (match_operand:SI 1 "register_operand" "%0")
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+ (extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))]
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+ ""
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+ "<memex_nocc:op>\t%<extend_types:letter>2, %0"
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+ [(set_attr "timings" "33")
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+ (set_attr "length" "5")] ;; Worst case sceanario. FIXME: If we defined separate patterns
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+) ;; rather than using iterators we could specify exact sizes.
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+
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+(define_peephole2
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+ [(set (match_operand:SI 0 "register_operand")
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+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
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+ (set (reg:CC CC_REG)
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+ (compare:CC (match_operand:SI 2 "register_operand")
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+ (match_dup 0)))]
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+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
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+ [(set (reg:CC CC_REG)
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+ (compare:CC (match_dup 2)
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+ (extend_types:SI (match_dup 1))))]
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+)
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+
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+(define_insn "*comparesi3_<extend_types:code><small_int_modes:mode>"
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+ [(set (reg:CC CC_REG)
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+ (compare:CC (match_operand:SI 0 "register_operand" "=r")
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+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand" "Q"))))]
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+ ""
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+ "cmp\t%<extend_types:letter>1, %0"
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+ [(set_attr "timings" "33")
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+ (set_attr "length" "5")] ;; Worst case sceanario. FIXME: If we defined separate patterns
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+) ;; rather than using iterators we could specify exact sizes.
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+
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||
;; Floating Point Instructions
|
||
|
||
(define_insn "addsf3"
|
||
--
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||
1.7.0.4
|
||
|