337 lines
13 KiB
Diff
337 lines
13 KiB
Diff
From 8b941bea1d0fe0c5cf0de938cd0bd89ce6640dbb Mon Sep 17 00:00:00 2001
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From: Shaohua Li <shaohua.li@intel.com>
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Date: Mon, 23 Feb 2009 15:19:19 +0800
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Subject: drm/i915: Add support for new G33-like chipset.
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This chip is nearly the same, but has new clock settings required.
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Signed-off-by: Shaohua Li <shaohua.li@intel.com>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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---
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drivers/gpu/drm/i915/i915_drv.h | 10 +++-
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drivers/gpu/drm/i915/i915_reg.h | 4 +
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drivers/gpu/drm/i915/intel_display.c | 111 +++++++++++++++++++++++++++++-----
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include/drm/drm_pciids.h | 2 +
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4 files changed, 109 insertions(+), 18 deletions(-)
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diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
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index 0e27854..36d6bc3 100644
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--- a/drivers/gpu/drm/i915/i915_drv.h
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+++ b/drivers/gpu/drm/i915/i915_drv.h
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@@ -787,15 +787,21 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
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(dev)->pci_device == 0x2E22 || \
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IS_GM45(dev))
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+#define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
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+#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
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+#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
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+
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#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
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(dev)->pci_device == 0x29B2 || \
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- (dev)->pci_device == 0x29D2)
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+ (dev)->pci_device == 0x29D2 || \
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+ (IS_IGD(dev)))
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#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
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IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
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#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
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- IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
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+ IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
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+ IS_IGD(dev))
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#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
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/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
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index 9d6539a..f07d315 100644
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--- a/drivers/gpu/drm/i915/i915_reg.h
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+++ b/drivers/gpu/drm/i915/i915_reg.h
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@@ -358,6 +358,7 @@
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#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
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#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
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#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
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+#define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */
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#define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
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#define I915_CRC_ERROR_ENABLE (1UL<<29)
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@@ -434,6 +435,7 @@
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*/
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#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
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#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
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+#define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15
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/* i830, required in DVO non-gang */
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#define PLL_P2_DIVIDE_BY_4 (1 << 23)
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#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
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@@ -500,10 +502,12 @@
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#define FPB0 0x06048
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#define FPB1 0x0604c
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#define FP_N_DIV_MASK 0x003f0000
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+#define FP_N_IGD_DIV_MASK 0x00ff0000
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#define FP_N_DIV_SHIFT 16
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#define FP_M1_DIV_MASK 0x00003f00
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#define FP_M1_DIV_SHIFT 8
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#define FP_M2_DIV_MASK 0x0000003f
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+#define FP_M2_IGD_DIV_MASK 0x000000ff
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#define FP_M2_DIV_SHIFT 0
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#define DPLL_TEST 0x606c
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#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
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diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
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index a283427..1702564 100644
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--- a/drivers/gpu/drm/i915/intel_display.c
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+++ b/drivers/gpu/drm/i915/intel_display.c
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@@ -90,18 +90,32 @@ typedef struct {
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#define I9XX_DOT_MAX 400000
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#define I9XX_VCO_MIN 1400000
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#define I9XX_VCO_MAX 2800000
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+#define IGD_VCO_MIN 1700000
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+#define IGD_VCO_MAX 3500000
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#define I9XX_N_MIN 1
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#define I9XX_N_MAX 6
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+/* IGD's Ncounter is a ring counter */
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+#define IGD_N_MIN 3
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+#define IGD_N_MAX 6
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#define I9XX_M_MIN 70
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#define I9XX_M_MAX 120
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+#define IGD_M_MIN 2
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+#define IGD_M_MAX 256
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#define I9XX_M1_MIN 10
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#define I9XX_M1_MAX 22
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#define I9XX_M2_MIN 5
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#define I9XX_M2_MAX 9
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+/* IGD M1 is reserved, and must be 0 */
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+#define IGD_M1_MIN 0
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+#define IGD_M1_MAX 0
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+#define IGD_M2_MIN 0
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+#define IGD_M2_MAX 254
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#define I9XX_P_SDVO_DAC_MIN 5
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#define I9XX_P_SDVO_DAC_MAX 80
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#define I9XX_P_LVDS_MIN 7
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#define I9XX_P_LVDS_MAX 98
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+#define IGD_P_LVDS_MIN 7
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+#define IGD_P_LVDS_MAX 112
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#define I9XX_P1_MIN 1
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#define I9XX_P1_MAX 8
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#define I9XX_P2_SDVO_DAC_SLOW 10
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@@ -115,6 +129,8 @@ typedef struct {
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#define INTEL_LIMIT_I8XX_LVDS 1
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#define INTEL_LIMIT_I9XX_SDVO_DAC 2
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#define INTEL_LIMIT_I9XX_LVDS 3
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+#define INTEL_LIMIT_IGD_SDVO_DAC 4
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+#define INTEL_LIMIT_IGD_LVDS 5
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static const intel_limit_t intel_limits[] = {
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{ /* INTEL_LIMIT_I8XX_DVO_DAC */
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@@ -168,6 +184,32 @@ static const intel_limit_t intel_limits[] = {
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.p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
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.p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
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},
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+ { /* INTEL_LIMIT_IGD_SDVO */
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+ .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
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+ .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
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+ .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
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+ .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
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+ .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
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+ .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
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+ .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
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+ .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
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+ .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
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+ .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
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+ },
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+ { /* INTEL_LIMIT_IGD_LVDS */
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+ .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
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+ .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
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+ .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
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+ .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
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+ .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
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+ .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
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+ .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
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+ .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
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+ /* IGD only supports single-channel mode. */
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+ .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
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+ .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
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+ },
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+
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};
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static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
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@@ -175,11 +217,16 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
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struct drm_device *dev = crtc->dev;
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const intel_limit_t *limit;
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- if (IS_I9XX(dev)) {
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+ if (IS_I9XX(dev) && !IS_IGD(dev)) {
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
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else
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limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
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+ } else if (IS_IGD(dev)) {
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+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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+ limit = &intel_limits[INTEL_LIMIT_IGD_LVDS];
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+ else
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+ limit = &intel_limits[INTEL_LIMIT_IGD_SDVO_DAC];
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} else {
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
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@@ -189,8 +236,21 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
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return limit;
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}
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-static void intel_clock(int refclk, intel_clock_t *clock)
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+/* m1 is reserved as 0 in IGD, n is a ring counter */
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+static void igd_clock(int refclk, intel_clock_t *clock)
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{
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+ clock->m = clock->m2 + 2;
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+ clock->p = clock->p1 * clock->p2;
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+ clock->vco = refclk * clock->m / clock->n;
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+ clock->dot = clock->vco / clock->p;
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+}
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+
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+static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
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+{
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+ if (IS_IGD(dev)) {
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+ igd_clock(refclk, clock);
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+ return;
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+ }
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clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
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clock->p = clock->p1 * clock->p2;
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clock->vco = refclk * clock->m / (clock->n + 2);
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@@ -226,6 +286,7 @@ bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
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static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
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{
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const intel_limit_t *limit = intel_limit (crtc);
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+ struct drm_device *dev = crtc->dev;
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if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
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INTELPllInvalid ("p1 out of range\n");
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@@ -235,7 +296,7 @@ static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
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INTELPllInvalid ("m2 out of range\n");
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if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
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INTELPllInvalid ("m1 out of range\n");
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- if (clock->m1 <= clock->m2)
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+ if (clock->m1 <= clock->m2 && !IS_IGD(dev))
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INTELPllInvalid ("m1 <= m2\n");
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if (clock->m < limit->m.min || limit->m.max < clock->m)
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INTELPllInvalid ("m out of range\n");
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@@ -289,15 +350,17 @@ static bool intel_find_best_PLL(struct drm_crtc *crtc, int target,
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memset (best_clock, 0, sizeof (*best_clock));
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for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
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- for (clock.m2 = limit->m2.min; clock.m2 < clock.m1 &&
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- clock.m2 <= limit->m2.max; clock.m2++) {
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+ for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
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+ /* m1 is always 0 in IGD */
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+ if (clock.m2 >= clock.m1 && !IS_IGD(dev))
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+ break;
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for (clock.n = limit->n.min; clock.n <= limit->n.max;
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clock.n++) {
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for (clock.p1 = limit->p1.min;
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clock.p1 <= limit->p1.max; clock.p1++) {
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int this_err;
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- intel_clock(refclk, &clock);
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+ intel_clock(dev, refclk, &clock);
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if (!intel_PLL_is_valid(crtc, &clock))
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continue;
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@@ -634,7 +697,7 @@ static int intel_get_core_clock_speed(struct drm_device *dev)
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return 400000;
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else if (IS_I915G(dev))
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return 333000;
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- else if (IS_I945GM(dev) || IS_845G(dev))
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+ else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
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return 200000;
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else if (IS_I915GM(dev)) {
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u16 gcfgc = 0;
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@@ -782,7 +845,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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return -EINVAL;
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}
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- fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
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+ if (IS_IGD(dev))
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+ fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
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+ else
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+ fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
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dpll = DPLL_VGA_MODE_DIS;
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if (IS_I9XX(dev)) {
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@@ -799,7 +865,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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}
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/* compute bitmask from p1 value */
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- dpll |= (1 << (clock.p1 - 1)) << 16;
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+ if (IS_IGD(dev))
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+ dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
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+ else
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+ dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
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switch (clock.p2) {
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case 5:
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dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
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@@ -1279,10 +1348,20 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
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fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
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clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
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- clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
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- clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
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+ if (IS_IGD(dev)) {
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+ clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
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+ clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
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+ } else {
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+ clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
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+ clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
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+ }
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+
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if (IS_I9XX(dev)) {
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- clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
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+ if (IS_IGD(dev))
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+ clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
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+ DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
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+ else
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+ clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
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DPLL_FPA01_P1_POST_DIV_SHIFT);
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switch (dpll & DPLL_MODE_MASK) {
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@@ -1301,7 +1380,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
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}
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/* XXX: Handle the 100Mhz refclk */
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- intel_clock(96000, &clock);
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+ intel_clock(dev, 96000, &clock);
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} else {
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bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
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@@ -1313,9 +1392,9 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
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if ((dpll & PLL_REF_INPUT_MASK) ==
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PLLB_REF_INPUT_SPREADSPECTRUMIN) {
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/* XXX: might not be 66MHz */
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- intel_clock(66000, &clock);
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+ intel_clock(dev, 66000, &clock);
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} else
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- intel_clock(48000, &clock);
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+ intel_clock(dev, 48000, &clock);
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} else {
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if (dpll & PLL_P1_DIVIDE_BY_TWO)
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clock.p1 = 2;
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@@ -1328,7 +1407,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
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else
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clock.p2 = 2;
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- intel_clock(48000, &clock);
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+ intel_clock(dev, 48000, &clock);
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}
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}
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diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
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index 5165f24..76c4c82 100644
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--- a/include/drm/drm_pciids.h
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+++ b/include/drm/drm_pciids.h
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@@ -418,4 +418,6 @@
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{0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
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{0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
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{0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
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+ {0x8086, 0xa001, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
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+ {0x8086, 0xa011, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
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{0, 0, 0}
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--
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1.6.1.3
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