69 lines
2.4 KiB
Diff
69 lines
2.4 KiB
Diff
From a5c235a6f0094494ae1fc1a1ba4728e0d33dfd3b Mon Sep 17 00:00:00 2001
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From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
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Date: Thu, 2 Apr 2009 16:49:27 +0300
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Subject: [PATCH] DSS2: DSI: calculate VP_CLK_RATIO properly
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---
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drivers/video/omap2/dss/dsi.c | 17 +++++++++++------
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1 files changed, 11 insertions(+), 6 deletions(-)
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diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
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index 4442931..aecb89d 100644
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--- a/drivers/video/omap2/dss/dsi.c
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+++ b/drivers/video/omap2/dss/dsi.c
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@@ -1104,7 +1104,10 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
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enable_clocks(1);
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dsi_enable_pll_clock(1);
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- /* configure dispc fck and pixel clock to something sane */
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+ /* XXX this should be calculated depending on the screen size,
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+ * required framerate and DSI speed.
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+ * For now 48MHz is enough for 864x480@60 with 360Mbps/lane
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+ * with two lanes */
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r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo);
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if (r)
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goto err0;
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@@ -1119,7 +1122,7 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
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if (r)
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goto err0;
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- /* PLL does not come out of reset without this... */
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+ /* XXX PLL does not come out of reset without this... */
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dispc_pck_free_enable(1);
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if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
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@@ -1128,8 +1131,8 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
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goto err1;
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}
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- /* ... but if left on, we get problems when planes do not
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- * fill the whole display. No idea about this XXX */
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+ /* XXX ... but if left on, we get problems when planes do not
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+ * fill the whole display. No idea about this */
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dispc_pck_free_enable(0);
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if (enable_hsclk && enable_hsdiv)
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@@ -2214,6 +2217,7 @@ static int dsi_proto_config(struct omap_display *display)
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{
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u32 r;
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int buswidth = 0;
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+ int div;
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dsi_config_tx_fifo(DSI_FIFO_SIZE_128,
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DSI_FIFO_SIZE_0,
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@@ -2254,8 +2258,9 @@ static int dsi_proto_config(struct omap_display *display)
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r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
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r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
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r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
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- /* XXX what should the ratio be */
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- r = FLD_MOD(r, 0, 4, 4); /* VP_CLK_RATIO, VP_PCLK = VP_CLK/2 */
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+
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+ div = dispc_lclk_rate() / dispc_pclk_rate();
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+ r = FLD_MOD(r, div == 2 ? 0 : 1, 4, 4); /* VP_CLK_RATIO */
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r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
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r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
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r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
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--
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1.5.6.5
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