14451 lines
343 KiB
Diff
14451 lines
343 KiB
Diff
From 284deec412f9c6f15c971d8eaf4d0156a51a2f3b Mon Sep 17 00:00:00 2001
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From: Tomi Valkeinen <tomi.valkeinen@nokia.com>
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Date: Thu, 2 Apr 2009 10:23:42 +0300
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Subject: [PATCH] DSS2: OMAP2/3 Display Subsystem driver
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Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
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---
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Documentation/arm/OMAP/DSS | 311 +++
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arch/arm/plat-omap/Makefile | 2 +-
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arch/arm/plat-omap/include/mach/display.h | 520 ++++
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arch/arm/plat-omap/include/mach/vram.h | 33 +
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arch/arm/plat-omap/include/mach/vrfb.h | 47 +
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arch/arm/plat-omap/vram.c | 615 +++++
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arch/arm/plat-omap/vrfb.c | 159 ++
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drivers/video/Kconfig | 1 +
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drivers/video/Makefile | 1 +
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drivers/video/omap2/Kconfig | 3 +
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drivers/video/omap2/Makefile | 4 +
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drivers/video/omap2/dss/Kconfig | 89 +
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drivers/video/omap2/dss/Makefile | 6 +
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drivers/video/omap2/dss/core.c | 641 +++++
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drivers/video/omap2/dss/dispc.c | 2968 +++++++++++++++++++++++
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drivers/video/omap2/dss/display.c | 693 ++++++
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drivers/video/omap2/dss/dpi.c | 393 +++
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drivers/video/omap2/dss/dsi.c | 3752 +++++++++++++++++++++++++++++
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drivers/video/omap2/dss/dss.c | 345 +++
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drivers/video/omap2/dss/dss.h | 331 +++
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drivers/video/omap2/dss/manager.c | 576 +++++
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drivers/video/omap2/dss/overlay.c | 587 +++++
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drivers/video/omap2/dss/rfbi.c | 1304 ++++++++++
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drivers/video/omap2/dss/sdi.c | 245 ++
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drivers/video/omap2/dss/venc.c | 600 +++++
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25 files changed, 14225 insertions(+), 1 deletions(-)
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create mode 100644 Documentation/arm/OMAP/DSS
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create mode 100644 arch/arm/plat-omap/include/mach/display.h
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create mode 100644 arch/arm/plat-omap/include/mach/vram.h
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create mode 100644 arch/arm/plat-omap/include/mach/vrfb.h
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create mode 100644 arch/arm/plat-omap/vram.c
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create mode 100644 arch/arm/plat-omap/vrfb.c
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create mode 100644 drivers/video/omap2/Kconfig
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create mode 100644 drivers/video/omap2/Makefile
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create mode 100644 drivers/video/omap2/dss/Kconfig
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create mode 100644 drivers/video/omap2/dss/Makefile
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create mode 100644 drivers/video/omap2/dss/core.c
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create mode 100644 drivers/video/omap2/dss/dispc.c
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create mode 100644 drivers/video/omap2/dss/display.c
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create mode 100644 drivers/video/omap2/dss/dpi.c
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create mode 100644 drivers/video/omap2/dss/dsi.c
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create mode 100644 drivers/video/omap2/dss/dss.c
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create mode 100644 drivers/video/omap2/dss/dss.h
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create mode 100644 drivers/video/omap2/dss/manager.c
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create mode 100644 drivers/video/omap2/dss/overlay.c
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create mode 100644 drivers/video/omap2/dss/rfbi.c
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create mode 100644 drivers/video/omap2/dss/sdi.c
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create mode 100644 drivers/video/omap2/dss/venc.c
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diff --git a/Documentation/arm/OMAP/DSS b/Documentation/arm/OMAP/DSS
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new file mode 100644
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index 0000000..9e902a2
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--- /dev/null
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+++ b/Documentation/arm/OMAP/DSS
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@@ -0,0 +1,311 @@
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+OMAP2/3 Display Subsystem
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+-------------------------
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+
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+This is an almost total rewrite of the OMAP FB driver in drivers/video/omap
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+(let's call it DSS1). The main differences between DSS1 and DSS2 are DSI,
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+TV-out and multiple display support, but there are lots of small improvements
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+also.
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+
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+The DSS2 driver (omapdss module) is in arch/arm/plat-omap/dss/, and the FB,
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+panel and controller drivers are in drivers/video/omap2/. DSS1 and DSS2 live
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+currently side by side, you can choose which one to use.
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+
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+Features
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+--------
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+
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+Working and tested features include:
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+
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+- MIPI DPI (parallel) output
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+- MIPI DSI output in command mode
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+- MIPI DBI (RFBI) output
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+- SDI output
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+- TV output
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+- All pieces can be compiled as a module or inside kernel
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+- Use DISPC to update any of the outputs
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+- Use CPU to update RFBI or DSI output
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+- OMAP DISPC planes
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+- RGB16, RGB24 packed, RGB24 unpacked
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+- YUV2, UYVY
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+- Scaling
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+- Adjusting DSS FCK to find a good pixel clock
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+- Use DSI DPLL to create DSS FCK
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+
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+Tested boards include:
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+- OMAP3 SDP board
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+- Beagle board
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+- N810
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+
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+omapdss driver
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+--------------
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+
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+The DSS driver does not itself have any support for Linux framebuffer, V4L or
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+such like the current ones, but it has an internal kernel API that upper level
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+drivers can use.
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+
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+The DSS driver models OMAP's overlays, overlay managers and displays in a
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+flexible way to enable non-common multi-display configuration. In addition to
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+modelling the hardware overlays, omapdss supports virtual overlays and overlay
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+managers. These can be used when updating a display with CPU or system DMA.
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+
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+Panel and controller drivers
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+----------------------------
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+
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+The drivers implement panel or controller specific functionality and are not
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+usually visible to users except through omapfb driver. They register
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+themselves to the DSS driver.
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+
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+omapfb driver
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+-------------
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+
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+The omapfb driver implements arbitrary number of standard linux framebuffers.
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+These framebuffers can be routed flexibly to any overlays, thus allowing very
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+dynamic display architecture.
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+
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+The driver exports some omapfb specific ioctls, which are compatible with the
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+ioctls in the old driver.
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+
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+The rest of the non standard features are exported via sysfs. Whether the final
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+implementation will use sysfs, or ioctls, is still open.
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+
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+V4L2 drivers
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+------------
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+
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+V4L2 is being implemented in TI.
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+
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+From omapdss point of view the V4L2 drivers should be similar to framebuffer
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+driver.
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+
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+Architecture
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+--------------------
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+
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+Some clarification what the different components do:
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+
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+ - Framebuffer is a memory area inside OMAP's SRAM/SDRAM that contains the
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+ pixel data for the image. Framebuffer has width and height and color
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+ depth.
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+ - Overlay defines where the pixels are read from and where they go on the
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+ screen. The overlay may be smaller than framebuffer, thus displaying only
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+ part of the framebuffer. The position of the overlay may be changed if
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+ the overlay is smaller than the display.
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+ - Overlay manager combines the overlays in to one image and feeds them to
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+ display.
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+ - Display is the actual physical display device.
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+
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+A framebuffer can be connected to multiple overlays to show the same pixel data
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+on all of the overlays. Note that in this case the overlay input sizes must be
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+the same, but, in case of video overlays, the output size can be different. Any
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+framebuffer can be connected to any overlay.
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+
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+An overlay can be connected to one overlay manager. Also DISPC overlays can be
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+connected only to DISPC overlay managers, and virtual overlays can be only
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+connected to virtual overlays.
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+
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+An overlay manager can be connected to one display. There are certain
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+restrictions which kinds of displays an overlay manager can be connected:
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+
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+ - DISPC TV overlay manager can be only connected to TV display.
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+ - Virtual overlay managers can only be connected to DBI or DSI displays.
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+ - DISPC LCD overlay manager can be connected to all displays, except TV
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+ display.
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+
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+Sysfs
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+-----
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+The sysfs interface is mainly used for testing. I don't think sysfs
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+interface is the best for this in the final version, but I don't quite know
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+what would be the best interfaces for these things.
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+
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+The sysfs interface is divided to two parts: DSS and FB.
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+
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+/sys/class/graphics/fb? directory:
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+mirror 0=off, 1=on
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+rotate Rotation 0-3 for 0, 90, 180, 270 degrees
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+rotate_type 0 = DMA rotation, 1 = VRFB rotation
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+overlays List of overlay numbers to which framebuffer pixels go
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+phys_addr Physical address of the framebuffer
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+virt_addr Virtual address of the framebuffer
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+size Size of the framebuffer
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+
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+/sys/devices/platform/omapdss/overlay? directory:
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+enabled 0=off, 1=on
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+input_size width,height (ie. the framebuffer size)
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+manager Destination overlay manager name
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+name
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+output_size width,height
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+position x,y
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+screen_width width
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+
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+/sys/devices/platform/omapdss/manager? directory:
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+display Destination display
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+name
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+
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+/sys/devices/platform/omapdss/display? directory:
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+ctrl_name Controller name
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+mirror 0=off, 1=on
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+update_mode 0=off, 1=auto, 2=manual
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+enabled 0=off, 1=on
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+name
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+rotate Rotation 0-3 for 0, 90, 180, 270 degrees
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+timings Display timings (pixclock,xres/hfp/hbp/hsw,yres/vfp/vbp/vsw)
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+ When writing, two special timings are accepted for tv-out:
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+ "pal" and "ntsc"
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+panel_name
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+tear_elim Tearing elimination 0=off, 1=on
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+
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+There are also some debugfs files at <debugfs>/omapdss/ which show information
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+about clocks and registers.
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+
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+Examples
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+--------
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+
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+The following definitions have been made for the examples below:
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+
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+ovl0=/sys/devices/platform/omapdss/overlay0
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+ovl1=/sys/devices/platform/omapdss/overlay1
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+ovl2=/sys/devices/platform/omapdss/overlay2
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+
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+mgr0=/sys/devices/platform/omapdss/manager0
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+mgr1=/sys/devices/platform/omapdss/manager1
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+
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+lcd=/sys/devices/platform/omapdss/display0
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+dvi=/sys/devices/platform/omapdss/display1
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+tv=/sys/devices/platform/omapdss/display2
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+
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+fb0=/sys/class/graphics/fb0
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+fb1=/sys/class/graphics/fb1
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+fb2=/sys/class/graphics/fb2
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+
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+Default setup on OMAP3 SDP
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+--------------------------
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+
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+Here's the default setup on OMAP3 SDP board. All planes go to LCD. DVI
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+and TV-out are not in use. The columns from left to right are:
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+framebuffers, overlays, overlay managers, displays. Framebuffers are
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+handled by omapfb, and the rest by the DSS.
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+
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+FB0 --- GFX -\ DVI
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+FB1 --- VID1 --+- LCD ---- LCD
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+FB2 --- VID2 -/ TV ----- TV
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+
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+Example: Switch from LCD to DVI
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+----------------------
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+
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+w=`cat $dvi/horizontal | cut -d "," -f 1`
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+h=`cat $dvi/vertical | cut -d "," -f 1`
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+
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+echo "0" > $lcd/enabled
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+echo "" > $mgr0/display
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+fbset -fb /dev/fb0 -xres $w -yres $h -vxres $w -vyres $h
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+# at this point you have to switch the dvi/lcd dip-switch from the omap board
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+echo "dvi" > $mgr0/display
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+echo "1" > $dvi/enabled
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+
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+After this the configuration looks like:
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+
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+FB0 --- GFX -\ -- DVI
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+FB1 --- VID1 --+- LCD -/ LCD
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+FB2 --- VID2 -/ TV ----- TV
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+
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+Example: Clone GFX overlay to LCD and TV
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+-------------------------------
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+
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+w=`cat $tv/horizontal | cut -d "," -f 1`
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+h=`cat $tv/vertical | cut -d "," -f 1`
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+
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+echo "0" > $ovl0/enabled
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+echo "0" > $ovl1/enabled
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+
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+echo "" > $fb1/overlays
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+echo "0,1" > $fb0/overlays
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+
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+echo "$w,$h" > $ovl1/output_size
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+echo "tv" > $ovl1/manager
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+
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+echo "1" > $ovl0/enabled
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+echo "1" > $ovl1/enabled
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+
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+echo "1" > $tv/enabled
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+
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+After this the configuration looks like (only relevant parts shown):
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+
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+FB0 +-- GFX ---- LCD ---- LCD
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+ \- VID1 ---- TV ---- TV
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+
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+Misc notes
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+----------
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+
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+OMAP FB allocates the framebuffer memory using the OMAP VRAM allocator.
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+
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+Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
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+of 86.5MHz (max possible), and with that you get 1280x1024@57 output from DVI.
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+
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+Rotation and mirroring currently only supports RGB565 and RGB8888 modes. VRFB
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+does not support mirroring.
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+
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+VRFB rotation requires much more memory than non-rotated framebuffer, so you
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+probably need to increase your vram setting before using VRFB rotation. Also,
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+many applications may not work with VRFB if they do not pay attention to all
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+framebuffer parameters.
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+
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+Kernel boot arguments
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+---------------------
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+
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+vram=<size>
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+ - Amount of total VRAM to preallocate. For example, "10M". omapfb
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+ allocates memory for framebuffers from VRAM.
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+
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+omapfb.mode=<display>:<mode>[,...]
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+ - Default video mode for specified displays. For example,
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+ "dvi:800x400MR-24@60". See drivers/video/modedb.c.
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+ There are also two special modes: "pal" and "ntsc" that
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+ can be used to tv out.
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+
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+omapfb.vram=<fbnum>:<size>[@<physaddr>][,...]
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+ - VRAM allocated for a framebuffer. Normally omapfb allocates vram
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+ depending on the display size. With this you can manually allocate
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+ more or define the physical address of each framebuffer. For example,
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+ "1:4M" to allocate 4M for fb1.
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+
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+omapfb.debug=<y|n>
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+ - Enable debug printing. You have to have OMAPFB debug support enabled
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+ in kernel config.
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+
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+omapfb.test=<y|n>
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+ - Draw test pattern to framebuffer whenever framebuffer settings change.
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+ You need to have OMAPFB debug support enabled in kernel config.
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+
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+omapfb.vrfb=<y|n>
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+ - Use VRFB rotation for all framebuffers.
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+
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+omapfb.rotate=<angle>
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+ - Default rotation applied to all framebuffers.
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+ 0 - 0 degree rotation
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+ 1 - 90 degree rotation
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+ 2 - 180 degree rotation
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+ 3 - 270 degree rotation
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+
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+omapfb.mirror=<y|n>
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+ - Default mirror for all framebuffers. Only works with DMA rotation.
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+
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+omapdss.def_disp=<display>
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+ - Name of default display, to which all overlays will be connected.
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+ Common examples are "lcd" or "tv".
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+
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+omapdss.debug=<y|n>
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+ - Enable debug printing. You have to have DSS debug support enabled in
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+ kernel config.
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+
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+TODO
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+----
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+
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+DSS locking
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+
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+Error checking
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+- Lots of checks are missing or implemented just as BUG()
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+
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+System DMA update for DSI
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+- Can be used for RGB16 and RGB24P modes. Probably not for RGB24U (how
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+ to skip the empty byte?)
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+
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+OMAP1 support
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+- Not sure if needed
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+
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diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
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index 3ebc09e..e6146b2 100644
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--- a/arch/arm/plat-omap/Makefile
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+++ b/arch/arm/plat-omap/Makefile
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@@ -4,7 +4,7 @@
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# Common support
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obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
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- usb.o fb.o io.o
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+ usb.o fb.o vram.o vrfb.o io.o
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obj-m :=
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obj-n :=
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obj- :=
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diff --git a/arch/arm/plat-omap/include/mach/display.h b/arch/arm/plat-omap/include/mach/display.h
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new file mode 100644
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index 0000000..6288353
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--- /dev/null
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+++ b/arch/arm/plat-omap/include/mach/display.h
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@@ -0,0 +1,520 @@
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+/*
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+ * linux/include/asm-arm/arch-omap/display.h
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+ *
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+ * Copyright (C) 2008 Nokia Corporation
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+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
|
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published by
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+ * the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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+ * more details.
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+ *
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+ * You should have received a copy of the GNU General Public License along with
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+ * this program. If not, see <http://www.gnu.org/licenses/>.
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+ */
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+
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+#ifndef __ASM_ARCH_OMAP_DISPLAY_H
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+#define __ASM_ARCH_OMAP_DISPLAY_H
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+
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+#include <linux/list.h>
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+#include <linux/kobject.h>
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+#include <asm/atomic.h>
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+
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+#define DISPC_IRQ_FRAMEDONE (1 << 0)
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+#define DISPC_IRQ_VSYNC (1 << 1)
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+#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
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+#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
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+#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
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+#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
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+#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
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+#define DISPC_IRQ_GFX_END_WIN (1 << 7)
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+#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
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+#define DISPC_IRQ_OCP_ERR (1 << 9)
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+#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
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+#define DISPC_IRQ_VID1_END_WIN (1 << 11)
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+#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
|
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+#define DISPC_IRQ_VID2_END_WIN (1 << 13)
|
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+#define DISPC_IRQ_SYNC_LOST (1 << 14)
|
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+#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
|
|
+#define DISPC_IRQ_WAKEUP (1 << 16)
|
|
+
|
|
+enum omap_display_type {
|
|
+ OMAP_DISPLAY_TYPE_NONE = 0,
|
|
+ OMAP_DISPLAY_TYPE_DPI = 1 << 0,
|
|
+ OMAP_DISPLAY_TYPE_DBI = 1 << 1,
|
|
+ OMAP_DISPLAY_TYPE_SDI = 1 << 2,
|
|
+ OMAP_DISPLAY_TYPE_DSI = 1 << 3,
|
|
+ OMAP_DISPLAY_TYPE_VENC = 1 << 4,
|
|
+};
|
|
+
|
|
+enum omap_plane {
|
|
+ OMAP_DSS_GFX = 0,
|
|
+ OMAP_DSS_VIDEO1 = 1,
|
|
+ OMAP_DSS_VIDEO2 = 2
|
|
+};
|
|
+
|
|
+enum omap_channel {
|
|
+ OMAP_DSS_CHANNEL_LCD = 0,
|
|
+ OMAP_DSS_CHANNEL_DIGIT = 1,
|
|
+};
|
|
+
|
|
+enum omap_color_mode {
|
|
+ OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
|
|
+ OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
|
|
+ OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
|
|
+ OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
|
|
+ OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
|
|
+ OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
|
|
+ OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
|
|
+ OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
|
|
+ OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
|
|
+ OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
|
|
+ OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
|
|
+ OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
|
|
+ OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
|
|
+ OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
|
|
+
|
|
+ OMAP_DSS_COLOR_GFX_OMAP3 =
|
|
+ OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
|
|
+ OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
|
|
+ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
|
|
+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
|
|
+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
|
|
+ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
|
|
+
|
|
+ OMAP_DSS_COLOR_VID_OMAP3 =
|
|
+ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
|
|
+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
|
|
+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
|
|
+ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
|
|
+ OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
|
|
+};
|
|
+
|
|
+enum omap_lcd_display_type {
|
|
+ OMAP_DSS_LCD_DISPLAY_STN,
|
|
+ OMAP_DSS_LCD_DISPLAY_TFT,
|
|
+};
|
|
+
|
|
+enum omap_dss_load_mode {
|
|
+ OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
|
|
+ OMAP_DSS_LOAD_CLUT_ONLY = 1,
|
|
+ OMAP_DSS_LOAD_FRAME_ONLY = 2,
|
|
+ OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
|
|
+};
|
|
+
|
|
+enum omap_dss_color_key_type {
|
|
+ OMAP_DSS_COLOR_KEY_GFX_DST = 0,
|
|
+ OMAP_DSS_COLOR_KEY_VID_SRC = 1,
|
|
+};
|
|
+
|
|
+enum omap_rfbi_te_mode {
|
|
+ OMAP_DSS_RFBI_TE_MODE_1 = 1,
|
|
+ OMAP_DSS_RFBI_TE_MODE_2 = 2,
|
|
+};
|
|
+
|
|
+enum omap_panel_config {
|
|
+ OMAP_DSS_LCD_IVS = 1<<0,
|
|
+ OMAP_DSS_LCD_IHS = 1<<1,
|
|
+ OMAP_DSS_LCD_IPC = 1<<2,
|
|
+ OMAP_DSS_LCD_IEO = 1<<3,
|
|
+ OMAP_DSS_LCD_RF = 1<<4,
|
|
+ OMAP_DSS_LCD_ONOFF = 1<<5,
|
|
+
|
|
+ OMAP_DSS_LCD_TFT = 1<<20,
|
|
+};
|
|
+
|
|
+enum omap_dss_venc_type {
|
|
+ OMAP_DSS_VENC_TYPE_COMPOSITE,
|
|
+ OMAP_DSS_VENC_TYPE_SVIDEO,
|
|
+};
|
|
+
|
|
+struct omap_display;
|
|
+struct omap_panel;
|
|
+struct omap_ctrl;
|
|
+
|
|
+/* RFBI */
|
|
+
|
|
+struct rfbi_timings {
|
|
+ int cs_on_time;
|
|
+ int cs_off_time;
|
|
+ int we_on_time;
|
|
+ int we_off_time;
|
|
+ int re_on_time;
|
|
+ int re_off_time;
|
|
+ int we_cycle_time;
|
|
+ int re_cycle_time;
|
|
+ int cs_pulse_width;
|
|
+ int access_time;
|
|
+
|
|
+ int clk_div;
|
|
+
|
|
+ u32 tim[5]; /* set by rfbi_convert_timings() */
|
|
+
|
|
+ int converted;
|
|
+};
|
|
+
|
|
+void omap_rfbi_write_command(const void *buf, u32 len);
|
|
+void omap_rfbi_read_data(void *buf, u32 len);
|
|
+void omap_rfbi_write_data(const void *buf, u32 len);
|
|
+void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
|
|
+ u16 x, u16 y,
|
|
+ u16 w, u16 h);
|
|
+int omap_rfbi_enable_te(bool enable, unsigned line);
|
|
+int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
|
|
+ unsigned hs_pulse_time, unsigned vs_pulse_time,
|
|
+ int hs_pol_inv, int vs_pol_inv, int extif_div);
|
|
+
|
|
+/* DSI */
|
|
+int dsi_vc_dcs_write(int channel, u8 *data, int len);
|
|
+int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
|
|
+int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
|
|
+int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
|
|
+int dsi_vc_send_null(int channel);
|
|
+
|
|
+/* Board specific data */
|
|
+struct omap_dss_display_config {
|
|
+ enum omap_display_type type;
|
|
+
|
|
+ union {
|
|
+ struct {
|
|
+ u8 data_lines;
|
|
+ } dpi;
|
|
+
|
|
+ struct {
|
|
+ u8 channel;
|
|
+ u8 data_lines;
|
|
+ } rfbi;
|
|
+
|
|
+ struct {
|
|
+ u8 datapairs;
|
|
+ } sdi;
|
|
+
|
|
+ struct {
|
|
+ u8 clk_lane;
|
|
+ u8 clk_pol;
|
|
+ u8 data1_lane;
|
|
+ u8 data1_pol;
|
|
+ u8 data2_lane;
|
|
+ u8 data2_pol;
|
|
+ unsigned long ddr_clk_hz;
|
|
+ } dsi;
|
|
+
|
|
+ struct {
|
|
+ enum omap_dss_venc_type type;
|
|
+ } venc;
|
|
+ } u;
|
|
+
|
|
+ int panel_reset_gpio;
|
|
+ int ctrl_reset_gpio;
|
|
+
|
|
+ const char *name; /* for debug */
|
|
+ const char *ctrl_name;
|
|
+ const char *panel_name;
|
|
+
|
|
+ void *panel_data;
|
|
+ void *ctrl_data;
|
|
+
|
|
+ /* platform specific enable/disable */
|
|
+ int (*panel_enable)(struct omap_display *display);
|
|
+ void (*panel_disable)(struct omap_display *display);
|
|
+ int (*ctrl_enable)(struct omap_display *display);
|
|
+ void (*ctrl_disable)(struct omap_display *display);
|
|
+ int (*set_backlight)(struct omap_display *display,
|
|
+ int level);
|
|
+};
|
|
+
|
|
+struct device;
|
|
+
|
|
+/* Board specific data */
|
|
+struct omap_dss_board_info {
|
|
+ unsigned (*get_last_off_on_transaction_id)(struct device *dev);
|
|
+ int (*dsi_power_up)(void);
|
|
+ void (*dsi_power_down)(void);
|
|
+ int num_displays;
|
|
+ struct omap_dss_display_config *displays[];
|
|
+};
|
|
+
|
|
+struct omap_ctrl {
|
|
+ struct module *owner;
|
|
+
|
|
+ const char *name;
|
|
+
|
|
+ int (*init)(struct omap_display *display);
|
|
+ void (*cleanup)(struct omap_display *display);
|
|
+ int (*enable)(struct omap_display *display);
|
|
+ void (*disable)(struct omap_display *display);
|
|
+ int (*suspend)(struct omap_display *display);
|
|
+ int (*resume)(struct omap_display *display);
|
|
+ void (*setup_update)(struct omap_display *display,
|
|
+ u16 x, u16 y, u16 w, u16 h);
|
|
+
|
|
+ int (*enable_te)(struct omap_display *display, bool enable);
|
|
+
|
|
+ u8 (*get_rotate)(struct omap_display *display);
|
|
+ int (*set_rotate)(struct omap_display *display, u8 rotate);
|
|
+
|
|
+ bool (*get_mirror)(struct omap_display *display);
|
|
+ int (*set_mirror)(struct omap_display *display, bool enable);
|
|
+
|
|
+ int (*run_test)(struct omap_display *display, int test);
|
|
+ int (*memory_read)(struct omap_display *display,
|
|
+ void *buf, size_t size,
|
|
+ u16 x, u16 y, u16 w, u16 h);
|
|
+
|
|
+ u8 pixel_size;
|
|
+
|
|
+ struct rfbi_timings timings;
|
|
+
|
|
+ void *priv;
|
|
+};
|
|
+
|
|
+struct omap_video_timings {
|
|
+ /* Unit: pixels */
|
|
+ u16 x_res;
|
|
+ /* Unit: pixels */
|
|
+ u16 y_res;
|
|
+ /* Unit: KHz */
|
|
+ u32 pixel_clock;
|
|
+ /* Unit: pixel clocks */
|
|
+ u16 hsw; /* Horizontal synchronization pulse width */
|
|
+ /* Unit: pixel clocks */
|
|
+ u16 hfp; /* Horizontal front porch */
|
|
+ /* Unit: pixel clocks */
|
|
+ u16 hbp; /* Horizontal back porch */
|
|
+ /* Unit: line clocks */
|
|
+ u16 vsw; /* Vertical synchronization pulse width */
|
|
+ /* Unit: line clocks */
|
|
+ u16 vfp; /* Vertical front porch */
|
|
+ /* Unit: line clocks */
|
|
+ u16 vbp; /* Vertical back porch */
|
|
+
|
|
+};
|
|
+
|
|
+#ifdef CONFIG_OMAP2_DSS_VENC
|
|
+/* Hardcoded timings for tv modes. Venc only uses these to
|
|
+ * identify the mode, and does not actually use the configs
|
|
+ * itself. However, the configs should be something that
|
|
+ * a normal monitor can also show */
|
|
+const extern struct omap_video_timings omap_dss_pal_timings;
|
|
+const extern struct omap_video_timings omap_dss_ntsc_timings;
|
|
+#endif
|
|
+
|
|
+struct omap_panel {
|
|
+ struct module *owner;
|
|
+
|
|
+ const char *name;
|
|
+
|
|
+ int (*init)(struct omap_display *display);
|
|
+ void (*cleanup)(struct omap_display *display);
|
|
+ int (*remove)(struct omap_display *display);
|
|
+ int (*enable)(struct omap_display *display);
|
|
+ void (*disable)(struct omap_display *display);
|
|
+ int (*suspend)(struct omap_display *display);
|
|
+ int (*resume)(struct omap_display *display);
|
|
+ int (*run_test)(struct omap_display *display, int test);
|
|
+
|
|
+ struct omap_video_timings timings;
|
|
+
|
|
+ int acbi; /* ac-bias pin transitions per interrupt */
|
|
+ /* Unit: line clocks */
|
|
+ int acb; /* ac-bias pin frequency */
|
|
+
|
|
+ enum omap_panel_config config;
|
|
+
|
|
+ u8 recommended_bpp;
|
|
+
|
|
+ void *priv;
|
|
+};
|
|
+
|
|
+/* XXX perhaps this should be removed */
|
|
+enum omap_dss_overlay_managers {
|
|
+ OMAP_DSS_OVL_MGR_LCD,
|
|
+ OMAP_DSS_OVL_MGR_TV,
|
|
+};
|
|
+
|
|
+struct omap_overlay_manager;
|
|
+
|
|
+struct omap_overlay_info {
|
|
+ bool enabled;
|
|
+
|
|
+ u32 paddr;
|
|
+ void __iomem *vaddr;
|
|
+ u16 screen_width;
|
|
+ u16 width;
|
|
+ u16 height;
|
|
+ enum omap_color_mode color_mode;
|
|
+ u8 rotation;
|
|
+ bool mirror;
|
|
+
|
|
+ u16 pos_x;
|
|
+ u16 pos_y;
|
|
+ u16 out_width; /* if 0, out_width == width */
|
|
+ u16 out_height; /* if 0, out_height == height */
|
|
+};
|
|
+
|
|
+enum omap_overlay_caps {
|
|
+ OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
|
|
+ OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
|
|
+};
|
|
+
|
|
+struct omap_overlay {
|
|
+ struct kobject kobj;
|
|
+ struct list_head list;
|
|
+
|
|
+ const char *name;
|
|
+ int id;
|
|
+ struct omap_overlay_manager *manager;
|
|
+ enum omap_color_mode supported_modes;
|
|
+ struct omap_overlay_info info;
|
|
+ enum omap_overlay_caps caps;
|
|
+
|
|
+ int (*set_manager)(struct omap_overlay *ovl,
|
|
+ struct omap_overlay_manager *mgr);
|
|
+ int (*unset_manager)(struct omap_overlay *ovl);
|
|
+
|
|
+ int (*set_overlay_info)(struct omap_overlay *ovl,
|
|
+ struct omap_overlay_info *info);
|
|
+ void (*get_overlay_info)(struct omap_overlay *ovl,
|
|
+ struct omap_overlay_info *info);
|
|
+};
|
|
+
|
|
+enum omap_overlay_manager_caps {
|
|
+ OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
|
|
+};
|
|
+
|
|
+struct omap_overlay_manager {
|
|
+ struct kobject kobj;
|
|
+ struct list_head list;
|
|
+
|
|
+ const char *name;
|
|
+ int id;
|
|
+ enum omap_overlay_manager_caps caps;
|
|
+ struct omap_display *display;
|
|
+ int num_overlays;
|
|
+ struct omap_overlay **overlays;
|
|
+ enum omap_display_type supported_displays;
|
|
+
|
|
+ int (*set_display)(struct omap_overlay_manager *mgr,
|
|
+ struct omap_display *display);
|
|
+ int (*unset_display)(struct omap_overlay_manager *mgr);
|
|
+
|
|
+ int (*apply)(struct omap_overlay_manager *mgr);
|
|
+
|
|
+ void (*set_default_color)(struct omap_overlay_manager *mgr, u32 color);
|
|
+ void (*set_trans_key)(struct omap_overlay_manager *mgr,
|
|
+ enum omap_dss_color_key_type type,
|
|
+ u32 trans_key);
|
|
+ void (*enable_trans_key)(struct omap_overlay_manager *mgr,
|
|
+ bool enable);
|
|
+};
|
|
+
|
|
+enum omap_display_caps {
|
|
+ OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
|
|
+};
|
|
+
|
|
+enum omap_dss_update_mode {
|
|
+ OMAP_DSS_UPDATE_DISABLED = 0,
|
|
+ OMAP_DSS_UPDATE_AUTO,
|
|
+ OMAP_DSS_UPDATE_MANUAL,
|
|
+};
|
|
+
|
|
+enum omap_dss_display_state {
|
|
+ OMAP_DSS_DISPLAY_DISABLED = 0,
|
|
+ OMAP_DSS_DISPLAY_ACTIVE,
|
|
+ OMAP_DSS_DISPLAY_SUSPENDED,
|
|
+};
|
|
+
|
|
+struct omap_display {
|
|
+ struct kobject kobj;
|
|
+ struct list_head list;
|
|
+
|
|
+ /*atomic_t ref_count;*/
|
|
+ int ref_count;
|
|
+ /* helper variable for driver suspend/resume */
|
|
+ int activate_after_resume;
|
|
+
|
|
+ enum omap_display_type type;
|
|
+ const char *name;
|
|
+
|
|
+ enum omap_display_caps caps;
|
|
+
|
|
+ struct omap_overlay_manager *manager;
|
|
+
|
|
+ enum omap_dss_display_state state;
|
|
+
|
|
+ struct omap_dss_display_config hw_config; /* board specific data */
|
|
+ struct omap_ctrl *ctrl; /* static common data */
|
|
+ struct omap_panel *panel; /* static common data */
|
|
+
|
|
+ int (*enable)(struct omap_display *display);
|
|
+ void (*disable)(struct omap_display *display);
|
|
+
|
|
+ int (*suspend)(struct omap_display *display);
|
|
+ int (*resume)(struct omap_display *display);
|
|
+
|
|
+ void (*get_resolution)(struct omap_display *display,
|
|
+ u16 *xres, u16 *yres);
|
|
+ int (*get_recommended_bpp)(struct omap_display *display);
|
|
+
|
|
+ int (*check_timings)(struct omap_display *display,
|
|
+ struct omap_video_timings *timings);
|
|
+ void (*set_timings)(struct omap_display *display,
|
|
+ struct omap_video_timings *timings);
|
|
+ void (*get_timings)(struct omap_display *display,
|
|
+ struct omap_video_timings *timings);
|
|
+ int (*update)(struct omap_display *display,
|
|
+ u16 x, u16 y, u16 w, u16 h);
|
|
+ int (*sync)(struct omap_display *display);
|
|
+ int (*wait_vsync)(struct omap_display *display);
|
|
+
|
|
+ int (*set_update_mode)(struct omap_display *display,
|
|
+ enum omap_dss_update_mode);
|
|
+ enum omap_dss_update_mode (*get_update_mode)
|
|
+ (struct omap_display *display);
|
|
+
|
|
+ int (*enable_te)(struct omap_display *display, bool enable);
|
|
+ int (*get_te)(struct omap_display *display);
|
|
+
|
|
+ u8 (*get_rotate)(struct omap_display *display);
|
|
+ int (*set_rotate)(struct omap_display *display, u8 rotate);
|
|
+
|
|
+ bool (*get_mirror)(struct omap_display *display);
|
|
+ int (*set_mirror)(struct omap_display *display, bool enable);
|
|
+
|
|
+ int (*run_test)(struct omap_display *display, int test);
|
|
+ int (*memory_read)(struct omap_display *display,
|
|
+ void *buf, size_t size,
|
|
+ u16 x, u16 y, u16 w, u16 h);
|
|
+
|
|
+ void (*configure_overlay)(struct omap_overlay *overlay);
|
|
+};
|
|
+
|
|
+int omap_dss_get_num_displays(void);
|
|
+struct omap_display *omap_dss_get_display(int no);
|
|
+void omap_dss_put_display(struct omap_display *display);
|
|
+
|
|
+void omap_dss_register_ctrl(struct omap_ctrl *ctrl);
|
|
+void omap_dss_unregister_ctrl(struct omap_ctrl *ctrl);
|
|
+
|
|
+void omap_dss_register_panel(struct omap_panel *panel);
|
|
+void omap_dss_unregister_panel(struct omap_panel *panel);
|
|
+
|
|
+int omap_dss_get_num_overlay_managers(void);
|
|
+struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
|
|
+
|
|
+int omap_dss_get_num_overlays(void);
|
|
+struct omap_overlay *omap_dss_get_overlay(int num);
|
|
+
|
|
+typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
|
|
+int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
|
|
+int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
|
|
+
|
|
+int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
|
|
+int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
|
|
+ unsigned long timeout);
|
|
+
|
|
+#endif
|
|
diff --git a/arch/arm/plat-omap/include/mach/vram.h b/arch/arm/plat-omap/include/mach/vram.h
|
|
new file mode 100644
|
|
index 0000000..f176562
|
|
--- /dev/null
|
|
+++ b/arch/arm/plat-omap/include/mach/vram.h
|
|
@@ -0,0 +1,33 @@
|
|
+/*
|
|
+ * File: arch/arm/plat-omap/include/mach/vram.h
|
|
+ *
|
|
+ * Copyright (C) 2009 Nokia Corporation
|
|
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License as published by the
|
|
+ * Free Software Foundation; either version 2 of the License, or (at your
|
|
+ * option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful, but
|
|
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
+ * General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License along
|
|
+ * with this program; if not, write to the Free Software Foundation, Inc.,
|
|
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
|
+ */
|
|
+
|
|
+#ifndef __OMAPVRAM_H
|
|
+#define __OMAPVRAM_H
|
|
+
|
|
+#include <asm/types.h>
|
|
+
|
|
+extern int omap_vram_free(unsigned long paddr, size_t size);
|
|
+extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
|
|
+extern int omap_vram_reserve(unsigned long paddr, size_t size);
|
|
+extern void omap2_set_sdram_vram(u32 size, u32 start);
|
|
+extern void omap2_set_sram_vram(u32 size, u32 start);
|
|
+
|
|
+#endif
|
|
diff --git a/arch/arm/plat-omap/include/mach/vrfb.h b/arch/arm/plat-omap/include/mach/vrfb.h
|
|
new file mode 100644
|
|
index 0000000..2047862
|
|
--- /dev/null
|
|
+++ b/arch/arm/plat-omap/include/mach/vrfb.h
|
|
@@ -0,0 +1,47 @@
|
|
+/*
|
|
+ * File: arch/arm/plat-omap/include/mach/vrfb.h
|
|
+ *
|
|
+ * VRFB
|
|
+ *
|
|
+ * Copyright (C) 2009 Nokia Corporation
|
|
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License as published by the
|
|
+ * Free Software Foundation; either version 2 of the License, or (at your
|
|
+ * option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful, but
|
|
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
+ * General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License along
|
|
+ * with this program; if not, write to the Free Software Foundation, Inc.,
|
|
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
|
+ */
|
|
+
|
|
+#ifndef __VRFB_H
|
|
+#define __VRFB_H
|
|
+
|
|
+#define OMAP_VRFB_LINE_LEN 2048
|
|
+
|
|
+struct vrfb
|
|
+{
|
|
+ u8 context;
|
|
+ void __iomem *vaddr[4];
|
|
+ unsigned long paddr[4];
|
|
+ u16 xoffset;
|
|
+ u16 yoffset;
|
|
+ u8 bytespp;
|
|
+};
|
|
+
|
|
+extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
|
|
+extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
|
|
+extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
|
|
+ u8 bytespp);
|
|
+extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
|
|
+ u16 width, u16 height,
|
|
+ u8 bytespp);
|
|
+
|
|
+#endif /* __VRFB_H */
|
|
diff --git a/arch/arm/plat-omap/vram.c b/arch/arm/plat-omap/vram.c
|
|
new file mode 100644
|
|
index 0000000..f24a110
|
|
--- /dev/null
|
|
+++ b/arch/arm/plat-omap/vram.c
|
|
@@ -0,0 +1,615 @@
|
|
+/*
|
|
+ * linux/arch/arm/plat-omap/vram.c
|
|
+ *
|
|
+ * Copyright (C) 2008 Nokia Corporation
|
|
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
|
|
+ *
|
|
+ * Some code and ideas taken from drivers/video/omap/ driver
|
|
+ * by Imre Deak.
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published by
|
|
+ * the Free Software Foundation.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful, but WITHOUT
|
|
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
+ * more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License along with
|
|
+ * this program. If not, see <http://www.gnu.org/licenses/>.
|
|
+ */
|
|
+
|
|
+/*#define DEBUG*/
|
|
+
|
|
+#include <linux/vmalloc.h>
|
|
+#include <linux/kernel.h>
|
|
+#include <linux/mm.h>
|
|
+#include <linux/list.h>
|
|
+#include <linux/dma-mapping.h>
|
|
+#include <linux/proc_fs.h>
|
|
+#include <linux/seq_file.h>
|
|
+#include <linux/bootmem.h>
|
|
+#include <linux/omapfb.h>
|
|
+
|
|
+#include <asm/setup.h>
|
|
+
|
|
+#include <mach/sram.h>
|
|
+#include <mach/vram.h>
|
|
+
|
|
+#ifdef DEBUG
|
|
+#define DBG(format, ...) printk(KERN_DEBUG "VRAM: " format, ## __VA_ARGS__)
|
|
+#else
|
|
+#define DBG(format, ...)
|
|
+#endif
|
|
+
|
|
+#define OMAP2_SRAM_START 0x40200000
|
|
+/* Maximum size, in reality this is smaller if SRAM is partially locked. */
|
|
+#define OMAP2_SRAM_SIZE 0xa0000 /* 640k */
|
|
+
|
|
+#define REG_MAP_SIZE(_page_cnt) \
|
|
+ ((_page_cnt + (sizeof(unsigned long) * 8) - 1) / 8)
|
|
+#define REG_MAP_PTR(_rg, _page_nr) \
|
|
+ (((_rg)->map) + (_page_nr) / (sizeof(unsigned long) * 8))
|
|
+#define REG_MAP_MASK(_page_nr) \
|
|
+ (1 << ((_page_nr) & (sizeof(unsigned long) * 8 - 1)))
|
|
+
|
|
+#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
|
|
+
|
|
+/* postponed regions are used to temporarily store region information at boot
|
|
+ * time when we cannot yet allocate the region list */
|
|
+#define MAX_POSTPONED_REGIONS 10
|
|
+
|
|
+static int postponed_cnt __initdata;
|
|
+static struct {
|
|
+ unsigned long paddr;
|
|
+ size_t size;
|
|
+} postponed_regions[MAX_POSTPONED_REGIONS] __initdata;
|
|
+
|
|
+struct vram_alloc {
|
|
+ struct list_head list;
|
|
+ unsigned long paddr;
|
|
+ unsigned pages;
|
|
+};
|
|
+
|
|
+struct vram_region {
|
|
+ struct list_head list;
|
|
+ struct list_head alloc_list;
|
|
+ unsigned long paddr;
|
|
+ unsigned pages;
|
|
+};
|
|
+
|
|
+static DEFINE_MUTEX(region_mutex);
|
|
+static LIST_HEAD(region_list);
|
|
+
|
|
+static inline int region_mem_type(unsigned long paddr)
|
|
+{
|
|
+ if (paddr >= OMAP2_SRAM_START &&
|
|
+ paddr < OMAP2_SRAM_START + OMAP2_SRAM_SIZE)
|
|
+ return OMAPFB_MEMTYPE_SRAM;
|
|
+ else
|
|
+ return OMAPFB_MEMTYPE_SDRAM;
|
|
+}
|
|
+
|
|
+static struct vram_region *omap_vram_create_region(unsigned long paddr,
|
|
+ unsigned pages)
|
|
+{
|
|
+ struct vram_region *rm;
|
|
+
|
|
+ rm = kzalloc(sizeof(*rm), GFP_KERNEL);
|
|
+
|
|
+ if (rm) {
|
|
+ INIT_LIST_HEAD(&rm->alloc_list);
|
|
+ rm->paddr = paddr;
|
|
+ rm->pages = pages;
|
|
+ }
|
|
+
|
|
+ return rm;
|
|
+}
|
|
+
|
|
+#if 0
|
|
+static void omap_vram_free_region(struct vram_region *vr)
|
|
+{
|
|
+ list_del(&vr->list);
|
|
+ kfree(vr);
|
|
+}
|
|
+#endif
|
|
+
|
|
+static struct vram_alloc *omap_vram_create_allocation(struct vram_region *vr,
|
|
+ unsigned long paddr, unsigned pages)
|
|
+{
|
|
+ struct vram_alloc *va;
|
|
+ struct vram_alloc *new;
|
|
+
|
|
+ new = kzalloc(sizeof(*va), GFP_KERNEL);
|
|
+
|
|
+ if (!new)
|
|
+ return NULL;
|
|
+
|
|
+ new->paddr = paddr;
|
|
+ new->pages = pages;
|
|
+
|
|
+ list_for_each_entry(va, &vr->alloc_list, list) {
|
|
+ if (va->paddr > new->paddr)
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ list_add_tail(&new->list, &va->list);
|
|
+
|
|
+ return new;
|
|
+}
|
|
+
|
|
+static void omap_vram_free_allocation(struct vram_alloc *va)
|
|
+{
|
|
+ list_del(&va->list);
|
|
+ kfree(va);
|
|
+}
|
|
+
|
|
+static __init int omap_vram_add_region_postponed(unsigned long paddr,
|
|
+ size_t size)
|
|
+{
|
|
+ if (postponed_cnt == MAX_POSTPONED_REGIONS)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ postponed_regions[postponed_cnt].paddr = paddr;
|
|
+ postponed_regions[postponed_cnt].size = size;
|
|
+
|
|
+ ++postponed_cnt;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/* add/remove_region can be exported if there's need to add/remove regions
|
|
+ * runtime */
|
|
+static int omap_vram_add_region(unsigned long paddr, size_t size)
|
|
+{
|
|
+ struct vram_region *rm;
|
|
+ unsigned pages;
|
|
+
|
|
+ DBG("adding region paddr %08lx size %d\n",
|
|
+ paddr, size);
|
|
+
|
|
+ size &= PAGE_MASK;
|
|
+ pages = size >> PAGE_SHIFT;
|
|
+
|
|
+ rm = omap_vram_create_region(paddr, pages);
|
|
+ if (rm == NULL)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ list_add(&rm->list, ®ion_list);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+int omap_vram_free(unsigned long paddr, size_t size)
|
|
+{
|
|
+ struct vram_region *rm;
|
|
+ struct vram_alloc *alloc;
|
|
+ unsigned start, end;
|
|
+
|
|
+ DBG("free mem paddr %08lx size %d\n", paddr, size);
|
|
+
|
|
+ size = PAGE_ALIGN(size);
|
|
+
|
|
+ mutex_lock(®ion_mutex);
|
|
+
|
|
+ list_for_each_entry(rm, ®ion_list, list) {
|
|
+ list_for_each_entry(alloc, &rm->alloc_list, list) {
|
|
+ start = alloc->paddr;
|
|
+ end = alloc->paddr + (alloc->pages >> PAGE_SHIFT);
|
|
+
|
|
+ if (start >= paddr && end < paddr + size)
|
|
+ goto found;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ mutex_unlock(®ion_mutex);
|
|
+ return -EINVAL;
|
|
+
|
|
+found:
|
|
+ omap_vram_free_allocation(alloc);
|
|
+
|
|
+ mutex_unlock(®ion_mutex);
|
|
+ return 0;
|
|
+}
|
|
+EXPORT_SYMBOL(omap_vram_free);
|
|
+
|
|
+static int _omap_vram_reserve(unsigned long paddr, unsigned pages)
|
|
+{
|
|
+ struct vram_region *rm;
|
|
+ struct vram_alloc *alloc;
|
|
+ size_t size;
|
|
+
|
|
+ size = pages << PAGE_SHIFT;
|
|
+
|
|
+ list_for_each_entry(rm, ®ion_list, list) {
|
|
+ unsigned long start, end;
|
|
+
|
|
+ DBG("checking region %lx %d\n", rm->paddr, rm->pages);
|
|
+
|
|
+ if (region_mem_type(rm->paddr) != region_mem_type(paddr))
|
|
+ continue;
|
|
+
|
|
+ start = rm->paddr;
|
|
+ end = start + (rm->pages << PAGE_SHIFT) - 1;
|
|
+ if (start > paddr || end < paddr + size - 1)
|
|
+ continue;
|
|
+
|
|
+ DBG("block ok, checking allocs\n");
|
|
+
|
|
+ list_for_each_entry(alloc, &rm->alloc_list, list) {
|
|
+ end = alloc->paddr - 1;
|
|
+
|
|
+ if (start <= paddr && end >= paddr + size - 1)
|
|
+ goto found;
|
|
+
|
|
+ start = alloc->paddr + (alloc->pages << PAGE_SHIFT);
|
|
+ }
|
|
+
|
|
+ end = rm->paddr + (rm->pages << PAGE_SHIFT) - 1;
|
|
+
|
|
+ if (!(start <= paddr && end >= paddr + size - 1))
|
|
+ continue;
|
|
+found:
|
|
+ DBG("FOUND area start %lx, end %lx\n", start, end);
|
|
+
|
|
+ if (omap_vram_create_allocation(rm, paddr, pages) == NULL)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
+ return -ENOMEM;
|
|
+}
|
|
+
|
|
+int omap_vram_reserve(unsigned long paddr, size_t size)
|
|
+{
|
|
+ unsigned pages;
|
|
+ int r;
|
|
+
|
|
+ DBG("reserve mem paddr %08lx size %d\n", paddr, size);
|
|
+
|
|
+ size = PAGE_ALIGN(size);
|
|
+ pages = size >> PAGE_SHIFT;
|
|
+
|
|
+ mutex_lock(®ion_mutex);
|
|
+
|
|
+ r = _omap_vram_reserve(paddr, pages);
|
|
+
|
|
+ mutex_unlock(®ion_mutex);
|
|
+
|
|
+ return r;
|
|
+}
|
|
+EXPORT_SYMBOL(omap_vram_reserve);
|
|
+
|
|
+static int _omap_vram_alloc(int mtype, unsigned pages, unsigned long *paddr)
|
|
+{
|
|
+ struct vram_region *rm;
|
|
+ struct vram_alloc *alloc;
|
|
+
|
|
+ list_for_each_entry(rm, ®ion_list, list) {
|
|
+ unsigned long start, end;
|
|
+
|
|
+ DBG("checking region %lx %d\n", rm->paddr, rm->pages);
|
|
+
|
|
+ if (region_mem_type(rm->paddr) != mtype)
|
|
+ continue;
|
|
+
|
|
+ start = rm->paddr;
|
|
+
|
|
+ list_for_each_entry(alloc, &rm->alloc_list, list) {
|
|
+ end = alloc->paddr;
|
|
+
|
|
+ if (end - start >= pages << PAGE_SHIFT)
|
|
+ goto found;
|
|
+
|
|
+ start = alloc->paddr + (alloc->pages << PAGE_SHIFT);
|
|
+ }
|
|
+
|
|
+ end = rm->paddr + (rm->pages << PAGE_SHIFT);
|
|
+found:
|
|
+ if (end - start < pages << PAGE_SHIFT)
|
|
+ continue;
|
|
+
|
|
+ DBG("FOUND %lx, end %lx\n", start, end);
|
|
+
|
|
+ alloc = omap_vram_create_allocation(rm, start, pages);
|
|
+ if (alloc == NULL)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ *paddr = start;
|
|
+
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
+ return -ENOMEM;
|
|
+}
|
|
+
|
|
+int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr)
|
|
+{
|
|
+ unsigned pages;
|
|
+ int r;
|
|
+
|
|
+ BUG_ON(mtype > OMAPFB_MEMTYPE_MAX || !size);
|
|
+
|
|
+ DBG("alloc mem type %d size %d\n", mtype, size);
|
|
+
|
|
+ size = PAGE_ALIGN(size);
|
|
+ pages = size >> PAGE_SHIFT;
|
|
+
|
|
+ mutex_lock(®ion_mutex);
|
|
+
|
|
+ r = _omap_vram_alloc(mtype, pages, paddr);
|
|
+
|
|
+ mutex_unlock(®ion_mutex);
|
|
+
|
|
+ return r;
|
|
+}
|
|
+EXPORT_SYMBOL(omap_vram_alloc);
|
|
+
|
|
+#ifdef CONFIG_PROC_FS
|
|
+static void *r_next(struct seq_file *m, void *v, loff_t *pos)
|
|
+{
|
|
+ struct list_head *l = v;
|
|
+
|
|
+ (*pos)++;
|
|
+
|
|
+ if (list_is_last(l, ®ion_list))
|
|
+ return NULL;
|
|
+
|
|
+ return l->next;
|
|
+}
|
|
+
|
|
+static void *r_start(struct seq_file *m, loff_t *pos)
|
|
+{
|
|
+ loff_t p = *pos;
|
|
+ struct list_head *l = ®ion_list;
|
|
+
|
|
+ mutex_lock(®ion_mutex);
|
|
+
|
|
+ do {
|
|
+ l = l->next;
|
|
+ if (l == ®ion_list)
|
|
+ return NULL;
|
|
+ } while (p--);
|
|
+
|
|
+ return l;
|
|
+}
|
|
+
|
|
+static void r_stop(struct seq_file *m, void *v)
|
|
+{
|
|
+ mutex_unlock(®ion_mutex);
|
|
+}
|
|
+
|
|
+static int r_show(struct seq_file *m, void *v)
|
|
+{
|
|
+ struct vram_region *vr;
|
|
+ struct vram_alloc *va;
|
|
+ unsigned size;
|
|
+
|
|
+ vr = list_entry(v, struct vram_region, list);
|
|
+
|
|
+ size = vr->pages << PAGE_SHIFT;
|
|
+
|
|
+ seq_printf(m, "%08lx-%08lx (%d bytes)\n",
|
|
+ vr->paddr, vr->paddr + size - 1,
|
|
+ size);
|
|
+
|
|
+ list_for_each_entry(va, &vr->alloc_list, list) {
|
|
+ size = va->pages << PAGE_SHIFT;
|
|
+ seq_printf(m, " %08lx-%08lx (%d bytes)\n",
|
|
+ va->paddr, va->paddr + size - 1,
|
|
+ size);
|
|
+ }
|
|
+
|
|
+
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct seq_operations resource_op = {
|
|
+ .start = r_start,
|
|
+ .next = r_next,
|
|
+ .stop = r_stop,
|
|
+ .show = r_show,
|
|
+};
|
|
+
|
|
+static int vram_open(struct inode *inode, struct file *file)
|
|
+{
|
|
+ return seq_open(file, &resource_op);
|
|
+}
|
|
+
|
|
+static const struct file_operations proc_vram_operations = {
|
|
+ .open = vram_open,
|
|
+ .read = seq_read,
|
|
+ .llseek = seq_lseek,
|
|
+ .release = seq_release,
|
|
+};
|
|
+
|
|
+static int __init omap_vram_create_proc(void)
|
|
+{
|
|
+ proc_create("omap-vram", 0, NULL, &proc_vram_operations);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+#endif
|
|
+
|
|
+static __init int omap_vram_init(void)
|
|
+{
|
|
+ int i, r;
|
|
+
|
|
+ for (i = 0; i < postponed_cnt; i++)
|
|
+ omap_vram_add_region(postponed_regions[i].paddr,
|
|
+ postponed_regions[i].size);
|
|
+
|
|
+#ifdef CONFIG_PROC_FS
|
|
+ r = omap_vram_create_proc();
|
|
+ if (r)
|
|
+ return -ENOMEM;
|
|
+#endif
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+arch_initcall(omap_vram_init);
|
|
+
|
|
+/* boottime vram alloc stuff */
|
|
+
|
|
+/* set from board file */
|
|
+static u32 omapfb_sram_vram_start __initdata;
|
|
+static u32 omapfb_sram_vram_size __initdata;
|
|
+
|
|
+/* set from board file */
|
|
+static u32 omapfb_sdram_vram_start __initdata;
|
|
+static u32 omapfb_sdram_vram_size __initdata;
|
|
+
|
|
+/* set from kernel cmdline */
|
|
+static u32 omapfb_def_sdram_vram_size __initdata;
|
|
+static u32 omapfb_def_sdram_vram_start __initdata;
|
|
+
|
|
+static void __init omapfb_early_vram(char **p)
|
|
+{
|
|
+ omapfb_def_sdram_vram_size = memparse(*p, p);
|
|
+ if (**p == ',')
|
|
+ omapfb_def_sdram_vram_start = simple_strtoul((*p) + 1, p, 16);
|
|
+
|
|
+ printk("omapfb_early_vram, %d, 0x%x\n",
|
|
+ omapfb_def_sdram_vram_size,
|
|
+ omapfb_def_sdram_vram_start);
|
|
+}
|
|
+__early_param("vram=", omapfb_early_vram);
|
|
+
|
|
+/*
|
|
+ * Called from map_io. We need to call to this early enough so that we
|
|
+ * can reserve the fixed SDRAM regions before VM could get hold of them.
|
|
+ */
|
|
+void __init omapfb_reserve_sdram(void)
|
|
+{
|
|
+ struct bootmem_data *bdata;
|
|
+ unsigned long sdram_start, sdram_size;
|
|
+ u32 paddr;
|
|
+ u32 size = 0;
|
|
+
|
|
+ /* cmdline arg overrides the board file definition */
|
|
+ if (omapfb_def_sdram_vram_size) {
|
|
+ size = omapfb_def_sdram_vram_size;
|
|
+ paddr = omapfb_def_sdram_vram_start;
|
|
+ }
|
|
+
|
|
+ if (!size) {
|
|
+ size = omapfb_sdram_vram_size;
|
|
+ paddr = omapfb_sdram_vram_start;
|
|
+ }
|
|
+
|
|
+#ifdef CONFIG_OMAP2_DSS_VRAM_SIZE
|
|
+ if (!size) {
|
|
+ size = CONFIG_OMAP2_DSS_VRAM_SIZE * 1024 * 1024;
|
|
+ paddr = 0;
|
|
+ }
|
|
+#endif
|
|
+
|
|
+ if (!size)
|
|
+ return;
|
|
+
|
|
+ size = PAGE_ALIGN(size);
|
|
+
|
|
+ bdata = NODE_DATA(0)->bdata;
|
|
+ sdram_start = bdata->node_min_pfn << PAGE_SHIFT;
|
|
+ sdram_size = (bdata->node_low_pfn << PAGE_SHIFT) - sdram_start;
|
|
+
|
|
+ if (paddr) {
|
|
+ if ((paddr & ~PAGE_MASK) || paddr < sdram_start ||
|
|
+ paddr + size > sdram_start + sdram_size) {
|
|
+ printk(KERN_ERR "Illegal SDRAM region for VRAM\n");
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ reserve_bootmem(paddr, size, BOOTMEM_DEFAULT);
|
|
+ } else {
|
|
+ if (size > sdram_size) {
|
|
+ printk(KERN_ERR "Illegal SDRAM size for VRAM\n");
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ paddr = virt_to_phys(alloc_bootmem_pages(size));
|
|
+ BUG_ON(paddr & ~PAGE_MASK);
|
|
+ }
|
|
+
|
|
+ omap_vram_add_region_postponed(paddr, size);
|
|
+
|
|
+ pr_info("Reserving %u bytes SDRAM for VRAM\n", size);
|
|
+}
|
|
+
|
|
+/*
|
|
+ * Called at sram init time, before anything is pushed to the SRAM stack.
|
|
+ * Because of the stack scheme, we will allocate everything from the
|
|
+ * start of the lowest address region to the end of SRAM. This will also
|
|
+ * include padding for page alignment and possible holes between regions.
|
|
+ *
|
|
+ * As opposed to the SDRAM case, we'll also do any dynamic allocations at
|
|
+ * this point, since the driver built as a module would have problem with
|
|
+ * freeing / reallocating the regions.
|
|
+ */
|
|
+unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
|
|
+ unsigned long sram_vstart,
|
|
+ unsigned long sram_size,
|
|
+ unsigned long pstart_avail,
|
|
+ unsigned long size_avail)
|
|
+{
|
|
+ unsigned long pend_avail;
|
|
+ unsigned long reserved;
|
|
+ u32 paddr;
|
|
+ u32 size;
|
|
+
|
|
+ paddr = omapfb_sram_vram_start;
|
|
+ size = omapfb_sram_vram_size;
|
|
+
|
|
+ if (!size)
|
|
+ return 0;
|
|
+
|
|
+ reserved = 0;
|
|
+ pend_avail = pstart_avail + size_avail;
|
|
+
|
|
+ if (!paddr) {
|
|
+ /* Dynamic allocation */
|
|
+ if ((size_avail & PAGE_MASK) < size) {
|
|
+ printk(KERN_ERR "Not enough SRAM for VRAM\n");
|
|
+ return 0;
|
|
+ }
|
|
+ size_avail = (size_avail - size) & PAGE_MASK;
|
|
+ paddr = pstart_avail + size_avail;
|
|
+ }
|
|
+
|
|
+ if (paddr < sram_pstart ||
|
|
+ paddr + size > sram_pstart + sram_size) {
|
|
+ printk(KERN_ERR "Illegal SRAM region for VRAM\n");
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
+ /* Reserve everything above the start of the region. */
|
|
+ if (pend_avail - paddr > reserved)
|
|
+ reserved = pend_avail - paddr;
|
|
+ size_avail = pend_avail - reserved - pstart_avail;
|
|
+
|
|
+ omap_vram_add_region_postponed(paddr, size);
|
|
+
|
|
+ if (reserved)
|
|
+ pr_info("Reserving %lu bytes SRAM for VRAM\n", reserved);
|
|
+
|
|
+ return reserved;
|
|
+}
|
|
+
|
|
+void __init omap2_set_sdram_vram(u32 size, u32 start)
|
|
+{
|
|
+ omapfb_sdram_vram_start = start;
|
|
+ omapfb_sdram_vram_size = size;
|
|
+}
|
|
+
|
|
+void __init omap2_set_sram_vram(u32 size, u32 start)
|
|
+{
|
|
+ omapfb_sram_vram_start = start;
|
|
+ omapfb_sram_vram_size = size;
|
|
+}
|
|
+
|
|
+#endif
|
|
+
|
|
diff --git a/arch/arm/plat-omap/vrfb.c b/arch/arm/plat-omap/vrfb.c
|
|
new file mode 100644
|
|
index 0000000..7e0f8fc
|
|
--- /dev/null
|
|
+++ b/arch/arm/plat-omap/vrfb.c
|
|
@@ -0,0 +1,159 @@
|
|
+#include <linux/kernel.h>
|
|
+#include <linux/module.h>
|
|
+#include <linux/ioport.h>
|
|
+#include <asm/io.h>
|
|
+
|
|
+#include <mach/io.h>
|
|
+#include <mach/vrfb.h>
|
|
+
|
|
+/*#define DEBUG*/
|
|
+
|
|
+#ifdef DEBUG
|
|
+#define DBG(format, ...) printk(KERN_DEBUG "VRFB: " format, ## __VA_ARGS__)
|
|
+#else
|
|
+#define DBG(format, ...)
|
|
+#endif
|
|
+
|
|
+#define SMS_ROT_VIRT_BASE(context, rot) \
|
|
+ (((context >= 4) ? 0xD0000000 : 0x70000000) \
|
|
+ | 0x4000000 * (context) \
|
|
+ | 0x1000000 * (rot))
|
|
+
|
|
+#define OMAP_VRFB_SIZE (2048 * 2048 * 4)
|
|
+
|
|
+#define VRFB_PAGE_WIDTH_EXP 5 /* Assuming SDRAM pagesize= 1024 */
|
|
+#define VRFB_PAGE_HEIGHT_EXP 5 /* 1024 = 2^5 * 2^5 */
|
|
+#define VRFB_PAGE_WIDTH (1 << VRFB_PAGE_WIDTH_EXP)
|
|
+#define VRFB_PAGE_HEIGHT (1 << VRFB_PAGE_HEIGHT_EXP)
|
|
+#define SMS_IMAGEHEIGHT_OFFSET 16
|
|
+#define SMS_IMAGEWIDTH_OFFSET 0
|
|
+#define SMS_PH_OFFSET 8
|
|
+#define SMS_PW_OFFSET 4
|
|
+#define SMS_PS_OFFSET 0
|
|
+
|
|
+#define OMAP_SMS_BASE 0x6C000000
|
|
+#define SMS_ROT_CONTROL(context) (OMAP_SMS_BASE + 0x180 + 0x10 * context)
|
|
+#define SMS_ROT_SIZE(context) (OMAP_SMS_BASE + 0x184 + 0x10 * context)
|
|
+#define SMS_ROT_PHYSICAL_BA(context) (OMAP_SMS_BASE + 0x188 + 0x10 * context)
|
|
+
|
|
+#define VRFB_NUM_CTXS 12
|
|
+/* bitmap of reserved contexts */
|
|
+static unsigned ctx_map;
|
|
+
|
|
+void omap_vrfb_adjust_size(u16 *width, u16 *height,
|
|
+ u8 bytespp)
|
|
+{
|
|
+ *width = ALIGN(*width * bytespp, VRFB_PAGE_WIDTH) / bytespp;
|
|
+ *height = ALIGN(*height, VRFB_PAGE_HEIGHT);
|
|
+}
|
|
+EXPORT_SYMBOL(omap_vrfb_adjust_size);
|
|
+
|
|
+void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
|
|
+ u16 width, u16 height,
|
|
+ u8 bytespp)
|
|
+{
|
|
+ unsigned pixel_size_exp;
|
|
+ u16 vrfb_width;
|
|
+ u16 vrfb_height;
|
|
+ u8 ctx = vrfb->context;
|
|
+
|
|
+ DBG("omapfb_set_vrfb(%d, %lx, %dx%d, %d)\n", ctx, paddr,
|
|
+ width, height, bytespp);
|
|
+
|
|
+ if (bytespp == 4)
|
|
+ pixel_size_exp = 2;
|
|
+ else if (bytespp == 2)
|
|
+ pixel_size_exp = 1;
|
|
+ else
|
|
+ BUG();
|
|
+
|
|
+ vrfb_width = ALIGN(width * bytespp, VRFB_PAGE_WIDTH) / bytespp;
|
|
+ vrfb_height = ALIGN(height, VRFB_PAGE_HEIGHT);
|
|
+
|
|
+ DBG("vrfb w %u, h %u\n", vrfb_width, vrfb_height);
|
|
+
|
|
+ omap_writel(paddr, SMS_ROT_PHYSICAL_BA(ctx));
|
|
+ omap_writel((vrfb_width << SMS_IMAGEWIDTH_OFFSET) |
|
|
+ (vrfb_height << SMS_IMAGEHEIGHT_OFFSET),
|
|
+ SMS_ROT_SIZE(ctx));
|
|
+
|
|
+ omap_writel(pixel_size_exp << SMS_PS_OFFSET |
|
|
+ VRFB_PAGE_WIDTH_EXP << SMS_PW_OFFSET |
|
|
+ VRFB_PAGE_HEIGHT_EXP << SMS_PH_OFFSET,
|
|
+ SMS_ROT_CONTROL(ctx));
|
|
+
|
|
+ DBG("vrfb offset pixels %d, %d\n",
|
|
+ vrfb_width - width, vrfb_height - height);
|
|
+
|
|
+ vrfb->xoffset = vrfb_width - width;
|
|
+ vrfb->yoffset = vrfb_height - height;
|
|
+ vrfb->bytespp = bytespp;
|
|
+}
|
|
+EXPORT_SYMBOL(omap_vrfb_setup);
|
|
+
|
|
+void omap_vrfb_release_ctx(struct vrfb *vrfb)
|
|
+{
|
|
+ int rot;
|
|
+
|
|
+ if (vrfb->context == 0xff)
|
|
+ return;
|
|
+
|
|
+ DBG("release ctx %d\n", vrfb->context);
|
|
+
|
|
+ ctx_map &= ~(1 << vrfb->context);
|
|
+
|
|
+ for (rot = 0; rot < 4; ++rot) {
|
|
+ if(vrfb->paddr[rot]) {
|
|
+ release_mem_region(vrfb->paddr[rot], OMAP_VRFB_SIZE);
|
|
+ vrfb->paddr[rot] = 0;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ vrfb->context = 0xff;
|
|
+}
|
|
+EXPORT_SYMBOL(omap_vrfb_release_ctx);
|
|
+
|
|
+int omap_vrfb_request_ctx(struct vrfb *vrfb)
|
|
+{
|
|
+ int rot;
|
|
+ u32 paddr;
|
|
+ u8 ctx;
|
|
+
|
|
+ DBG("request ctx\n");
|
|
+
|
|
+ for (ctx = 0; ctx < VRFB_NUM_CTXS; ++ctx)
|
|
+ if ((ctx_map & (1 << ctx)) == 0)
|
|
+ break;
|
|
+
|
|
+ if (ctx == VRFB_NUM_CTXS) {
|
|
+ printk(KERN_ERR "vrfb: no free contexts\n");
|
|
+ return -EBUSY;
|
|
+ }
|
|
+
|
|
+ DBG("found free ctx %d\n", ctx);
|
|
+
|
|
+ ctx_map |= 1 << ctx;
|
|
+
|
|
+ memset(vrfb, 0, sizeof(*vrfb));
|
|
+
|
|
+ vrfb->context = ctx;
|
|
+
|
|
+ for (rot = 0; rot < 4; ++rot) {
|
|
+ paddr = SMS_ROT_VIRT_BASE(ctx, rot);
|
|
+ if (!request_mem_region(paddr, OMAP_VRFB_SIZE, "vrfb")) {
|
|
+ printk(KERN_ERR "vrfb: failed to reserve VRFB "
|
|
+ "area for ctx %d, rotation %d\n",
|
|
+ ctx, rot * 90);
|
|
+ omap_vrfb_release_ctx(vrfb);
|
|
+ return -ENOMEM;
|
|
+ }
|
|
+
|
|
+ vrfb->paddr[rot] = paddr;
|
|
+
|
|
+ DBG("VRFB %d/%d: %lx\n", ctx, rot*90, vrfb->paddr[rot]);
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+EXPORT_SYMBOL(omap_vrfb_request_ctx);
|
|
+
|
|
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
|
|
index fb19803..8b3752b 100644
|
|
--- a/drivers/video/Kconfig
|
|
+++ b/drivers/video/Kconfig
|
|
@@ -2132,6 +2132,7 @@ config FB_MX3
|
|
an LCD display with your i.MX31 system, say Y here.
|
|
|
|
source "drivers/video/omap/Kconfig"
|
|
+source "drivers/video/omap2/Kconfig"
|
|
|
|
source "drivers/video/backlight/Kconfig"
|
|
source "drivers/video/display/Kconfig"
|
|
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
|
|
index 2a998ca..1db8dd4 100644
|
|
--- a/drivers/video/Makefile
|
|
+++ b/drivers/video/Makefile
|
|
@@ -120,6 +120,7 @@ obj-$(CONFIG_FB_SM501) += sm501fb.o
|
|
obj-$(CONFIG_FB_XILINX) += xilinxfb.o
|
|
obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o
|
|
obj-$(CONFIG_FB_OMAP) += omap/
|
|
+obj-$(CONFIG_OMAP2_DSS) += omap2/
|
|
obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o
|
|
obj-$(CONFIG_FB_CARMINE) += carminefb.o
|
|
obj-$(CONFIG_FB_MB862XX) += mb862xx/
|
|
diff --git a/drivers/video/omap2/Kconfig b/drivers/video/omap2/Kconfig
|
|
new file mode 100644
|
|
index 0000000..89bf210
|
|
--- /dev/null
|
|
+++ b/drivers/video/omap2/Kconfig
|
|
@@ -0,0 +1,3 @@
|
|
+source "drivers/video/omap2/dss/Kconfig"
|
|
+source "drivers/video/omap2/displays/Kconfig"
|
|
+source "drivers/video/omap2/omapfb/Kconfig"
|
|
diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
|
|
new file mode 100644
|
|
index 0000000..72134db
|
|
--- /dev/null
|
|
+++ b/drivers/video/omap2/Makefile
|
|
@@ -0,0 +1,4 @@
|
|
+# OMAP2/3 Display Subsystem
|
|
+obj-y += dss/
|
|
+obj-y += displays/
|
|
+obj-y += omapfb/
|
|
diff --git a/drivers/video/omap2/dss/Kconfig b/drivers/video/omap2/dss/Kconfig
|
|
new file mode 100644
|
|
index 0000000..f2ce068
|
|
--- /dev/null
|
|
+++ b/drivers/video/omap2/dss/Kconfig
|
|
@@ -0,0 +1,89 @@
|
|
+menuconfig OMAP2_DSS
|
|
+ tristate "OMAP2/3 Display Subsystem support (EXPERIMENTAL)"
|
|
+ depends on ARCH_OMAP2 || ARCH_OMAP3
|
|
+ help
|
|
+ OMAP2/3 Display Subsystem support.
|
|
+
|
|
+if OMAP2_DSS
|
|
+
|
|
+config OMAP2_DSS_VRAM_SIZE
|
|
+ int "VRAM size (MB)"
|
|
+ range 0 32
|
|
+ default 4
|
|
+ help
|
|
+ The amount of SDRAM to reserve at boot time for video RAM use.
|
|
+ This VRAM will be used by omapfb and other drivers that need
|
|
+ large continuous RAM area for video use.
|
|
+
|
|
+ You can also set this with "vram=<bytes>" kernel argument, or
|
|
+ in the board file.
|
|
+
|
|
+config OMAP2_DSS_DEBUG_SUPPORT
|
|
+ bool "Debug support"
|
|
+ default y
|
|
+ help
|
|
+ This enables debug messages. You need to enable printing
|
|
+ with 'debug' module parameter.
|
|
+
|
|
+config OMAP2_DSS_RFBI
|
|
+ bool "RFBI support"
|
|
+ default n
|
|
+ help
|
|
+ MIPI DBI, or RFBI (Remote Framebuffer Interface), support.
|
|
+
|
|
+config OMAP2_DSS_VENC
|
|
+ bool "VENC support"
|
|
+ default y
|
|
+ help
|
|
+ OMAP Video Encoder support.
|
|
+
|
|
+config OMAP2_DSS_SDI
|
|
+ bool "SDI support"
|
|
+ depends on ARCH_OMAP3
|
|
+ default n
|
|
+ help
|
|
+ SDI (Serial Display Interface) support.
|
|
+
|
|
+config OMAP2_DSS_DSI
|
|
+ bool "DSI support"
|
|
+ depends on ARCH_OMAP3
|
|
+ default n
|
|
+ help
|
|
+ MIPI DSI support.
|
|
+
|
|
+config OMAP2_DSS_USE_DSI_PLL
|
|
+ bool "Use DSI PLL for PCLK (EXPERIMENTAL)"
|
|
+ default n
|
|
+ depends on OMAP2_DSS_DSI
|
|
+ help
|
|
+ Use DSI PLL to generate pixel clock. Currently only for DPI output.
|
|
+ DSI PLL can be used to generate higher and more precise pixel clocks.
|
|
+
|
|
+config OMAP2_DSS_FAKE_VSYNC
|
|
+ bool "Fake VSYNC irq from manual update displays"
|
|
+ default n
|
|
+ help
|
|
+ If this is selected, DSI will generate a fake DISPC VSYNC interrupt
|
|
+ when DSI has sent a frame. This is only needed with DSI or RFBI
|
|
+ displays using manual mode, and you want VSYNC to, for example,
|
|
+ time animation.
|
|
+
|
|
+config OMAP2_DSS_MIN_FCK_PER_PCK
|
|
+ int "Minimum FCK/PCK ratio (for scaling)"
|
|
+ range 0 32
|
|
+ default 0
|
|
+ help
|
|
+ This can be used to adjust the minimum FCK/PCK ratio.
|
|
+
|
|
+ With this you can make sure that DISPC FCK is at least
|
|
+ n x PCK. Video plane scaling requires higher FCK than
|
|
+ normally.
|
|
+
|
|
+ If this is set to 0, there's no extra constraint on the
|
|
+ DISPC FCK. However, the FCK will at minimum be
|
|
+ 2xPCK (if active matrix) or 3xPCK (if passive matrix).
|
|
+
|
|
+ Max FCK is 173MHz, so this doesn't work if your PCK
|
|
+ is very high.
|
|
+
|
|
+endif
|
|
diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile
|
|
new file mode 100644
|
|
index 0000000..980c72c
|
|
--- /dev/null
|
|
+++ b/drivers/video/omap2/dss/Makefile
|
|
@@ -0,0 +1,6 @@
|
|
+obj-$(CONFIG_OMAP2_DSS) += omapdss.o
|
|
+omapdss-y := core.o dss.o dispc.o dpi.o display.o manager.o overlay.o
|
|
+omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o
|
|
+omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o
|
|
+omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o
|
|
+omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
|
|
diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
|
|
new file mode 100644
|
|
index 0000000..ae7cd06
|
|
--- /dev/null
|
|
+++ b/drivers/video/omap2/dss/core.c
|
|
@@ -0,0 +1,641 @@
|
|
+/*
|
|
+ * linux/drivers/video/omap2/dss/core.c
|
|
+ *
|
|
+ * Copyright (C) 2009 Nokia Corporation
|
|
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
|
|
+ *
|
|
+ * Some code and ideas taken from drivers/video/omap/ driver
|
|
+ * by Imre Deak.
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published by
|
|
+ * the Free Software Foundation.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful, but WITHOUT
|
|
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
+ * more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License along with
|
|
+ * this program. If not, see <http://www.gnu.org/licenses/>.
|
|
+ */
|
|
+
|
|
+#define DSS_SUBSYS_NAME "CORE"
|
|
+
|
|
+#include <linux/kernel.h>
|
|
+#include <linux/module.h>
|
|
+#include <linux/clk.h>
|
|
+#include <linux/err.h>
|
|
+#include <linux/platform_device.h>
|
|
+#include <linux/seq_file.h>
|
|
+#include <linux/debugfs.h>
|
|
+#include <linux/io.h>
|
|
+
|
|
+#include <mach/display.h>
|
|
+#include <mach/clock.h>
|
|
+
|
|
+#include "dss.h"
|
|
+
|
|
+static struct {
|
|
+ struct platform_device *pdev;
|
|
+ unsigned ctx_id;
|
|
+
|
|
+ struct clk *dss_ick;
|
|
+ struct clk *dss1_fck;
|
|
+ struct clk *dss2_fck;
|
|
+ struct clk *dss_54m_fck;
|
|
+ struct clk *dss_96m_fck;
|
|
+ unsigned num_clks_enabled;
|
|
+} core;
|
|
+
|
|
+static void dss_clk_enable_all_no_ctx(void);
|
|
+static void dss_clk_disable_all_no_ctx(void);
|
|
+static void dss_clk_enable_no_ctx(enum dss_clock clks);
|
|
+static void dss_clk_disable_no_ctx(enum dss_clock clks);
|
|
+
|
|
+static char *def_disp_name;
|
|
+module_param_named(def_disp, def_disp_name, charp, 0);
|
|
+MODULE_PARM_DESC(def_disp_name, "default display name");
|
|
+
|
|
+#ifdef DEBUG
|
|
+unsigned int dss_debug;
|
|
+module_param_named(debug, dss_debug, bool, 0644);
|
|
+#endif
|
|
+
|
|
+/* CONTEXT */
|
|
+static unsigned dss_get_ctx_id(void)
|
|
+{
|
|
+ struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
|
|
+
|
|
+ if (!pdata->get_last_off_on_transaction_id)
|
|
+ return 0;
|
|
+
|
|
+ return pdata->get_last_off_on_transaction_id(&core.pdev->dev);
|
|
+}
|
|
+
|
|
+int dss_need_ctx_restore(void)
|
|
+{
|
|
+ int id = dss_get_ctx_id();
|
|
+
|
|
+ if (id != core.ctx_id) {
|
|
+ DSSDBG("ctx id %u -> id %u\n",
|
|
+ core.ctx_id, id);
|
|
+ core.ctx_id = id;
|
|
+ return 1;
|
|
+ } else {
|
|
+ return 0;
|
|
+ }
|
|
+}
|
|
+
|
|
+static void save_all_ctx(void)
|
|
+{
|
|
+ DSSDBG("save context\n");
|
|
+
|
|
+ dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+
|
|
+ dss_save_context();
|
|
+ dispc_save_context();
|
|
+#ifdef CONFIG_OMAP2_DSS_DSI
|
|
+ dsi_save_context();
|
|
+#endif
|
|
+
|
|
+ dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+}
|
|
+
|
|
+static void restore_all_ctx(void)
|
|
+{
|
|
+ DSSDBG("restore context\n");
|
|
+
|
|
+ dss_clk_enable_all_no_ctx();
|
|
+
|
|
+ dss_restore_context();
|
|
+ dispc_restore_context();
|
|
+#ifdef CONFIG_OMAP2_DSS_DSI
|
|
+ dsi_restore_context();
|
|
+#endif
|
|
+
|
|
+ dss_clk_disable_all_no_ctx();
|
|
+}
|
|
+
|
|
+/* CLOCKS */
|
|
+void dss_dump_clocks(struct seq_file *s)
|
|
+{
|
|
+ int i;
|
|
+ struct clk *clocks[5] = {
|
|
+ core.dss_ick,
|
|
+ core.dss1_fck,
|
|
+ core.dss2_fck,
|
|
+ core.dss_54m_fck,
|
|
+ core.dss_96m_fck
|
|
+ };
|
|
+
|
|
+ seq_printf(s, "- dss -\n");
|
|
+
|
|
+ seq_printf(s, "internal clk count\t%u\n", core.num_clks_enabled);
|
|
+
|
|
+ for (i = 0; i < 5; i++) {
|
|
+ if (!clocks[i])
|
|
+ continue;
|
|
+ seq_printf(s, "%-15s\t%lu\t%d\n",
|
|
+ clocks[i]->name,
|
|
+ clk_get_rate(clocks[i]),
|
|
+ clocks[i]->usecount);
|
|
+ }
|
|
+}
|
|
+
|
|
+static int dss_get_clocks(void)
|
|
+{
|
|
+ const struct {
|
|
+ struct clk **clock;
|
|
+ char *omap2_name;
|
|
+ char *omap3_name;
|
|
+ } clocks[5] = {
|
|
+ { &core.dss_ick, "dss_ick", "dss_ick" }, /* L3 & L4 ick */
|
|
+ { &core.dss1_fck, "dss1_fck", "dss1_alwon_fck" },
|
|
+ { &core.dss2_fck, "dss2_fck", "dss2_alwon_fck" },
|
|
+ { &core.dss_54m_fck, "dss_54m_fck", "dss_tv_fck" },
|
|
+ { &core.dss_96m_fck, NULL, "dss_96m_fck" },
|
|
+ };
|
|
+
|
|
+ int r = 0;
|
|
+ int i;
|
|
+ const int num_clocks = 5;
|
|
+
|
|
+ for (i = 0; i < num_clocks; i++)
|
|
+ *clocks[i].clock = NULL;
|
|
+
|
|
+ for (i = 0; i < num_clocks; i++) {
|
|
+ struct clk *clk;
|
|
+ const char *clk_name;
|
|
+
|
|
+ clk_name = cpu_is_omap34xx() ? clocks[i].omap3_name
|
|
+ : clocks[i].omap2_name;
|
|
+
|
|
+ if (!clk_name)
|
|
+ continue;
|
|
+
|
|
+ clk = clk_get(NULL, clk_name);
|
|
+
|
|
+ if (IS_ERR(clk)) {
|
|
+ DSSERR("can't get clock %s", clk_name);
|
|
+ r = PTR_ERR(clk);
|
|
+ goto err;
|
|
+ }
|
|
+
|
|
+ DSSDBG("clk %s, rate %ld\n",
|
|
+ clk_name, clk_get_rate(clk));
|
|
+
|
|
+ *clocks[i].clock = clk;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+
|
|
+err:
|
|
+ for (i = 0; i < num_clocks; i++) {
|
|
+ if (!IS_ERR(*clocks[i].clock))
|
|
+ clk_put(*clocks[i].clock);
|
|
+ }
|
|
+
|
|
+ return r;
|
|
+}
|
|
+
|
|
+static void dss_put_clocks(void)
|
|
+{
|
|
+ if (core.dss_96m_fck)
|
|
+ clk_put(core.dss_96m_fck);
|
|
+ clk_put(core.dss_54m_fck);
|
|
+ clk_put(core.dss1_fck);
|
|
+ clk_put(core.dss2_fck);
|
|
+ clk_put(core.dss_ick);
|
|
+}
|
|
+
|
|
+unsigned long dss_clk_get_rate(enum dss_clock clk)
|
|
+{
|
|
+ switch (clk) {
|
|
+ case DSS_CLK_ICK:
|
|
+ return clk_get_rate(core.dss_ick);
|
|
+ case DSS_CLK_FCK1:
|
|
+ return clk_get_rate(core.dss1_fck);
|
|
+ case DSS_CLK_FCK2:
|
|
+ return clk_get_rate(core.dss2_fck);
|
|
+ case DSS_CLK_54M:
|
|
+ return clk_get_rate(core.dss_54m_fck);
|
|
+ case DSS_CLK_96M:
|
|
+ return clk_get_rate(core.dss_96m_fck);
|
|
+ }
|
|
+
|
|
+ BUG();
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static unsigned count_clk_bits(enum dss_clock clks)
|
|
+{
|
|
+ unsigned num_clks = 0;
|
|
+
|
|
+ if (clks & DSS_CLK_ICK)
|
|
+ ++num_clks;
|
|
+ if (clks & DSS_CLK_FCK1)
|
|
+ ++num_clks;
|
|
+ if (clks & DSS_CLK_FCK2)
|
|
+ ++num_clks;
|
|
+ if (clks & DSS_CLK_54M)
|
|
+ ++num_clks;
|
|
+ if (clks & DSS_CLK_96M)
|
|
+ ++num_clks;
|
|
+
|
|
+ return num_clks;
|
|
+}
|
|
+
|
|
+static void dss_clk_enable_no_ctx(enum dss_clock clks)
|
|
+{
|
|
+ unsigned num_clks = count_clk_bits(clks);
|
|
+
|
|
+ if (clks & DSS_CLK_ICK)
|
|
+ clk_enable(core.dss_ick);
|
|
+ if (clks & DSS_CLK_FCK1)
|
|
+ clk_enable(core.dss1_fck);
|
|
+ if (clks & DSS_CLK_FCK2)
|
|
+ clk_enable(core.dss2_fck);
|
|
+ if (clks & DSS_CLK_54M)
|
|
+ clk_enable(core.dss_54m_fck);
|
|
+ if (clks & DSS_CLK_96M)
|
|
+ clk_enable(core.dss_96m_fck);
|
|
+
|
|
+ core.num_clks_enabled += num_clks;
|
|
+}
|
|
+
|
|
+void dss_clk_enable(enum dss_clock clks)
|
|
+{
|
|
+ dss_clk_enable_no_ctx(clks);
|
|
+
|
|
+ if (cpu_is_omap34xx() && dss_need_ctx_restore())
|
|
+ restore_all_ctx();
|
|
+}
|
|
+
|
|
+static void dss_clk_disable_no_ctx(enum dss_clock clks)
|
|
+{
|
|
+ unsigned num_clks = count_clk_bits(clks);
|
|
+
|
|
+ if (clks & DSS_CLK_ICK)
|
|
+ clk_disable(core.dss_ick);
|
|
+ if (clks & DSS_CLK_FCK1)
|
|
+ clk_disable(core.dss1_fck);
|
|
+ if (clks & DSS_CLK_FCK2)
|
|
+ clk_disable(core.dss2_fck);
|
|
+ if (clks & DSS_CLK_54M)
|
|
+ clk_disable(core.dss_54m_fck);
|
|
+ if (clks & DSS_CLK_96M)
|
|
+ clk_disable(core.dss_96m_fck);
|
|
+
|
|
+ core.num_clks_enabled -= num_clks;
|
|
+}
|
|
+
|
|
+void dss_clk_disable(enum dss_clock clks)
|
|
+{
|
|
+ if (cpu_is_omap34xx()) {
|
|
+ unsigned num_clks = count_clk_bits(clks);
|
|
+
|
|
+ BUG_ON(core.num_clks_enabled < num_clks);
|
|
+
|
|
+ if (core.num_clks_enabled == num_clks)
|
|
+ save_all_ctx();
|
|
+ }
|
|
+
|
|
+ dss_clk_disable_no_ctx(clks);
|
|
+}
|
|
+
|
|
+static void dss_clk_enable_all_no_ctx(void)
|
|
+{
|
|
+ enum dss_clock clks;
|
|
+
|
|
+ clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
|
|
+ if (cpu_is_omap34xx())
|
|
+ clks |= DSS_CLK_96M;
|
|
+ dss_clk_enable_no_ctx(clks);
|
|
+}
|
|
+
|
|
+static void dss_clk_disable_all_no_ctx(void)
|
|
+{
|
|
+ enum dss_clock clks;
|
|
+
|
|
+ clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
|
|
+ if (cpu_is_omap34xx())
|
|
+ clks |= DSS_CLK_96M;
|
|
+ dss_clk_disable_no_ctx(clks);
|
|
+}
|
|
+
|
|
+static void dss_clk_disable_all(void)
|
|
+{
|
|
+ enum dss_clock clks;
|
|
+
|
|
+ clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
|
|
+ if (cpu_is_omap34xx())
|
|
+ clks |= DSS_CLK_96M;
|
|
+ dss_clk_disable(clks);
|
|
+}
|
|
+
|
|
+/* DEBUGFS */
|
|
+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
|
|
+static void dss_debug_dump_clocks(struct seq_file *s)
|
|
+{
|
|
+ dss_dump_clocks(s);
|
|
+ dispc_dump_clocks(s);
|
|
+#ifdef CONFIG_OMAP2_DSS_DSI
|
|
+ dsi_dump_clocks(s);
|
|
+#endif
|
|
+}
|
|
+
|
|
+static int dss_debug_show(struct seq_file *s, void *unused)
|
|
+{
|
|
+ void (*func)(struct seq_file *) = s->private;
|
|
+ func(s);
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int dss_debug_open(struct inode *inode, struct file *file)
|
|
+{
|
|
+ return single_open(file, dss_debug_show, inode->i_private);
|
|
+}
|
|
+
|
|
+static const struct file_operations dss_debug_fops = {
|
|
+ .open = dss_debug_open,
|
|
+ .read = seq_read,
|
|
+ .llseek = seq_lseek,
|
|
+ .release = single_release,
|
|
+};
|
|
+
|
|
+static struct dentry *dss_debugfs_dir;
|
|
+
|
|
+static int dss_initialize_debugfs(void)
|
|
+{
|
|
+ dss_debugfs_dir = debugfs_create_dir("omapdss", NULL);
|
|
+ if (IS_ERR(dss_debugfs_dir)) {
|
|
+ int err = PTR_ERR(dss_debugfs_dir);
|
|
+ dss_debugfs_dir = NULL;
|
|
+ return err;
|
|
+ }
|
|
+
|
|
+ debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir,
|
|
+ &dss_debug_dump_clocks, &dss_debug_fops);
|
|
+
|
|
+ debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir,
|
|
+ &dss_dump_regs, &dss_debug_fops);
|
|
+ debugfs_create_file("dispc", S_IRUGO, dss_debugfs_dir,
|
|
+ &dispc_dump_regs, &dss_debug_fops);
|
|
+#ifdef CONFIG_OMAP2_DSS_RFBI
|
|
+ debugfs_create_file("rfbi", S_IRUGO, dss_debugfs_dir,
|
|
+ &rfbi_dump_regs, &dss_debug_fops);
|
|
+#endif
|
|
+#ifdef CONFIG_OMAP2_DSS_DSI
|
|
+ debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir,
|
|
+ &dsi_dump_regs, &dss_debug_fops);
|
|
+#endif
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void dss_uninitialize_debugfs(void)
|
|
+{
|
|
+ if (dss_debugfs_dir)
|
|
+ debugfs_remove_recursive(dss_debugfs_dir);
|
|
+}
|
|
+#endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */
|
|
+
|
|
+
|
|
+/* DSI powers */
|
|
+int dss_dsi_power_up(void)
|
|
+{
|
|
+ struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
|
|
+
|
|
+ if (!pdata->dsi_power_up)
|
|
+ return 0; /* presume power is always on then */
|
|
+
|
|
+ return pdata->dsi_power_up();
|
|
+}
|
|
+
|
|
+void dss_dsi_power_down(void)
|
|
+{
|
|
+ struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
|
|
+
|
|
+ if (!pdata->dsi_power_down)
|
|
+ return;
|
|
+
|
|
+ pdata->dsi_power_down();
|
|
+}
|
|
+
|
|
+
|
|
+
|
|
+/* PLATFORM DEVICE */
|
|
+static int omap_dss_probe(struct platform_device *pdev)
|
|
+{
|
|
+ int skip_init = 0;
|
|
+ int r;
|
|
+
|
|
+ core.pdev = pdev;
|
|
+
|
|
+ r = dss_get_clocks();
|
|
+ if (r)
|
|
+ goto fail0;
|
|
+
|
|
+ dss_clk_enable_all_no_ctx();
|
|
+
|
|
+ core.ctx_id = dss_get_ctx_id();
|
|
+ DSSDBG("initial ctx id %u\n", core.ctx_id);
|
|
+
|
|
+#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
|
|
+ /* DISPC_CONTROL */
|
|
+ if (omap_readl(0x48050440) & 1) /* LCD enabled? */
|
|
+ skip_init = 1;
|
|
+#endif
|
|
+
|
|
+ r = dss_init(skip_init);
|
|
+ if (r) {
|
|
+ DSSERR("Failed to initialize DSS\n");
|
|
+ goto fail0;
|
|
+ }
|
|
+
|
|
+#ifdef CONFIG_OMAP2_DSS_RFBI
|
|
+ r = rfbi_init();
|
|
+ if (r) {
|
|
+ DSSERR("Failed to initialize rfbi\n");
|
|
+ goto fail0;
|
|
+ }
|
|
+#endif
|
|
+
|
|
+ r = dpi_init();
|
|
+ if (r) {
|
|
+ DSSERR("Failed to initialize dpi\n");
|
|
+ goto fail0;
|
|
+ }
|
|
+
|
|
+ r = dispc_init();
|
|
+ if (r) {
|
|
+ DSSERR("Failed to initialize dispc\n");
|
|
+ goto fail0;
|
|
+ }
|
|
+#ifdef CONFIG_OMAP2_DSS_VENC
|
|
+ r = venc_init();
|
|
+ if (r) {
|
|
+ DSSERR("Failed to initialize venc\n");
|
|
+ goto fail0;
|
|
+ }
|
|
+#endif
|
|
+ if (cpu_is_omap34xx()) {
|
|
+#ifdef CONFIG_OMAP2_DSS_SDI
|
|
+ r = sdi_init(skip_init);
|
|
+ if (r) {
|
|
+ DSSERR("Failed to initialize SDI\n");
|
|
+ goto fail0;
|
|
+ }
|
|
+#endif
|
|
+#ifdef CONFIG_OMAP2_DSS_DSI
|
|
+ r = dsi_init();
|
|
+ if (r) {
|
|
+ DSSERR("Failed to initialize DSI\n");
|
|
+ goto fail0;
|
|
+ }
|
|
+#endif
|
|
+ }
|
|
+
|
|
+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
|
|
+ r = dss_initialize_debugfs();
|
|
+ if (r)
|
|
+ goto fail0;
|
|
+#endif
|
|
+
|
|
+ dss_init_displays(pdev);
|
|
+ dss_init_overlay_managers(pdev);
|
|
+ dss_init_overlays(pdev, def_disp_name);
|
|
+
|
|
+ dss_clk_disable_all();
|
|
+
|
|
+ return 0;
|
|
+
|
|
+ /* XXX fail correctly */
|
|
+fail0:
|
|
+ return r;
|
|
+}
|
|
+
|
|
+static int omap_dss_remove(struct platform_device *pdev)
|
|
+{
|
|
+ int c;
|
|
+
|
|
+ dss_uninit_overlays(pdev);
|
|
+ dss_uninit_overlay_managers(pdev);
|
|
+ dss_uninit_displays(pdev);
|
|
+
|
|
+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
|
|
+ dss_uninitialize_debugfs();
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_OMAP2_DSS_VENC
|
|
+ venc_exit();
|
|
+#endif
|
|
+ dispc_exit();
|
|
+ dpi_exit();
|
|
+#ifdef CONFIG_OMAP2_DSS_RFBI
|
|
+ rfbi_exit();
|
|
+#endif
|
|
+ if (cpu_is_omap34xx()) {
|
|
+#ifdef CONFIG_OMAP2_DSS_DSI
|
|
+ dsi_exit();
|
|
+#endif
|
|
+#ifdef CONFIG_OMAP2_DSS_SDI
|
|
+ sdi_exit();
|
|
+#endif
|
|
+ }
|
|
+
|
|
+ dss_exit();
|
|
+
|
|
+ /* these should be removed at some point */
|
|
+ c = core.dss_ick->usecount;
|
|
+ if (c > 0) {
|
|
+ DSSERR("warning: dss_ick usecount %d, disabling\n", c);
|
|
+ while (c-- > 0)
|
|
+ clk_disable(core.dss_ick);
|
|
+ }
|
|
+
|
|
+ c = core.dss1_fck->usecount;
|
|
+ if (c > 0) {
|
|
+ DSSERR("warning: dss1_fck usecount %d, disabling\n", c);
|
|
+ while (c-- > 0)
|
|
+ clk_disable(core.dss1_fck);
|
|
+ }
|
|
+
|
|
+ c = core.dss2_fck->usecount;
|
|
+ if (c > 0) {
|
|
+ DSSERR("warning: dss2_fck usecount %d, disabling\n", c);
|
|
+ while (c-- > 0)
|
|
+ clk_disable(core.dss2_fck);
|
|
+ }
|
|
+
|
|
+ c = core.dss_54m_fck->usecount;
|
|
+ if (c > 0) {
|
|
+ DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c);
|
|
+ while (c-- > 0)
|
|
+ clk_disable(core.dss_54m_fck);
|
|
+ }
|
|
+
|
|
+ if (core.dss_96m_fck) {
|
|
+ c = core.dss_96m_fck->usecount;
|
|
+ if (c > 0) {
|
|
+ DSSERR("warning: dss_96m_fck usecount %d, disabling\n",
|
|
+ c);
|
|
+ while (c-- > 0)
|
|
+ clk_disable(core.dss_96m_fck);
|
|
+ }
|
|
+ }
|
|
+
|
|
+ dss_put_clocks();
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void omap_dss_shutdown(struct platform_device *pdev)
|
|
+{
|
|
+ DSSDBG("shutdown\n");
|
|
+}
|
|
+
|
|
+static int omap_dss_suspend(struct platform_device *pdev, pm_message_t state)
|
|
+{
|
|
+ DSSDBG("suspend %d\n", state.event);
|
|
+
|
|
+ return dss_suspend_all_displays();
|
|
+}
|
|
+
|
|
+static int omap_dss_resume(struct platform_device *pdev)
|
|
+{
|
|
+ DSSDBG("resume\n");
|
|
+
|
|
+ return dss_resume_all_displays();
|
|
+}
|
|
+
|
|
+static struct platform_driver omap_dss_driver = {
|
|
+ .probe = omap_dss_probe,
|
|
+ .remove = omap_dss_remove,
|
|
+ .shutdown = omap_dss_shutdown,
|
|
+ .suspend = omap_dss_suspend,
|
|
+ .resume = omap_dss_resume,
|
|
+ .driver = {
|
|
+ .name = "omapdss",
|
|
+ .owner = THIS_MODULE,
|
|
+ },
|
|
+};
|
|
+
|
|
+static int __init omap_dss_init(void)
|
|
+{
|
|
+ return platform_driver_register(&omap_dss_driver);
|
|
+}
|
|
+
|
|
+static void __exit omap_dss_exit(void)
|
|
+{
|
|
+ platform_driver_unregister(&omap_dss_driver);
|
|
+}
|
|
+
|
|
+subsys_initcall(omap_dss_init);
|
|
+module_exit(omap_dss_exit);
|
|
+
|
|
+
|
|
+MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
|
|
+MODULE_DESCRIPTION("OMAP2/3 Display Subsystem");
|
|
+MODULE_LICENSE("GPL v2");
|
|
+
|
|
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
|
|
new file mode 100644
|
|
index 0000000..ffb5648
|
|
--- /dev/null
|
|
+++ b/drivers/video/omap2/dss/dispc.c
|
|
@@ -0,0 +1,2968 @@
|
|
+/*
|
|
+ * linux/drivers/video/omap2/dss/dispc.c
|
|
+ *
|
|
+ * Copyright (C) 2009 Nokia Corporation
|
|
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
|
|
+ *
|
|
+ * Some code and ideas taken from drivers/video/omap/ driver
|
|
+ * by Imre Deak.
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published by
|
|
+ * the Free Software Foundation.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful, but WITHOUT
|
|
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
+ * more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License along with
|
|
+ * this program. If not, see <http://www.gnu.org/licenses/>.
|
|
+ */
|
|
+
|
|
+#define DSS_SUBSYS_NAME "DISPC"
|
|
+
|
|
+#include <linux/kernel.h>
|
|
+#include <linux/dma-mapping.h>
|
|
+#include <linux/vmalloc.h>
|
|
+#include <linux/clk.h>
|
|
+#include <linux/io.h>
|
|
+#include <linux/jiffies.h>
|
|
+#include <linux/seq_file.h>
|
|
+#include <linux/delay.h>
|
|
+#include <linux/workqueue.h>
|
|
+
|
|
+#include <mach/sram.h>
|
|
+#include <mach/board.h>
|
|
+#include <mach/clock.h>
|
|
+
|
|
+#include <mach/display.h>
|
|
+
|
|
+#include "dss.h"
|
|
+
|
|
+/* DISPC */
|
|
+#define DISPC_BASE 0x48050400
|
|
+
|
|
+#define DISPC_SZ_REGS SZ_1K
|
|
+
|
|
+struct dispc_reg { u16 idx; };
|
|
+
|
|
+#define DISPC_REG(idx) ((const struct dispc_reg) { idx })
|
|
+
|
|
+/* DISPC common */
|
|
+#define DISPC_REVISION DISPC_REG(0x0000)
|
|
+#define DISPC_SYSCONFIG DISPC_REG(0x0010)
|
|
+#define DISPC_SYSSTATUS DISPC_REG(0x0014)
|
|
+#define DISPC_IRQSTATUS DISPC_REG(0x0018)
|
|
+#define DISPC_IRQENABLE DISPC_REG(0x001C)
|
|
+#define DISPC_CONTROL DISPC_REG(0x0040)
|
|
+#define DISPC_CONFIG DISPC_REG(0x0044)
|
|
+#define DISPC_CAPABLE DISPC_REG(0x0048)
|
|
+#define DISPC_DEFAULT_COLOR0 DISPC_REG(0x004C)
|
|
+#define DISPC_DEFAULT_COLOR1 DISPC_REG(0x0050)
|
|
+#define DISPC_TRANS_COLOR0 DISPC_REG(0x0054)
|
|
+#define DISPC_TRANS_COLOR1 DISPC_REG(0x0058)
|
|
+#define DISPC_LINE_STATUS DISPC_REG(0x005C)
|
|
+#define DISPC_LINE_NUMBER DISPC_REG(0x0060)
|
|
+#define DISPC_TIMING_H DISPC_REG(0x0064)
|
|
+#define DISPC_TIMING_V DISPC_REG(0x0068)
|
|
+#define DISPC_POL_FREQ DISPC_REG(0x006C)
|
|
+#define DISPC_DIVISOR DISPC_REG(0x0070)
|
|
+#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
|
|
+#define DISPC_SIZE_DIG DISPC_REG(0x0078)
|
|
+#define DISPC_SIZE_LCD DISPC_REG(0x007C)
|
|
+
|
|
+/* DISPC GFX plane */
|
|
+#define DISPC_GFX_BA0 DISPC_REG(0x0080)
|
|
+#define DISPC_GFX_BA1 DISPC_REG(0x0084)
|
|
+#define DISPC_GFX_POSITION DISPC_REG(0x0088)
|
|
+#define DISPC_GFX_SIZE DISPC_REG(0x008C)
|
|
+#define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0)
|
|
+#define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4)
|
|
+#define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8)
|
|
+#define DISPC_GFX_ROW_INC DISPC_REG(0x00AC)
|
|
+#define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0)
|
|
+#define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
|
|
+#define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
|
|
+
|
|
+#define DISPC_DATA_CYCLE1 DISPC_REG(0x01D4)
|
|
+#define DISPC_DATA_CYCLE2 DISPC_REG(0x01D8)
|
|
+#define DISPC_DATA_CYCLE3 DISPC_REG(0x01DC)
|
|
+
|
|
+#define DISPC_CPR_COEF_R DISPC_REG(0x0220)
|
|
+#define DISPC_CPR_COEF_G DISPC_REG(0x0224)
|
|
+#define DISPC_CPR_COEF_B DISPC_REG(0x0228)
|
|
+
|
|
+#define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
|
|
+
|
|
+/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
|
|
+#define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx)
|
|
+
|
|
+#define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000)
|
|
+#define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004)
|
|
+#define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008)
|
|
+#define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C)
|
|
+#define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010)
|
|
+#define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014)
|
|
+#define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018)
|
|
+#define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C)
|
|
+#define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020)
|
|
+#define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024)
|
|
+#define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028)
|
|
+#define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C)
|
|
+#define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030)
|
|
+
|
|
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
|
|
+#define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
|
|
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
|
|
+#define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
|
|
+/* coef index i = {0, 1, 2, 3, 4} */
|
|
+#define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
|
|
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
|
|
+#define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
|
|
+
|
|
+#define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
|
|
+
|
|
+
|
|
+#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
|
|
+ DISPC_IRQ_OCP_ERR | \
|
|
+ DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
|
|
+ DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
|
|
+ DISPC_IRQ_SYNC_LOST | \
|
|
+ DISPC_IRQ_SYNC_LOST_DIGIT)
|
|
+
|
|
+#define DISPC_MAX_NR_ISRS 8
|
|
+
|
|
+struct omap_dispc_isr_data {
|
|
+ omap_dispc_isr_t isr;
|
|
+ void *arg;
|
|
+ u32 mask;
|
|
+};
|
|
+
|
|
+#define REG_GET(idx, start, end) \
|
|
+ FLD_GET(dispc_read_reg(idx), start, end)
|
|
+
|
|
+#define REG_FLD_MOD(idx, val, start, end) \
|
|
+ dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
|
|
+
|
|
+static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
|
|
+ DISPC_VID_ATTRIBUTES(0),
|
|
+ DISPC_VID_ATTRIBUTES(1) };
|
|
+
|
|
+static struct {
|
|
+ void __iomem *base;
|
|
+
|
|
+ struct clk *dpll4_m4_ck;
|
|
+
|
|
+ spinlock_t irq_lock;
|
|
+
|
|
+ unsigned long cache_req_pck;
|
|
+ unsigned long cache_prate;
|
|
+ struct dispc_clock_info cache_cinfo;
|
|
+
|
|
+ u32 irq_error_mask;
|
|
+ struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
|
|
+
|
|
+ spinlock_t error_lock;
|
|
+ u32 error_irqs;
|
|
+ struct work_struct error_work;
|
|
+
|
|
+ u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
|
|
+} dispc;
|
|
+
|
|
+static void omap_dispc_set_irqs(void);
|
|
+
|
|
+static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
|
|
+{
|
|
+ __raw_writel(val, dispc.base + idx.idx);
|
|
+}
|
|
+
|
|
+static inline u32 dispc_read_reg(const struct dispc_reg idx)
|
|
+{
|
|
+ return __raw_readl(dispc.base + idx.idx);
|
|
+}
|
|
+
|
|
+#define SR(reg) \
|
|
+ dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
|
|
+#define RR(reg) \
|
|
+ dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
|
|
+
|
|
+void dispc_save_context(void)
|
|
+{
|
|
+ if (cpu_is_omap24xx())
|
|
+ return;
|
|
+
|
|
+ SR(SYSCONFIG);
|
|
+ SR(IRQENABLE);
|
|
+ SR(CONTROL);
|
|
+ SR(CONFIG);
|
|
+ SR(DEFAULT_COLOR0);
|
|
+ SR(DEFAULT_COLOR1);
|
|
+ SR(TRANS_COLOR0);
|
|
+ SR(TRANS_COLOR1);
|
|
+ SR(LINE_NUMBER);
|
|
+ SR(TIMING_H);
|
|
+ SR(TIMING_V);
|
|
+ SR(POL_FREQ);
|
|
+ SR(DIVISOR);
|
|
+ SR(GLOBAL_ALPHA);
|
|
+ SR(SIZE_DIG);
|
|
+ SR(SIZE_LCD);
|
|
+
|
|
+ SR(GFX_BA0);
|
|
+ SR(GFX_BA1);
|
|
+ SR(GFX_POSITION);
|
|
+ SR(GFX_SIZE);
|
|
+ SR(GFX_ATTRIBUTES);
|
|
+ SR(GFX_FIFO_THRESHOLD);
|
|
+ SR(GFX_ROW_INC);
|
|
+ SR(GFX_PIXEL_INC);
|
|
+ SR(GFX_WINDOW_SKIP);
|
|
+ SR(GFX_TABLE_BA);
|
|
+
|
|
+ SR(DATA_CYCLE1);
|
|
+ SR(DATA_CYCLE2);
|
|
+ SR(DATA_CYCLE3);
|
|
+
|
|
+ SR(CPR_COEF_R);
|
|
+ SR(CPR_COEF_G);
|
|
+ SR(CPR_COEF_B);
|
|
+
|
|
+ SR(GFX_PRELOAD);
|
|
+
|
|
+ /* VID1 */
|
|
+ SR(VID_BA0(0));
|
|
+ SR(VID_BA1(0));
|
|
+ SR(VID_POSITION(0));
|
|
+ SR(VID_SIZE(0));
|
|
+ SR(VID_ATTRIBUTES(0));
|
|
+ SR(VID_FIFO_THRESHOLD(0));
|
|
+ SR(VID_ROW_INC(0));
|
|
+ SR(VID_PIXEL_INC(0));
|
|
+ SR(VID_FIR(0));
|
|
+ SR(VID_PICTURE_SIZE(0));
|
|
+ SR(VID_ACCU0(0));
|
|
+ SR(VID_ACCU1(0));
|
|
+
|
|
+ SR(VID_FIR_COEF_H(0, 0));
|
|
+ SR(VID_FIR_COEF_H(0, 1));
|
|
+ SR(VID_FIR_COEF_H(0, 2));
|
|
+ SR(VID_FIR_COEF_H(0, 3));
|
|
+ SR(VID_FIR_COEF_H(0, 4));
|
|
+ SR(VID_FIR_COEF_H(0, 5));
|
|
+ SR(VID_FIR_COEF_H(0, 6));
|
|
+ SR(VID_FIR_COEF_H(0, 7));
|
|
+
|
|
+ SR(VID_FIR_COEF_HV(0, 0));
|
|
+ SR(VID_FIR_COEF_HV(0, 1));
|
|
+ SR(VID_FIR_COEF_HV(0, 2));
|
|
+ SR(VID_FIR_COEF_HV(0, 3));
|
|
+ SR(VID_FIR_COEF_HV(0, 4));
|
|
+ SR(VID_FIR_COEF_HV(0, 5));
|
|
+ SR(VID_FIR_COEF_HV(0, 6));
|
|
+ SR(VID_FIR_COEF_HV(0, 7));
|
|
+
|
|
+ SR(VID_CONV_COEF(0, 0));
|
|
+ SR(VID_CONV_COEF(0, 1));
|
|
+ SR(VID_CONV_COEF(0, 2));
|
|
+ SR(VID_CONV_COEF(0, 3));
|
|
+ SR(VID_CONV_COEF(0, 4));
|
|
+
|
|
+ SR(VID_FIR_COEF_V(0, 0));
|
|
+ SR(VID_FIR_COEF_V(0, 1));
|
|
+ SR(VID_FIR_COEF_V(0, 2));
|
|
+ SR(VID_FIR_COEF_V(0, 3));
|
|
+ SR(VID_FIR_COEF_V(0, 4));
|
|
+ SR(VID_FIR_COEF_V(0, 5));
|
|
+ SR(VID_FIR_COEF_V(0, 6));
|
|
+ SR(VID_FIR_COEF_V(0, 7));
|
|
+
|
|
+ SR(VID_PRELOAD(0));
|
|
+
|
|
+ /* VID2 */
|
|
+ SR(VID_BA0(1));
|
|
+ SR(VID_BA1(1));
|
|
+ SR(VID_POSITION(1));
|
|
+ SR(VID_SIZE(1));
|
|
+ SR(VID_ATTRIBUTES(1));
|
|
+ SR(VID_FIFO_THRESHOLD(1));
|
|
+ SR(VID_ROW_INC(1));
|
|
+ SR(VID_PIXEL_INC(1));
|
|
+ SR(VID_FIR(1));
|
|
+ SR(VID_PICTURE_SIZE(1));
|
|
+ SR(VID_ACCU0(1));
|
|
+ SR(VID_ACCU1(1));
|
|
+
|
|
+ SR(VID_FIR_COEF_H(1, 0));
|
|
+ SR(VID_FIR_COEF_H(1, 1));
|
|
+ SR(VID_FIR_COEF_H(1, 2));
|
|
+ SR(VID_FIR_COEF_H(1, 3));
|
|
+ SR(VID_FIR_COEF_H(1, 4));
|
|
+ SR(VID_FIR_COEF_H(1, 5));
|
|
+ SR(VID_FIR_COEF_H(1, 6));
|
|
+ SR(VID_FIR_COEF_H(1, 7));
|
|
+
|
|
+ SR(VID_FIR_COEF_HV(1, 0));
|
|
+ SR(VID_FIR_COEF_HV(1, 1));
|
|
+ SR(VID_FIR_COEF_HV(1, 2));
|
|
+ SR(VID_FIR_COEF_HV(1, 3));
|
|
+ SR(VID_FIR_COEF_HV(1, 4));
|
|
+ SR(VID_FIR_COEF_HV(1, 5));
|
|
+ SR(VID_FIR_COEF_HV(1, 6));
|
|
+ SR(VID_FIR_COEF_HV(1, 7));
|
|
+
|
|
+ SR(VID_CONV_COEF(1, 0));
|
|
+ SR(VID_CONV_COEF(1, 1));
|
|
+ SR(VID_CONV_COEF(1, 2));
|
|
+ SR(VID_CONV_COEF(1, 3));
|
|
+ SR(VID_CONV_COEF(1, 4));
|
|
+
|
|
+ SR(VID_FIR_COEF_V(1, 0));
|
|
+ SR(VID_FIR_COEF_V(1, 1));
|
|
+ SR(VID_FIR_COEF_V(1, 2));
|
|
+ SR(VID_FIR_COEF_V(1, 3));
|
|
+ SR(VID_FIR_COEF_V(1, 4));
|
|
+ SR(VID_FIR_COEF_V(1, 5));
|
|
+ SR(VID_FIR_COEF_V(1, 6));
|
|
+ SR(VID_FIR_COEF_V(1, 7));
|
|
+
|
|
+ SR(VID_PRELOAD(1));
|
|
+}
|
|
+
|
|
+void dispc_restore_context(void)
|
|
+{
|
|
+ RR(SYSCONFIG);
|
|
+ RR(IRQENABLE);
|
|
+ /*RR(CONTROL);*/
|
|
+ RR(CONFIG);
|
|
+ RR(DEFAULT_COLOR0);
|
|
+ RR(DEFAULT_COLOR1);
|
|
+ RR(TRANS_COLOR0);
|
|
+ RR(TRANS_COLOR1);
|
|
+ RR(LINE_NUMBER);
|
|
+ RR(TIMING_H);
|
|
+ RR(TIMING_V);
|
|
+ RR(POL_FREQ);
|
|
+ RR(DIVISOR);
|
|
+ RR(GLOBAL_ALPHA);
|
|
+ RR(SIZE_DIG);
|
|
+ RR(SIZE_LCD);
|
|
+
|
|
+ RR(GFX_BA0);
|
|
+ RR(GFX_BA1);
|
|
+ RR(GFX_POSITION);
|
|
+ RR(GFX_SIZE);
|
|
+ RR(GFX_ATTRIBUTES);
|
|
+ RR(GFX_FIFO_THRESHOLD);
|
|
+ RR(GFX_ROW_INC);
|
|
+ RR(GFX_PIXEL_INC);
|
|
+ RR(GFX_WINDOW_SKIP);
|
|
+ RR(GFX_TABLE_BA);
|
|
+
|
|
+ RR(DATA_CYCLE1);
|
|
+ RR(DATA_CYCLE2);
|
|
+ RR(DATA_CYCLE3);
|
|
+
|
|
+ RR(CPR_COEF_R);
|
|
+ RR(CPR_COEF_G);
|
|
+ RR(CPR_COEF_B);
|
|
+
|
|
+ RR(GFX_PRELOAD);
|
|
+
|
|
+ /* VID1 */
|
|
+ RR(VID_BA0(0));
|
|
+ RR(VID_BA1(0));
|
|
+ RR(VID_POSITION(0));
|
|
+ RR(VID_SIZE(0));
|
|
+ RR(VID_ATTRIBUTES(0));
|
|
+ RR(VID_FIFO_THRESHOLD(0));
|
|
+ RR(VID_ROW_INC(0));
|
|
+ RR(VID_PIXEL_INC(0));
|
|
+ RR(VID_FIR(0));
|
|
+ RR(VID_PICTURE_SIZE(0));
|
|
+ RR(VID_ACCU0(0));
|
|
+ RR(VID_ACCU1(0));
|
|
+
|
|
+ RR(VID_FIR_COEF_H(0, 0));
|
|
+ RR(VID_FIR_COEF_H(0, 1));
|
|
+ RR(VID_FIR_COEF_H(0, 2));
|
|
+ RR(VID_FIR_COEF_H(0, 3));
|
|
+ RR(VID_FIR_COEF_H(0, 4));
|
|
+ RR(VID_FIR_COEF_H(0, 5));
|
|
+ RR(VID_FIR_COEF_H(0, 6));
|
|
+ RR(VID_FIR_COEF_H(0, 7));
|
|
+
|
|
+ RR(VID_FIR_COEF_HV(0, 0));
|
|
+ RR(VID_FIR_COEF_HV(0, 1));
|
|
+ RR(VID_FIR_COEF_HV(0, 2));
|
|
+ RR(VID_FIR_COEF_HV(0, 3));
|
|
+ RR(VID_FIR_COEF_HV(0, 4));
|
|
+ RR(VID_FIR_COEF_HV(0, 5));
|
|
+ RR(VID_FIR_COEF_HV(0, 6));
|
|
+ RR(VID_FIR_COEF_HV(0, 7));
|
|
+
|
|
+ RR(VID_CONV_COEF(0, 0));
|
|
+ RR(VID_CONV_COEF(0, 1));
|
|
+ RR(VID_CONV_COEF(0, 2));
|
|
+ RR(VID_CONV_COEF(0, 3));
|
|
+ RR(VID_CONV_COEF(0, 4));
|
|
+
|
|
+ RR(VID_FIR_COEF_V(0, 0));
|
|
+ RR(VID_FIR_COEF_V(0, 1));
|
|
+ RR(VID_FIR_COEF_V(0, 2));
|
|
+ RR(VID_FIR_COEF_V(0, 3));
|
|
+ RR(VID_FIR_COEF_V(0, 4));
|
|
+ RR(VID_FIR_COEF_V(0, 5));
|
|
+ RR(VID_FIR_COEF_V(0, 6));
|
|
+ RR(VID_FIR_COEF_V(0, 7));
|
|
+
|
|
+ RR(VID_PRELOAD(0));
|
|
+
|
|
+ /* VID2 */
|
|
+ RR(VID_BA0(1));
|
|
+ RR(VID_BA1(1));
|
|
+ RR(VID_POSITION(1));
|
|
+ RR(VID_SIZE(1));
|
|
+ RR(VID_ATTRIBUTES(1));
|
|
+ RR(VID_FIFO_THRESHOLD(1));
|
|
+ RR(VID_ROW_INC(1));
|
|
+ RR(VID_PIXEL_INC(1));
|
|
+ RR(VID_FIR(1));
|
|
+ RR(VID_PICTURE_SIZE(1));
|
|
+ RR(VID_ACCU0(1));
|
|
+ RR(VID_ACCU1(1));
|
|
+
|
|
+ RR(VID_FIR_COEF_H(1, 0));
|
|
+ RR(VID_FIR_COEF_H(1, 1));
|
|
+ RR(VID_FIR_COEF_H(1, 2));
|
|
+ RR(VID_FIR_COEF_H(1, 3));
|
|
+ RR(VID_FIR_COEF_H(1, 4));
|
|
+ RR(VID_FIR_COEF_H(1, 5));
|
|
+ RR(VID_FIR_COEF_H(1, 6));
|
|
+ RR(VID_FIR_COEF_H(1, 7));
|
|
+
|
|
+ RR(VID_FIR_COEF_HV(1, 0));
|
|
+ RR(VID_FIR_COEF_HV(1, 1));
|
|
+ RR(VID_FIR_COEF_HV(1, 2));
|
|
+ RR(VID_FIR_COEF_HV(1, 3));
|
|
+ RR(VID_FIR_COEF_HV(1, 4));
|
|
+ RR(VID_FIR_COEF_HV(1, 5));
|
|
+ RR(VID_FIR_COEF_HV(1, 6));
|
|
+ RR(VID_FIR_COEF_HV(1, 7));
|
|
+
|
|
+ RR(VID_CONV_COEF(1, 0));
|
|
+ RR(VID_CONV_COEF(1, 1));
|
|
+ RR(VID_CONV_COEF(1, 2));
|
|
+ RR(VID_CONV_COEF(1, 3));
|
|
+ RR(VID_CONV_COEF(1, 4));
|
|
+
|
|
+ RR(VID_FIR_COEF_V(1, 0));
|
|
+ RR(VID_FIR_COEF_V(1, 1));
|
|
+ RR(VID_FIR_COEF_V(1, 2));
|
|
+ RR(VID_FIR_COEF_V(1, 3));
|
|
+ RR(VID_FIR_COEF_V(1, 4));
|
|
+ RR(VID_FIR_COEF_V(1, 5));
|
|
+ RR(VID_FIR_COEF_V(1, 6));
|
|
+ RR(VID_FIR_COEF_V(1, 7));
|
|
+
|
|
+ RR(VID_PRELOAD(1));
|
|
+
|
|
+ /* enable last, because LCD & DIGIT enable are here */
|
|
+ RR(CONTROL);
|
|
+}
|
|
+
|
|
+#undef SR
|
|
+#undef RR
|
|
+
|
|
+static inline void enable_clocks(bool enable)
|
|
+{
|
|
+ if (enable)
|
|
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+ else
|
|
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+}
|
|
+
|
|
+void dispc_go(enum omap_channel channel)
|
|
+{
|
|
+ int bit;
|
|
+ unsigned long tmo;
|
|
+
|
|
+ enable_clocks(1);
|
|
+
|
|
+ if (channel == OMAP_DSS_CHANNEL_LCD)
|
|
+ bit = 0; /* LCDENABLE */
|
|
+ else
|
|
+ bit = 1; /* DIGITALENABLE */
|
|
+
|
|
+ /* if the channel is not enabled, we don't need GO */
|
|
+ if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
|
|
+ goto end;
|
|
+
|
|
+ if (channel == OMAP_DSS_CHANNEL_LCD)
|
|
+ bit = 5; /* GOLCD */
|
|
+ else
|
|
+ bit = 6; /* GODIGIT */
|
|
+
|
|
+ tmo = jiffies + msecs_to_jiffies(200);
|
|
+ while (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
|
|
+ if (time_after(jiffies, tmo)) {
|
|
+ DSSERR("timeout waiting GO flag\n");
|
|
+ goto end;
|
|
+ }
|
|
+ cpu_relax();
|
|
+ }
|
|
+
|
|
+ DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
|
|
+
|
|
+ REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
|
|
+end:
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
|
|
+{
|
|
+ BUG_ON(plane == OMAP_DSS_GFX);
|
|
+
|
|
+ dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
|
|
+}
|
|
+
|
|
+static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
|
|
+{
|
|
+ BUG_ON(plane == OMAP_DSS_GFX);
|
|
+
|
|
+ dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
|
|
+}
|
|
+
|
|
+static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
|
|
+{
|
|
+ BUG_ON(plane == OMAP_DSS_GFX);
|
|
+
|
|
+ dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
|
|
+}
|
|
+
|
|
+static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
|
|
+ int vscaleup, int five_taps)
|
|
+{
|
|
+ /* Coefficients for horizontal up-sampling */
|
|
+ static const u32 coef_hup[8] = {
|
|
+ 0x00800000,
|
|
+ 0x0D7CF800,
|
|
+ 0x1E70F5FF,
|
|
+ 0x335FF5FE,
|
|
+ 0xF74949F7,
|
|
+ 0xF55F33FB,
|
|
+ 0xF5701EFE,
|
|
+ 0xF87C0DFF,
|
|
+ };
|
|
+
|
|
+ /* Coefficients for horizontal down-sampling */
|
|
+ static const u32 coef_hdown[8] = {
|
|
+ 0x24382400,
|
|
+ 0x28371FFE,
|
|
+ 0x2C361BFB,
|
|
+ 0x303516F9,
|
|
+ 0x11343311,
|
|
+ 0x1635300C,
|
|
+ 0x1B362C08,
|
|
+ 0x1F372804,
|
|
+ };
|
|
+
|
|
+ /* Coefficients for horizontal and vertical up-sampling */
|
|
+ static const u32 coef_hvup[2][8] = {
|
|
+ {
|
|
+ 0x00800000,
|
|
+ 0x037B02FF,
|
|
+ 0x0C6F05FE,
|
|
+ 0x205907FB,
|
|
+ 0x00404000,
|
|
+ 0x075920FE,
|
|
+ 0x056F0CFF,
|
|
+ 0x027B0300,
|
|
+ },
|
|
+ {
|
|
+ 0x00800000,
|
|
+ 0x0D7CF8FF,
|
|
+ 0x1E70F5FE,
|
|
+ 0x335FF5FB,
|
|
+ 0xF7404000,
|
|
+ 0xF55F33FE,
|
|
+ 0xF5701EFF,
|
|
+ 0xF87C0D00,
|
|
+ },
|
|
+ };
|
|
+
|
|
+ /* Coefficients for horizontal and vertical down-sampling */
|
|
+ static const u32 coef_hvdown[2][8] = {
|
|
+ {
|
|
+ 0x24382400,
|
|
+ 0x28391F04,
|
|
+ 0x2D381B08,
|
|
+ 0x3237170C,
|
|
+ 0x123737F7,
|
|
+ 0x173732F9,
|
|
+ 0x1B382DFB,
|
|
+ 0x1F3928FE,
|
|
+ },
|
|
+ {
|
|
+ 0x24382400,
|
|
+ 0x28371F04,
|
|
+ 0x2C361B08,
|
|
+ 0x3035160C,
|
|
+ 0x113433F7,
|
|
+ 0x163530F9,
|
|
+ 0x1B362CFB,
|
|
+ 0x1F3728FE,
|
|
+ },
|
|
+ };
|
|
+
|
|
+ /* Coefficients for vertical up-sampling */
|
|
+ static const u32 coef_vup[8] = {
|
|
+ 0x00000000,
|
|
+ 0x0000FF00,
|
|
+ 0x0000FEFF,
|
|
+ 0x0000FBFE,
|
|
+ 0x000000F7,
|
|
+ 0x0000FEFB,
|
|
+ 0x0000FFFE,
|
|
+ 0x000000FF,
|
|
+ };
|
|
+
|
|
+
|
|
+ /* Coefficients for vertical down-sampling */
|
|
+ static const u32 coef_vdown[8] = {
|
|
+ 0x00000000,
|
|
+ 0x000004FE,
|
|
+ 0x000008FB,
|
|
+ 0x00000CF9,
|
|
+ 0x0000F711,
|
|
+ 0x0000F90C,
|
|
+ 0x0000FB08,
|
|
+ 0x0000FE04,
|
|
+ };
|
|
+
|
|
+ const u32 *h_coef;
|
|
+ const u32 *hv_coef;
|
|
+ const u32 *hv_coef_mod;
|
|
+ const u32 *v_coef;
|
|
+ int i;
|
|
+
|
|
+ if (hscaleup)
|
|
+ h_coef = coef_hup;
|
|
+ else
|
|
+ h_coef = coef_hdown;
|
|
+
|
|
+ if (vscaleup) {
|
|
+ hv_coef = coef_hvup[five_taps];
|
|
+ v_coef = coef_vup;
|
|
+
|
|
+ if (hscaleup)
|
|
+ hv_coef_mod = NULL;
|
|
+ else
|
|
+ hv_coef_mod = coef_hvdown[five_taps];
|
|
+ } else {
|
|
+ hv_coef = coef_hvdown[five_taps];
|
|
+ v_coef = coef_vdown;
|
|
+
|
|
+ if (hscaleup)
|
|
+ hv_coef_mod = coef_hvup[five_taps];
|
|
+ else
|
|
+ hv_coef_mod = NULL;
|
|
+ }
|
|
+
|
|
+ for (i = 0; i < 8; i++) {
|
|
+ u32 h, hv;
|
|
+
|
|
+ h = h_coef[i];
|
|
+
|
|
+ hv = hv_coef[i];
|
|
+
|
|
+ if (hv_coef_mod) {
|
|
+ hv &= 0xffffff00;
|
|
+ hv |= (hv_coef_mod[i] & 0xff);
|
|
+ }
|
|
+
|
|
+ _dispc_write_firh_reg(plane, i, h);
|
|
+ _dispc_write_firhv_reg(plane, i, hv);
|
|
+ }
|
|
+
|
|
+ if (!five_taps)
|
|
+ return;
|
|
+
|
|
+ for (i = 0; i < 8; i++) {
|
|
+ u32 v;
|
|
+ v = v_coef[i];
|
|
+ _dispc_write_firv_reg(plane, i, v);
|
|
+ }
|
|
+}
|
|
+
|
|
+static void _dispc_setup_color_conv_coef(void)
|
|
+{
|
|
+ const struct color_conv_coef {
|
|
+ int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
|
|
+ int full_range;
|
|
+ } ctbl_bt601_5 = {
|
|
+ 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
|
|
+ };
|
|
+
|
|
+ const struct color_conv_coef *ct;
|
|
+
|
|
+#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
|
|
+
|
|
+ ct = &ctbl_bt601_5;
|
|
+
|
|
+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
|
|
+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb));
|
|
+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
|
|
+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
|
|
+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb));
|
|
+
|
|
+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
|
|
+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb));
|
|
+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
|
|
+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
|
|
+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb));
|
|
+
|
|
+#undef CVAL
|
|
+
|
|
+ REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
|
|
+ REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
|
|
+}
|
|
+
|
|
+
|
|
+static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
|
|
+{
|
|
+ const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
|
|
+ DISPC_VID_BA0(0),
|
|
+ DISPC_VID_BA0(1) };
|
|
+
|
|
+ dispc_write_reg(ba0_reg[plane], paddr);
|
|
+}
|
|
+
|
|
+static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
|
|
+{
|
|
+ const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
|
|
+ DISPC_VID_BA1(0),
|
|
+ DISPC_VID_BA1(1) };
|
|
+
|
|
+ dispc_write_reg(ba1_reg[plane], paddr);
|
|
+}
|
|
+
|
|
+static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
|
|
+{
|
|
+ const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
|
|
+ DISPC_VID_POSITION(0),
|
|
+ DISPC_VID_POSITION(1) };
|
|
+
|
|
+ u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
|
|
+ dispc_write_reg(pos_reg[plane], val);
|
|
+}
|
|
+
|
|
+static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
|
|
+{
|
|
+ const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
|
|
+ DISPC_VID_PICTURE_SIZE(0),
|
|
+ DISPC_VID_PICTURE_SIZE(1) };
|
|
+ u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
|
|
+ dispc_write_reg(siz_reg[plane], val);
|
|
+}
|
|
+
|
|
+static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
|
|
+{
|
|
+ u32 val;
|
|
+ const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
|
|
+ DISPC_VID_SIZE(1) };
|
|
+
|
|
+ BUG_ON(plane == OMAP_DSS_GFX);
|
|
+
|
|
+ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
|
|
+ dispc_write_reg(vsi_reg[plane-1], val);
|
|
+}
|
|
+
|
|
+static void _dispc_set_pix_inc(enum omap_plane plane, u16 inc)
|
|
+{
|
|
+ const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
|
|
+ DISPC_VID_PIXEL_INC(0),
|
|
+ DISPC_VID_PIXEL_INC(1) };
|
|
+
|
|
+ dispc_write_reg(ri_reg[plane], inc);
|
|
+}
|
|
+
|
|
+static void _dispc_set_row_inc(enum omap_plane plane, u16 inc)
|
|
+{
|
|
+ const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
|
|
+ DISPC_VID_ROW_INC(0),
|
|
+ DISPC_VID_ROW_INC(1) };
|
|
+
|
|
+ dispc_write_reg(ri_reg[plane], inc);
|
|
+}
|
|
+
|
|
+static void _dispc_set_color_mode(enum omap_plane plane,
|
|
+ enum omap_color_mode color_mode)
|
|
+{
|
|
+ u32 m = 0;
|
|
+
|
|
+ switch (color_mode) {
|
|
+ case OMAP_DSS_COLOR_CLUT1:
|
|
+ m = 0x0; break;
|
|
+ case OMAP_DSS_COLOR_CLUT2:
|
|
+ m = 0x1; break;
|
|
+ case OMAP_DSS_COLOR_CLUT4:
|
|
+ m = 0x2; break;
|
|
+ case OMAP_DSS_COLOR_CLUT8:
|
|
+ m = 0x3; break;
|
|
+ case OMAP_DSS_COLOR_RGB12U:
|
|
+ m = 0x4; break;
|
|
+ case OMAP_DSS_COLOR_ARGB16:
|
|
+ m = 0x5; break;
|
|
+ case OMAP_DSS_COLOR_RGB16:
|
|
+ m = 0x6; break;
|
|
+ case OMAP_DSS_COLOR_RGB24U:
|
|
+ m = 0x8; break;
|
|
+ case OMAP_DSS_COLOR_RGB24P:
|
|
+ m = 0x9; break;
|
|
+ case OMAP_DSS_COLOR_YUV2:
|
|
+ m = 0xa; break;
|
|
+ case OMAP_DSS_COLOR_UYVY:
|
|
+ m = 0xb; break;
|
|
+ case OMAP_DSS_COLOR_ARGB32:
|
|
+ m = 0xc; break;
|
|
+ case OMAP_DSS_COLOR_RGBA32:
|
|
+ m = 0xd; break;
|
|
+ case OMAP_DSS_COLOR_RGBX32:
|
|
+ m = 0xe; break;
|
|
+ default:
|
|
+ BUG(); break;
|
|
+ }
|
|
+
|
|
+ REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
|
|
+}
|
|
+
|
|
+static void _dispc_set_channel_out(enum omap_plane plane,
|
|
+ enum omap_channel channel)
|
|
+{
|
|
+ int shift;
|
|
+ u32 val;
|
|
+
|
|
+ switch (plane) {
|
|
+ case OMAP_DSS_GFX:
|
|
+ shift = 8;
|
|
+ break;
|
|
+ case OMAP_DSS_VIDEO1:
|
|
+ case OMAP_DSS_VIDEO2:
|
|
+ shift = 16;
|
|
+ break;
|
|
+ default:
|
|
+ BUG();
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ val = dispc_read_reg(dispc_reg_att[plane]);
|
|
+ val = FLD_MOD(val, channel, shift, shift);
|
|
+ dispc_write_reg(dispc_reg_att[plane], val);
|
|
+}
|
|
+
|
|
+void dispc_set_burst_size(enum omap_plane plane,
|
|
+ enum omap_burst_size burst_size)
|
|
+{
|
|
+ int shift;
|
|
+ u32 val;
|
|
+
|
|
+ enable_clocks(1);
|
|
+
|
|
+ switch (plane) {
|
|
+ case OMAP_DSS_GFX:
|
|
+ shift = 6;
|
|
+ break;
|
|
+ case OMAP_DSS_VIDEO1:
|
|
+ case OMAP_DSS_VIDEO2:
|
|
+ shift = 14;
|
|
+ break;
|
|
+ default:
|
|
+ BUG();
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ val = dispc_read_reg(dispc_reg_att[plane]);
|
|
+ val = FLD_MOD(val, burst_size, shift+1, shift);
|
|
+ dispc_write_reg(dispc_reg_att[plane], val);
|
|
+
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
|
|
+{
|
|
+ u32 val;
|
|
+
|
|
+ BUG_ON(plane == OMAP_DSS_GFX);
|
|
+
|
|
+ val = dispc_read_reg(dispc_reg_att[plane]);
|
|
+ val = FLD_MOD(val, enable, 9, 9);
|
|
+ dispc_write_reg(dispc_reg_att[plane], val);
|
|
+}
|
|
+
|
|
+void dispc_set_lcd_size(u16 width, u16 height)
|
|
+{
|
|
+ u32 val;
|
|
+ BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
|
|
+ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
|
|
+ enable_clocks(1);
|
|
+ dispc_write_reg(DISPC_SIZE_LCD, val);
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+void dispc_set_digit_size(u16 width, u16 height)
|
|
+{
|
|
+ u32 val;
|
|
+ BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
|
|
+ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
|
|
+ enable_clocks(1);
|
|
+ dispc_write_reg(DISPC_SIZE_DIG, val);
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+u32 dispc_get_plane_fifo_size(enum omap_plane plane)
|
|
+{
|
|
+ const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
|
|
+ DISPC_VID_FIFO_SIZE_STATUS(0),
|
|
+ DISPC_VID_FIFO_SIZE_STATUS(1) };
|
|
+ u32 size;
|
|
+
|
|
+ enable_clocks(1);
|
|
+
|
|
+ if (cpu_is_omap24xx())
|
|
+ size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
|
|
+ else if (cpu_is_omap34xx())
|
|
+ size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
|
|
+ else
|
|
+ BUG();
|
|
+
|
|
+ if (cpu_is_omap34xx()) {
|
|
+ /* FIFOMERGE */
|
|
+ if (REG_GET(DISPC_CONFIG, 14, 14))
|
|
+ size *= 3;
|
|
+ }
|
|
+
|
|
+ enable_clocks(0);
|
|
+
|
|
+ return size;
|
|
+}
|
|
+
|
|
+void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
|
|
+{
|
|
+ const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
|
|
+ DISPC_VID_FIFO_THRESHOLD(0),
|
|
+ DISPC_VID_FIFO_THRESHOLD(1) };
|
|
+ u32 size;
|
|
+
|
|
+ enable_clocks(1);
|
|
+
|
|
+ size = dispc_get_plane_fifo_size(plane);
|
|
+
|
|
+ BUG_ON(low > size || high > size);
|
|
+
|
|
+ DSSDBG("fifo(%d) size %d, low/high old %u/%u, new %u/%u\n",
|
|
+ plane, size,
|
|
+ REG_GET(ftrs_reg[plane], 11, 0),
|
|
+ REG_GET(ftrs_reg[plane], 27, 16),
|
|
+ low, high);
|
|
+
|
|
+ if (cpu_is_omap24xx())
|
|
+ dispc_write_reg(ftrs_reg[plane],
|
|
+ FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
|
|
+ else
|
|
+ dispc_write_reg(ftrs_reg[plane],
|
|
+ FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
|
|
+
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+void dispc_enable_fifomerge(bool enable)
|
|
+{
|
|
+ enable_clocks(1);
|
|
+
|
|
+ DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
|
|
+ REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
|
|
+
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
|
|
+{
|
|
+ u32 val;
|
|
+ const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
|
|
+ DISPC_VID_FIR(1) };
|
|
+
|
|
+ BUG_ON(plane == OMAP_DSS_GFX);
|
|
+
|
|
+ val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
|
|
+ dispc_write_reg(fir_reg[plane-1], val);
|
|
+}
|
|
+
|
|
+static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
|
|
+{
|
|
+ u32 val;
|
|
+ const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
|
|
+ DISPC_VID_ACCU0(1) };
|
|
+
|
|
+ BUG_ON(plane == OMAP_DSS_GFX);
|
|
+
|
|
+ val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
|
|
+ dispc_write_reg(ac0_reg[plane-1], val);
|
|
+}
|
|
+
|
|
+static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
|
|
+{
|
|
+ u32 val;
|
|
+ const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
|
|
+ DISPC_VID_ACCU1(1) };
|
|
+
|
|
+ BUG_ON(plane == OMAP_DSS_GFX);
|
|
+
|
|
+ val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
|
|
+ dispc_write_reg(ac1_reg[plane-1], val);
|
|
+}
|
|
+
|
|
+
|
|
+static void _dispc_set_scaling(enum omap_plane plane,
|
|
+ u16 orig_width, u16 orig_height,
|
|
+ u16 out_width, u16 out_height,
|
|
+ bool ilace)
|
|
+{
|
|
+ int fir_hinc;
|
|
+ int fir_vinc;
|
|
+ int hscaleup, vscaleup, five_taps;
|
|
+ int fieldmode = 0;
|
|
+ int accu0 = 0;
|
|
+ int accu1 = 0;
|
|
+ u32 l;
|
|
+
|
|
+ BUG_ON(plane == OMAP_DSS_GFX);
|
|
+
|
|
+ hscaleup = orig_width <= out_width;
|
|
+ vscaleup = orig_height <= out_height;
|
|
+ five_taps = orig_height > out_height * 2;
|
|
+
|
|
+ _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
|
|
+
|
|
+ if (!orig_width || orig_width == out_width)
|
|
+ fir_hinc = 0;
|
|
+ else
|
|
+ fir_hinc = 1024 * orig_width / out_width;
|
|
+
|
|
+ if (!orig_height || orig_height == out_height)
|
|
+ fir_vinc = 0;
|
|
+ else
|
|
+ fir_vinc = 1024 * orig_height / out_height;
|
|
+
|
|
+ _dispc_set_fir(plane, fir_hinc, fir_vinc);
|
|
+
|
|
+ l = dispc_read_reg(dispc_reg_att[plane]);
|
|
+ l &= ~((0x0f << 5) | (0x3 << 21));
|
|
+
|
|
+ l |= fir_hinc ? (1 << 5) : 0;
|
|
+ l |= fir_vinc ? (1 << 6) : 0;
|
|
+
|
|
+ l |= hscaleup ? 0 : (1 << 7);
|
|
+ l |= vscaleup ? 0 : (1 << 8);
|
|
+
|
|
+ l |= five_taps ? (1 << 21) : 0;
|
|
+ l |= five_taps ? (1 << 22) : 0;
|
|
+
|
|
+ dispc_write_reg(dispc_reg_att[plane], l);
|
|
+
|
|
+ if (ilace) {
|
|
+ if (fieldmode) {
|
|
+ accu0 = fir_vinc / 2;
|
|
+ accu1 = 0;
|
|
+ } else {
|
|
+ accu0 = 0;
|
|
+ accu1 = fir_vinc / 2;
|
|
+ if (accu1 >= 1024/2) {
|
|
+ accu0 = 1024/2;
|
|
+ accu1 -= accu0;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
|
+ _dispc_set_vid_accu0(plane, 0, accu0);
|
|
+ _dispc_set_vid_accu1(plane, 0, accu1);
|
|
+}
|
|
+
|
|
+static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
|
|
+ bool mirroring, enum omap_color_mode color_mode)
|
|
+{
|
|
+ if (color_mode == OMAP_DSS_COLOR_YUV2 ||
|
|
+ color_mode == OMAP_DSS_COLOR_UYVY) {
|
|
+ int vidrot = 0;
|
|
+
|
|
+ if (mirroring) {
|
|
+ switch (rotation) {
|
|
+ case 0: vidrot = 2; break;
|
|
+ case 1: vidrot = 3; break;
|
|
+ case 2: vidrot = 0; break;
|
|
+ case 3: vidrot = 1; break;
|
|
+ }
|
|
+ } else {
|
|
+ switch (rotation) {
|
|
+ case 0: vidrot = 0; break;
|
|
+ case 1: vidrot = 1; break;
|
|
+ case 2: vidrot = 2; break;
|
|
+ case 3: vidrot = 1; break;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
|
|
+
|
|
+ if (rotation == 1 || rotation == 3)
|
|
+ REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
|
|
+ else
|
|
+ REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
|
|
+ } else {
|
|
+ REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
|
|
+ REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
|
|
+ }
|
|
+}
|
|
+
|
|
+static int pixinc(int pixels, u8 ps)
|
|
+{
|
|
+ if (pixels == 1)
|
|
+ return 1;
|
|
+ else if (pixels > 1)
|
|
+ return 1 + (pixels - 1) * ps;
|
|
+ else if (pixels < 0)
|
|
+ return 1 - (-pixels + 1) * ps;
|
|
+ else
|
|
+ BUG();
|
|
+}
|
|
+
|
|
+static void calc_rotation_offset(u8 rotation, bool mirror,
|
|
+ u16 screen_width,
|
|
+ u16 width, u16 height,
|
|
+ enum omap_color_mode color_mode, bool fieldmode,
|
|
+ unsigned *offset0, unsigned *offset1,
|
|
+ u16 *row_inc, u16 *pix_inc)
|
|
+{
|
|
+ u8 ps;
|
|
+ u16 fbw, fbh;
|
|
+
|
|
+ switch (color_mode) {
|
|
+ case OMAP_DSS_COLOR_RGB16:
|
|
+ case OMAP_DSS_COLOR_ARGB16:
|
|
+ ps = 2;
|
|
+ break;
|
|
+
|
|
+ case OMAP_DSS_COLOR_RGB24P:
|
|
+ ps = 3;
|
|
+ break;
|
|
+
|
|
+ case OMAP_DSS_COLOR_RGB24U:
|
|
+ case OMAP_DSS_COLOR_ARGB32:
|
|
+ case OMAP_DSS_COLOR_RGBA32:
|
|
+ case OMAP_DSS_COLOR_RGBX32:
|
|
+ ps = 4;
|
|
+ break;
|
|
+
|
|
+ case OMAP_DSS_COLOR_YUV2:
|
|
+ case OMAP_DSS_COLOR_UYVY:
|
|
+ ps = 2;
|
|
+ break;
|
|
+ default:
|
|
+ BUG();
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
|
|
+ width, height);
|
|
+
|
|
+ /* width & height are overlay sizes, convert to fb sizes */
|
|
+
|
|
+ if (rotation == 0 || rotation == 2) {
|
|
+ fbw = width;
|
|
+ fbh = height;
|
|
+ } else {
|
|
+ fbw = height;
|
|
+ fbh = width;
|
|
+ }
|
|
+
|
|
+ switch (rotation + mirror * 4) {
|
|
+ case 0:
|
|
+ *offset0 = 0;
|
|
+ if (fieldmode)
|
|
+ *offset1 = screen_width * ps;
|
|
+ else
|
|
+ *offset1 = 0;
|
|
+ *row_inc = pixinc(1 + (screen_width - fbw) +
|
|
+ (fieldmode ? screen_width : 0),
|
|
+ ps);
|
|
+ *pix_inc = pixinc(1, ps);
|
|
+ break;
|
|
+ case 1:
|
|
+ *offset0 = screen_width * (fbh - 1) * ps;
|
|
+ if (fieldmode)
|
|
+ *offset1 = *offset0 + ps;
|
|
+ else
|
|
+ *offset1 = *offset0;
|
|
+ *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
|
|
+ (fieldmode ? 1 : 0), ps);
|
|
+ *pix_inc = pixinc(-screen_width, ps);
|
|
+ break;
|
|
+ case 2:
|
|
+ *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
|
|
+ if (fieldmode)
|
|
+ *offset1 = *offset0 - screen_width * ps;
|
|
+ else
|
|
+ *offset1 = *offset0;
|
|
+ *row_inc = pixinc(-1 -
|
|
+ (screen_width - fbw) -
|
|
+ (fieldmode ? screen_width : 0),
|
|
+ ps);
|
|
+ *pix_inc = pixinc(-1, ps);
|
|
+ break;
|
|
+ case 3:
|
|
+ *offset0 = (fbw - 1) * ps;
|
|
+ if (fieldmode)
|
|
+ *offset1 = *offset0 - ps;
|
|
+ else
|
|
+ *offset1 = *offset0;
|
|
+ *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
|
|
+ (fieldmode ? 1 : 0), ps);
|
|
+ *pix_inc = pixinc(screen_width, ps);
|
|
+ break;
|
|
+
|
|
+ /* mirroring */
|
|
+ case 0 + 4:
|
|
+ *offset0 = (fbw - 1) * ps;
|
|
+ if (fieldmode)
|
|
+ *offset1 = *offset0 + screen_width * ps;
|
|
+ else
|
|
+ *offset1 = *offset0;
|
|
+ *row_inc = pixinc(screen_width * 2 - 1 +
|
|
+ (fieldmode ? screen_width : 0),
|
|
+ ps);
|
|
+ *pix_inc = pixinc(-1, ps);
|
|
+ break;
|
|
+
|
|
+ case 1 + 4:
|
|
+ *offset0 = 0;
|
|
+ if (fieldmode)
|
|
+ *offset1 = *offset0 + screen_width * ps;
|
|
+ else
|
|
+ *offset1 = *offset0;
|
|
+ *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
|
|
+ (fieldmode ? 1 : 0),
|
|
+ ps);
|
|
+ *pix_inc = pixinc(screen_width, ps);
|
|
+ break;
|
|
+
|
|
+ case 2 + 4:
|
|
+ *offset0 = screen_width * (fbh - 1) * ps;
|
|
+ if (fieldmode)
|
|
+ *offset1 = *offset0 + screen_width * ps;
|
|
+ else
|
|
+ *offset1 = *offset0;
|
|
+ *row_inc = pixinc(1 - screen_width * 2 -
|
|
+ (fieldmode ? screen_width : 0),
|
|
+ ps);
|
|
+ *pix_inc = pixinc(1, ps);
|
|
+ break;
|
|
+
|
|
+ case 3 + 4:
|
|
+ *offset0 = (screen_width * (fbh - 1) + fbw - 1) * ps;
|
|
+ if (fieldmode)
|
|
+ *offset1 = *offset0 + screen_width * ps;
|
|
+ else
|
|
+ *offset1 = *offset0;
|
|
+ *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
|
|
+ (fieldmode ? 1 : 0),
|
|
+ ps);
|
|
+ *pix_inc = pixinc(-screen_width, ps);
|
|
+ break;
|
|
+
|
|
+ default:
|
|
+ BUG();
|
|
+ }
|
|
+}
|
|
+
|
|
+static int _dispc_setup_plane(enum omap_plane plane,
|
|
+ enum omap_channel channel_out,
|
|
+ u32 paddr, u16 screen_width,
|
|
+ u16 pos_x, u16 pos_y,
|
|
+ u16 width, u16 height,
|
|
+ u16 out_width, u16 out_height,
|
|
+ enum omap_color_mode color_mode,
|
|
+ bool ilace,
|
|
+ u8 rotation, int mirror)
|
|
+{
|
|
+ const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
|
|
+ bool five_taps = height > out_height * 2;
|
|
+ bool fieldmode = 0;
|
|
+ int cconv = 0;
|
|
+ unsigned offset0, offset1;
|
|
+ u16 row_inc;
|
|
+ u16 pix_inc;
|
|
+
|
|
+ if (plane == OMAP_DSS_GFX) {
|
|
+ if (width != out_width || height != out_height)
|
|
+ return -EINVAL;
|
|
+
|
|
+ switch (color_mode) {
|
|
+ case OMAP_DSS_COLOR_ARGB16:
|
|
+ case OMAP_DSS_COLOR_RGB16:
|
|
+ case OMAP_DSS_COLOR_RGB24P:
|
|
+ case OMAP_DSS_COLOR_RGB24U:
|
|
+ case OMAP_DSS_COLOR_ARGB32:
|
|
+ case OMAP_DSS_COLOR_RGBA32:
|
|
+ case OMAP_DSS_COLOR_RGBX32:
|
|
+ break;
|
|
+
|
|
+ default:
|
|
+ return -EINVAL;
|
|
+ }
|
|
+ } else {
|
|
+ /* video plane */
|
|
+ if (width > (2048 >> five_taps))
|
|
+ return -EINVAL;
|
|
+
|
|
+ if (out_width < width / maxdownscale ||
|
|
+ out_width > width * 8)
|
|
+ return -EINVAL;
|
|
+
|
|
+ if (out_height < height / maxdownscale ||
|
|
+ out_height > height * 8)
|
|
+ return -EINVAL;
|
|
+
|
|
+ switch (color_mode) {
|
|
+ case OMAP_DSS_COLOR_RGB16:
|
|
+ case OMAP_DSS_COLOR_RGB24P:
|
|
+ case OMAP_DSS_COLOR_RGB24U:
|
|
+ case OMAP_DSS_COLOR_RGBX32:
|
|
+ break;
|
|
+
|
|
+ case OMAP_DSS_COLOR_ARGB16:
|
|
+ case OMAP_DSS_COLOR_ARGB32:
|
|
+ case OMAP_DSS_COLOR_RGBA32:
|
|
+ if (plane == OMAP_DSS_VIDEO1)
|
|
+ return -EINVAL;
|
|
+ break;
|
|
+
|
|
+ case OMAP_DSS_COLOR_YUV2:
|
|
+ case OMAP_DSS_COLOR_UYVY:
|
|
+ cconv = 1;
|
|
+ break;
|
|
+
|
|
+ default:
|
|
+ return -EINVAL;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (ilace && height >= out_height)
|
|
+ fieldmode = 1;
|
|
+
|
|
+ calc_rotation_offset(rotation, mirror,
|
|
+ screen_width, width, height, color_mode,
|
|
+ fieldmode,
|
|
+ &offset0, &offset1, &row_inc, &pix_inc);
|
|
+
|
|
+ DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
|
|
+ offset0, offset1, row_inc, pix_inc);
|
|
+
|
|
+ if (ilace) {
|
|
+ if (fieldmode)
|
|
+ height /= 2;
|
|
+ pos_y /= 2;
|
|
+ out_height /= 2;
|
|
+
|
|
+ DSSDBG("adjusting for ilace: height %d, pos_y %d, "
|
|
+ "out_height %d\n",
|
|
+ height, pos_y, out_height);
|
|
+ }
|
|
+
|
|
+ _dispc_set_channel_out(plane, channel_out);
|
|
+ _dispc_set_color_mode(plane, color_mode);
|
|
+
|
|
+ _dispc_set_plane_ba0(plane, paddr + offset0);
|
|
+ _dispc_set_plane_ba1(plane, paddr + offset1);
|
|
+
|
|
+ _dispc_set_row_inc(plane, row_inc);
|
|
+ _dispc_set_pix_inc(plane, pix_inc);
|
|
+
|
|
+ DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
|
|
+ out_width, out_height);
|
|
+
|
|
+ _dispc_set_plane_pos(plane, pos_x, pos_y);
|
|
+
|
|
+ _dispc_set_pic_size(plane, width, height);
|
|
+
|
|
+ if (plane != OMAP_DSS_GFX) {
|
|
+ _dispc_set_scaling(plane, width, height,
|
|
+ out_width, out_height,
|
|
+ ilace);
|
|
+ _dispc_set_vid_size(plane, out_width, out_height);
|
|
+ _dispc_set_vid_color_conv(plane, cconv);
|
|
+ }
|
|
+
|
|
+ _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void _dispc_enable_plane(enum omap_plane plane, bool enable)
|
|
+{
|
|
+ REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
|
|
+}
|
|
+
|
|
+static void dispc_disable_isr(void *data, u32 mask)
|
|
+{
|
|
+ struct completion *compl = data;
|
|
+ complete(compl);
|
|
+}
|
|
+
|
|
+static void _enable_lcd_out(bool enable)
|
|
+{
|
|
+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
|
|
+}
|
|
+
|
|
+void dispc_enable_lcd_out(bool enable)
|
|
+{
|
|
+ struct completion frame_done_completion;
|
|
+ bool is_on;
|
|
+ int r;
|
|
+
|
|
+ enable_clocks(1);
|
|
+
|
|
+ /* When we disable LCD output, we need to wait until frame is done.
|
|
+ * Otherwise the DSS is still working, and turning off the clocks
|
|
+ * prevents DSS from going to OFF mode */
|
|
+ is_on = REG_GET(DISPC_CONTROL, 0, 0);
|
|
+
|
|
+ if (!enable && is_on) {
|
|
+ init_completion(&frame_done_completion);
|
|
+
|
|
+ r = omap_dispc_register_isr(dispc_disable_isr,
|
|
+ &frame_done_completion,
|
|
+ DISPC_IRQ_FRAMEDONE);
|
|
+
|
|
+ if (r)
|
|
+ DSSERR("failed to register FRAMEDONE isr\n");
|
|
+ }
|
|
+
|
|
+ _enable_lcd_out(enable);
|
|
+
|
|
+ if (!enable && is_on) {
|
|
+ if (!wait_for_completion_timeout(&frame_done_completion,
|
|
+ msecs_to_jiffies(100)))
|
|
+ DSSERR("timeout waiting for FRAME DONE\n");
|
|
+
|
|
+ r = omap_dispc_unregister_isr(dispc_disable_isr,
|
|
+ &frame_done_completion,
|
|
+ DISPC_IRQ_FRAMEDONE);
|
|
+
|
|
+ if (r)
|
|
+ DSSERR("failed to unregister FRAMEDONE isr\n");
|
|
+ }
|
|
+
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+static void _enable_digit_out(bool enable)
|
|
+{
|
|
+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
|
|
+}
|
|
+
|
|
+void dispc_enable_digit_out(bool enable)
|
|
+{
|
|
+ struct completion frame_done_completion;
|
|
+ int r;
|
|
+
|
|
+ enable_clocks(1);
|
|
+
|
|
+ if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
|
|
+ enable_clocks(0);
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ if (enable) {
|
|
+ /* When we enable digit output, we'll get an extra digit
|
|
+ * sync lost interrupt, that we need to ignore */
|
|
+ dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
|
|
+ omap_dispc_set_irqs();
|
|
+ }
|
|
+
|
|
+ /* When we disable digit output, we need to wait until fields are done.
|
|
+ * Otherwise the DSS is still working, and turning off the clocks
|
|
+ * prevents DSS from going to OFF mode. And when enabling, we need to
|
|
+ * wait for the extra sync losts */
|
|
+ init_completion(&frame_done_completion);
|
|
+
|
|
+ r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
|
|
+ DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
|
|
+ if (r)
|
|
+ DSSERR("failed to register EVSYNC isr\n");
|
|
+
|
|
+ _enable_digit_out(enable);
|
|
+
|
|
+ /* XXX I understand from TRM that we should only wait for the
|
|
+ * current field to complete. But it seems we have to wait
|
|
+ * for both fields */
|
|
+ if (!wait_for_completion_timeout(&frame_done_completion,
|
|
+ msecs_to_jiffies(100)))
|
|
+ DSSERR("timeout waiting for EVSYNC\n");
|
|
+
|
|
+ if (!wait_for_completion_timeout(&frame_done_completion,
|
|
+ msecs_to_jiffies(100)))
|
|
+ DSSERR("timeout waiting for EVSYNC\n");
|
|
+
|
|
+ r = omap_dispc_unregister_isr(dispc_disable_isr,
|
|
+ &frame_done_completion,
|
|
+ DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
|
|
+ if (r)
|
|
+ DSSERR("failed to unregister EVSYNC isr\n");
|
|
+
|
|
+ if (enable) {
|
|
+ dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
|
|
+ dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
|
|
+ omap_dispc_set_irqs();
|
|
+ }
|
|
+
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+void dispc_lcd_enable_signal_polarity(bool act_high)
|
|
+{
|
|
+ enable_clocks(1);
|
|
+ REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+void dispc_lcd_enable_signal(bool enable)
|
|
+{
|
|
+ enable_clocks(1);
|
|
+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+void dispc_pck_free_enable(bool enable)
|
|
+{
|
|
+ enable_clocks(1);
|
|
+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+void dispc_enable_fifohandcheck(bool enable)
|
|
+{
|
|
+ enable_clocks(1);
|
|
+ REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+
|
|
+void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
|
|
+{
|
|
+ int mode;
|
|
+
|
|
+ switch (type) {
|
|
+ case OMAP_DSS_LCD_DISPLAY_STN:
|
|
+ mode = 0;
|
|
+ break;
|
|
+
|
|
+ case OMAP_DSS_LCD_DISPLAY_TFT:
|
|
+ mode = 1;
|
|
+ break;
|
|
+
|
|
+ default:
|
|
+ BUG();
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ enable_clocks(1);
|
|
+ REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+void dispc_set_loadmode(enum omap_dss_load_mode mode)
|
|
+{
|
|
+ enable_clocks(1);
|
|
+ REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+
|
|
+void dispc_set_default_color(enum omap_channel channel, u32 color)
|
|
+{
|
|
+ const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
|
|
+ DISPC_DEFAULT_COLOR1 };
|
|
+
|
|
+ enable_clocks(1);
|
|
+ dispc_write_reg(def_reg[channel], color);
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+u32 dispc_get_default_color(enum omap_channel channel)
|
|
+{
|
|
+ const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
|
|
+ DISPC_DEFAULT_COLOR1 };
|
|
+ u32 l;
|
|
+
|
|
+ BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
|
|
+ channel != OMAP_DSS_CHANNEL_LCD);
|
|
+
|
|
+ enable_clocks(1);
|
|
+ l = dispc_read_reg(def_reg[channel]);
|
|
+ enable_clocks(0);
|
|
+
|
|
+ return l;
|
|
+}
|
|
+
|
|
+void dispc_set_trans_key(enum omap_channel ch,
|
|
+ enum omap_dss_color_key_type type,
|
|
+ u32 trans_key)
|
|
+{
|
|
+ const struct dispc_reg tr_reg[] = {
|
|
+ DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
|
|
+
|
|
+ enable_clocks(1);
|
|
+ if (ch == OMAP_DSS_CHANNEL_LCD)
|
|
+ REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
|
|
+ else /* OMAP_DSS_CHANNEL_DIGIT */
|
|
+ REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
|
|
+
|
|
+ dispc_write_reg(tr_reg[ch], trans_key);
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+void dispc_get_trans_key(enum omap_channel ch,
|
|
+ enum omap_dss_color_key_type *type,
|
|
+ u32 *trans_key)
|
|
+{
|
|
+ const struct dispc_reg tr_reg[] = {
|
|
+ DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
|
|
+
|
|
+ enable_clocks(1);
|
|
+ if (type) {
|
|
+ if (ch == OMAP_DSS_CHANNEL_LCD)
|
|
+ *type = REG_GET(DISPC_CONFIG, 11, 11) >> 11;
|
|
+ else if (ch == OMAP_DSS_CHANNEL_DIGIT)
|
|
+ *type = REG_GET(DISPC_CONFIG, 13, 13) >> 13;
|
|
+ else
|
|
+ BUG();
|
|
+ }
|
|
+
|
|
+ if (trans_key)
|
|
+ *trans_key = dispc_read_reg(tr_reg[ch]);
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+void dispc_enable_trans_key(enum omap_channel ch, bool enable)
|
|
+{
|
|
+ enable_clocks(1);
|
|
+ if (ch == OMAP_DSS_CHANNEL_LCD)
|
|
+ REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
|
|
+ else /* OMAP_DSS_CHANNEL_DIGIT */
|
|
+ REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+bool dispc_trans_key_enabled(enum omap_channel ch)
|
|
+{
|
|
+ bool enabled;
|
|
+
|
|
+ enable_clocks(1);
|
|
+ if (ch == OMAP_DSS_CHANNEL_LCD)
|
|
+ enabled = REG_GET(DISPC_CONFIG, 10, 10);
|
|
+ else if (ch == OMAP_DSS_CHANNEL_DIGIT)
|
|
+ enabled = REG_GET(DISPC_CONFIG, 12, 12);
|
|
+ else BUG();
|
|
+ enable_clocks(0);
|
|
+
|
|
+ return enabled;
|
|
+}
|
|
+
|
|
+
|
|
+void dispc_set_tft_data_lines(u8 data_lines)
|
|
+{
|
|
+ int code;
|
|
+
|
|
+ switch (data_lines) {
|
|
+ case 12:
|
|
+ code = 0;
|
|
+ break;
|
|
+ case 16:
|
|
+ code = 1;
|
|
+ break;
|
|
+ case 18:
|
|
+ code = 2;
|
|
+ break;
|
|
+ case 24:
|
|
+ code = 3;
|
|
+ break;
|
|
+ default:
|
|
+ BUG();
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ enable_clocks(1);
|
|
+ REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
|
|
+{
|
|
+ u32 l;
|
|
+ int stallmode;
|
|
+ int gpout0 = 1;
|
|
+ int gpout1;
|
|
+
|
|
+ switch (mode) {
|
|
+ case OMAP_DSS_PARALLELMODE_BYPASS:
|
|
+ stallmode = 0;
|
|
+ gpout1 = 1;
|
|
+ break;
|
|
+
|
|
+ case OMAP_DSS_PARALLELMODE_RFBI:
|
|
+ stallmode = 1;
|
|
+ gpout1 = 0;
|
|
+ break;
|
|
+
|
|
+ case OMAP_DSS_PARALLELMODE_DSI:
|
|
+ stallmode = 1;
|
|
+ gpout1 = 1;
|
|
+ break;
|
|
+
|
|
+ default:
|
|
+ BUG();
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ enable_clocks(1);
|
|
+
|
|
+ l = dispc_read_reg(DISPC_CONTROL);
|
|
+
|
|
+ l = FLD_MOD(l, stallmode, 11, 11);
|
|
+ l = FLD_MOD(l, gpout0, 15, 15);
|
|
+ l = FLD_MOD(l, gpout1, 16, 16);
|
|
+
|
|
+ dispc_write_reg(DISPC_CONTROL, l);
|
|
+
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
|
|
+ int vsw, int vfp, int vbp)
|
|
+{
|
|
+ u32 timing_h, timing_v;
|
|
+
|
|
+ if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
|
|
+ BUG_ON(hsw < 1 || hsw > 64);
|
|
+ BUG_ON(hfp < 1 || hfp > 256);
|
|
+ BUG_ON(hbp < 1 || hbp > 256);
|
|
+
|
|
+ BUG_ON(vsw < 1 || vsw > 64);
|
|
+ BUG_ON(vfp < 0 || vfp > 255);
|
|
+ BUG_ON(vbp < 0 || vbp > 255);
|
|
+
|
|
+ timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
|
|
+ FLD_VAL(hbp-1, 27, 20);
|
|
+
|
|
+ timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
|
|
+ FLD_VAL(vbp, 27, 20);
|
|
+ } else {
|
|
+ BUG_ON(hsw < 1 || hsw > 256);
|
|
+ BUG_ON(hfp < 1 || hfp > 4096);
|
|
+ BUG_ON(hbp < 1 || hbp > 4096);
|
|
+
|
|
+ BUG_ON(vsw < 1 || vsw > 256);
|
|
+ BUG_ON(vfp < 0 || vfp > 4095);
|
|
+ BUG_ON(vbp < 0 || vbp > 4095);
|
|
+
|
|
+ timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
|
|
+ FLD_VAL(hbp-1, 31, 20);
|
|
+
|
|
+ timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
|
|
+ FLD_VAL(vbp, 31, 20);
|
|
+ }
|
|
+
|
|
+ enable_clocks(1);
|
|
+ dispc_write_reg(DISPC_TIMING_H, timing_h);
|
|
+ dispc_write_reg(DISPC_TIMING_V, timing_v);
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+/* change name to mode? */
|
|
+void dispc_set_lcd_timings(struct omap_video_timings *timings)
|
|
+{
|
|
+ unsigned xtot, ytot;
|
|
+ unsigned long ht, vt;
|
|
+
|
|
+ _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
|
|
+ timings->vsw, timings->vfp, timings->vbp);
|
|
+
|
|
+ dispc_set_lcd_size(timings->x_res, timings->y_res);
|
|
+
|
|
+ xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
|
|
+ ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
|
|
+
|
|
+ ht = (timings->pixel_clock * 1000) / xtot;
|
|
+ vt = (timings->pixel_clock * 1000) / xtot / ytot;
|
|
+
|
|
+ DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
|
|
+ DSSDBG("pck %u\n", timings->pixel_clock);
|
|
+ DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
|
|
+ timings->hsw, timings->hfp, timings->hbp,
|
|
+ timings->vsw, timings->vfp, timings->vbp);
|
|
+
|
|
+ DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
|
|
+}
|
|
+
|
|
+void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
|
|
+{
|
|
+ BUG_ON(lck_div < 1);
|
|
+ BUG_ON(pck_div < 2);
|
|
+
|
|
+ enable_clocks(1);
|
|
+ dispc_write_reg(DISPC_DIVISOR,
|
|
+ FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
|
|
+{
|
|
+ u32 l;
|
|
+ l = dispc_read_reg(DISPC_DIVISOR);
|
|
+ *lck_div = FLD_GET(l, 23, 16);
|
|
+ *pck_div = FLD_GET(l, 7, 0);
|
|
+}
|
|
+
|
|
+unsigned long dispc_fclk_rate(void)
|
|
+{
|
|
+ unsigned long r = 0;
|
|
+
|
|
+ if (dss_get_dispc_clk_source() == 0)
|
|
+ r = dss_clk_get_rate(DSS_CLK_FCK1);
|
|
+ else
|
|
+#ifdef CONFIG_OMAP2_DSS_DSI
|
|
+ r = dsi_get_dsi1_pll_rate();
|
|
+#else
|
|
+ BUG();
|
|
+#endif
|
|
+ return r;
|
|
+}
|
|
+
|
|
+unsigned long dispc_pclk_rate(void)
|
|
+{
|
|
+ int lcd, pcd;
|
|
+ unsigned long r;
|
|
+ u32 l;
|
|
+
|
|
+ l = dispc_read_reg(DISPC_DIVISOR);
|
|
+
|
|
+ lcd = FLD_GET(l, 23, 16);
|
|
+ pcd = FLD_GET(l, 7, 0);
|
|
+
|
|
+ r = dispc_fclk_rate();
|
|
+
|
|
+ return r / lcd / pcd;
|
|
+}
|
|
+
|
|
+void dispc_dump_clocks(struct seq_file *s)
|
|
+{
|
|
+ int lcd, pcd;
|
|
+
|
|
+ enable_clocks(1);
|
|
+
|
|
+ dispc_get_lcd_divisor(&lcd, &pcd);
|
|
+
|
|
+ seq_printf(s, "- dispc -\n");
|
|
+
|
|
+ seq_printf(s, "dispc fclk source = %s\n",
|
|
+ dss_get_dispc_clk_source() == 0 ?
|
|
+ "dss1_alwon_fclk" : "dsi1_pll_fclk");
|
|
+
|
|
+ seq_printf(s, "pixel clk = %lu / %d / %d = %lu\n",
|
|
+ dispc_fclk_rate(),
|
|
+ lcd, pcd,
|
|
+ dispc_pclk_rate());
|
|
+
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+void dispc_dump_regs(struct seq_file *s)
|
|
+{
|
|
+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
|
|
+
|
|
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+
|
|
+ DUMPREG(DISPC_REVISION);
|
|
+ DUMPREG(DISPC_SYSCONFIG);
|
|
+ DUMPREG(DISPC_SYSSTATUS);
|
|
+ DUMPREG(DISPC_IRQSTATUS);
|
|
+ DUMPREG(DISPC_IRQENABLE);
|
|
+ DUMPREG(DISPC_CONTROL);
|
|
+ DUMPREG(DISPC_CONFIG);
|
|
+ DUMPREG(DISPC_CAPABLE);
|
|
+ DUMPREG(DISPC_DEFAULT_COLOR0);
|
|
+ DUMPREG(DISPC_DEFAULT_COLOR1);
|
|
+ DUMPREG(DISPC_TRANS_COLOR0);
|
|
+ DUMPREG(DISPC_TRANS_COLOR1);
|
|
+ DUMPREG(DISPC_LINE_STATUS);
|
|
+ DUMPREG(DISPC_LINE_NUMBER);
|
|
+ DUMPREG(DISPC_TIMING_H);
|
|
+ DUMPREG(DISPC_TIMING_V);
|
|
+ DUMPREG(DISPC_POL_FREQ);
|
|
+ DUMPREG(DISPC_DIVISOR);
|
|
+ DUMPREG(DISPC_GLOBAL_ALPHA);
|
|
+ DUMPREG(DISPC_SIZE_DIG);
|
|
+ DUMPREG(DISPC_SIZE_LCD);
|
|
+
|
|
+ DUMPREG(DISPC_GFX_BA0);
|
|
+ DUMPREG(DISPC_GFX_BA1);
|
|
+ DUMPREG(DISPC_GFX_POSITION);
|
|
+ DUMPREG(DISPC_GFX_SIZE);
|
|
+ DUMPREG(DISPC_GFX_ATTRIBUTES);
|
|
+ DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
|
|
+ DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
|
|
+ DUMPREG(DISPC_GFX_ROW_INC);
|
|
+ DUMPREG(DISPC_GFX_PIXEL_INC);
|
|
+ DUMPREG(DISPC_GFX_WINDOW_SKIP);
|
|
+ DUMPREG(DISPC_GFX_TABLE_BA);
|
|
+
|
|
+ DUMPREG(DISPC_DATA_CYCLE1);
|
|
+ DUMPREG(DISPC_DATA_CYCLE2);
|
|
+ DUMPREG(DISPC_DATA_CYCLE3);
|
|
+
|
|
+ DUMPREG(DISPC_CPR_COEF_R);
|
|
+ DUMPREG(DISPC_CPR_COEF_G);
|
|
+ DUMPREG(DISPC_CPR_COEF_B);
|
|
+
|
|
+ DUMPREG(DISPC_GFX_PRELOAD);
|
|
+
|
|
+ DUMPREG(DISPC_VID_BA0(0));
|
|
+ DUMPREG(DISPC_VID_BA1(0));
|
|
+ DUMPREG(DISPC_VID_POSITION(0));
|
|
+ DUMPREG(DISPC_VID_SIZE(0));
|
|
+ DUMPREG(DISPC_VID_ATTRIBUTES(0));
|
|
+ DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
|
|
+ DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
|
|
+ DUMPREG(DISPC_VID_ROW_INC(0));
|
|
+ DUMPREG(DISPC_VID_PIXEL_INC(0));
|
|
+ DUMPREG(DISPC_VID_FIR(0));
|
|
+ DUMPREG(DISPC_VID_PICTURE_SIZE(0));
|
|
+ DUMPREG(DISPC_VID_ACCU0(0));
|
|
+ DUMPREG(DISPC_VID_ACCU1(0));
|
|
+
|
|
+ DUMPREG(DISPC_VID_BA0(1));
|
|
+ DUMPREG(DISPC_VID_BA1(1));
|
|
+ DUMPREG(DISPC_VID_POSITION(1));
|
|
+ DUMPREG(DISPC_VID_SIZE(1));
|
|
+ DUMPREG(DISPC_VID_ATTRIBUTES(1));
|
|
+ DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
|
|
+ DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
|
|
+ DUMPREG(DISPC_VID_ROW_INC(1));
|
|
+ DUMPREG(DISPC_VID_PIXEL_INC(1));
|
|
+ DUMPREG(DISPC_VID_FIR(1));
|
|
+ DUMPREG(DISPC_VID_PICTURE_SIZE(1));
|
|
+ DUMPREG(DISPC_VID_ACCU0(1));
|
|
+ DUMPREG(DISPC_VID_ACCU1(1));
|
|
+
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
|
|
+ DUMPREG(DISPC_VID_CONV_COEF(0, 0));
|
|
+ DUMPREG(DISPC_VID_CONV_COEF(0, 1));
|
|
+ DUMPREG(DISPC_VID_CONV_COEF(0, 2));
|
|
+ DUMPREG(DISPC_VID_CONV_COEF(0, 3));
|
|
+ DUMPREG(DISPC_VID_CONV_COEF(0, 4));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
|
|
+
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
|
|
+ DUMPREG(DISPC_VID_CONV_COEF(1, 0));
|
|
+ DUMPREG(DISPC_VID_CONV_COEF(1, 1));
|
|
+ DUMPREG(DISPC_VID_CONV_COEF(1, 2));
|
|
+ DUMPREG(DISPC_VID_CONV_COEF(1, 3));
|
|
+ DUMPREG(DISPC_VID_CONV_COEF(1, 4));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
|
|
+ DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
|
|
+
|
|
+ DUMPREG(DISPC_VID_PRELOAD(0));
|
|
+ DUMPREG(DISPC_VID_PRELOAD(1));
|
|
+
|
|
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+#undef DUMPREG
|
|
+}
|
|
+
|
|
+static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
|
|
+ bool ihs, bool ivs, u8 acbi, u8 acb)
|
|
+{
|
|
+ u32 l = 0;
|
|
+
|
|
+ DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
|
|
+ onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
|
|
+
|
|
+ l |= FLD_VAL(onoff, 17, 17);
|
|
+ l |= FLD_VAL(rf, 16, 16);
|
|
+ l |= FLD_VAL(ieo, 15, 15);
|
|
+ l |= FLD_VAL(ipc, 14, 14);
|
|
+ l |= FLD_VAL(ihs, 13, 13);
|
|
+ l |= FLD_VAL(ivs, 12, 12);
|
|
+ l |= FLD_VAL(acbi, 11, 8);
|
|
+ l |= FLD_VAL(acb, 7, 0);
|
|
+
|
|
+ enable_clocks(1);
|
|
+ dispc_write_reg(DISPC_POL_FREQ, l);
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+void dispc_set_pol_freq(struct omap_panel *panel)
|
|
+{
|
|
+ _dispc_set_pol_freq((panel->config & OMAP_DSS_LCD_ONOFF) != 0,
|
|
+ (panel->config & OMAP_DSS_LCD_RF) != 0,
|
|
+ (panel->config & OMAP_DSS_LCD_IEO) != 0,
|
|
+ (panel->config & OMAP_DSS_LCD_IPC) != 0,
|
|
+ (panel->config & OMAP_DSS_LCD_IHS) != 0,
|
|
+ (panel->config & OMAP_DSS_LCD_IVS) != 0,
|
|
+ panel->acbi, panel->acb);
|
|
+}
|
|
+
|
|
+void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
|
|
+ u16 *lck_div, u16 *pck_div)
|
|
+{
|
|
+ u16 pcd_min = is_tft ? 2 : 3;
|
|
+ unsigned long best_pck;
|
|
+ u16 best_ld, cur_ld;
|
|
+ u16 best_pd, cur_pd;
|
|
+
|
|
+ best_pck = 0;
|
|
+ best_ld = 0;
|
|
+ best_pd = 0;
|
|
+
|
|
+ for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
|
|
+ unsigned long lck = fck / cur_ld;
|
|
+
|
|
+ for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
|
|
+ unsigned long pck = lck / cur_pd;
|
|
+ long old_delta = abs(best_pck - req_pck);
|
|
+ long new_delta = abs(pck - req_pck);
|
|
+
|
|
+ if (best_pck == 0 || new_delta < old_delta) {
|
|
+ best_pck = pck;
|
|
+ best_ld = cur_ld;
|
|
+ best_pd = cur_pd;
|
|
+
|
|
+ if (pck == req_pck)
|
|
+ goto found;
|
|
+ }
|
|
+
|
|
+ if (pck < req_pck)
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ if (lck / pcd_min < req_pck)
|
|
+ break;
|
|
+ }
|
|
+
|
|
+found:
|
|
+ *lck_div = best_ld;
|
|
+ *pck_div = best_pd;
|
|
+}
|
|
+
|
|
+int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
|
|
+ struct dispc_clock_info *cinfo)
|
|
+{
|
|
+ unsigned long prate;
|
|
+ struct dispc_clock_info cur, best;
|
|
+ int match = 0;
|
|
+ int min_fck_per_pck;
|
|
+ unsigned long fck_rate = dss_clk_get_rate(DSS_CLK_FCK1);
|
|
+
|
|
+ if (cpu_is_omap34xx())
|
|
+ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
|
|
+ else
|
|
+ prate = 0;
|
|
+
|
|
+ if (req_pck == dispc.cache_req_pck &&
|
|
+ ((cpu_is_omap34xx() && prate == dispc.cache_prate) ||
|
|
+ dispc.cache_cinfo.fck == fck_rate)) {
|
|
+ DSSDBG("dispc clock info found from cache.\n");
|
|
+ *cinfo = dispc.cache_cinfo;
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
+ min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
|
|
+
|
|
+ if (min_fck_per_pck &&
|
|
+ req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
|
|
+ DSSERR("Requested pixel clock not possible with the current "
|
|
+ "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
|
|
+ "the constraint off.\n");
|
|
+ min_fck_per_pck = 0;
|
|
+ }
|
|
+
|
|
+retry:
|
|
+ memset(&cur, 0, sizeof(cur));
|
|
+ memset(&best, 0, sizeof(best));
|
|
+
|
|
+ if (cpu_is_omap24xx()) {
|
|
+ /* XXX can we change the clock on omap2? */
|
|
+ cur.fck = dss_clk_get_rate(DSS_CLK_FCK1);
|
|
+ cur.fck_div = 1;
|
|
+
|
|
+ match = 1;
|
|
+
|
|
+ find_lck_pck_divs(is_tft, req_pck, cur.fck,
|
|
+ &cur.lck_div, &cur.pck_div);
|
|
+
|
|
+ cur.lck = cur.fck / cur.lck_div;
|
|
+ cur.pck = cur.lck / cur.pck_div;
|
|
+
|
|
+ best = cur;
|
|
+
|
|
+ goto found;
|
|
+ } else if (cpu_is_omap34xx()) {
|
|
+ for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) {
|
|
+ cur.fck = prate / cur.fck_div * 2;
|
|
+
|
|
+ if (cur.fck > DISPC_MAX_FCK)
|
|
+ continue;
|
|
+
|
|
+ if (min_fck_per_pck &&
|
|
+ cur.fck < req_pck * min_fck_per_pck)
|
|
+ continue;
|
|
+
|
|
+ match = 1;
|
|
+
|
|
+ find_lck_pck_divs(is_tft, req_pck, cur.fck,
|
|
+ &cur.lck_div, &cur.pck_div);
|
|
+
|
|
+ cur.lck = cur.fck / cur.lck_div;
|
|
+ cur.pck = cur.lck / cur.pck_div;
|
|
+
|
|
+ if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) {
|
|
+ best = cur;
|
|
+
|
|
+ if (cur.pck == req_pck)
|
|
+ goto found;
|
|
+ }
|
|
+ }
|
|
+ } else {
|
|
+ BUG();
|
|
+ }
|
|
+
|
|
+found:
|
|
+ if (!match) {
|
|
+ if (min_fck_per_pck) {
|
|
+ DSSERR("Could not find suitable clock settings.\n"
|
|
+ "Turning FCK/PCK constraint off and"
|
|
+ "trying again.\n");
|
|
+ min_fck_per_pck = 0;
|
|
+ goto retry;
|
|
+ }
|
|
+
|
|
+ DSSERR("Could not find suitable clock settings.\n");
|
|
+
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ if (cinfo)
|
|
+ *cinfo = best;
|
|
+
|
|
+ dispc.cache_req_pck = req_pck;
|
|
+ dispc.cache_prate = prate;
|
|
+ dispc.cache_cinfo = best;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+int dispc_set_clock_div(struct dispc_clock_info *cinfo)
|
|
+{
|
|
+ unsigned long prate;
|
|
+ int r;
|
|
+
|
|
+ if (cpu_is_omap34xx()) {
|
|
+ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
|
|
+ DSSDBG("dpll4_m4 = %ld\n", prate);
|
|
+ }
|
|
+
|
|
+ DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
|
|
+ DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div);
|
|
+ DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div);
|
|
+
|
|
+ if (cpu_is_omap34xx()) {
|
|
+ r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div);
|
|
+ if (r)
|
|
+ return r;
|
|
+ }
|
|
+
|
|
+ dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+int dispc_get_clock_div(struct dispc_clock_info *cinfo)
|
|
+{
|
|
+ cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
|
|
+
|
|
+ if (cpu_is_omap34xx()) {
|
|
+ unsigned long prate;
|
|
+ prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
|
|
+ cinfo->fck_div = prate / (cinfo->fck / 2);
|
|
+ } else {
|
|
+ cinfo->fck_div = 0;
|
|
+ }
|
|
+
|
|
+ cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
|
|
+ cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
|
|
+
|
|
+ cinfo->lck = cinfo->fck / cinfo->lck_div;
|
|
+ cinfo->pck = cinfo->lck / cinfo->pck_div;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void omap_dispc_set_irqs(void)
|
|
+{
|
|
+ unsigned long flags;
|
|
+ u32 mask = dispc.irq_error_mask;
|
|
+ int i;
|
|
+ struct omap_dispc_isr_data *isr_data;
|
|
+
|
|
+ spin_lock_irqsave(&dispc.irq_lock, flags);
|
|
+
|
|
+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
|
|
+ isr_data = &dispc.registered_isr[i];
|
|
+
|
|
+ if (isr_data->isr == NULL)
|
|
+ continue;
|
|
+
|
|
+ mask |= isr_data->mask;
|
|
+ }
|
|
+
|
|
+ enable_clocks(1);
|
|
+ dispc_write_reg(DISPC_IRQENABLE, mask);
|
|
+ enable_clocks(0);
|
|
+
|
|
+ spin_unlock_irqrestore(&dispc.irq_lock, flags);
|
|
+}
|
|
+
|
|
+int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
|
|
+{
|
|
+ int i;
|
|
+ int ret;
|
|
+ unsigned long flags;
|
|
+ struct omap_dispc_isr_data *isr_data;
|
|
+
|
|
+ if (isr == NULL)
|
|
+ return -EINVAL;
|
|
+
|
|
+ spin_lock_irqsave(&dispc.irq_lock, flags);
|
|
+
|
|
+ /* check for duplicate entry */
|
|
+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
|
|
+ isr_data = &dispc.registered_isr[i];
|
|
+ if (isr_data->isr == isr && isr_data->arg == arg &&
|
|
+ isr_data->mask == mask) {
|
|
+ ret = -EINVAL;
|
|
+ goto err;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ isr_data = NULL;
|
|
+ ret = -EBUSY;
|
|
+
|
|
+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
|
|
+ isr_data = &dispc.registered_isr[i];
|
|
+
|
|
+ if (isr_data->isr != NULL)
|
|
+ continue;
|
|
+
|
|
+ isr_data->isr = isr;
|
|
+ isr_data->arg = arg;
|
|
+ isr_data->mask = mask;
|
|
+ ret = 0;
|
|
+
|
|
+ break;
|
|
+ }
|
|
+err:
|
|
+ spin_unlock_irqrestore(&dispc.irq_lock, flags);
|
|
+
|
|
+ if (ret == 0)
|
|
+ omap_dispc_set_irqs();
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+EXPORT_SYMBOL(omap_dispc_register_isr);
|
|
+
|
|
+int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
|
|
+{
|
|
+ int i;
|
|
+ unsigned long flags;
|
|
+ int ret = -EINVAL;
|
|
+ struct omap_dispc_isr_data *isr_data;
|
|
+
|
|
+ spin_lock_irqsave(&dispc.irq_lock, flags);
|
|
+
|
|
+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
|
|
+ isr_data = &dispc.registered_isr[i];
|
|
+ if (isr_data->isr != isr || isr_data->arg != arg ||
|
|
+ isr_data->mask != mask)
|
|
+ continue;
|
|
+
|
|
+ /* found the correct isr */
|
|
+
|
|
+ isr_data->isr = NULL;
|
|
+ isr_data->arg = NULL;
|
|
+ isr_data->mask = 0;
|
|
+
|
|
+ ret = 0;
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ spin_unlock_irqrestore(&dispc.irq_lock, flags);
|
|
+
|
|
+ if (ret == 0)
|
|
+ omap_dispc_set_irqs();
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+EXPORT_SYMBOL(omap_dispc_unregister_isr);
|
|
+
|
|
+#ifdef DEBUG
|
|
+static void print_irq_status(u32 status)
|
|
+{
|
|
+ if ((status & dispc.irq_error_mask) == 0)
|
|
+ return;
|
|
+
|
|
+ printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
|
|
+
|
|
+#define PIS(x) \
|
|
+ if (status & DISPC_IRQ_##x) \
|
|
+ printk(#x " ");
|
|
+ PIS(GFX_FIFO_UNDERFLOW);
|
|
+ PIS(OCP_ERR);
|
|
+ PIS(VID1_FIFO_UNDERFLOW);
|
|
+ PIS(VID2_FIFO_UNDERFLOW);
|
|
+ PIS(SYNC_LOST);
|
|
+ PIS(SYNC_LOST_DIGIT);
|
|
+#undef PIS
|
|
+
|
|
+ printk("\n");
|
|
+}
|
|
+#endif
|
|
+
|
|
+/* Called from dss.c. Note that we don't touch clocks here,
|
|
+ * but we presume they are on because we got an IRQ. However,
|
|
+ * an irq handler may turn the clocks off, so we may not have
|
|
+ * clock later in the function. */
|
|
+void dispc_irq_handler(void)
|
|
+{
|
|
+ int i;
|
|
+ u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
|
|
+ u32 handledirqs = 0;
|
|
+ u32 unhandled_errors;
|
|
+ struct omap_dispc_isr_data *isr_data;
|
|
+
|
|
+#ifdef DEBUG
|
|
+ if (dss_debug)
|
|
+ print_irq_status(irqstatus);
|
|
+#endif
|
|
+ /* Ack the interrupt. Do it here before clocks are possibly turned
|
|
+ * off */
|
|
+ dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
|
|
+
|
|
+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
|
|
+ isr_data = &dispc.registered_isr[i];
|
|
+
|
|
+ if (!isr_data->isr)
|
|
+ continue;
|
|
+
|
|
+ if (isr_data->mask & irqstatus) {
|
|
+ isr_data->isr(isr_data->arg, irqstatus);
|
|
+ handledirqs |= isr_data->mask;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
|
|
+
|
|
+ if (unhandled_errors) {
|
|
+ spin_lock(&dispc.error_lock);
|
|
+ dispc.error_irqs |= unhandled_errors;
|
|
+ spin_unlock(&dispc.error_lock);
|
|
+
|
|
+ dispc.irq_error_mask &= ~unhandled_errors;
|
|
+ omap_dispc_set_irqs();
|
|
+
|
|
+ schedule_work(&dispc.error_work);
|
|
+ }
|
|
+}
|
|
+
|
|
+static void dispc_error_worker(struct work_struct *work)
|
|
+{
|
|
+ int i;
|
|
+ u32 errors;
|
|
+ unsigned long flags;
|
|
+
|
|
+ spin_lock_irqsave(&dispc.error_lock, flags);
|
|
+ errors = dispc.error_irqs;
|
|
+ dispc.error_irqs = 0;
|
|
+ spin_unlock_irqrestore(&dispc.error_lock, flags);
|
|
+
|
|
+ if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
|
|
+ DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
|
|
+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
|
|
+ struct omap_overlay *ovl;
|
|
+ ovl = omap_dss_get_overlay(i);
|
|
+
|
|
+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
|
|
+ continue;
|
|
+
|
|
+ if (ovl->id == 0) {
|
|
+ dispc_enable_plane(ovl->id, 0);
|
|
+ dispc_go(ovl->manager->id);
|
|
+ mdelay(50);
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
|
|
+ DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
|
|
+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
|
|
+ struct omap_overlay *ovl;
|
|
+ ovl = omap_dss_get_overlay(i);
|
|
+
|
|
+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
|
|
+ continue;
|
|
+
|
|
+ if (ovl->id == 1) {
|
|
+ dispc_enable_plane(ovl->id, 0);
|
|
+ dispc_go(ovl->manager->id);
|
|
+ mdelay(50);
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
|
|
+ DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
|
|
+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
|
|
+ struct omap_overlay *ovl;
|
|
+ ovl = omap_dss_get_overlay(i);
|
|
+
|
|
+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
|
|
+ continue;
|
|
+
|
|
+ if (ovl->id == 2) {
|
|
+ dispc_enable_plane(ovl->id, 0);
|
|
+ dispc_go(ovl->manager->id);
|
|
+ mdelay(50);
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (errors & DISPC_IRQ_SYNC_LOST) {
|
|
+ DSSERR("SYNC_LOST, disabling LCD\n");
|
|
+ for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
|
|
+ struct omap_overlay_manager *mgr;
|
|
+ mgr = omap_dss_get_overlay_manager(i);
|
|
+
|
|
+ if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
|
|
+ mgr->display->disable(mgr->display);
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
|
|
+ DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
|
|
+ for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
|
|
+ struct omap_overlay_manager *mgr;
|
|
+ mgr = omap_dss_get_overlay_manager(i);
|
|
+
|
|
+ if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
|
|
+ mgr->display->disable(mgr->display);
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (errors & DISPC_IRQ_OCP_ERR) {
|
|
+ DSSERR("OCP_ERR\n");
|
|
+ for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
|
|
+ struct omap_overlay_manager *mgr;
|
|
+ mgr = omap_dss_get_overlay_manager(i);
|
|
+
|
|
+ if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
|
|
+ mgr->display->disable(mgr->display);
|
|
+ }
|
|
+ }
|
|
+
|
|
+ dispc.irq_error_mask |= errors;
|
|
+ omap_dispc_set_irqs();
|
|
+}
|
|
+
|
|
+int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
|
|
+{
|
|
+ void dispc_irq_wait_handler(void *data, u32 mask)
|
|
+ {
|
|
+ complete((struct completion *)data);
|
|
+ }
|
|
+
|
|
+ int r;
|
|
+ DECLARE_COMPLETION_ONSTACK(completion);
|
|
+
|
|
+ r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
|
|
+ irqmask);
|
|
+
|
|
+ if (r)
|
|
+ return r;
|
|
+
|
|
+ timeout = wait_for_completion_timeout(&completion, timeout);
|
|
+
|
|
+ omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
|
|
+
|
|
+ if (timeout == 0)
|
|
+ return -ETIMEDOUT;
|
|
+
|
|
+ if (timeout == -ERESTARTSYS)
|
|
+ return -ERESTARTSYS;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
|
|
+ unsigned long timeout)
|
|
+{
|
|
+ void dispc_irq_wait_handler(void *data, u32 mask)
|
|
+ {
|
|
+ complete((struct completion *)data);
|
|
+ }
|
|
+
|
|
+ int r;
|
|
+ DECLARE_COMPLETION_ONSTACK(completion);
|
|
+
|
|
+ r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
|
|
+ irqmask);
|
|
+
|
|
+ if (r)
|
|
+ return r;
|
|
+
|
|
+ timeout = wait_for_completion_interruptible_timeout(&completion,
|
|
+ timeout);
|
|
+
|
|
+ omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
|
|
+
|
|
+ if (timeout == 0)
|
|
+ return -ETIMEDOUT;
|
|
+
|
|
+ if (timeout == -ERESTARTSYS)
|
|
+ return -ERESTARTSYS;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
|
|
+void dispc_fake_vsync_irq(void)
|
|
+{
|
|
+ u32 irqstatus = DISPC_IRQ_VSYNC;
|
|
+ int i;
|
|
+
|
|
+ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
|
|
+ struct omap_dispc_isr_data *isr_data;
|
|
+ isr_data = &dispc.registered_isr[i];
|
|
+
|
|
+ if (!isr_data->isr)
|
|
+ continue;
|
|
+
|
|
+ if (isr_data->mask & irqstatus)
|
|
+ isr_data->isr(isr_data->arg, irqstatus);
|
|
+ }
|
|
+}
|
|
+#endif
|
|
+
|
|
+static void _omap_dispc_initialize_irq(void)
|
|
+{
|
|
+ memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
|
|
+
|
|
+ dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
|
|
+
|
|
+ /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
|
|
+ * so clear it */
|
|
+ dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
|
|
+
|
|
+ omap_dispc_set_irqs();
|
|
+}
|
|
+
|
|
+static void _omap_dispc_initial_config(void)
|
|
+{
|
|
+ u32 l;
|
|
+
|
|
+ l = dispc_read_reg(DISPC_SYSCONFIG);
|
|
+ l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
|
|
+ l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
|
|
+ l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
|
|
+ l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
|
|
+ dispc_write_reg(DISPC_SYSCONFIG, l);
|
|
+
|
|
+ /* FUNCGATED */
|
|
+ REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
|
|
+
|
|
+ /* L3 firewall setting: enable access to OCM RAM */
|
|
+ if (cpu_is_omap24xx())
|
|
+ __raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
|
|
+
|
|
+ _dispc_setup_color_conv_coef();
|
|
+
|
|
+ dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
|
|
+}
|
|
+
|
|
+int dispc_init(void)
|
|
+{
|
|
+ u32 rev;
|
|
+
|
|
+ spin_lock_init(&dispc.irq_lock);
|
|
+ spin_lock_init(&dispc.error_lock);
|
|
+
|
|
+ INIT_WORK(&dispc.error_work, dispc_error_worker);
|
|
+
|
|
+ dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
|
|
+ if (!dispc.base) {
|
|
+ DSSERR("can't ioremap DISPC\n");
|
|
+ return -ENOMEM;
|
|
+ }
|
|
+
|
|
+ if (cpu_is_omap34xx()) {
|
|
+ dispc.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
|
|
+ if (IS_ERR(dispc.dpll4_m4_ck)) {
|
|
+ DSSERR("Failed to get dpll4_m4_ck\n");
|
|
+ return -ENODEV;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ enable_clocks(1);
|
|
+
|
|
+ _omap_dispc_initial_config();
|
|
+
|
|
+ _omap_dispc_initialize_irq();
|
|
+
|
|
+ dispc_save_context();
|
|
+
|
|
+ rev = dispc_read_reg(DISPC_REVISION);
|
|
+ printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
|
|
+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
|
|
+
|
|
+ enable_clocks(0);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+void dispc_exit(void)
|
|
+{
|
|
+ if (cpu_is_omap34xx())
|
|
+ clk_put(dispc.dpll4_m4_ck);
|
|
+ iounmap(dispc.base);
|
|
+}
|
|
+
|
|
+int dispc_enable_plane(enum omap_plane plane, bool enable)
|
|
+{
|
|
+ DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
|
|
+
|
|
+ enable_clocks(1);
|
|
+ _dispc_enable_plane(plane, enable);
|
|
+ enable_clocks(0);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
|
|
+ u32 paddr, u16 screen_width,
|
|
+ u16 pos_x, u16 pos_y,
|
|
+ u16 width, u16 height,
|
|
+ u16 out_width, u16 out_height,
|
|
+ enum omap_color_mode color_mode,
|
|
+ bool ilace,
|
|
+ u8 rotation, bool mirror)
|
|
+{
|
|
+ int r = 0;
|
|
+
|
|
+ DSSDBG("dispc_setup_plane %d, ch %d, pa %x, sw %d, %d,%d, %dx%d -> "
|
|
+ "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
|
|
+ plane, channel_out, paddr, screen_width, pos_x, pos_y,
|
|
+ width, height,
|
|
+ out_width, out_height,
|
|
+ ilace, color_mode,
|
|
+ rotation, mirror);
|
|
+
|
|
+ enable_clocks(1);
|
|
+
|
|
+ r = _dispc_setup_plane(plane, channel_out,
|
|
+ paddr, screen_width,
|
|
+ pos_x, pos_y,
|
|
+ width, height,
|
|
+ out_width, out_height,
|
|
+ color_mode, ilace,
|
|
+ rotation, mirror);
|
|
+
|
|
+ enable_clocks(0);
|
|
+
|
|
+ return r;
|
|
+}
|
|
+
|
|
+static int dispc_is_intersecting(int x1, int y1, int w1, int h1,
|
|
+ int x2, int y2, int w2, int h2)
|
|
+{
|
|
+ if (x1 >= (x2+w2))
|
|
+ return 0;
|
|
+
|
|
+ if ((x1+w1) <= x2)
|
|
+ return 0;
|
|
+
|
|
+ if (y1 >= (y2+h2))
|
|
+ return 0;
|
|
+
|
|
+ if ((y1+h1) <= y2)
|
|
+ return 0;
|
|
+
|
|
+ return 1;
|
|
+}
|
|
+
|
|
+static int dispc_is_overlay_scaled(struct omap_overlay_info *pi)
|
|
+{
|
|
+ if (pi->width != pi->out_width)
|
|
+ return 1;
|
|
+
|
|
+ if (pi->height != pi->out_height)
|
|
+ return 1;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/* returns the area that needs updating */
|
|
+void dispc_setup_partial_planes(struct omap_display *display,
|
|
+ u16 *xi, u16 *yi, u16 *wi, u16 *hi)
|
|
+{
|
|
+ struct omap_overlay_manager *mgr;
|
|
+ int i;
|
|
+
|
|
+ int x, y, w, h;
|
|
+
|
|
+ x = *xi;
|
|
+ y = *yi;
|
|
+ w = *wi;
|
|
+ h = *hi;
|
|
+
|
|
+ DSSDBG("dispc_setup_partial_planes %d,%d %dx%d\n",
|
|
+ *xi, *yi, *wi, *hi);
|
|
+
|
|
+
|
|
+ mgr = display->manager;
|
|
+
|
|
+ if (!mgr) {
|
|
+ DSSDBG("no manager\n");
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ for (i = 0; i < mgr->num_overlays; i++) {
|
|
+ struct omap_overlay *ovl;
|
|
+ struct omap_overlay_info *pi;
|
|
+ ovl = mgr->overlays[i];
|
|
+
|
|
+ if (ovl->manager != mgr)
|
|
+ continue;
|
|
+
|
|
+ if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
|
|
+ continue;
|
|
+
|
|
+ pi = &ovl->info;
|
|
+
|
|
+ if (!pi->enabled)
|
|
+ continue;
|
|
+ /*
|
|
+ * If the plane is intersecting and scaled, we
|
|
+ * enlarge the update region to accomodate the
|
|
+ * whole area
|
|
+ */
|
|
+
|
|
+ if (dispc_is_intersecting(x, y, w, h,
|
|
+ pi->pos_x, pi->pos_y,
|
|
+ pi->out_width, pi->out_height)) {
|
|
+ if (dispc_is_overlay_scaled(pi)) {
|
|
+
|
|
+ int x1, y1, x2, y2;
|
|
+
|
|
+ if (x > pi->pos_x)
|
|
+ x1 = pi->pos_x;
|
|
+ else
|
|
+ x1 = x;
|
|
+
|
|
+ if (y > pi->pos_y)
|
|
+ y1 = pi->pos_y;
|
|
+ else
|
|
+ y1 = y;
|
|
+
|
|
+ if ((x + w) < (pi->pos_x + pi->out_width))
|
|
+ x2 = pi->pos_x + pi->out_width;
|
|
+ else
|
|
+ x2 = x + w;
|
|
+
|
|
+ if ((y + h) < (pi->pos_y + pi->out_height))
|
|
+ y2 = pi->pos_y + pi->out_height;
|
|
+ else
|
|
+ y2 = y + h;
|
|
+
|
|
+ x = x1;
|
|
+ y = y1;
|
|
+ w = x2 - x1;
|
|
+ h = y2 - y1;
|
|
+
|
|
+ DSSDBG("Update area after enlarge due to "
|
|
+ "scaling %d, %d %dx%d\n",
|
|
+ x, y, w, h);
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
|
+ for (i = 0; i < mgr->num_overlays; i++) {
|
|
+ struct omap_overlay *ovl = mgr->overlays[i];
|
|
+ struct omap_overlay_info *pi = &ovl->info;
|
|
+
|
|
+ int px = pi->pos_x;
|
|
+ int py = pi->pos_y;
|
|
+ int pw = pi->width;
|
|
+ int ph = pi->height;
|
|
+ int pow = pi->out_width;
|
|
+ int poh = pi->out_height;
|
|
+ u32 pa = pi->paddr;
|
|
+ int psw = pi->screen_width;
|
|
+ int bpp;
|
|
+
|
|
+ if (ovl->manager != mgr)
|
|
+ continue;
|
|
+
|
|
+ /*
|
|
+ * If plane is not enabled or the update region
|
|
+ * does not intersect with the plane in question,
|
|
+ * we really disable the plane from hardware
|
|
+ */
|
|
+
|
|
+ if (!pi->enabled ||
|
|
+ !dispc_is_intersecting(x, y, w, h,
|
|
+ px, py, pow, poh)) {
|
|
+ dispc_enable_plane(ovl->id, 0);
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+ switch (pi->color_mode) {
|
|
+ case OMAP_DSS_COLOR_RGB16:
|
|
+ case OMAP_DSS_COLOR_ARGB16:
|
|
+ case OMAP_DSS_COLOR_YUV2:
|
|
+ case OMAP_DSS_COLOR_UYVY:
|
|
+ bpp = 16;
|
|
+ break;
|
|
+
|
|
+ case OMAP_DSS_COLOR_RGB24P:
|
|
+ bpp = 24;
|
|
+ break;
|
|
+
|
|
+ case OMAP_DSS_COLOR_RGB24U:
|
|
+ case OMAP_DSS_COLOR_ARGB32:
|
|
+ case OMAP_DSS_COLOR_RGBA32:
|
|
+ case OMAP_DSS_COLOR_RGBX32:
|
|
+ bpp = 32;
|
|
+ break;
|
|
+
|
|
+ default:
|
|
+ BUG();
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ if (x > pi->pos_x) {
|
|
+ px = 0;
|
|
+ pw -= (x - pi->pos_x);
|
|
+ pa += (x - pi->pos_x) * bpp / 8;
|
|
+ } else {
|
|
+ px = pi->pos_x - x;
|
|
+ }
|
|
+
|
|
+ if (y > pi->pos_y) {
|
|
+ py = 0;
|
|
+ ph -= (y - pi->pos_y);
|
|
+ pa += (y - pi->pos_y) * psw * bpp / 8;
|
|
+ } else {
|
|
+ py = pi->pos_y - y;
|
|
+ }
|
|
+
|
|
+ if (w < (px+pw))
|
|
+ pw -= (px+pw) - (w);
|
|
+
|
|
+ if (h < (py+ph))
|
|
+ ph -= (py+ph) - (h);
|
|
+
|
|
+ /* Can't scale the GFX plane */
|
|
+ if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0 ||
|
|
+ dispc_is_overlay_scaled(pi) == 0) {
|
|
+ pow = pw;
|
|
+ poh = ph;
|
|
+ }
|
|
+
|
|
+ DSSDBG("calc plane %d, %x, sw %d, %d,%d, %dx%d -> %dx%d\n",
|
|
+ ovl->id, pa, psw, px, py, pw, ph, pow, poh);
|
|
+
|
|
+ dispc_setup_plane(ovl->id, mgr->id,
|
|
+ pa, psw,
|
|
+ px, py,
|
|
+ pw, ph,
|
|
+ pow, poh,
|
|
+ pi->color_mode, 0,
|
|
+ pi->rotation, // XXX rotation probably wrong
|
|
+ pi->mirror);
|
|
+
|
|
+ dispc_enable_plane(ovl->id, 1);
|
|
+ }
|
|
+
|
|
+ *xi = x;
|
|
+ *yi = y;
|
|
+ *wi = w;
|
|
+ *hi = h;
|
|
+
|
|
+}
|
|
+
|
|
diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c
|
|
new file mode 100644
|
|
index 0000000..9aaf392
|
|
--- /dev/null
|
|
+++ b/drivers/video/omap2/dss/display.c
|
|
@@ -0,0 +1,693 @@
|
|
+/*
|
|
+ * linux/drivers/video/omap2/dss/display.c
|
|
+ *
|
|
+ * Copyright (C) 2009 Nokia Corporation
|
|
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
|
|
+ *
|
|
+ * Some code and ideas taken from drivers/video/omap/ driver
|
|
+ * by Imre Deak.
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published by
|
|
+ * the Free Software Foundation.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful, but WITHOUT
|
|
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
+ * more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License along with
|
|
+ * this program. If not, see <http://www.gnu.org/licenses/>.
|
|
+ */
|
|
+
|
|
+#define DSS_SUBSYS_NAME "DISPLAY"
|
|
+
|
|
+#include <linux/kernel.h>
|
|
+#include <linux/module.h>
|
|
+#include <linux/jiffies.h>
|
|
+#include <linux/list.h>
|
|
+#include <linux/platform_device.h>
|
|
+
|
|
+#include <mach/display.h>
|
|
+#include "dss.h"
|
|
+
|
|
+static int num_displays;
|
|
+static LIST_HEAD(display_list);
|
|
+
|
|
+static ssize_t display_name_show(struct omap_display *display, char *buf)
|
|
+{
|
|
+ return snprintf(buf, PAGE_SIZE, "%s\n", display->name);
|
|
+}
|
|
+
|
|
+static ssize_t display_enabled_show(struct omap_display *display, char *buf)
|
|
+{
|
|
+ bool enabled = display->state != OMAP_DSS_DISPLAY_DISABLED;
|
|
+
|
|
+ return snprintf(buf, PAGE_SIZE, "%d\n", enabled);
|
|
+}
|
|
+
|
|
+static ssize_t display_enabled_store(struct omap_display *display,
|
|
+ const char *buf, size_t size)
|
|
+{
|
|
+ bool enabled, r;
|
|
+
|
|
+ enabled = simple_strtoul(buf, NULL, 10);
|
|
+
|
|
+ if (enabled != (display->state != OMAP_DSS_DISPLAY_DISABLED)) {
|
|
+ if (enabled) {
|
|
+ r = display->enable(display);
|
|
+ if (r)
|
|
+ return r;
|
|
+ } else {
|
|
+ display->disable(display);
|
|
+ }
|
|
+ }
|
|
+
|
|
+ return size;
|
|
+}
|
|
+
|
|
+static ssize_t display_upd_mode_show(struct omap_display *display, char *buf)
|
|
+{
|
|
+ enum omap_dss_update_mode mode = OMAP_DSS_UPDATE_AUTO;
|
|
+ if (display->get_update_mode)
|
|
+ mode = display->get_update_mode(display);
|
|
+ return snprintf(buf, PAGE_SIZE, "%d\n", mode);
|
|
+}
|
|
+
|
|
+static ssize_t display_upd_mode_store(struct omap_display *display,
|
|
+ const char *buf, size_t size)
|
|
+{
|
|
+ int val, r;
|
|
+ enum omap_dss_update_mode mode;
|
|
+
|
|
+ val = simple_strtoul(buf, NULL, 10);
|
|
+
|
|
+ switch (val) {
|
|
+ case OMAP_DSS_UPDATE_DISABLED:
|
|
+ case OMAP_DSS_UPDATE_AUTO:
|
|
+ case OMAP_DSS_UPDATE_MANUAL:
|
|
+ mode = (enum omap_dss_update_mode)val;
|
|
+ break;
|
|
+ default:
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ if ((r = display->set_update_mode(display, mode)))
|
|
+ return r;
|
|
+
|
|
+ return size;
|
|
+}
|
|
+
|
|
+static ssize_t display_tear_show(struct omap_display *display, char *buf)
|
|
+{
|
|
+ return snprintf(buf, PAGE_SIZE, "%d\n",
|
|
+ display->get_te ? display->get_te(display) : 0);
|
|
+}
|
|
+
|
|
+static ssize_t display_tear_store(struct omap_display *display,
|
|
+ const char *buf, size_t size)
|
|
+{
|
|
+ unsigned long te;
|
|
+ int r;
|
|
+
|
|
+ if (!display->enable_te || !display->get_te)
|
|
+ return -ENOENT;
|
|
+
|
|
+ te = simple_strtoul(buf, NULL, 0);
|
|
+
|
|
+ if ((r = display->enable_te(display, te)))
|
|
+ return r;
|
|
+
|
|
+ return size;
|
|
+}
|
|
+
|
|
+static ssize_t display_timings_show(struct omap_display *display, char *buf)
|
|
+{
|
|
+ struct omap_video_timings t;
|
|
+
|
|
+ if (!display->get_timings)
|
|
+ return -ENOENT;
|
|
+
|
|
+ display->get_timings(display, &t);
|
|
+
|
|
+ return snprintf(buf, PAGE_SIZE, "%u,%u/%u/%u/%u,%u/%u/%u/%u\n",
|
|
+ t.pixel_clock,
|
|
+ t.x_res, t.hfp, t.hbp, t.hsw,
|
|
+ t.y_res, t.vfp, t.vbp, t.vsw);
|
|
+}
|
|
+
|
|
+static ssize_t display_timings_store(struct omap_display *display,
|
|
+ const char *buf, size_t size)
|
|
+{
|
|
+ struct omap_video_timings t;
|
|
+ int r, found;
|
|
+
|
|
+ if (!display->set_timings || !display->check_timings)
|
|
+ return -ENOENT;
|
|
+
|
|
+ found = 0;
|
|
+#ifdef CONFIG_OMAP2_DSS_VENC
|
|
+ if (strncmp("pal", buf, 3) == 0) {
|
|
+ t = omap_dss_pal_timings;
|
|
+ found = 1;
|
|
+ } else if (strncmp("ntsc", buf, 4) == 0) {
|
|
+ t = omap_dss_ntsc_timings;
|
|
+ found = 1;
|
|
+ }
|
|
+#endif
|
|
+ if (!found && sscanf(buf, "%u,%hu/%hu/%hu/%hu,%hu/%hu/%hu/%hu",
|
|
+ &t.pixel_clock,
|
|
+ &t.x_res, &t.hfp, &t.hbp, &t.hsw,
|
|
+ &t.y_res, &t.vfp, &t.vbp, &t.vsw) != 9)
|
|
+ return -EINVAL;
|
|
+
|
|
+ if ((r = display->check_timings(display, &t)))
|
|
+ return r;
|
|
+
|
|
+ display->set_timings(display, &t);
|
|
+
|
|
+ return size;
|
|
+}
|
|
+
|
|
+static ssize_t display_rotate_show(struct omap_display *display, char *buf)
|
|
+{
|
|
+ int rotate;
|
|
+ if (!display->get_rotate)
|
|
+ return -ENOENT;
|
|
+ rotate = display->get_rotate(display);
|
|
+ return snprintf(buf, PAGE_SIZE, "%u\n", rotate);
|
|
+}
|
|
+
|
|
+static ssize_t display_rotate_store(struct omap_display *display,
|
|
+ const char *buf, size_t size)
|
|
+{
|
|
+ unsigned long rot;
|
|
+ int r;
|
|
+
|
|
+ if (!display->set_rotate || !display->get_rotate)
|
|
+ return -ENOENT;
|
|
+
|
|
+ rot = simple_strtoul(buf, NULL, 0);
|
|
+
|
|
+ if ((r = display->set_rotate(display, rot)))
|
|
+ return r;
|
|
+
|
|
+ return size;
|
|
+}
|
|
+
|
|
+static ssize_t display_mirror_show(struct omap_display *display, char *buf)
|
|
+{
|
|
+ int mirror;
|
|
+ if (!display->get_mirror)
|
|
+ return -ENOENT;
|
|
+ mirror = display->get_mirror(display);
|
|
+ return snprintf(buf, PAGE_SIZE, "%u\n", mirror);
|
|
+}
|
|
+
|
|
+static ssize_t display_mirror_store(struct omap_display *display,
|
|
+ const char *buf, size_t size)
|
|
+{
|
|
+ unsigned long mirror;
|
|
+ int r;
|
|
+
|
|
+ if (!display->set_mirror || !display->get_mirror)
|
|
+ return -ENOENT;
|
|
+
|
|
+ mirror = simple_strtoul(buf, NULL, 0);
|
|
+
|
|
+ if ((r = display->set_mirror(display, mirror)))
|
|
+ return r;
|
|
+
|
|
+ return size;
|
|
+}
|
|
+
|
|
+static ssize_t display_panel_name_show(struct omap_display *display, char *buf)
|
|
+{
|
|
+ return snprintf(buf, PAGE_SIZE, "%s\n",
|
|
+ display->panel ? display->panel->name : "");
|
|
+}
|
|
+
|
|
+static ssize_t display_ctrl_name_show(struct omap_display *display, char *buf)
|
|
+{
|
|
+ return snprintf(buf, PAGE_SIZE, "%s\n",
|
|
+ display->ctrl ? display->ctrl->name : "");
|
|
+}
|
|
+
|
|
+struct display_attribute {
|
|
+ struct attribute attr;
|
|
+ ssize_t (*show)(struct omap_display *, char *);
|
|
+ ssize_t (*store)(struct omap_display *, const char *, size_t);
|
|
+};
|
|
+
|
|
+#define DISPLAY_ATTR(_name, _mode, _show, _store) \
|
|
+ struct display_attribute display_attr_##_name = \
|
|
+ __ATTR(_name, _mode, _show, _store)
|
|
+
|
|
+static DISPLAY_ATTR(name, S_IRUGO, display_name_show, NULL);
|
|
+static DISPLAY_ATTR(enabled, S_IRUGO|S_IWUSR,
|
|
+ display_enabled_show, display_enabled_store);
|
|
+static DISPLAY_ATTR(update_mode, S_IRUGO|S_IWUSR,
|
|
+ display_upd_mode_show, display_upd_mode_store);
|
|
+static DISPLAY_ATTR(tear_elim, S_IRUGO|S_IWUSR,
|
|
+ display_tear_show, display_tear_store);
|
|
+static DISPLAY_ATTR(timings, S_IRUGO|S_IWUSR,
|
|
+ display_timings_show, display_timings_store);
|
|
+static DISPLAY_ATTR(rotate, S_IRUGO|S_IWUSR,
|
|
+ display_rotate_show, display_rotate_store);
|
|
+static DISPLAY_ATTR(mirror, S_IRUGO|S_IWUSR,
|
|
+ display_mirror_show, display_mirror_store);
|
|
+static DISPLAY_ATTR(panel_name, S_IRUGO, display_panel_name_show, NULL);
|
|
+static DISPLAY_ATTR(ctrl_name, S_IRUGO, display_ctrl_name_show, NULL);
|
|
+
|
|
+static struct attribute *display_sysfs_attrs[] = {
|
|
+ &display_attr_name.attr,
|
|
+ &display_attr_enabled.attr,
|
|
+ &display_attr_update_mode.attr,
|
|
+ &display_attr_tear_elim.attr,
|
|
+ &display_attr_timings.attr,
|
|
+ &display_attr_rotate.attr,
|
|
+ &display_attr_mirror.attr,
|
|
+ &display_attr_panel_name.attr,
|
|
+ &display_attr_ctrl_name.attr,
|
|
+ NULL
|
|
+};
|
|
+
|
|
+static ssize_t display_attr_show(struct kobject *kobj, struct attribute *attr, char *buf)
|
|
+{
|
|
+ struct omap_display *display;
|
|
+ struct display_attribute *display_attr;
|
|
+
|
|
+ display = container_of(kobj, struct omap_display, kobj);
|
|
+ display_attr = container_of(attr, struct display_attribute, attr);
|
|
+
|
|
+ if (!display_attr->show)
|
|
+ return -ENOENT;
|
|
+
|
|
+ return display_attr->show(display, buf);
|
|
+}
|
|
+
|
|
+static ssize_t display_attr_store(struct kobject *kobj, struct attribute *attr,
|
|
+ const char *buf, size_t size)
|
|
+{
|
|
+ struct omap_display *display;
|
|
+ struct display_attribute *display_attr;
|
|
+
|
|
+ display = container_of(kobj, struct omap_display, kobj);
|
|
+ display_attr = container_of(attr, struct display_attribute, attr);
|
|
+
|
|
+ if (!display_attr->store)
|
|
+ return -ENOENT;
|
|
+
|
|
+ return display_attr->store(display, buf, size);
|
|
+}
|
|
+
|
|
+static struct sysfs_ops display_sysfs_ops = {
|
|
+ .show = display_attr_show,
|
|
+ .store = display_attr_store,
|
|
+};
|
|
+
|
|
+static struct kobj_type display_ktype = {
|
|
+ .sysfs_ops = &display_sysfs_ops,
|
|
+ .default_attrs = display_sysfs_attrs,
|
|
+};
|
|
+
|
|
+static void default_get_resolution(struct omap_display *display,
|
|
+ u16 *xres, u16 *yres)
|
|
+{
|
|
+ *xres = display->panel->timings.x_res;
|
|
+ *yres = display->panel->timings.y_res;
|
|
+}
|
|
+
|
|
+static void default_configure_overlay(struct omap_overlay *ovl)
|
|
+{
|
|
+ unsigned low, high, size;
|
|
+ enum omap_burst_size burst;
|
|
+ enum omap_plane plane = ovl->id;
|
|
+
|
|
+ burst = OMAP_DSS_BURST_16x32;
|
|
+ size = 16 * 32 / 8;
|
|
+
|
|
+ dispc_set_burst_size(plane, burst);
|
|
+
|
|
+ high = dispc_get_plane_fifo_size(plane) - 1;
|
|
+ low = dispc_get_plane_fifo_size(plane) - size;
|
|
+
|
|
+ dispc_setup_plane_fifo(plane, low, high);
|
|
+}
|
|
+
|
|
+static int default_wait_vsync(struct omap_display *display)
|
|
+{
|
|
+ unsigned long timeout = msecs_to_jiffies(500);
|
|
+ u32 irq;
|
|
+
|
|
+ if (display->type == OMAP_DISPLAY_TYPE_VENC)
|
|
+ irq = DISPC_IRQ_EVSYNC_ODD;
|
|
+ else
|
|
+ irq = DISPC_IRQ_VSYNC;
|
|
+
|
|
+ return omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
|
|
+}
|
|
+
|
|
+static int default_get_recommended_bpp(struct omap_display *display)
|
|
+{
|
|
+ if (display->panel->recommended_bpp)
|
|
+ return display->panel->recommended_bpp;
|
|
+
|
|
+ switch (display->type) {
|
|
+ case OMAP_DISPLAY_TYPE_DPI:
|
|
+ if (display->hw_config.u.dpi.data_lines == 24)
|
|
+ return 24;
|
|
+ else
|
|
+ return 16;
|
|
+
|
|
+ case OMAP_DISPLAY_TYPE_DBI:
|
|
+ case OMAP_DISPLAY_TYPE_DSI:
|
|
+ if (display->ctrl->pixel_size == 24)
|
|
+ return 24;
|
|
+ else
|
|
+ return 16;
|
|
+ case OMAP_DISPLAY_TYPE_VENC:
|
|
+ case OMAP_DISPLAY_TYPE_SDI:
|
|
+ return 24;
|
|
+ return 24;
|
|
+ default:
|
|
+ BUG();
|
|
+ }
|
|
+}
|
|
+
|
|
+void dss_init_displays(struct platform_device *pdev)
|
|
+{
|
|
+ struct omap_dss_board_info *pdata = pdev->dev.platform_data;
|
|
+ int i, r;
|
|
+
|
|
+ INIT_LIST_HEAD(&display_list);
|
|
+
|
|
+ num_displays = 0;
|
|
+
|
|
+ for (i = 0; i < pdata->num_displays; ++i) {
|
|
+ struct omap_display *display;
|
|
+
|
|
+ switch (pdata->displays[i]->type) {
|
|
+ case OMAP_DISPLAY_TYPE_DPI:
|
|
+#ifdef CONFIG_OMAP2_DSS_RFBI
|
|
+ case OMAP_DISPLAY_TYPE_DBI:
|
|
+#endif
|
|
+#ifdef CONFIG_OMAP2_DSS_SDI
|
|
+ case OMAP_DISPLAY_TYPE_SDI:
|
|
+#endif
|
|
+#ifdef CONFIG_OMAP2_DSS_DSI
|
|
+ case OMAP_DISPLAY_TYPE_DSI:
|
|
+#endif
|
|
+#ifdef CONFIG_OMAP2_DSS_VENC
|
|
+ case OMAP_DISPLAY_TYPE_VENC:
|
|
+#endif
|
|
+ break;
|
|
+ default:
|
|
+ DSSERR("Support for display '%s' not compiled in.\n",
|
|
+ pdata->displays[i]->name);
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+ display = kzalloc(sizeof(*display), GFP_KERNEL);
|
|
+
|
|
+ /*atomic_set(&display->ref_count, 0);*/
|
|
+ display->ref_count = 0;
|
|
+
|
|
+ display->hw_config = *pdata->displays[i];
|
|
+ display->type = pdata->displays[i]->type;
|
|
+ display->name = pdata->displays[i]->name;
|
|
+
|
|
+ display->get_resolution = default_get_resolution;
|
|
+ display->get_recommended_bpp = default_get_recommended_bpp;
|
|
+ display->configure_overlay = default_configure_overlay;
|
|
+ display->wait_vsync = default_wait_vsync;
|
|
+
|
|
+ switch (display->type) {
|
|
+ case OMAP_DISPLAY_TYPE_DPI:
|
|
+ dpi_init_display(display);
|
|
+ break;
|
|
+#ifdef CONFIG_OMAP2_DSS_RFBI
|
|
+ case OMAP_DISPLAY_TYPE_DBI:
|
|
+ rfbi_init_display(display);
|
|
+ break;
|
|
+#endif
|
|
+#ifdef CONFIG_OMAP2_DSS_VENC
|
|
+ case OMAP_DISPLAY_TYPE_VENC:
|
|
+ venc_init_display(display);
|
|
+ break;
|
|
+#endif
|
|
+#ifdef CONFIG_OMAP2_DSS_SDI
|
|
+ case OMAP_DISPLAY_TYPE_SDI:
|
|
+ sdi_init_display(display);
|
|
+ break;
|
|
+#endif
|
|
+#ifdef CONFIG_OMAP2_DSS_DSI
|
|
+ case OMAP_DISPLAY_TYPE_DSI:
|
|
+ dsi_init_display(display);
|
|
+ break;
|
|
+#endif
|
|
+ default:
|
|
+ BUG();
|
|
+ }
|
|
+
|
|
+ r = kobject_init_and_add(&display->kobj, &display_ktype,
|
|
+ &pdev->dev.kobj, "display%d", num_displays);
|
|
+
|
|
+ if (r) {
|
|
+ DSSERR("failed to create sysfs file\n");
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+ num_displays++;
|
|
+
|
|
+ list_add_tail(&display->list, &display_list);
|
|
+ }
|
|
+}
|
|
+
|
|
+void dss_uninit_displays(struct platform_device *pdev)
|
|
+{
|
|
+ struct omap_display *display;
|
|
+
|
|
+ while (!list_empty(&display_list)) {
|
|
+ display = list_first_entry(&display_list,
|
|
+ struct omap_display, list);
|
|
+ list_del(&display->list);
|
|
+ kobject_del(&display->kobj);
|
|
+ kobject_put(&display->kobj);
|
|
+ kfree(display);
|
|
+ }
|
|
+
|
|
+ num_displays = 0;
|
|
+}
|
|
+
|
|
+int dss_suspend_all_displays(void)
|
|
+{
|
|
+ int r;
|
|
+ struct omap_display *display;
|
|
+
|
|
+ list_for_each_entry(display, &display_list, list) {
|
|
+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE) {
|
|
+ display->activate_after_resume = 0;
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+ if (!display->suspend) {
|
|
+ DSSERR("display '%s' doesn't implement suspend\n",
|
|
+ display->name);
|
|
+ r = -ENOSYS;
|
|
+ goto err;
|
|
+ }
|
|
+
|
|
+ r = display->suspend(display);
|
|
+
|
|
+ if (r)
|
|
+ goto err;
|
|
+
|
|
+ display->activate_after_resume = 1;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+err:
|
|
+ /* resume all displays that were suspended */
|
|
+ dss_resume_all_displays();
|
|
+ return r;
|
|
+}
|
|
+
|
|
+int dss_resume_all_displays(void)
|
|
+{
|
|
+ int r;
|
|
+ struct omap_display *display;
|
|
+
|
|
+ list_for_each_entry(display, &display_list, list) {
|
|
+ if (display->activate_after_resume && display->resume) {
|
|
+ r = display->resume(display);
|
|
+ if (r)
|
|
+ return r;
|
|
+ }
|
|
+
|
|
+ display->activate_after_resume = 0;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+int omap_dss_get_num_displays(void)
|
|
+{
|
|
+ return num_displays;
|
|
+}
|
|
+EXPORT_SYMBOL(omap_dss_get_num_displays);
|
|
+
|
|
+struct omap_display *dss_get_display(int no)
|
|
+{
|
|
+ int i = 0;
|
|
+ struct omap_display *display;
|
|
+
|
|
+ list_for_each_entry(display, &display_list, list) {
|
|
+ if (i++ == no)
|
|
+ return display;
|
|
+ }
|
|
+
|
|
+ return NULL;
|
|
+}
|
|
+
|
|
+struct omap_display *omap_dss_get_display(int no)
|
|
+{
|
|
+ struct omap_display *display;
|
|
+
|
|
+ display = dss_get_display(no);
|
|
+
|
|
+ if (!display)
|
|
+ return NULL;
|
|
+
|
|
+ switch (display->type) {
|
|
+ case OMAP_DISPLAY_TYPE_VENC:
|
|
+ break;
|
|
+
|
|
+ case OMAP_DISPLAY_TYPE_DPI:
|
|
+ case OMAP_DISPLAY_TYPE_SDI:
|
|
+ if (display->panel == NULL)
|
|
+ return NULL;
|
|
+ break;
|
|
+
|
|
+ case OMAP_DISPLAY_TYPE_DBI:
|
|
+ case OMAP_DISPLAY_TYPE_DSI:
|
|
+ if (display->panel == NULL || display->ctrl == NULL)
|
|
+ return NULL;
|
|
+ break;
|
|
+
|
|
+ default:
|
|
+ return NULL;
|
|
+ }
|
|
+
|
|
+ if (display->ctrl) {
|
|
+ if (!try_module_get(display->ctrl->owner))
|
|
+ goto err0;
|
|
+
|
|
+ if (display->ctrl->init)
|
|
+ if (display->ctrl->init(display) != 0)
|
|
+ goto err1;
|
|
+ }
|
|
+
|
|
+ if (display->panel) {
|
|
+ if (!try_module_get(display->panel->owner))
|
|
+ goto err2;
|
|
+
|
|
+ if (display->panel->init)
|
|
+ if (display->panel->init(display) != 0)
|
|
+ goto err3;
|
|
+ }
|
|
+
|
|
+ display->ref_count++;
|
|
+ /*
|
|
+ if (atomic_cmpxchg(&display->ref_count, 0, 1) != 0)
|
|
+ return 0;
|
|
+*/
|
|
+
|
|
+ return display;
|
|
+err3:
|
|
+ if (display->panel)
|
|
+ module_put(display->panel->owner);
|
|
+err2:
|
|
+ if (display->ctrl && display->ctrl->cleanup)
|
|
+ display->ctrl->cleanup(display);
|
|
+err1:
|
|
+ if (display->ctrl)
|
|
+ module_put(display->ctrl->owner);
|
|
+err0:
|
|
+ return NULL;
|
|
+}
|
|
+EXPORT_SYMBOL(omap_dss_get_display);
|
|
+
|
|
+void omap_dss_put_display(struct omap_display *display)
|
|
+{
|
|
+ if (--display->ref_count > 0)
|
|
+ return;
|
|
+/*
|
|
+ if (atomic_cmpxchg(&display->ref_count, 1, 0) != 1)
|
|
+ return;
|
|
+*/
|
|
+ if (display->ctrl) {
|
|
+ if (display->ctrl->cleanup)
|
|
+ display->ctrl->cleanup(display);
|
|
+ module_put(display->ctrl->owner);
|
|
+ }
|
|
+
|
|
+ if (display->panel) {
|
|
+ if (display->panel->cleanup)
|
|
+ display->panel->cleanup(display);
|
|
+ module_put(display->panel->owner);
|
|
+ }
|
|
+}
|
|
+EXPORT_SYMBOL(omap_dss_put_display);
|
|
+
|
|
+void omap_dss_register_ctrl(struct omap_ctrl *ctrl)
|
|
+{
|
|
+ struct omap_display *display;
|
|
+
|
|
+ list_for_each_entry(display, &display_list, list) {
|
|
+ if (display->hw_config.ctrl_name &&
|
|
+ strcmp(display->hw_config.ctrl_name, ctrl->name) == 0) {
|
|
+ display->ctrl = ctrl;
|
|
+ DSSDBG("ctrl '%s' registered\n", ctrl->name);
|
|
+ }
|
|
+ }
|
|
+}
|
|
+EXPORT_SYMBOL(omap_dss_register_ctrl);
|
|
+
|
|
+void omap_dss_register_panel(struct omap_panel *panel)
|
|
+{
|
|
+ struct omap_display *display;
|
|
+
|
|
+ list_for_each_entry(display, &display_list, list) {
|
|
+ if (display->hw_config.panel_name &&
|
|
+ strcmp(display->hw_config.panel_name, panel->name) == 0) {
|
|
+ display->panel = panel;
|
|
+ DSSDBG("panel '%s' registered\n", panel->name);
|
|
+ }
|
|
+ }
|
|
+}
|
|
+EXPORT_SYMBOL(omap_dss_register_panel);
|
|
+
|
|
+void omap_dss_unregister_ctrl(struct omap_ctrl *ctrl)
|
|
+{
|
|
+ struct omap_display *display;
|
|
+
|
|
+ list_for_each_entry(display, &display_list, list) {
|
|
+ if (display->hw_config.ctrl_name &&
|
|
+ strcmp(display->hw_config.ctrl_name, ctrl->name) == 0)
|
|
+ display->ctrl = NULL;
|
|
+ }
|
|
+}
|
|
+EXPORT_SYMBOL(omap_dss_unregister_ctrl);
|
|
+
|
|
+void omap_dss_unregister_panel(struct omap_panel *panel)
|
|
+{
|
|
+ struct omap_display *display;
|
|
+
|
|
+ list_for_each_entry(display, &display_list, list) {
|
|
+ if (display->hw_config.panel_name &&
|
|
+ strcmp(display->hw_config.panel_name, panel->name) == 0)
|
|
+ display->panel = NULL;
|
|
+ }
|
|
+}
|
|
+EXPORT_SYMBOL(omap_dss_unregister_panel);
|
|
diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
|
|
new file mode 100644
|
|
index 0000000..71fffca
|
|
--- /dev/null
|
|
+++ b/drivers/video/omap2/dss/dpi.c
|
|
@@ -0,0 +1,393 @@
|
|
+/*
|
|
+ * linux/drivers/video/omap2/dss/dpi.c
|
|
+ *
|
|
+ * Copyright (C) 2009 Nokia Corporation
|
|
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
|
|
+ *
|
|
+ * Some code and ideas taken from drivers/video/omap/ driver
|
|
+ * by Imre Deak.
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published by
|
|
+ * the Free Software Foundation.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful, but WITHOUT
|
|
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
+ * more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License along with
|
|
+ * this program. If not, see <http://www.gnu.org/licenses/>.
|
|
+ */
|
|
+
|
|
+#include <linux/kernel.h>
|
|
+#include <linux/clk.h>
|
|
+#include <linux/delay.h>
|
|
+#include <linux/errno.h>
|
|
+
|
|
+#include <mach/board.h>
|
|
+#include <mach/display.h>
|
|
+#include <mach/cpu.h>
|
|
+
|
|
+#include "dss.h"
|
|
+
|
|
+static struct {
|
|
+ int update_enabled;
|
|
+} dpi;
|
|
+
|
|
+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
|
|
+static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
|
|
+ unsigned long *fck, int *lck_div, int *pck_div)
|
|
+{
|
|
+ struct dsi_clock_info cinfo;
|
|
+ int r;
|
|
+
|
|
+ r = dsi_pll_calc_pck(is_tft, pck_req, &cinfo);
|
|
+ if (r)
|
|
+ return r;
|
|
+
|
|
+ r = dsi_pll_program(&cinfo);
|
|
+ if (r)
|
|
+ return r;
|
|
+
|
|
+ dss_select_clk_source(0, 1);
|
|
+
|
|
+ dispc_set_lcd_divisor(cinfo.lck_div, cinfo.pck_div);
|
|
+
|
|
+ *fck = cinfo.dsi1_pll_fclk;
|
|
+ *lck_div = cinfo.lck_div;
|
|
+ *pck_div = cinfo.pck_div;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+#else
|
|
+static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req,
|
|
+ unsigned long *fck, int *lck_div, int *pck_div)
|
|
+{
|
|
+ struct dispc_clock_info cinfo;
|
|
+ int r;
|
|
+
|
|
+ r = dispc_calc_clock_div(is_tft, pck_req, &cinfo);
|
|
+ if (r)
|
|
+ return r;
|
|
+
|
|
+ r = dispc_set_clock_div(&cinfo);
|
|
+ if (r)
|
|
+ return r;
|
|
+
|
|
+ *fck = cinfo.fck;
|
|
+ *lck_div = cinfo.lck_div;
|
|
+ *pck_div = cinfo.pck_div;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+#endif
|
|
+
|
|
+static int dpi_set_mode(struct omap_display *display)
|
|
+{
|
|
+ struct omap_panel *panel = display->panel;
|
|
+ int lck_div, pck_div;
|
|
+ unsigned long fck;
|
|
+ unsigned long pck;
|
|
+ bool is_tft;
|
|
+ int r = 0;
|
|
+
|
|
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+
|
|
+ dispc_set_pol_freq(panel);
|
|
+
|
|
+ is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
|
|
+
|
|
+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
|
|
+ r = dpi_set_dsi_clk(is_tft, panel->timings.pixel_clock * 1000,
|
|
+ &fck, &lck_div, &pck_div);
|
|
+#else
|
|
+ r = dpi_set_dispc_clk(is_tft, panel->timings.pixel_clock * 1000,
|
|
+ &fck, &lck_div, &pck_div);
|
|
+#endif
|
|
+ if (r)
|
|
+ goto err0;
|
|
+
|
|
+ pck = fck / lck_div / pck_div / 1000;
|
|
+
|
|
+ if (pck != panel->timings.pixel_clock) {
|
|
+ DSSWARN("Could not find exact pixel clock. "
|
|
+ "Requested %d kHz, got %lu kHz\n",
|
|
+ panel->timings.pixel_clock, pck);
|
|
+
|
|
+ panel->timings.pixel_clock = pck;
|
|
+ }
|
|
+
|
|
+ dispc_set_lcd_timings(&panel->timings);
|
|
+
|
|
+err0:
|
|
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+ return r;
|
|
+}
|
|
+
|
|
+static int dpi_basic_init(struct omap_display *display)
|
|
+{
|
|
+ bool is_tft;
|
|
+
|
|
+ is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
|
|
+
|
|
+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
|
|
+ dispc_set_lcd_display_type(is_tft ? OMAP_DSS_LCD_DISPLAY_TFT :
|
|
+ OMAP_DSS_LCD_DISPLAY_STN);
|
|
+ dispc_set_tft_data_lines(display->hw_config.u.dpi.data_lines);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int dpi_display_enable(struct omap_display *display)
|
|
+{
|
|
+ struct omap_panel *panel = display->panel;
|
|
+ int r;
|
|
+
|
|
+ if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
|
|
+ DSSERR("display already enabled\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+
|
|
+ r = dpi_basic_init(display);
|
|
+ if (r)
|
|
+ goto err0;
|
|
+
|
|
+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
|
|
+ dss_clk_enable(DSS_CLK_FCK2);
|
|
+ r = dsi_pll_init(0, 1);
|
|
+ if (r)
|
|
+ goto err1;
|
|
+#endif
|
|
+ r = dpi_set_mode(display);
|
|
+ if (r)
|
|
+ goto err2;
|
|
+
|
|
+ mdelay(2);
|
|
+
|
|
+ dispc_enable_lcd_out(1);
|
|
+
|
|
+ r = panel->enable(display);
|
|
+ if (r)
|
|
+ goto err3;
|
|
+
|
|
+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
|
|
+
|
|
+ return 0;
|
|
+
|
|
+err3:
|
|
+ dispc_enable_lcd_out(0);
|
|
+err2:
|
|
+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
|
|
+ dsi_pll_uninit();
|
|
+err1:
|
|
+ dss_clk_disable(DSS_CLK_FCK2);
|
|
+#endif
|
|
+err0:
|
|
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+ return r;
|
|
+}
|
|
+
|
|
+static int dpi_display_resume(struct omap_display *display);
|
|
+
|
|
+static void dpi_display_disable(struct omap_display *display)
|
|
+{
|
|
+ if (display->state == OMAP_DSS_DISPLAY_DISABLED)
|
|
+ return;
|
|
+
|
|
+ if (display->state == OMAP_DSS_DISPLAY_SUSPENDED)
|
|
+ dpi_display_resume(display);
|
|
+
|
|
+ display->panel->disable(display);
|
|
+
|
|
+ dispc_enable_lcd_out(0);
|
|
+
|
|
+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
|
|
+ dss_select_clk_source(0, 0);
|
|
+ dsi_pll_uninit();
|
|
+ dss_clk_disable(DSS_CLK_FCK2);
|
|
+#endif
|
|
+
|
|
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+
|
|
+ display->state = OMAP_DSS_DISPLAY_DISABLED;
|
|
+}
|
|
+
|
|
+static int dpi_display_suspend(struct omap_display *display)
|
|
+{
|
|
+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
|
|
+ return -EINVAL;
|
|
+
|
|
+ DSSDBG("dpi_display_suspend\n");
|
|
+
|
|
+ if (display->panel->suspend)
|
|
+ display->panel->suspend(display);
|
|
+
|
|
+ dispc_enable_lcd_out(0);
|
|
+
|
|
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+
|
|
+ display->state = OMAP_DSS_DISPLAY_SUSPENDED;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int dpi_display_resume(struct omap_display *display)
|
|
+{
|
|
+ if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
|
|
+ return -EINVAL;
|
|
+
|
|
+ DSSDBG("dpi_display_resume\n");
|
|
+
|
|
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+
|
|
+ dispc_enable_lcd_out(1);
|
|
+
|
|
+ if (display->panel->resume)
|
|
+ display->panel->resume(display);
|
|
+
|
|
+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void dpi_set_timings(struct omap_display *display,
|
|
+ struct omap_video_timings *timings)
|
|
+{
|
|
+ DSSDBG("dpi_set_timings\n");
|
|
+ display->panel->timings = *timings;
|
|
+ if (display->state == OMAP_DSS_DISPLAY_ACTIVE) {
|
|
+ dpi_set_mode(display);
|
|
+ dispc_go(OMAP_DSS_CHANNEL_LCD);
|
|
+ }
|
|
+}
|
|
+
|
|
+static int dpi_check_timings(struct omap_display *display,
|
|
+ struct omap_video_timings *timings)
|
|
+{
|
|
+ bool is_tft;
|
|
+ int r;
|
|
+ int lck_div, pck_div;
|
|
+ unsigned long fck;
|
|
+ unsigned long pck;
|
|
+
|
|
+ if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
|
|
+ if (timings->hsw < 1 || timings->hsw > 64 ||
|
|
+ timings->hfp < 1 || timings->hfp > 256 ||
|
|
+ timings->hbp < 1 || timings->hbp > 256) {
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ if (timings->vsw < 1 || timings->vsw > 64 ||
|
|
+ timings->vfp > 255 || timings->vbp > 255) {
|
|
+ return -EINVAL;
|
|
+ }
|
|
+ } else {
|
|
+ if (timings->hsw < 1 || timings->hsw > 256 ||
|
|
+ timings->hfp < 1 || timings->hfp > 4096 ||
|
|
+ timings->hbp < 1 || timings->hbp > 4096) {
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ if (timings->vsw < 1 || timings->vsw > 64 ||
|
|
+ timings->vfp > 4095 || timings->vbp > 4095) {
|
|
+ return -EINVAL;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (timings->pixel_clock == 0)
|
|
+ return -EINVAL;
|
|
+
|
|
+ is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
|
|
+
|
|
+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
|
|
+ {
|
|
+ struct dsi_clock_info cinfo;
|
|
+ r = dsi_pll_calc_pck(is_tft, timings->pixel_clock * 1000,
|
|
+ &cinfo);
|
|
+
|
|
+ if (r)
|
|
+ return r;
|
|
+
|
|
+ fck = cinfo.dsi1_pll_fclk;
|
|
+ lck_div = cinfo.lck_div;
|
|
+ pck_div = cinfo.pck_div;
|
|
+ }
|
|
+#else
|
|
+ {
|
|
+ struct dispc_clock_info cinfo;
|
|
+ r = dispc_calc_clock_div(is_tft, timings->pixel_clock * 1000,
|
|
+ &cinfo);
|
|
+
|
|
+ if (r)
|
|
+ return r;
|
|
+
|
|
+ fck = cinfo.fck;
|
|
+ lck_div = cinfo.lck_div;
|
|
+ pck_div = cinfo.pck_div;
|
|
+ }
|
|
+#endif
|
|
+
|
|
+ pck = fck / lck_div / pck_div / 1000;
|
|
+
|
|
+ timings->pixel_clock = pck;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void dpi_get_timings(struct omap_display *display,
|
|
+ struct omap_video_timings *timings)
|
|
+{
|
|
+ *timings = display->panel->timings;
|
|
+}
|
|
+
|
|
+static int dpi_display_set_update_mode(struct omap_display *display,
|
|
+ enum omap_dss_update_mode mode)
|
|
+{
|
|
+ if (mode == OMAP_DSS_UPDATE_MANUAL)
|
|
+ return -EINVAL;
|
|
+
|
|
+ if (mode == OMAP_DSS_UPDATE_DISABLED) {
|
|
+ dispc_enable_lcd_out(0);
|
|
+ dpi.update_enabled = 0;
|
|
+ } else {
|
|
+ dispc_enable_lcd_out(1);
|
|
+ dpi.update_enabled = 1;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static enum omap_dss_update_mode dpi_display_get_update_mode(
|
|
+ struct omap_display *display)
|
|
+{
|
|
+ return dpi.update_enabled ? OMAP_DSS_UPDATE_AUTO :
|
|
+ OMAP_DSS_UPDATE_DISABLED;
|
|
+}
|
|
+
|
|
+void dpi_init_display(struct omap_display *display)
|
|
+{
|
|
+ DSSDBG("DPI init_display\n");
|
|
+
|
|
+ display->enable = dpi_display_enable;
|
|
+ display->disable = dpi_display_disable;
|
|
+ display->suspend = dpi_display_suspend;
|
|
+ display->resume = dpi_display_resume;
|
|
+ display->set_timings = dpi_set_timings;
|
|
+ display->check_timings = dpi_check_timings;
|
|
+ display->get_timings = dpi_get_timings;
|
|
+ display->set_update_mode = dpi_display_set_update_mode;
|
|
+ display->get_update_mode = dpi_display_get_update_mode;
|
|
+}
|
|
+
|
|
+int dpi_init(void)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+void dpi_exit(void)
|
|
+{
|
|
+}
|
|
+
|
|
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
|
|
new file mode 100644
|
|
index 0000000..4442931
|
|
--- /dev/null
|
|
+++ b/drivers/video/omap2/dss/dsi.c
|
|
@@ -0,0 +1,3752 @@
|
|
+/*
|
|
+ * linux/drivers/video/omap2/dss/dsi.c
|
|
+ *
|
|
+ * Copyright (C) 2009 Nokia Corporation
|
|
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published by
|
|
+ * the Free Software Foundation.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful, but WITHOUT
|
|
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
+ * more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License along with
|
|
+ * this program. If not, see <http://www.gnu.org/licenses/>.
|
|
+ */
|
|
+
|
|
+#define DSS_SUBSYS_NAME "DSI"
|
|
+
|
|
+#include <linux/kernel.h>
|
|
+#include <linux/io.h>
|
|
+#include <linux/clk.h>
|
|
+#include <linux/device.h>
|
|
+#include <linux/err.h>
|
|
+#include <linux/interrupt.h>
|
|
+#include <linux/delay.h>
|
|
+#include <linux/workqueue.h>
|
|
+#include <linux/mutex.h>
|
|
+#include <linux/seq_file.h>
|
|
+#include <linux/kfifo.h>
|
|
+
|
|
+#include <mach/board.h>
|
|
+#include <mach/display.h>
|
|
+#include <mach/clock.h>
|
|
+
|
|
+#include "dss.h"
|
|
+
|
|
+/*#define VERBOSE_IRQ*/
|
|
+
|
|
+#define DSI_BASE 0x4804FC00
|
|
+
|
|
+struct dsi_reg { u16 idx; };
|
|
+
|
|
+#define DSI_REG(idx) ((const struct dsi_reg) { idx })
|
|
+
|
|
+#define DSI_SZ_REGS SZ_1K
|
|
+/* DSI Protocol Engine */
|
|
+
|
|
+#define DSI_REVISION DSI_REG(0x0000)
|
|
+#define DSI_SYSCONFIG DSI_REG(0x0010)
|
|
+#define DSI_SYSSTATUS DSI_REG(0x0014)
|
|
+#define DSI_IRQSTATUS DSI_REG(0x0018)
|
|
+#define DSI_IRQENABLE DSI_REG(0x001C)
|
|
+#define DSI_CTRL DSI_REG(0x0040)
|
|
+#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
|
|
+#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
|
|
+#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
|
|
+#define DSI_CLK_CTRL DSI_REG(0x0054)
|
|
+#define DSI_TIMING1 DSI_REG(0x0058)
|
|
+#define DSI_TIMING2 DSI_REG(0x005C)
|
|
+#define DSI_VM_TIMING1 DSI_REG(0x0060)
|
|
+#define DSI_VM_TIMING2 DSI_REG(0x0064)
|
|
+#define DSI_VM_TIMING3 DSI_REG(0x0068)
|
|
+#define DSI_CLK_TIMING DSI_REG(0x006C)
|
|
+#define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
|
|
+#define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
|
|
+#define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
|
|
+#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
|
|
+#define DSI_VM_TIMING4 DSI_REG(0x0080)
|
|
+#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
|
|
+#define DSI_VM_TIMING5 DSI_REG(0x0088)
|
|
+#define DSI_VM_TIMING6 DSI_REG(0x008C)
|
|
+#define DSI_VM_TIMING7 DSI_REG(0x0090)
|
|
+#define DSI_STOPCLK_TIMING DSI_REG(0x0094)
|
|
+#define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
|
|
+#define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
|
|
+#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
|
|
+#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
|
|
+#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
|
|
+#define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
|
|
+#define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
|
|
+
|
|
+/* DSIPHY_SCP */
|
|
+
|
|
+#define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
|
|
+#define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
|
|
+#define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
|
|
+#define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
|
|
+
|
|
+/* DSI_PLL_CTRL_SCP */
|
|
+
|
|
+#define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
|
|
+#define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
|
|
+#define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
|
|
+#define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
|
|
+#define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
|
|
+
|
|
+#define REG_GET(idx, start, end) \
|
|
+ FLD_GET(dsi_read_reg(idx), start, end)
|
|
+
|
|
+#define REG_FLD_MOD(idx, val, start, end) \
|
|
+ dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
|
|
+
|
|
+/* Global interrupts */
|
|
+#define DSI_IRQ_VC0 (1 << 0)
|
|
+#define DSI_IRQ_VC1 (1 << 1)
|
|
+#define DSI_IRQ_VC2 (1 << 2)
|
|
+#define DSI_IRQ_VC3 (1 << 3)
|
|
+#define DSI_IRQ_WAKEUP (1 << 4)
|
|
+#define DSI_IRQ_RESYNC (1 << 5)
|
|
+#define DSI_IRQ_PLL_LOCK (1 << 7)
|
|
+#define DSI_IRQ_PLL_UNLOCK (1 << 8)
|
|
+#define DSI_IRQ_PLL_RECALL (1 << 9)
|
|
+#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
|
|
+#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
|
|
+#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
|
|
+#define DSI_IRQ_TE_TRIGGER (1 << 16)
|
|
+#define DSI_IRQ_ACK_TRIGGER (1 << 17)
|
|
+#define DSI_IRQ_SYNC_LOST (1 << 18)
|
|
+#define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
|
|
+#define DSI_IRQ_TA_TIMEOUT (1 << 20)
|
|
+#define DSI_IRQ_ERROR_MASK \
|
|
+ (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
|
|
+ DSI_IRQ_TA_TIMEOUT)
|
|
+#define DSI_IRQ_CHANNEL_MASK 0xf
|
|
+
|
|
+/* Virtual channel interrupts */
|
|
+#define DSI_VC_IRQ_CS (1 << 0)
|
|
+#define DSI_VC_IRQ_ECC_CORR (1 << 1)
|
|
+#define DSI_VC_IRQ_PACKET_SENT (1 << 2)
|
|
+#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
|
|
+#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
|
|
+#define DSI_VC_IRQ_BTA (1 << 5)
|
|
+#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
|
|
+#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
|
|
+#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
|
|
+#define DSI_VC_IRQ_ERROR_MASK \
|
|
+ (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
|
|
+ DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
|
|
+ DSI_VC_IRQ_FIFO_TX_UDF)
|
|
+
|
|
+/* ComplexIO interrupts */
|
|
+#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
|
|
+#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
|
|
+#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
|
|
+#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
|
|
+#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
|
|
+#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
|
|
+#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
|
|
+#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
|
|
+#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
|
|
+#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
|
|
+#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
|
|
+#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
|
|
+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
|
|
+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
|
|
+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
|
|
+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
|
|
+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
|
|
+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
|
|
+#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
|
|
+#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
|
|
+
|
|
+#define DSI_DT_DCS_SHORT_WRITE_0 0x05
|
|
+#define DSI_DT_DCS_SHORT_WRITE_1 0x15
|
|
+#define DSI_DT_DCS_READ 0x06
|
|
+#define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
|
|
+#define DSI_DT_NULL_PACKET 0x09
|
|
+#define DSI_DT_DCS_LONG_WRITE 0x39
|
|
+
|
|
+#define DSI_DT_RX_ACK_WITH_ERR 0x02
|
|
+#define DSI_DT_RX_DCS_LONG_READ 0x1c
|
|
+#define DSI_DT_RX_SHORT_READ_1 0x21
|
|
+#define DSI_DT_RX_SHORT_READ_2 0x22
|
|
+
|
|
+#define FINT_MAX 2100000
|
|
+#define FINT_MIN 750000
|
|
+#define REGN_MAX (1 << 7)
|
|
+#define REGM_MAX ((1 << 11) - 1)
|
|
+#define REGM3_MAX (1 << 4)
|
|
+#define REGM4_MAX (1 << 4)
|
|
+
|
|
+enum fifo_size {
|
|
+ DSI_FIFO_SIZE_0 = 0,
|
|
+ DSI_FIFO_SIZE_32 = 1,
|
|
+ DSI_FIFO_SIZE_64 = 2,
|
|
+ DSI_FIFO_SIZE_96 = 3,
|
|
+ DSI_FIFO_SIZE_128 = 4,
|
|
+};
|
|
+
|
|
+#define DSI_CMD_FIFO_LEN 16
|
|
+
|
|
+struct dsi_cmd_update {
|
|
+ int bytespp;
|
|
+ u16 x;
|
|
+ u16 y;
|
|
+ u16 w;
|
|
+ u16 h;
|
|
+};
|
|
+
|
|
+struct dsi_cmd_mem_read {
|
|
+ void *buf;
|
|
+ size_t size;
|
|
+ u16 x;
|
|
+ u16 y;
|
|
+ u16 w;
|
|
+ u16 h;
|
|
+ size_t *ret_size;
|
|
+ struct completion *completion;
|
|
+};
|
|
+
|
|
+struct dsi_cmd_test {
|
|
+ int test_num;
|
|
+ int *result;
|
|
+ struct completion *completion;
|
|
+};
|
|
+
|
|
+enum dsi_cmd {
|
|
+ DSI_CMD_UPDATE,
|
|
+ DSI_CMD_AUTOUPDATE,
|
|
+ DSI_CMD_SYNC,
|
|
+ DSI_CMD_MEM_READ,
|
|
+ DSI_CMD_TEST,
|
|
+ DSI_CMD_SET_TE,
|
|
+ DSI_CMD_SET_UPDATE_MODE,
|
|
+ DSI_CMD_SET_ROTATE,
|
|
+ DSI_CMD_SET_MIRROR,
|
|
+};
|
|
+
|
|
+struct dsi_cmd_item {
|
|
+ struct omap_display *display;
|
|
+
|
|
+ enum dsi_cmd cmd;
|
|
+
|
|
+ union {
|
|
+ struct dsi_cmd_update r;
|
|
+ struct completion *sync;
|
|
+ struct dsi_cmd_mem_read mem_read;
|
|
+ struct dsi_cmd_test test;
|
|
+ int te;
|
|
+ enum omap_dss_update_mode update_mode;
|
|
+ int rotate;
|
|
+ int mirror;
|
|
+ } u;
|
|
+};
|
|
+
|
|
+static struct
|
|
+{
|
|
+ void __iomem *base;
|
|
+
|
|
+ unsigned long dsi1_pll_fclk; /* Hz */
|
|
+ unsigned long dsi2_pll_fclk; /* Hz */
|
|
+ unsigned long dsiphy; /* Hz */
|
|
+ unsigned long ddr_clk; /* Hz */
|
|
+
|
|
+ struct {
|
|
+ struct omap_display *display;
|
|
+ enum fifo_size fifo_size;
|
|
+ int dest_per; /* destination peripheral 0-3 */
|
|
+ } vc[4];
|
|
+
|
|
+ struct mutex lock;
|
|
+
|
|
+ unsigned pll_locked;
|
|
+
|
|
+ struct completion bta_completion;
|
|
+
|
|
+ struct work_struct framedone_work;
|
|
+ struct work_struct process_work;
|
|
+ struct workqueue_struct *workqueue;
|
|
+
|
|
+ enum omap_dss_update_mode user_update_mode;
|
|
+ enum omap_dss_update_mode target_update_mode;
|
|
+ enum omap_dss_update_mode update_mode;
|
|
+ int use_te;
|
|
+ int framedone_scheduled; /* helps to catch strange framedone bugs */
|
|
+
|
|
+ unsigned long cache_req_pck;
|
|
+ unsigned long cache_clk_freq;
|
|
+ struct dsi_clock_info cache_cinfo;
|
|
+
|
|
+ struct kfifo *cmd_fifo;
|
|
+ spinlock_t cmd_lock;
|
|
+ struct completion cmd_done;
|
|
+ atomic_t cmd_fifo_full;
|
|
+ atomic_t cmd_pending;
|
|
+
|
|
+ bool autoupdate_setup;
|
|
+
|
|
+#ifdef DEBUG
|
|
+ ktime_t perf_setup_time;
|
|
+ ktime_t perf_start_time;
|
|
+ int perf_measure_frames;
|
|
+
|
|
+ struct {
|
|
+ int x, y, w, h;
|
|
+ int bytespp;
|
|
+ } update_region;
|
|
+
|
|
+#endif
|
|
+ int debug_process;
|
|
+ int debug_read;
|
|
+ int debug_write;
|
|
+} dsi;
|
|
+
|
|
+#ifdef DEBUG
|
|
+static unsigned int dsi_perf;
|
|
+module_param_named(dsi_perf, dsi_perf, bool, 0644);
|
|
+#endif
|
|
+
|
|
+static void dsi_process_cmd_fifo(struct work_struct *work);
|
|
+static void dsi_push_update(struct omap_display *display,
|
|
+ int x, int y, int w, int h);
|
|
+static void dsi_push_autoupdate(struct omap_display *display);
|
|
+
|
|
+static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
|
|
+{
|
|
+ __raw_writel(val, dsi.base + idx.idx);
|
|
+}
|
|
+
|
|
+static inline u32 dsi_read_reg(const struct dsi_reg idx)
|
|
+{
|
|
+ return __raw_readl(dsi.base + idx.idx);
|
|
+}
|
|
+
|
|
+
|
|
+void dsi_save_context(void)
|
|
+{
|
|
+}
|
|
+
|
|
+void dsi_restore_context(void)
|
|
+{
|
|
+}
|
|
+
|
|
+static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
|
|
+ int value)
|
|
+{
|
|
+ int t = 100000;
|
|
+
|
|
+ while (REG_GET(idx, bitnum, bitnum) != value) {
|
|
+ if (--t == 0)
|
|
+ return !value;
|
|
+ }
|
|
+
|
|
+ return value;
|
|
+}
|
|
+
|
|
+#ifdef DEBUG
|
|
+static void perf_mark_setup(void)
|
|
+{
|
|
+ dsi.perf_setup_time = ktime_get();
|
|
+}
|
|
+
|
|
+static void perf_mark_start(void)
|
|
+{
|
|
+ dsi.perf_start_time = ktime_get();
|
|
+}
|
|
+
|
|
+static void perf_show(const char *name)
|
|
+{
|
|
+ ktime_t t, setup_time, trans_time;
|
|
+ u32 total_bytes;
|
|
+ u32 setup_us, trans_us, total_us;
|
|
+ const int numframes = 100;
|
|
+ static u32 s_trans_us, s_min_us = 0xffffffff, s_max_us;
|
|
+
|
|
+ if (!dsi_perf)
|
|
+ return;
|
|
+
|
|
+ if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
|
|
+ return;
|
|
+
|
|
+ t = ktime_get();
|
|
+
|
|
+ setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
|
|
+ setup_us = (u32)ktime_to_us(setup_time);
|
|
+ if (setup_us == 0)
|
|
+ setup_us = 1;
|
|
+
|
|
+ trans_time = ktime_sub(t, dsi.perf_start_time);
|
|
+ trans_us = (u32)ktime_to_us(trans_time);
|
|
+ if (trans_us == 0)
|
|
+ trans_us = 1;
|
|
+
|
|
+ total_us = setup_us + trans_us;
|
|
+
|
|
+ total_bytes = dsi.update_region.w *
|
|
+ dsi.update_region.h *
|
|
+ dsi.update_region.bytespp;
|
|
+
|
|
+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
|
|
+ dsi.perf_measure_frames++;
|
|
+
|
|
+ if (trans_us < s_min_us)
|
|
+ s_min_us = trans_us;
|
|
+
|
|
+ if (trans_us > s_max_us)
|
|
+ s_max_us = trans_us;
|
|
+
|
|
+ s_trans_us += trans_us;
|
|
+
|
|
+ if (dsi.perf_measure_frames < numframes)
|
|
+ return;
|
|
+
|
|
+ DSSINFO("%s update: %d frames in %u us "
|
|
+ "(min/max/avg %u/%u/%u), %u fps\n",
|
|
+ name, numframes,
|
|
+ s_trans_us,
|
|
+ s_min_us,
|
|
+ s_max_us,
|
|
+ s_trans_us / numframes,
|
|
+ 1000*1000 / (s_trans_us / numframes));
|
|
+
|
|
+ dsi.perf_measure_frames = 0;
|
|
+ s_trans_us = 0;
|
|
+ s_min_us = 0xffffffff;
|
|
+ s_max_us = 0;
|
|
+ } else {
|
|
+ DSSINFO("%s update %u us + %u us = %u us (%uHz), %u bytes, "
|
|
+ "%u kbytes/sec\n",
|
|
+ name,
|
|
+ setup_us,
|
|
+ trans_us,
|
|
+ total_us,
|
|
+ 1000*1000 / total_us,
|
|
+ total_bytes,
|
|
+ total_bytes * 1000 / total_us);
|
|
+ }
|
|
+}
|
|
+#else
|
|
+#define perf_mark_setup()
|
|
+#define perf_mark_start()
|
|
+#define perf_show(x)
|
|
+#endif
|
|
+
|
|
+static void print_irq_status(u32 status)
|
|
+{
|
|
+#ifndef VERBOSE_IRQ
|
|
+ if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
|
|
+ return;
|
|
+#endif
|
|
+ printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
|
|
+
|
|
+#define PIS(x) \
|
|
+ if (status & DSI_IRQ_##x) \
|
|
+ printk(#x " ");
|
|
+#ifdef VERBOSE_IRQ
|
|
+ PIS(VC0);
|
|
+ PIS(VC1);
|
|
+ PIS(VC2);
|
|
+ PIS(VC3);
|
|
+#endif
|
|
+ PIS(WAKEUP);
|
|
+ PIS(RESYNC);
|
|
+ PIS(PLL_LOCK);
|
|
+ PIS(PLL_UNLOCK);
|
|
+ PIS(PLL_RECALL);
|
|
+ PIS(COMPLEXIO_ERR);
|
|
+ PIS(HS_TX_TIMEOUT);
|
|
+ PIS(LP_RX_TIMEOUT);
|
|
+ PIS(TE_TRIGGER);
|
|
+ PIS(ACK_TRIGGER);
|
|
+ PIS(SYNC_LOST);
|
|
+ PIS(LDO_POWER_GOOD);
|
|
+ PIS(TA_TIMEOUT);
|
|
+#undef PIS
|
|
+
|
|
+ printk("\n");
|
|
+}
|
|
+
|
|
+static void print_irq_status_vc(int channel, u32 status)
|
|
+{
|
|
+#ifndef VERBOSE_IRQ
|
|
+ if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
|
|
+ return;
|
|
+#endif
|
|
+ printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
|
|
+
|
|
+#define PIS(x) \
|
|
+ if (status & DSI_VC_IRQ_##x) \
|
|
+ printk(#x " ");
|
|
+ PIS(CS);
|
|
+ PIS(ECC_CORR);
|
|
+#ifdef VERBOSE_IRQ
|
|
+ PIS(PACKET_SENT);
|
|
+#endif
|
|
+ PIS(FIFO_TX_OVF);
|
|
+ PIS(FIFO_RX_OVF);
|
|
+ PIS(BTA);
|
|
+ PIS(ECC_NO_CORR);
|
|
+ PIS(FIFO_TX_UDF);
|
|
+ PIS(PP_BUSY_CHANGE);
|
|
+#undef PIS
|
|
+ printk("\n");
|
|
+}
|
|
+
|
|
+static void print_irq_status_cio(u32 status)
|
|
+{
|
|
+ printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
|
|
+
|
|
+#define PIS(x) \
|
|
+ if (status & DSI_CIO_IRQ_##x) \
|
|
+ printk(#x " ");
|
|
+ PIS(ERRSYNCESC1);
|
|
+ PIS(ERRSYNCESC2);
|
|
+ PIS(ERRSYNCESC3);
|
|
+ PIS(ERRESC1);
|
|
+ PIS(ERRESC2);
|
|
+ PIS(ERRESC3);
|
|
+ PIS(ERRCONTROL1);
|
|
+ PIS(ERRCONTROL2);
|
|
+ PIS(ERRCONTROL3);
|
|
+ PIS(STATEULPS1);
|
|
+ PIS(STATEULPS2);
|
|
+ PIS(STATEULPS3);
|
|
+ PIS(ERRCONTENTIONLP0_1);
|
|
+ PIS(ERRCONTENTIONLP1_1);
|
|
+ PIS(ERRCONTENTIONLP0_2);
|
|
+ PIS(ERRCONTENTIONLP1_2);
|
|
+ PIS(ERRCONTENTIONLP0_3);
|
|
+ PIS(ERRCONTENTIONLP1_3);
|
|
+ PIS(ULPSACTIVENOT_ALL0);
|
|
+ PIS(ULPSACTIVENOT_ALL1);
|
|
+#undef PIS
|
|
+
|
|
+ printk("\n");
|
|
+}
|
|
+
|
|
+static int debug_irq;
|
|
+
|
|
+/* called from dss */
|
|
+void dsi_irq_handler(void)
|
|
+{
|
|
+ u32 irqstatus, vcstatus, ciostatus;
|
|
+ int i;
|
|
+
|
|
+ irqstatus = dsi_read_reg(DSI_IRQSTATUS);
|
|
+
|
|
+ if (irqstatus & DSI_IRQ_ERROR_MASK) {
|
|
+ DSSERR("DSI error, irqstatus %x\n", irqstatus);
|
|
+ print_irq_status(irqstatus);
|
|
+ } else if (debug_irq) {
|
|
+ print_irq_status(irqstatus);
|
|
+ }
|
|
+
|
|
+ for (i = 0; i < 4; ++i) {
|
|
+ if ((irqstatus & (1<<i)) == 0)
|
|
+ continue;
|
|
+
|
|
+ vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
|
|
+
|
|
+ if (vcstatus & DSI_VC_IRQ_BTA)
|
|
+ complete(&dsi.bta_completion);
|
|
+
|
|
+ if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
|
|
+ DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
|
|
+ i, vcstatus);
|
|
+ print_irq_status_vc(i, vcstatus);
|
|
+ } else if (debug_irq) {
|
|
+ print_irq_status_vc(i, vcstatus);
|
|
+ }
|
|
+
|
|
+ dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
|
|
+ }
|
|
+
|
|
+ if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
|
|
+ ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
|
|
+
|
|
+ dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
|
|
+
|
|
+ DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
|
|
+ print_irq_status_cio(ciostatus);
|
|
+ }
|
|
+
|
|
+ dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
|
|
+}
|
|
+
|
|
+
|
|
+static void _dsi_initialize_irq(void)
|
|
+{
|
|
+ u32 l;
|
|
+ int i;
|
|
+
|
|
+ /* disable all interrupts */
|
|
+ dsi_write_reg(DSI_IRQENABLE, 0);
|
|
+ for (i = 0; i < 4; ++i)
|
|
+ dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
|
|
+ dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
|
|
+
|
|
+ /* clear interrupt status */
|
|
+ l = dsi_read_reg(DSI_IRQSTATUS);
|
|
+ dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
|
|
+
|
|
+ for (i = 0; i < 4; ++i) {
|
|
+ l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
|
|
+ dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
|
|
+ }
|
|
+
|
|
+ l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
|
|
+ dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
|
|
+
|
|
+ /* enable error irqs */
|
|
+ l = DSI_IRQ_ERROR_MASK;
|
|
+ dsi_write_reg(DSI_IRQENABLE, l);
|
|
+
|
|
+ l = DSI_VC_IRQ_ERROR_MASK;
|
|
+ for (i = 0; i < 4; ++i)
|
|
+ dsi_write_reg(DSI_VC_IRQENABLE(i), l);
|
|
+
|
|
+ /* XXX zonda responds incorrectly, causing control error:
|
|
+ Exit from LP-ESC mode to LP11 uses wrong transition states on the
|
|
+ data lines LP0 and LN0. */
|
|
+ dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
|
|
+ -1 & (~DSI_CIO_IRQ_ERRCONTROL2));
|
|
+}
|
|
+
|
|
+static void dsi_vc_enable_bta_irq(int channel)
|
|
+{
|
|
+ u32 l;
|
|
+
|
|
+ l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
|
|
+ l |= DSI_VC_IRQ_BTA;
|
|
+ dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
|
|
+}
|
|
+
|
|
+static void dsi_vc_disable_bta_irq(int channel)
|
|
+{
|
|
+ u32 l;
|
|
+
|
|
+ l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
|
|
+ l &= ~DSI_VC_IRQ_BTA;
|
|
+ dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
|
|
+}
|
|
+
|
|
+/* DSI func clock. this could also be DSI2_PLL_FCLK */
|
|
+static inline void enable_clocks(bool enable)
|
|
+{
|
|
+ if (enable)
|
|
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+ else
|
|
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+}
|
|
+
|
|
+/* source clock for DSI PLL. this could also be PCLKFREE */
|
|
+static inline void dsi_enable_pll_clock(bool enable)
|
|
+{
|
|
+ if (enable)
|
|
+ dss_clk_enable(DSS_CLK_FCK2);
|
|
+ else
|
|
+ dss_clk_disable(DSS_CLK_FCK2);
|
|
+
|
|
+ if (enable && dsi.pll_locked) {
|
|
+ if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
|
|
+ DSSERR("cannot lock PLL when enabling clocks\n");
|
|
+ }
|
|
+}
|
|
+
|
|
+#ifdef DEBUG
|
|
+static void _dsi_print_reset_status(void)
|
|
+{
|
|
+ u32 l;
|
|
+
|
|
+ if (!dss_debug)
|
|
+ return;
|
|
+
|
|
+ /* A dummy read using the SCP interface to any DSIPHY register is
|
|
+ * required after DSIPHY reset to complete the reset of the DSI complex
|
|
+ * I/O. */
|
|
+ l = dsi_read_reg(DSI_DSIPHY_CFG5);
|
|
+
|
|
+ printk(KERN_DEBUG "DSI resets: ");
|
|
+
|
|
+ l = dsi_read_reg(DSI_PLL_STATUS);
|
|
+ printk("PLL (%d) ", FLD_GET(l, 0, 0));
|
|
+
|
|
+ l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
|
|
+ printk("CIO (%d) ", FLD_GET(l, 29, 29));
|
|
+
|
|
+ l = dsi_read_reg(DSI_DSIPHY_CFG5);
|
|
+ printk("PHY (%x, %d, %d, %d)\n",
|
|
+ FLD_GET(l, 28, 26),
|
|
+ FLD_GET(l, 29, 29),
|
|
+ FLD_GET(l, 30, 30),
|
|
+ FLD_GET(l, 31, 31));
|
|
+}
|
|
+#else
|
|
+#define _dsi_print_reset_status()
|
|
+#endif
|
|
+
|
|
+static inline int dsi_if_enable(bool enable)
|
|
+{
|
|
+ DSSDBG("dsi_if_enable(%d)\n", enable);
|
|
+
|
|
+ enable = enable ? 1 : 0;
|
|
+ REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
|
|
+
|
|
+ if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
|
|
+ DSSERR("Failed to set dsi_if_enable to %d\n", enable);
|
|
+ return -EIO;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static unsigned long dsi_fclk_rate(void)
|
|
+{
|
|
+ unsigned long r;
|
|
+
|
|
+ if (dss_get_dsi_clk_source() == 0) {
|
|
+ /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
|
|
+ r = dss_clk_get_rate(DSS_CLK_FCK1);
|
|
+ } else {
|
|
+ /* DSI FCLK source is DSI2_PLL_FCLK */
|
|
+ r = dsi.dsi2_pll_fclk;
|
|
+ }
|
|
+
|
|
+ return r;
|
|
+}
|
|
+
|
|
+static int dsi_set_lp_clk_divisor(void)
|
|
+{
|
|
+ int n;
|
|
+ unsigned long dsi_fclk;
|
|
+ unsigned long mhz;
|
|
+
|
|
+ /* LP_CLK_DIVISOR, DSI fclk/n, should be 20MHz - 32kHz */
|
|
+
|
|
+ dsi_fclk = dsi_fclk_rate();
|
|
+
|
|
+ for (n = 1; n < (1 << 13) - 1; ++n) {
|
|
+ mhz = dsi_fclk / n;
|
|
+ if (mhz <= 20*1000*1000)
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ if (n == (1 << 13) - 1) {
|
|
+ DSSERR("Failed to find LP_CLK_DIVISOR\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ DSSDBG("LP_CLK_DIV %d, LP_CLK %ld\n", n, mhz);
|
|
+
|
|
+ REG_FLD_MOD(DSI_CLK_CTRL, n, 12, 0); /* LP_CLK_DIVISOR */
|
|
+ if (dsi_fclk > 30*1000*1000)
|
|
+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 21, 21); /* LP_RX_SYNCHRO_ENABLE */
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+
|
|
+enum dsi_pll_power_state {
|
|
+ DSI_PLL_POWER_OFF = 0x0,
|
|
+ DSI_PLL_POWER_ON_HSCLK = 0x1,
|
|
+ DSI_PLL_POWER_ON_ALL = 0x2,
|
|
+ DSI_PLL_POWER_ON_DIV = 0x3,
|
|
+};
|
|
+
|
|
+static int dsi_pll_power(enum dsi_pll_power_state state)
|
|
+{
|
|
+ int t = 0;
|
|
+
|
|
+ REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
|
|
+
|
|
+ /* PLL_PWR_STATUS */
|
|
+ while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
|
|
+ udelay(1);
|
|
+ if (t++ > 1000) {
|
|
+ DSSERR("Failed to set DSI PLL power mode to %d\n",
|
|
+ state);
|
|
+ return -ENODEV;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+int dsi_pll_calc_pck(bool is_tft, unsigned long req_pck,
|
|
+ struct dsi_clock_info *cinfo)
|
|
+{
|
|
+ struct dsi_clock_info cur, best;
|
|
+ int min_fck_per_pck;
|
|
+ int match = 0;
|
|
+
|
|
+ if (req_pck == dsi.cache_req_pck &&
|
|
+ dsi.cache_cinfo.clkin == dss_clk_get_rate(DSS_CLK_FCK2)) {
|
|
+ DSSDBG("DSI clock info found from cache\n");
|
|
+ *cinfo = dsi.cache_cinfo;
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
+ min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
|
|
+
|
|
+ if (min_fck_per_pck &&
|
|
+ req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
|
|
+ DSSERR("Requested pixel clock not possible with the current "
|
|
+ "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
|
|
+ "the constraint off.\n");
|
|
+ min_fck_per_pck = 0;
|
|
+ }
|
|
+
|
|
+ DSSDBG("dsi_pll_calc\n");
|
|
+
|
|
+retry:
|
|
+ memset(&best, 0, sizeof(best));
|
|
+
|
|
+ memset(&cur, 0, sizeof(cur));
|
|
+ cur.clkin = dss_clk_get_rate(DSS_CLK_FCK2);
|
|
+ cur.use_dss2_fck = 1;
|
|
+ cur.highfreq = 0;
|
|
+
|
|
+ /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
|
|
+ /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
|
|
+ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
|
|
+ for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
|
|
+ if (cur.highfreq == 0)
|
|
+ cur.fint = cur.clkin / cur.regn;
|
|
+ else
|
|
+ cur.fint = cur.clkin / (2 * cur.regn);
|
|
+
|
|
+ if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
|
|
+ continue;
|
|
+
|
|
+ /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
|
|
+ for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
|
|
+ unsigned long a, b;
|
|
+
|
|
+ a = 2 * cur.regm * (cur.clkin/1000);
|
|
+ b = cur.regn * (cur.highfreq + 1);
|
|
+ cur.dsiphy = a / b * 1000;
|
|
+
|
|
+ if (cur.dsiphy > 1800 * 1000 * 1000)
|
|
+ break;
|
|
+
|
|
+ /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
|
|
+ for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
|
|
+ ++cur.regm3) {
|
|
+ cur.dsi1_pll_fclk = cur.dsiphy / cur.regm3;
|
|
+
|
|
+ /* this will narrow down the search a bit,
|
|
+ * but still give pixclocks below what was
|
|
+ * requested */
|
|
+ if (cur.dsi1_pll_fclk < req_pck)
|
|
+ break;
|
|
+
|
|
+ if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
|
|
+ continue;
|
|
+
|
|
+ if (min_fck_per_pck &&
|
|
+ cur.dsi1_pll_fclk <
|
|
+ req_pck * min_fck_per_pck)
|
|
+ continue;
|
|
+
|
|
+ match = 1;
|
|
+
|
|
+ find_lck_pck_divs(is_tft, req_pck,
|
|
+ cur.dsi1_pll_fclk,
|
|
+ &cur.lck_div,
|
|
+ &cur.pck_div);
|
|
+
|
|
+ cur.lck = cur.dsi1_pll_fclk / cur.lck_div;
|
|
+ cur.pck = cur.lck / cur.pck_div;
|
|
+
|
|
+ if (abs(cur.pck - req_pck) <
|
|
+ abs(best.pck - req_pck)) {
|
|
+ best = cur;
|
|
+
|
|
+ if (cur.pck == req_pck)
|
|
+ goto found;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+found:
|
|
+ if (!match) {
|
|
+ if (min_fck_per_pck) {
|
|
+ DSSERR("Could not find suitable clock settings.\n"
|
|
+ "Turning FCK/PCK constraint off and"
|
|
+ "trying again.\n");
|
|
+ min_fck_per_pck = 0;
|
|
+ goto retry;
|
|
+ }
|
|
+
|
|
+ DSSERR("Could not find suitable clock settings.\n");
|
|
+
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ /* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */
|
|
+ best.regm4 = best.dsiphy / 48000000;
|
|
+ if (best.regm4 > REGM4_MAX)
|
|
+ best.regm4 = REGM4_MAX;
|
|
+ else if (best.regm4 == 0)
|
|
+ best.regm4 = 1;
|
|
+ best.dsi2_pll_fclk = best.dsiphy / best.regm4;
|
|
+
|
|
+ if (cinfo)
|
|
+ *cinfo = best;
|
|
+
|
|
+ dsi.cache_req_pck = req_pck;
|
|
+ dsi.cache_clk_freq = 0;
|
|
+ dsi.cache_cinfo = best;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int dsi_pll_calc_ddrfreq(unsigned long clk_freq,
|
|
+ struct dsi_clock_info *cinfo)
|
|
+{
|
|
+ struct dsi_clock_info cur, best;
|
|
+ const bool use_dss2_fck = 1;
|
|
+ unsigned long datafreq;
|
|
+
|
|
+ DSSDBG("dsi_pll_calc_ddrfreq\n");
|
|
+
|
|
+ if (clk_freq == dsi.cache_clk_freq &&
|
|
+ dsi.cache_cinfo.clkin == dss_clk_get_rate(DSS_CLK_FCK2)) {
|
|
+ DSSDBG("DSI clock info found from cache\n");
|
|
+ *cinfo = dsi.cache_cinfo;
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
+ datafreq = clk_freq * 4;
|
|
+
|
|
+ memset(&best, 0, sizeof(best));
|
|
+
|
|
+ memset(&cur, 0, sizeof(cur));
|
|
+ cur.use_dss2_fck = use_dss2_fck;
|
|
+ if (use_dss2_fck) {
|
|
+ cur.clkin = dss_clk_get_rate(DSS_CLK_FCK2);
|
|
+ cur.highfreq = 0;
|
|
+ } else {
|
|
+ cur.clkin = dispc_pclk_rate();
|
|
+ if (cur.clkin < 32000000)
|
|
+ cur.highfreq = 0;
|
|
+ else
|
|
+ cur.highfreq = 1;
|
|
+ }
|
|
+
|
|
+ /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
|
|
+ /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
|
|
+ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
|
|
+ for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
|
|
+ if (cur.highfreq == 0)
|
|
+ cur.fint = cur.clkin / cur.regn;
|
|
+ else
|
|
+ cur.fint = cur.clkin / (2 * cur.regn);
|
|
+
|
|
+ if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
|
|
+ continue;
|
|
+
|
|
+ /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
|
|
+ for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
|
|
+ unsigned long a, b;
|
|
+
|
|
+ a = 2 * cur.regm * (cur.clkin/1000);
|
|
+ b = cur.regn * (cur.highfreq + 1);
|
|
+ cur.dsiphy = a / b * 1000;
|
|
+
|
|
+ if (cur.dsiphy > 1800 * 1000 * 1000)
|
|
+ break;
|
|
+
|
|
+ if (abs(cur.dsiphy - datafreq) <
|
|
+ abs(best.dsiphy - datafreq)) {
|
|
+ best = cur;
|
|
+ /* DSSDBG("best %ld\n", best.dsiphy); */
|
|
+ }
|
|
+
|
|
+ if (cur.dsiphy == datafreq)
|
|
+ goto found;
|
|
+ }
|
|
+ }
|
|
+found:
|
|
+ /* DSI1_PLL_FCLK (regm3) is not used. Set it to something sane. */
|
|
+ best.regm3 = best.dsiphy / 48000000;
|
|
+ if (best.regm3 > REGM3_MAX)
|
|
+ best.regm3 = REGM3_MAX;
|
|
+ else if (best.regm3 == 0)
|
|
+ best.regm3 = 1;
|
|
+ best.dsi1_pll_fclk = best.dsiphy / best.regm3;
|
|
+
|
|
+ /* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */
|
|
+ best.regm4 = best.dsiphy / 48000000;
|
|
+ if (best.regm4 > REGM4_MAX)
|
|
+ best.regm4 = REGM4_MAX;
|
|
+ else if (best.regm4 == 0)
|
|
+ best.regm4 = 1;
|
|
+ best.dsi2_pll_fclk = best.dsiphy / best.regm4;
|
|
+
|
|
+ if (cinfo)
|
|
+ *cinfo = best;
|
|
+
|
|
+ dsi.cache_clk_freq = clk_freq;
|
|
+ dsi.cache_req_pck = 0;
|
|
+ dsi.cache_cinfo = best;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+int dsi_pll_program(struct dsi_clock_info *cinfo)
|
|
+{
|
|
+ int r = 0;
|
|
+ u32 l;
|
|
+
|
|
+ DSSDBG("dsi_pll_program\n");
|
|
+
|
|
+ dsi.dsiphy = cinfo->dsiphy;
|
|
+ dsi.ddr_clk = dsi.dsiphy / 4;
|
|
+ dsi.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
|
|
+ dsi.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
|
|
+
|
|
+ DSSDBG("DSI Fint %ld\n", cinfo->fint);
|
|
+
|
|
+ DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
|
|
+ cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
|
|
+ cinfo->clkin,
|
|
+ cinfo->highfreq);
|
|
+
|
|
+ /* DSIPHY == CLKIN4DDR */
|
|
+ DSSDBG("DSIPHY = 2 * %d / %d * %lu / %d = %lu\n",
|
|
+ cinfo->regm,
|
|
+ cinfo->regn,
|
|
+ cinfo->clkin,
|
|
+ cinfo->highfreq + 1,
|
|
+ cinfo->dsiphy);
|
|
+
|
|
+ DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
|
|
+ dsi.dsiphy / 1000 / 1000 / 2);
|
|
+
|
|
+ DSSDBG("Clock lane freq %ld Hz\n", dsi.ddr_clk);
|
|
+
|
|
+ DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
|
|
+ cinfo->regm3, cinfo->dsi1_pll_fclk);
|
|
+ DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
|
|
+ cinfo->regm4, cinfo->dsi2_pll_fclk);
|
|
+
|
|
+ REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
|
|
+
|
|
+ l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
|
|
+ l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
|
|
+ l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
|
|
+ l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
|
|
+ l = FLD_MOD(l, cinfo->regm3 - 1, 22, 19); /* DSI_CLOCK_DIV */
|
|
+ l = FLD_MOD(l, cinfo->regm4 - 1, 26, 23); /* DSIPROTO_CLOCK_DIV */
|
|
+ dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
|
|
+
|
|
+ l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
|
|
+ l = FLD_MOD(l, 7, 4, 1); /* DSI_PLL_FREQSEL */
|
|
+ /* DSI_PLL_CLKSEL */
|
|
+ l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, 11, 11);
|
|
+ l = FLD_MOD(l, cinfo->highfreq, 12, 12); /* DSI_PLL_HIGHFREQ */
|
|
+ l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
|
|
+ l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
|
|
+ l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
|
|
+ dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
|
|
+
|
|
+ REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
|
|
+
|
|
+ if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
|
|
+ DSSERR("dsi pll go bit not going down.\n");
|
|
+ r = -EIO;
|
|
+ goto err;
|
|
+ }
|
|
+
|
|
+ if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
|
|
+ DSSERR("cannot lock PLL\n");
|
|
+ r = -EIO;
|
|
+ goto err;
|
|
+ }
|
|
+
|
|
+ dsi.pll_locked = 1;
|
|
+
|
|
+ l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
|
|
+ l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
|
|
+ l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
|
|
+ l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
|
|
+ l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
|
|
+ l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
|
|
+ l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
|
|
+ l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
|
|
+ l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
|
|
+ l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
|
|
+ l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
|
|
+ l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
|
|
+ l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
|
|
+ l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
|
|
+ l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
|
|
+ dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
|
|
+
|
|
+ DSSDBG("PLL config done\n");
|
|
+err:
|
|
+ return r;
|
|
+}
|
|
+
|
|
+int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
|
|
+{
|
|
+ int r = 0;
|
|
+ enum dsi_pll_power_state pwstate;
|
|
+ struct dispc_clock_info cinfo;
|
|
+
|
|
+ DSSDBG("PLL init\n");
|
|
+
|
|
+ enable_clocks(1);
|
|
+ dsi_enable_pll_clock(1);
|
|
+
|
|
+ /* configure dispc fck and pixel clock to something sane */
|
|
+ r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo);
|
|
+ if (r)
|
|
+ goto err0;
|
|
+
|
|
+ r = dispc_set_clock_div(&cinfo);
|
|
+ if (r) {
|
|
+ DSSERR("Failed to set basic clocks\n");
|
|
+ goto err0;
|
|
+ }
|
|
+
|
|
+ r = dss_dsi_power_up();
|
|
+ if (r)
|
|
+ goto err0;
|
|
+
|
|
+ /* PLL does not come out of reset without this... */
|
|
+ dispc_pck_free_enable(1);
|
|
+
|
|
+ if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
|
|
+ DSSERR("PLL not coming out of reset.\n");
|
|
+ r = -ENODEV;
|
|
+ goto err1;
|
|
+ }
|
|
+
|
|
+ /* ... but if left on, we get problems when planes do not
|
|
+ * fill the whole display. No idea about this XXX */
|
|
+ dispc_pck_free_enable(0);
|
|
+
|
|
+ if (enable_hsclk && enable_hsdiv)
|
|
+ pwstate = DSI_PLL_POWER_ON_ALL;
|
|
+ else if (enable_hsclk)
|
|
+ pwstate = DSI_PLL_POWER_ON_HSCLK;
|
|
+ else if (enable_hsdiv)
|
|
+ pwstate = DSI_PLL_POWER_ON_DIV;
|
|
+ else
|
|
+ pwstate = DSI_PLL_POWER_OFF;
|
|
+
|
|
+ r = dsi_pll_power(pwstate);
|
|
+
|
|
+ if (r)
|
|
+ goto err1;
|
|
+
|
|
+ DSSDBG("PLL init done\n");
|
|
+
|
|
+ return 0;
|
|
+err1:
|
|
+ dss_dsi_power_down();
|
|
+err0:
|
|
+ enable_clocks(0);
|
|
+ dsi_enable_pll_clock(0);
|
|
+ return r;
|
|
+}
|
|
+
|
|
+void dsi_pll_uninit(void)
|
|
+{
|
|
+ enable_clocks(0);
|
|
+ dsi_enable_pll_clock(0);
|
|
+
|
|
+ dsi.pll_locked = 0;
|
|
+ dsi_pll_power(DSI_PLL_POWER_OFF);
|
|
+ dss_dsi_power_down();
|
|
+ DSSDBG("PLL uninit done\n");
|
|
+}
|
|
+
|
|
+unsigned long dsi_get_dsi1_pll_rate(void)
|
|
+{
|
|
+ return dsi.dsi1_pll_fclk;
|
|
+}
|
|
+
|
|
+unsigned long dsi_get_dsi2_pll_rate(void)
|
|
+{
|
|
+ return dsi.dsi2_pll_fclk;
|
|
+}
|
|
+
|
|
+void dsi_dump_clocks(struct seq_file *s)
|
|
+{
|
|
+ int clksel;
|
|
+
|
|
+ enable_clocks(1);
|
|
+
|
|
+ clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
|
|
+
|
|
+ seq_printf(s, "- dsi -\n");
|
|
+
|
|
+ seq_printf(s, "dsi fclk source = %s\n",
|
|
+ dss_get_dsi_clk_source() == 0 ?
|
|
+ "dss1_alwon_fclk" : "dsi2_pll_fclk");
|
|
+
|
|
+ seq_printf(s, "dsi pll source = %s\n",
|
|
+ clksel == 0 ?
|
|
+ "dss2_alwon_fclk" : "pclkfree");
|
|
+
|
|
+ seq_printf(s, "DSIPHY\t\t%lu\nDDR_CLK\t\t%lu\n",
|
|
+ dsi.dsiphy, dsi.ddr_clk);
|
|
+
|
|
+ seq_printf(s, "dsi1_pll_fck\t%lu (%s)\n"
|
|
+ "dsi2_pll_fck\t%lu (%s)\n",
|
|
+ dsi.dsi1_pll_fclk,
|
|
+ dss_get_dispc_clk_source() == 0 ? "off" : "on",
|
|
+ dsi.dsi2_pll_fclk,
|
|
+ dss_get_dsi_clk_source() == 0 ? "off" : "on");
|
|
+
|
|
+ enable_clocks(0);
|
|
+}
|
|
+
|
|
+void dsi_dump_regs(struct seq_file *s)
|
|
+{
|
|
+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
|
|
+
|
|
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+
|
|
+ DUMPREG(DSI_REVISION);
|
|
+ DUMPREG(DSI_SYSCONFIG);
|
|
+ DUMPREG(DSI_SYSSTATUS);
|
|
+ DUMPREG(DSI_IRQSTATUS);
|
|
+ DUMPREG(DSI_IRQENABLE);
|
|
+ DUMPREG(DSI_CTRL);
|
|
+ DUMPREG(DSI_COMPLEXIO_CFG1);
|
|
+ DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
|
|
+ DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
|
|
+ DUMPREG(DSI_CLK_CTRL);
|
|
+ DUMPREG(DSI_TIMING1);
|
|
+ DUMPREG(DSI_TIMING2);
|
|
+ DUMPREG(DSI_VM_TIMING1);
|
|
+ DUMPREG(DSI_VM_TIMING2);
|
|
+ DUMPREG(DSI_VM_TIMING3);
|
|
+ DUMPREG(DSI_CLK_TIMING);
|
|
+ DUMPREG(DSI_TX_FIFO_VC_SIZE);
|
|
+ DUMPREG(DSI_RX_FIFO_VC_SIZE);
|
|
+ DUMPREG(DSI_COMPLEXIO_CFG2);
|
|
+ DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
|
|
+ DUMPREG(DSI_VM_TIMING4);
|
|
+ DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
|
|
+ DUMPREG(DSI_VM_TIMING5);
|
|
+ DUMPREG(DSI_VM_TIMING6);
|
|
+ DUMPREG(DSI_VM_TIMING7);
|
|
+ DUMPREG(DSI_STOPCLK_TIMING);
|
|
+
|
|
+ DUMPREG(DSI_VC_CTRL(0));
|
|
+ DUMPREG(DSI_VC_TE(0));
|
|
+ DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
|
|
+ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
|
|
+ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
|
|
+ DUMPREG(DSI_VC_IRQSTATUS(0));
|
|
+ DUMPREG(DSI_VC_IRQENABLE(0));
|
|
+
|
|
+ DUMPREG(DSI_VC_CTRL(1));
|
|
+ DUMPREG(DSI_VC_TE(1));
|
|
+ DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
|
|
+ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
|
|
+ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
|
|
+ DUMPREG(DSI_VC_IRQSTATUS(1));
|
|
+ DUMPREG(DSI_VC_IRQENABLE(1));
|
|
+
|
|
+ DUMPREG(DSI_VC_CTRL(2));
|
|
+ DUMPREG(DSI_VC_TE(2));
|
|
+ DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
|
|
+ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
|
|
+ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
|
|
+ DUMPREG(DSI_VC_IRQSTATUS(2));
|
|
+ DUMPREG(DSI_VC_IRQENABLE(2));
|
|
+
|
|
+ DUMPREG(DSI_VC_CTRL(3));
|
|
+ DUMPREG(DSI_VC_TE(3));
|
|
+ DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
|
|
+ DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
|
|
+ DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
|
|
+ DUMPREG(DSI_VC_IRQSTATUS(3));
|
|
+ DUMPREG(DSI_VC_IRQENABLE(3));
|
|
+
|
|
+ DUMPREG(DSI_DSIPHY_CFG0);
|
|
+ DUMPREG(DSI_DSIPHY_CFG1);
|
|
+ DUMPREG(DSI_DSIPHY_CFG2);
|
|
+ DUMPREG(DSI_DSIPHY_CFG5);
|
|
+
|
|
+ DUMPREG(DSI_PLL_CONTROL);
|
|
+ DUMPREG(DSI_PLL_STATUS);
|
|
+ DUMPREG(DSI_PLL_GO);
|
|
+ DUMPREG(DSI_PLL_CONFIGURATION1);
|
|
+ DUMPREG(DSI_PLL_CONFIGURATION2);
|
|
+
|
|
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+#undef DUMPREG
|
|
+}
|
|
+
|
|
+enum dsi_complexio_power_state {
|
|
+ DSI_COMPLEXIO_POWER_OFF = 0x0,
|
|
+ DSI_COMPLEXIO_POWER_ON = 0x1,
|
|
+ DSI_COMPLEXIO_POWER_ULPS = 0x2,
|
|
+};
|
|
+
|
|
+static int dsi_complexio_power(enum dsi_complexio_power_state state)
|
|
+{
|
|
+ int t = 0;
|
|
+
|
|
+ /* PWR_CMD */
|
|
+ REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
|
|
+
|
|
+ /* PWR_STATUS */
|
|
+ while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
|
|
+ udelay(1);
|
|
+ if (t++ > 1000) {
|
|
+ DSSERR("failed to set complexio power state to "
|
|
+ "%d\n", state);
|
|
+ return -ENODEV;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void dsi_complexio_config(struct omap_display *display)
|
|
+{
|
|
+ u32 r;
|
|
+
|
|
+ int clk_lane = display->hw_config.u.dsi.clk_lane;
|
|
+ int data1_lane = display->hw_config.u.dsi.data1_lane;
|
|
+ int data2_lane = display->hw_config.u.dsi.data2_lane;
|
|
+ int clk_pol = display->hw_config.u.dsi.clk_pol;
|
|
+ int data1_pol = display->hw_config.u.dsi.data1_pol;
|
|
+ int data2_pol = display->hw_config.u.dsi.data2_pol;
|
|
+
|
|
+ r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
|
|
+ r = FLD_MOD(r, clk_lane, 2, 0);
|
|
+ r = FLD_MOD(r, clk_pol, 3, 3);
|
|
+ r = FLD_MOD(r, data1_lane, 6, 4);
|
|
+ r = FLD_MOD(r, data1_pol, 7, 7);
|
|
+ r = FLD_MOD(r, data2_lane, 10, 8);
|
|
+ r = FLD_MOD(r, data2_pol, 11, 11);
|
|
+ dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
|
|
+
|
|
+ /* The configuration of the DSI complex I/O (number of data lanes,
|
|
+ position, differential order) should not be changed while
|
|
+ DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
|
|
+ the hardware to take into account a new configuration of the complex
|
|
+ I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
|
|
+ follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
|
|
+ then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
|
|
+ DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
|
|
+ DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
|
|
+ DSI complex I/O configuration is unknown. */
|
|
+
|
|
+ /*
|
|
+ REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
|
|
+ REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
|
|
+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
|
|
+ REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
|
|
+ */
|
|
+}
|
|
+
|
|
+static inline unsigned ns2ddr(unsigned ns)
|
|
+{
|
|
+ /* convert time in ns to ddr ticks, rounding up */
|
|
+ return (ns * (dsi.ddr_clk/1000/1000) + 999) / 1000;
|
|
+}
|
|
+
|
|
+static inline unsigned ddr2ns(unsigned ddr)
|
|
+{
|
|
+ return ddr * 1000 * 1000 / (dsi.ddr_clk / 1000);
|
|
+}
|
|
+
|
|
+static void dsi_complexio_timings(void)
|
|
+{
|
|
+ u32 r;
|
|
+ u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
|
|
+ u32 tlpx_half, tclk_trail, tclk_zero;
|
|
+ u32 tclk_prepare;
|
|
+
|
|
+ /* calculate timings */
|
|
+
|
|
+ /* 1 * DDR_CLK = 2 * UI */
|
|
+
|
|
+ /* min 40ns + 4*UI max 85ns + 6*UI */
|
|
+ ths_prepare = ns2ddr(59) + 2;
|
|
+
|
|
+ /* min 145ns + 10*UI */
|
|
+ ths_prepare_ths_zero = ns2ddr(145) + 5;
|
|
+
|
|
+ /* min max(8*UI, 60ns+4*UI) */
|
|
+ ths_trail = max((unsigned)4, ns2ddr(60) + 2);
|
|
+
|
|
+ /* min 100ns */
|
|
+ ths_exit = ns2ddr(100);
|
|
+
|
|
+ /* tlpx min 50n */
|
|
+ tlpx_half = ns2ddr(25);
|
|
+
|
|
+ /* min 60ns */
|
|
+ tclk_trail = ns2ddr(60);
|
|
+
|
|
+ /* min 38ns, max 95ns */
|
|
+ tclk_prepare = ns2ddr(38);
|
|
+
|
|
+ /* min tclk-prepare + tclk-zero = 300ns */
|
|
+ tclk_zero = ns2ddr(300 - 38);
|
|
+
|
|
+ DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
|
|
+ ths_prepare, ddr2ns(ths_prepare),
|
|
+ ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
|
|
+ DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
|
|
+ ths_trail, ddr2ns(ths_trail),
|
|
+ ths_exit, ddr2ns(ths_exit));
|
|
+
|
|
+ DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
|
|
+ "tclk_zero %u (%uns)\n",
|
|
+ tlpx_half, ddr2ns(tlpx_half),
|
|
+ tclk_trail, ddr2ns(tclk_trail),
|
|
+ tclk_zero, ddr2ns(tclk_zero));
|
|
+ DSSDBG("tclk_prepare %u (%uns)\n",
|
|
+ tclk_prepare, ddr2ns(tclk_prepare));
|
|
+
|
|
+ /* program timings */
|
|
+
|
|
+ r = dsi_read_reg(DSI_DSIPHY_CFG0);
|
|
+ r = FLD_MOD(r, ths_prepare, 31, 24);
|
|
+ r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
|
|
+ r = FLD_MOD(r, ths_trail, 15, 8);
|
|
+ r = FLD_MOD(r, ths_exit, 7, 0);
|
|
+ dsi_write_reg(DSI_DSIPHY_CFG0, r);
|
|
+
|
|
+ r = dsi_read_reg(DSI_DSIPHY_CFG1);
|
|
+ r = FLD_MOD(r, tlpx_half, 22, 16);
|
|
+ r = FLD_MOD(r, tclk_trail, 15, 8);
|
|
+ r = FLD_MOD(r, tclk_zero, 7, 0);
|
|
+ dsi_write_reg(DSI_DSIPHY_CFG1, r);
|
|
+
|
|
+ r = dsi_read_reg(DSI_DSIPHY_CFG2);
|
|
+ r = FLD_MOD(r, tclk_prepare, 7, 0);
|
|
+ dsi_write_reg(DSI_DSIPHY_CFG2, r);
|
|
+}
|
|
+
|
|
+
|
|
+static int dsi_complexio_init(struct omap_display *display)
|
|
+{
|
|
+ int r = 0;
|
|
+
|
|
+ DSSDBG("dsi_complexio_init\n");
|
|
+
|
|
+ /* CIO_CLK_ICG, enable L3 clk to CIO */
|
|
+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
|
|
+
|
|
+ /* A dummy read using the SCP interface to any DSIPHY register is
|
|
+ * required after DSIPHY reset to complete the reset of the DSI complex
|
|
+ * I/O. */
|
|
+ dsi_read_reg(DSI_DSIPHY_CFG5);
|
|
+
|
|
+ if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
|
|
+ DSSERR("ComplexIO PHY not coming out of reset.\n");
|
|
+ r = -ENODEV;
|
|
+ goto err;
|
|
+ }
|
|
+
|
|
+ dsi_complexio_config(display);
|
|
+
|
|
+ r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
|
|
+
|
|
+ if (r)
|
|
+ goto err;
|
|
+
|
|
+ if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
|
|
+ DSSERR("ComplexIO not coming out of reset.\n");
|
|
+ r = -ENODEV;
|
|
+ goto err;
|
|
+ }
|
|
+
|
|
+ if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
|
|
+ DSSERR("ComplexIO LDO power down.\n");
|
|
+ r = -ENODEV;
|
|
+ goto err;
|
|
+ }
|
|
+
|
|
+ dsi_complexio_timings();
|
|
+
|
|
+ /*
|
|
+ The configuration of the DSI complex I/O (number of data lanes,
|
|
+ position, differential order) should not be changed while
|
|
+ DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
|
|
+ hardware to recognize a new configuration of the complex I/O (done
|
|
+ in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
|
|
+ this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
|
|
+ reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
|
|
+ LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
|
|
+ bit to 1. If the sequence is not followed, the DSi complex I/O
|
|
+ configuration is undetermined.
|
|
+ */
|
|
+ dsi_if_enable(1);
|
|
+ dsi_if_enable(0);
|
|
+ REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
|
|
+ dsi_if_enable(1);
|
|
+ dsi_if_enable(0);
|
|
+
|
|
+ DSSDBG("CIO init done\n");
|
|
+err:
|
|
+ return r;
|
|
+}
|
|
+
|
|
+static void dsi_complexio_uninit(void)
|
|
+{
|
|
+ dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
|
|
+}
|
|
+
|
|
+static int _dsi_wait_reset(void)
|
|
+{
|
|
+ int i = 0;
|
|
+
|
|
+ while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
|
|
+ if (i++ > 5) {
|
|
+ DSSERR("soft reset failed\n");
|
|
+ return -ENODEV;
|
|
+ }
|
|
+ udelay(1);
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int _dsi_reset(void)
|
|
+{
|
|
+ /* Soft reset */
|
|
+ REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
|
|
+ return _dsi_wait_reset();
|
|
+}
|
|
+
|
|
+
|
|
+static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
|
|
+ enum fifo_size size3, enum fifo_size size4)
|
|
+{
|
|
+ u32 r = 0;
|
|
+ int add = 0;
|
|
+ int i;
|
|
+
|
|
+ dsi.vc[0].fifo_size = size1;
|
|
+ dsi.vc[1].fifo_size = size2;
|
|
+ dsi.vc[2].fifo_size = size3;
|
|
+ dsi.vc[3].fifo_size = size4;
|
|
+
|
|
+ for (i = 0; i < 4; i++) {
|
|
+ u8 v;
|
|
+ int size = dsi.vc[i].fifo_size;
|
|
+
|
|
+ if (add + size > 4) {
|
|
+ DSSERR("Illegal FIFO configuration\n");
|
|
+ BUG();
|
|
+ }
|
|
+
|
|
+ v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
|
|
+ r |= v << (8 * i);
|
|
+ /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
|
|
+ add += size;
|
|
+ }
|
|
+
|
|
+ dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
|
|
+}
|
|
+
|
|
+static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
|
|
+ enum fifo_size size3, enum fifo_size size4)
|
|
+{
|
|
+ u32 r = 0;
|
|
+ int add = 0;
|
|
+ int i;
|
|
+
|
|
+ dsi.vc[0].fifo_size = size1;
|
|
+ dsi.vc[1].fifo_size = size2;
|
|
+ dsi.vc[2].fifo_size = size3;
|
|
+ dsi.vc[3].fifo_size = size4;
|
|
+
|
|
+ for (i = 0; i < 4; i++) {
|
|
+ u8 v;
|
|
+ int size = dsi.vc[i].fifo_size;
|
|
+
|
|
+ if (add + size > 4) {
|
|
+ DSSERR("Illegal FIFO configuration\n");
|
|
+ BUG();
|
|
+ }
|
|
+
|
|
+ v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
|
|
+ r |= v << (8 * i);
|
|
+ /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
|
|
+ add += size;
|
|
+ }
|
|
+
|
|
+ dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
|
|
+}
|
|
+
|
|
+static int dsi_force_tx_stop_mode_io(void)
|
|
+{
|
|
+ u32 r;
|
|
+
|
|
+ r = dsi_read_reg(DSI_TIMING1);
|
|
+ r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
|
|
+ dsi_write_reg(DSI_TIMING1, r);
|
|
+
|
|
+ if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
|
|
+ DSSERR("TX_STOP bit not going down\n");
|
|
+ return -EIO;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void dsi_vc_print_status(int channel)
|
|
+{
|
|
+ u32 r;
|
|
+
|
|
+ r = dsi_read_reg(DSI_VC_CTRL(channel));
|
|
+ DSSDBG("vc %d: TX_FIFO_NOT_EMPTY %d, BTA_EN %d, VC_BUSY %d, "
|
|
+ "TX_FIFO_FULL %d, RX_FIFO_NOT_EMPTY %d, ",
|
|
+ channel,
|
|
+ FLD_GET(r, 5, 5),
|
|
+ FLD_GET(r, 6, 6),
|
|
+ FLD_GET(r, 15, 15),
|
|
+ FLD_GET(r, 16, 16),
|
|
+ FLD_GET(r, 20, 20));
|
|
+
|
|
+ r = dsi_read_reg(DSI_TX_FIFO_VC_EMPTINESS);
|
|
+ DSSDBG("EMPTINESS %d\n", (r >> (8 * channel)) & 0xff);
|
|
+}
|
|
+
|
|
+static void dsi_vc_config(int channel)
|
|
+{
|
|
+ u32 r;
|
|
+
|
|
+ DSSDBG("dsi_vc_config %d\n", channel);
|
|
+
|
|
+ r = dsi_read_reg(DSI_VC_CTRL(channel));
|
|
+
|
|
+ r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
|
|
+ r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
|
|
+ r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
|
|
+ r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
|
|
+ r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
|
|
+ r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
|
|
+ r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
|
|
+
|
|
+ r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
|
|
+ r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
|
|
+
|
|
+ dsi_write_reg(DSI_VC_CTRL(channel), r);
|
|
+}
|
|
+
|
|
+static void dsi_vc_config_vp(int channel)
|
|
+{
|
|
+ u32 r;
|
|
+
|
|
+ DSSDBG("dsi_vc_config_vp\n");
|
|
+
|
|
+ r = dsi_read_reg(DSI_VC_CTRL(channel));
|
|
+
|
|
+ r = FLD_MOD(r, 1, 1, 1); /* SOURCE, 1 = video port */
|
|
+ r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
|
|
+ r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
|
|
+ r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
|
|
+ r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
|
|
+ r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
|
|
+ r = FLD_MOD(r, 1, 9, 9); /* MODE_SPEED, high speed on/off */
|
|
+
|
|
+ r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
|
|
+ r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
|
|
+
|
|
+ dsi_write_reg(DSI_VC_CTRL(channel), r);
|
|
+}
|
|
+
|
|
+
|
|
+static int dsi_vc_enable(int channel, bool enable)
|
|
+{
|
|
+ DSSDBG("dsi_vc_enable channel %d, enable %d\n", channel, enable);
|
|
+
|
|
+ enable = enable ? 1 : 0;
|
|
+
|
|
+ REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
|
|
+
|
|
+ if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
|
|
+ DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
|
|
+ return -EIO;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void dsi_vc_enable_hs(int channel, bool enable)
|
|
+{
|
|
+ DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
|
|
+
|
|
+ dsi_vc_enable(channel, 0);
|
|
+ dsi_if_enable(0);
|
|
+
|
|
+ REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
|
|
+
|
|
+ dsi_vc_enable(channel, 1);
|
|
+ dsi_if_enable(1);
|
|
+
|
|
+ dsi_force_tx_stop_mode_io();
|
|
+}
|
|
+
|
|
+static void dsi_vc_flush_long_data(int channel)
|
|
+{
|
|
+ while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
|
|
+ u32 val;
|
|
+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
|
|
+ DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
|
|
+ (val >> 0) & 0xff,
|
|
+ (val >> 8) & 0xff,
|
|
+ (val >> 16) & 0xff,
|
|
+ (val >> 24) & 0xff);
|
|
+ }
|
|
+}
|
|
+
|
|
+static void dsi_show_rx_ack_with_err(u16 err)
|
|
+{
|
|
+ DSSERR("\tACK with ERROR (%#x):\n", err);
|
|
+ if (err & (1 << 0))
|
|
+ DSSERR("\t\tSoT Error\n");
|
|
+ if (err & (1 << 1))
|
|
+ DSSERR("\t\tSoT Sync Error\n");
|
|
+ if (err & (1 << 2))
|
|
+ DSSERR("\t\tEoT Sync Error\n");
|
|
+ if (err & (1 << 3))
|
|
+ DSSERR("\t\tEscape Mode Entry Command Error\n");
|
|
+ if (err & (1 << 4))
|
|
+ DSSERR("\t\tLP Transmit Sync Error\n");
|
|
+ if (err & (1 << 5))
|
|
+ DSSERR("\t\tHS Receive Timeout Error\n");
|
|
+ if (err & (1 << 6))
|
|
+ DSSERR("\t\tFalse Control Error\n");
|
|
+ if (err & (1 << 7))
|
|
+ DSSERR("\t\t(reserved7)\n");
|
|
+ if (err & (1 << 8))
|
|
+ DSSERR("\t\tECC Error, single-bit (corrected)\n");
|
|
+ if (err & (1 << 9))
|
|
+ DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
|
|
+ if (err & (1 << 10))
|
|
+ DSSERR("\t\tChecksum Error\n");
|
|
+ if (err & (1 << 11))
|
|
+ DSSERR("\t\tData type not recognized\n");
|
|
+ if (err & (1 << 12))
|
|
+ DSSERR("\t\tInvalid VC ID\n");
|
|
+ if (err & (1 << 13))
|
|
+ DSSERR("\t\tInvalid Transmission Length\n");
|
|
+ if (err & (1 << 14))
|
|
+ DSSERR("\t\t(reserved14)\n");
|
|
+ if (err & (1 << 15))
|
|
+ DSSERR("\t\tDSI Protocol Violation\n");
|
|
+}
|
|
+
|
|
+static u16 dsi_vc_flush_receive_data(int channel)
|
|
+{
|
|
+ /* RX_FIFO_NOT_EMPTY */
|
|
+ while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
|
|
+ u32 val;
|
|
+ u8 dt;
|
|
+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
|
|
+ DSSDBG("\trawval %#08x\n", val);
|
|
+ dt = FLD_GET(val, 5, 0);
|
|
+ if (dt == DSI_DT_RX_ACK_WITH_ERR) {
|
|
+ u16 err = FLD_GET(val, 23, 8);
|
|
+ dsi_show_rx_ack_with_err(err);
|
|
+ } else if (dt == DSI_DT_RX_SHORT_READ_1) {
|
|
+ DSSDBG("\tDCS short response, 1 byte: %#x\n",
|
|
+ FLD_GET(val, 23, 8));
|
|
+ } else if (dt == DSI_DT_RX_SHORT_READ_2) {
|
|
+ DSSDBG("\tDCS short response, 2 byte: %#x\n",
|
|
+ FLD_GET(val, 23, 8));
|
|
+ } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
|
|
+ DSSDBG("\tDCS long response, len %d\n",
|
|
+ FLD_GET(val, 23, 8));
|
|
+ dsi_vc_flush_long_data(channel);
|
|
+ } else {
|
|
+ DSSERR("\tunknown datatype 0x%02x\n", dt);
|
|
+ }
|
|
+ }
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int dsi_vc_send_bta(int channel)
|
|
+{
|
|
+ unsigned long tmo;
|
|
+
|
|
+ /*DSSDBG("dsi_vc_send_bta_sync %d\n", channel); */
|
|
+
|
|
+ if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
|
|
+ DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
|
|
+ dsi_vc_flush_receive_data(channel);
|
|
+ }
|
|
+
|
|
+ REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
|
|
+
|
|
+ tmo = jiffies + msecs_to_jiffies(10);
|
|
+ while (REG_GET(DSI_VC_CTRL(channel), 6, 6) == 1) {
|
|
+ if (time_after(jiffies, tmo)) {
|
|
+ DSSERR("Failed to send BTA\n");
|
|
+ return -EIO;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int dsi_vc_send_bta_sync(int channel)
|
|
+{
|
|
+ int r = 0;
|
|
+
|
|
+ init_completion(&dsi.bta_completion);
|
|
+
|
|
+ dsi_vc_enable_bta_irq(channel);
|
|
+
|
|
+ r = dsi_vc_send_bta(channel);
|
|
+ if (r)
|
|
+ goto err;
|
|
+
|
|
+ if (wait_for_completion_timeout(&dsi.bta_completion,
|
|
+ msecs_to_jiffies(500)) == 0) {
|
|
+ DSSERR("Failed to receive BTA\n");
|
|
+ r = -EIO;
|
|
+ goto err;
|
|
+ }
|
|
+err:
|
|
+ dsi_vc_disable_bta_irq(channel);
|
|
+
|
|
+ return r;
|
|
+}
|
|
+
|
|
+static inline void dsi_vc_write_long_header(int channel, u8 data_type,
|
|
+ u16 len, u8 ecc)
|
|
+{
|
|
+ u32 val;
|
|
+ u8 data_id;
|
|
+
|
|
+ /*data_id = data_type | channel << 6; */
|
|
+ data_id = data_type | dsi.vc[channel].dest_per << 6;
|
|
+
|
|
+ val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
|
|
+ FLD_VAL(ecc, 31, 24);
|
|
+
|
|
+ dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
|
|
+}
|
|
+
|
|
+static inline void dsi_vc_write_long_payload(int channel,
|
|
+ u8 b1, u8 b2, u8 b3, u8 b4)
|
|
+{
|
|
+ u32 val;
|
|
+
|
|
+ val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
|
|
+
|
|
+/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
|
|
+ b1, b2, b3, b4, val); */
|
|
+
|
|
+ dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
|
|
+}
|
|
+
|
|
+static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
|
|
+ u8 ecc)
|
|
+{
|
|
+ /*u32 val; */
|
|
+ int i;
|
|
+ u8 *p;
|
|
+ int r = 0;
|
|
+ u8 b1, b2, b3, b4;
|
|
+
|
|
+ if (dsi.debug_write)
|
|
+ DSSDBG("dsi_vc_send_long, %d bytes\n", len);
|
|
+
|
|
+ /* len + header */
|
|
+ if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
|
|
+ DSSERR("unable to send long packet: packet too long.\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ dsi_vc_write_long_header(channel, data_type, len, ecc);
|
|
+
|
|
+ /*dsi_vc_print_status(0); */
|
|
+
|
|
+ p = data;
|
|
+ for (i = 0; i < len >> 2; i++) {
|
|
+ if (dsi.debug_write)
|
|
+ DSSDBG("\tsending full packet %d\n", i);
|
|
+ /*dsi_vc_print_status(0); */
|
|
+
|
|
+ b1 = *p++;
|
|
+ b2 = *p++;
|
|
+ b3 = *p++;
|
|
+ b4 = *p++;
|
|
+
|
|
+ dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
|
|
+ }
|
|
+
|
|
+ i = len % 4;
|
|
+ if (i) {
|
|
+ b1 = 0; b2 = 0; b3 = 0;
|
|
+
|
|
+ if (dsi.debug_write)
|
|
+ DSSDBG("\tsending remainder bytes %d\n", i);
|
|
+
|
|
+ switch (i) {
|
|
+ case 3:
|
|
+ b1 = *p++;
|
|
+ b2 = *p++;
|
|
+ b3 = *p++;
|
|
+ break;
|
|
+ case 2:
|
|
+ b1 = *p++;
|
|
+ b2 = *p++;
|
|
+ break;
|
|
+ case 1:
|
|
+ b1 = *p++;
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
|
|
+ }
|
|
+
|
|
+ return r;
|
|
+}
|
|
+
|
|
+static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
|
|
+{
|
|
+ u32 r;
|
|
+ u8 data_id;
|
|
+
|
|
+ if (dsi.debug_write)
|
|
+ DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
|
|
+ channel,
|
|
+ data_type, data & 0xff, (data >> 8) & 0xff);
|
|
+
|
|
+ if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
|
|
+ DSSERR("ERROR FIFO FULL, aborting transfer\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ data_id = data_type | channel << 6;
|
|
+
|
|
+ r = (data_id << 0) | (data << 8) | (ecc << 24);
|
|
+
|
|
+ dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+int dsi_vc_send_null(int channel)
|
|
+{
|
|
+ u8 nullpkg[] = {0, 0, 0, 0};
|
|
+ return dsi_vc_send_long(0, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
|
|
+}
|
|
+EXPORT_SYMBOL(dsi_vc_send_null);
|
|
+
|
|
+int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
|
|
+{
|
|
+ int r;
|
|
+
|
|
+ BUG_ON(len == 0);
|
|
+
|
|
+ if (len == 1) {
|
|
+ r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
|
|
+ data[0], 0);
|
|
+ } else if (len == 2) {
|
|
+ r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
|
|
+ data[0] | (data[1] << 8), 0);
|
|
+ } else {
|
|
+ /* 0x39 = DCS Long Write */
|
|
+ r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
|
|
+ data, len, 0);
|
|
+ }
|
|
+
|
|
+ return r;
|
|
+}
|
|
+EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
|
|
+
|
|
+int dsi_vc_dcs_write(int channel, u8 *data, int len)
|
|
+{
|
|
+ int r;
|
|
+
|
|
+ r = dsi_vc_dcs_write_nosync(channel, data, len);
|
|
+ if (r)
|
|
+ return r;
|
|
+
|
|
+ /* Some devices need time to process the msg in low power mode.
|
|
+ This also makes the write synchronous, and checks that
|
|
+ the peripheral is still alive */
|
|
+ r = dsi_vc_send_bta_sync(channel);
|
|
+
|
|
+ return r;
|
|
+}
|
|
+EXPORT_SYMBOL(dsi_vc_dcs_write);
|
|
+
|
|
+int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
|
|
+{
|
|
+ u32 val;
|
|
+ u8 dt;
|
|
+ int r;
|
|
+
|
|
+ if (dsi.debug_read)
|
|
+ DSSDBG("dsi_vc_dcs_read\n");
|
|
+
|
|
+ r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
|
|
+ if (r)
|
|
+ return r;
|
|
+
|
|
+ r = dsi_vc_send_bta_sync(channel);
|
|
+ if (r)
|
|
+ return r;
|
|
+
|
|
+ if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) { /* RX_FIFO_NOT_EMPTY */
|
|
+ DSSERR("RX fifo empty when trying to read.\n");
|
|
+ return -EIO;
|
|
+ }
|
|
+
|
|
+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
|
|
+ if (dsi.debug_read)
|
|
+ DSSDBG("\theader: %08x\n", val);
|
|
+ dt = FLD_GET(val, 5, 0);
|
|
+ if (dt == DSI_DT_RX_ACK_WITH_ERR) {
|
|
+ u16 err = FLD_GET(val, 23, 8);
|
|
+ dsi_show_rx_ack_with_err(err);
|
|
+ return -1;
|
|
+
|
|
+ } else if (dt == DSI_DT_RX_SHORT_READ_1) {
|
|
+ u8 data = FLD_GET(val, 15, 8);
|
|
+ if (dsi.debug_read)
|
|
+ DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
|
|
+
|
|
+ if (buflen < 1)
|
|
+ return -1;
|
|
+
|
|
+ buf[0] = data;
|
|
+
|
|
+ return 1;
|
|
+ } else if (dt == DSI_DT_RX_SHORT_READ_2) {
|
|
+ u16 data = FLD_GET(val, 23, 8);
|
|
+ if (dsi.debug_read)
|
|
+ DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
|
|
+
|
|
+ if (buflen < 2)
|
|
+ return -1;
|
|
+
|
|
+ buf[0] = data & 0xff;
|
|
+ buf[1] = (data >> 8) & 0xff;
|
|
+
|
|
+ return 2;
|
|
+ } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
|
|
+ int w;
|
|
+ int len = FLD_GET(val, 23, 8);
|
|
+ if (dsi.debug_read)
|
|
+ DSSDBG("\tDCS long response, len %d\n", len);
|
|
+
|
|
+ if (len > buflen)
|
|
+ return -1;
|
|
+
|
|
+ /* two byte checksum ends the packet, not included in len */
|
|
+ for (w = 0; w < len + 2;) {
|
|
+ int b;
|
|
+ val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
|
|
+ if (dsi.debug_read)
|
|
+ DSSDBG("\t\t%02x %02x %02x %02x\n",
|
|
+ (val >> 0) & 0xff,
|
|
+ (val >> 8) & 0xff,
|
|
+ (val >> 16) & 0xff,
|
|
+ (val >> 24) & 0xff);
|
|
+
|
|
+ for (b = 0; b < 4; ++b) {
|
|
+ if (w < len)
|
|
+ buf[w] = (val >> (b * 8)) & 0xff;
|
|
+ /* we discard the 2 byte checksum */
|
|
+ ++w;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ return len;
|
|
+
|
|
+ } else {
|
|
+ DSSERR("\tunknown datatype 0x%02x\n", dt);
|
|
+ return -1;
|
|
+ }
|
|
+}
|
|
+EXPORT_SYMBOL(dsi_vc_dcs_read);
|
|
+
|
|
+
|
|
+int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
|
|
+{
|
|
+ return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
|
|
+ len, 0);
|
|
+}
|
|
+EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
|
|
+
|
|
+
|
|
+static int dsi_set_lp_rx_timeout(int ns, int x4, int x16)
|
|
+{
|
|
+ u32 r;
|
|
+ unsigned long fck;
|
|
+ int ticks;
|
|
+
|
|
+ /* ticks in DSI_FCK */
|
|
+
|
|
+ fck = dsi_fclk_rate();
|
|
+ ticks = (fck / 1000 / 1000) * ns / 1000;
|
|
+
|
|
+ if (ticks > 0x1fff) {
|
|
+ DSSERR("LP_TX_TO too high\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ r = dsi_read_reg(DSI_TIMING2);
|
|
+ r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
|
|
+ r = FLD_MOD(r, x16, 14, 14); /* LP_RX_TO_X16 */
|
|
+ r = FLD_MOD(r, x4, 13, 13); /* LP_RX_TO_X4 */
|
|
+ r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
|
|
+ dsi_write_reg(DSI_TIMING2, r);
|
|
+
|
|
+ DSSDBG("LP_RX_TO %ld ns (%#x ticks)\n",
|
|
+ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
|
|
+ (fck / 1000 / 1000),
|
|
+ ticks);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int dsi_set_ta_timeout(int ns, int x8, int x16)
|
|
+{
|
|
+ u32 r;
|
|
+ unsigned long fck;
|
|
+ int ticks;
|
|
+
|
|
+ /* ticks in DSI_FCK */
|
|
+
|
|
+ fck = dsi_fclk_rate();
|
|
+ ticks = (fck / 1000 / 1000) * ns / 1000;
|
|
+
|
|
+ if (ticks > 0x1fff) {
|
|
+ DSSERR("TA_TO too high\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ r = dsi_read_reg(DSI_TIMING1);
|
|
+ r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
|
|
+ r = FLD_MOD(r, x16, 30, 30); /* TA_TO_X16 */
|
|
+ r = FLD_MOD(r, x8, 29, 29); /* TA_TO_X8 */
|
|
+ r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
|
|
+ dsi_write_reg(DSI_TIMING1, r);
|
|
+
|
|
+ DSSDBG("TA_TO %ld ns (%#x ticks)\n",
|
|
+ (ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /
|
|
+ (fck / 1000 / 1000),
|
|
+ ticks);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int dsi_set_stop_state_counter(int ns, int x4, int x16)
|
|
+{
|
|
+ u32 r;
|
|
+ unsigned long fck;
|
|
+ int ticks;
|
|
+
|
|
+ /* ticks in DSI_FCK */
|
|
+
|
|
+ fck = dsi_fclk_rate();
|
|
+ ticks = (fck / 1000 / 1000) * ns / 1000;
|
|
+
|
|
+ if (ticks > 0x1fff) {
|
|
+ DSSERR("STOP_STATE_COUNTER_IO too high\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ r = dsi_read_reg(DSI_TIMING1);
|
|
+ r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
|
|
+ r = FLD_MOD(r, x16, 14, 14); /* STOP_STATE_X16_IO */
|
|
+ r = FLD_MOD(r, x4, 13, 13); /* STOP_STATE_X4_IO */
|
|
+ r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
|
|
+ dsi_write_reg(DSI_TIMING1, r);
|
|
+
|
|
+ DSSDBG("STOP_STATE_COUNTER %ld ns (%#x ticks)\n",
|
|
+ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
|
|
+ (fck / 1000 / 1000),
|
|
+ ticks);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int dsi_set_hs_tx_timeout(int ns, int x4, int x16)
|
|
+{
|
|
+ u32 r;
|
|
+ unsigned long fck;
|
|
+ int ticks;
|
|
+
|
|
+ /* ticks in TxByteClkHS */
|
|
+
|
|
+ fck = dsi.ddr_clk / 4;
|
|
+ ticks = (fck / 1000 / 1000) * ns / 1000;
|
|
+
|
|
+ if (ticks > 0x1fff) {
|
|
+ DSSERR("HS_TX_TO too high\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ r = dsi_read_reg(DSI_TIMING2);
|
|
+ r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
|
|
+ r = FLD_MOD(r, x16, 30, 30); /* HS_TX_TO_X16 */
|
|
+ r = FLD_MOD(r, x4, 29, 29); /* HS_TX_TO_X8 (4 really) */
|
|
+ r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
|
|
+ dsi_write_reg(DSI_TIMING2, r);
|
|
+
|
|
+ DSSDBG("HS_TX_TO %ld ns (%#x ticks)\n",
|
|
+ (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
|
|
+ (fck / 1000 / 1000),
|
|
+ ticks);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+static int dsi_proto_config(struct omap_display *display)
|
|
+{
|
|
+ u32 r;
|
|
+ int buswidth = 0;
|
|
+
|
|
+ dsi_config_tx_fifo(DSI_FIFO_SIZE_128,
|
|
+ DSI_FIFO_SIZE_0,
|
|
+ DSI_FIFO_SIZE_0,
|
|
+ DSI_FIFO_SIZE_0);
|
|
+
|
|
+ dsi_config_rx_fifo(DSI_FIFO_SIZE_128,
|
|
+ DSI_FIFO_SIZE_0,
|
|
+ DSI_FIFO_SIZE_0,
|
|
+ DSI_FIFO_SIZE_0);
|
|
+
|
|
+ /* XXX what values for the timeouts? */
|
|
+ dsi_set_stop_state_counter(1000, 0, 0);
|
|
+
|
|
+ dsi_set_ta_timeout(50000, 1, 1);
|
|
+
|
|
+ /* 3000ns * 16 */
|
|
+ dsi_set_lp_rx_timeout(3000, 0, 1);
|
|
+
|
|
+ /* 10000ns * 4 */
|
|
+ dsi_set_hs_tx_timeout(10000, 1, 0);
|
|
+
|
|
+ switch (display->ctrl->pixel_size) {
|
|
+ case 16:
|
|
+ buswidth = 0;
|
|
+ break;
|
|
+ case 18:
|
|
+ buswidth = 1;
|
|
+ break;
|
|
+ case 24:
|
|
+ buswidth = 2;
|
|
+ break;
|
|
+ default:
|
|
+ BUG();
|
|
+ }
|
|
+
|
|
+ r = dsi_read_reg(DSI_CTRL);
|
|
+ r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
|
|
+ r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
|
|
+ r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
|
|
+ /* XXX what should the ratio be */
|
|
+ r = FLD_MOD(r, 0, 4, 4); /* VP_CLK_RATIO, VP_PCLK = VP_CLK/2 */
|
|
+ r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
|
|
+ r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
|
|
+ r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
|
|
+ r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
|
|
+ r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
|
|
+ r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
|
|
+ r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
|
|
+
|
|
+ dsi_write_reg(DSI_CTRL, r);
|
|
+
|
|
+ /* we configure vc0 for L4 communication, and
|
|
+ * vc1 for dispc */
|
|
+ dsi_vc_config(0);
|
|
+ dsi_vc_config_vp(1);
|
|
+
|
|
+ /* set all vc targets to peripheral 0 */
|
|
+ dsi.vc[0].dest_per = 0;
|
|
+ dsi.vc[1].dest_per = 0;
|
|
+ dsi.vc[2].dest_per = 0;
|
|
+ dsi.vc[3].dest_per = 0;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void dsi_proto_timings(void)
|
|
+{
|
|
+ int tlpx_half, tclk_zero, tclk_prepare, tclk_trail;
|
|
+ int tclk_pre, tclk_post;
|
|
+ int ddr_clk_pre, ddr_clk_post;
|
|
+ u32 r;
|
|
+
|
|
+ r = dsi_read_reg(DSI_DSIPHY_CFG1);
|
|
+ tlpx_half = FLD_GET(r, 22, 16);
|
|
+ tclk_trail = FLD_GET(r, 15, 8);
|
|
+ tclk_zero = FLD_GET(r, 7, 0);
|
|
+
|
|
+ r = dsi_read_reg(DSI_DSIPHY_CFG2);
|
|
+ tclk_prepare = FLD_GET(r, 7, 0);
|
|
+
|
|
+ /* min 8*UI */
|
|
+ tclk_pre = 20;
|
|
+ /* min 60ns + 52*UI */
|
|
+ tclk_post = ns2ddr(60) + 26;
|
|
+
|
|
+ ddr_clk_pre = (tclk_pre + tlpx_half*2 + tclk_zero + tclk_prepare) / 4;
|
|
+ ddr_clk_post = (tclk_post + tclk_trail) / 4;
|
|
+
|
|
+ r = dsi_read_reg(DSI_CLK_TIMING);
|
|
+ r = FLD_MOD(r, ddr_clk_pre, 15, 8);
|
|
+ r = FLD_MOD(r, ddr_clk_post, 7, 0);
|
|
+ dsi_write_reg(DSI_CLK_TIMING, r);
|
|
+
|
|
+ DSSDBG("ddr_clk_pre %d, ddr_clk_post %d\n",
|
|
+ ddr_clk_pre,
|
|
+ ddr_clk_post);
|
|
+}
|
|
+
|
|
+
|
|
+#define DSI_DECL_VARS \
|
|
+ int __dsi_cb = 0; u32 __dsi_cv = 0;
|
|
+
|
|
+#define DSI_FLUSH(ch) \
|
|
+ if (__dsi_cb > 0) { \
|
|
+ /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
|
|
+ dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
|
|
+ __dsi_cb = __dsi_cv = 0; \
|
|
+ }
|
|
+
|
|
+#define DSI_PUSH(ch, data) \
|
|
+ do { \
|
|
+ __dsi_cv |= (data) << (__dsi_cb * 8); \
|
|
+ /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
|
|
+ if (++__dsi_cb > 3) \
|
|
+ DSI_FLUSH(ch); \
|
|
+ } while (0)
|
|
+
|
|
+static int dsi_update_screen_l4(struct omap_display *display,
|
|
+ int x, int y, int w, int h)
|
|
+{
|
|
+ /* Note: supports only 24bit colors in 32bit container */
|
|
+ int first = 1;
|
|
+ int fifo_stalls = 0;
|
|
+ int max_dsi_packet_size;
|
|
+ int max_data_per_packet;
|
|
+ int max_pixels_per_packet;
|
|
+ int pixels_left;
|
|
+ int bytespp = 3;
|
|
+ int scr_width;
|
|
+ u32 __iomem *data;
|
|
+ int start_offset;
|
|
+ int horiz_inc;
|
|
+ int current_x;
|
|
+ struct omap_overlay *ovl;
|
|
+
|
|
+ debug_irq = 0;
|
|
+
|
|
+ DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
|
|
+ x, y, w, h);
|
|
+
|
|
+ ovl = display->manager->overlays[0];
|
|
+
|
|
+ if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
|
|
+ return -EINVAL;
|
|
+
|
|
+ if (display->ctrl->pixel_size != 24)
|
|
+ return -EINVAL;
|
|
+
|
|
+ scr_width = ovl->info.screen_width;
|
|
+ data = ovl->info.vaddr;
|
|
+
|
|
+ start_offset = scr_width * y + x;
|
|
+ horiz_inc = scr_width - w;
|
|
+ current_x = x;
|
|
+
|
|
+ /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
|
|
+ * in fifo */
|
|
+
|
|
+ /* When using CPU, max long packet size is TX buffer size */
|
|
+ max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
|
|
+
|
|
+ /* we seem to get better perf if we divide the tx fifo to half,
|
|
+ and while the other half is being sent, we fill the other half
|
|
+ max_dsi_packet_size /= 2; */
|
|
+
|
|
+ max_data_per_packet = max_dsi_packet_size - 4 - 1;
|
|
+
|
|
+ max_pixels_per_packet = max_data_per_packet / bytespp;
|
|
+
|
|
+ DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
|
|
+
|
|
+ display->ctrl->setup_update(display, x, y, w, h);
|
|
+
|
|
+ pixels_left = w * h;
|
|
+
|
|
+ DSSDBG("total pixels %d\n", pixels_left);
|
|
+
|
|
+ data += start_offset;
|
|
+
|
|
+#ifdef DEBUG
|
|
+ dsi.update_region.x = x;
|
|
+ dsi.update_region.y = y;
|
|
+ dsi.update_region.w = w;
|
|
+ dsi.update_region.h = h;
|
|
+ dsi.update_region.bytespp = bytespp;
|
|
+#endif
|
|
+
|
|
+ perf_mark_start();
|
|
+
|
|
+ while (pixels_left > 0) {
|
|
+ /* 0x2c = write_memory_start */
|
|
+ /* 0x3c = write_memory_continue */
|
|
+ u8 dcs_cmd = first ? 0x2c : 0x3c;
|
|
+ int pixels;
|
|
+ DSI_DECL_VARS;
|
|
+ first = 0;
|
|
+
|
|
+#if 1
|
|
+ /* using fifo not empty */
|
|
+ /* TX_FIFO_NOT_EMPTY */
|
|
+ while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
|
|
+ udelay(1);
|
|
+ fifo_stalls++;
|
|
+ if (fifo_stalls > 0xfffff) {
|
|
+ DSSERR("fifo stalls overflow, pixels left %d\n",
|
|
+ pixels_left);
|
|
+ dsi_if_enable(0);
|
|
+ return -EIO;
|
|
+ }
|
|
+ }
|
|
+#elif 1
|
|
+ /* using fifo emptiness */
|
|
+ while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
|
|
+ max_dsi_packet_size) {
|
|
+ fifo_stalls++;
|
|
+ if (fifo_stalls > 0xfffff) {
|
|
+ DSSERR("fifo stalls overflow, pixels left %d\n",
|
|
+ pixels_left);
|
|
+ dsi_if_enable(0);
|
|
+ return -EIO;
|
|
+ }
|
|
+ }
|
|
+#else
|
|
+ while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
|
|
+ fifo_stalls++;
|
|
+ if (fifo_stalls > 0xfffff) {
|
|
+ DSSERR("fifo stalls overflow, pixels left %d\n",
|
|
+ pixels_left);
|
|
+ dsi_if_enable(0);
|
|
+ return -EIO;
|
|
+ }
|
|
+ }
|
|
+#endif
|
|
+ pixels = min(max_pixels_per_packet, pixels_left);
|
|
+
|
|
+ pixels_left -= pixels;
|
|
+
|
|
+ dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
|
|
+ 1 + pixels * bytespp, 0);
|
|
+
|
|
+ DSI_PUSH(0, dcs_cmd);
|
|
+
|
|
+ while (pixels-- > 0) {
|
|
+ u32 pix = __raw_readl(data++);
|
|
+
|
|
+ DSI_PUSH(0, (pix >> 16) & 0xff);
|
|
+ DSI_PUSH(0, (pix >> 8) & 0xff);
|
|
+ DSI_PUSH(0, (pix >> 0) & 0xff);
|
|
+
|
|
+ current_x++;
|
|
+ if (current_x == x+w) {
|
|
+ current_x = x;
|
|
+ data += horiz_inc;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ DSI_FLUSH(0);
|
|
+ }
|
|
+
|
|
+ perf_show("L4");
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+#if 0
|
|
+static void dsi_clear_screen_l4(struct omap_display *display,
|
|
+ int x, int y, int w, int h)
|
|
+{
|
|
+ int first = 1;
|
|
+ int fifo_stalls = 0;
|
|
+ int max_dsi_packet_size;
|
|
+ int max_data_per_packet;
|
|
+ int max_pixels_per_packet;
|
|
+ int pixels_left;
|
|
+ int bytespp = 3;
|
|
+ int pixnum;
|
|
+
|
|
+ debug_irq = 0;
|
|
+
|
|
+ DSSDBG("dsi_clear_screen_l4 (%d,%d %dx%d)\n",
|
|
+ x, y, w, h);
|
|
+
|
|
+ if (display->ctrl->bpp != 24)
|
|
+ return -EINVAL;
|
|
+
|
|
+ /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp)
|
|
+ * bytes in fifo */
|
|
+
|
|
+ /* When using CPU, max long packet size is TX buffer size */
|
|
+ max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
|
|
+
|
|
+ max_data_per_packet = max_dsi_packet_size - 4 - 1;
|
|
+
|
|
+ max_pixels_per_packet = max_data_per_packet / bytespp;
|
|
+
|
|
+ enable_clocks(1);
|
|
+
|
|
+ display->ctrl->setup_update(display, x, y, w, h);
|
|
+
|
|
+ pixels_left = w * h;
|
|
+
|
|
+ dsi.update_region.x = x;
|
|
+ dsi.update_region.y = y;
|
|
+ dsi.update_region.w = w;
|
|
+ dsi.update_region.h = h;
|
|
+ dsi.update_region.bytespp = bytespp;
|
|
+
|
|
+ start_measuring();
|
|
+
|
|
+ pixnum = 0;
|
|
+
|
|
+ while (pixels_left > 0) {
|
|
+ /* 0x2c = write_memory_start */
|
|
+ /* 0x3c = write_memory_continue */
|
|
+ u8 dcs_cmd = first ? 0x2c : 0x3c;
|
|
+ int pixels;
|
|
+ DSI_DECL_VARS;
|
|
+ first = 0;
|
|
+
|
|
+ /* TX_FIFO_NOT_EMPTY */
|
|
+ while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
|
|
+ fifo_stalls++;
|
|
+ if (fifo_stalls > 0xfffff) {
|
|
+ DSSERR("fifo stalls overflow\n");
|
|
+ dsi_if_enable(0);
|
|
+ enable_clocks(0);
|
|
+ return;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ pixels = min(max_pixels_per_packet, pixels_left);
|
|
+
|
|
+ pixels_left -= pixels;
|
|
+
|
|
+ dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
|
|
+ 1 + pixels * bytespp, 0);
|
|
+
|
|
+ DSI_PUSH(0, dcs_cmd);
|
|
+
|
|
+ while (pixels-- > 0) {
|
|
+ u32 pix;
|
|
+
|
|
+ pix = 0x000000;
|
|
+
|
|
+ DSI_PUSH(0, (pix >> 16) & 0xff);
|
|
+ DSI_PUSH(0, (pix >> 8) & 0xff);
|
|
+ DSI_PUSH(0, (pix >> 0) & 0xff);
|
|
+ }
|
|
+
|
|
+ DSI_FLUSH(0);
|
|
+ }
|
|
+
|
|
+ enable_clocks(0);
|
|
+
|
|
+ end_measuring("L4 CLEAR");
|
|
+}
|
|
+#endif
|
|
+
|
|
+static void dsi_setup_update_dispc(struct omap_display *display,
|
|
+ u16 x, u16 y, u16 w, u16 h)
|
|
+{
|
|
+ DSSDBG("dsi_setup_update_dispc(%d,%d %dx%d)\n",
|
|
+ x, y, w, h);
|
|
+
|
|
+#ifdef DEBUG
|
|
+ dsi.update_region.x = x;
|
|
+ dsi.update_region.y = y;
|
|
+ dsi.update_region.w = w;
|
|
+ dsi.update_region.h = h;
|
|
+ dsi.update_region.bytespp = 3; // XXX
|
|
+#endif
|
|
+
|
|
+ dispc_setup_partial_planes(display, &x, &y, &w, &h);
|
|
+
|
|
+ dispc_set_lcd_size(w, h);
|
|
+}
|
|
+
|
|
+static void dsi_setup_autoupdate_dispc(struct omap_display *display)
|
|
+{
|
|
+ u16 w, h;
|
|
+
|
|
+ display->get_resolution(display, &w, &h);
|
|
+
|
|
+#ifdef DEBUG
|
|
+ dsi.update_region.x = 0;
|
|
+ dsi.update_region.y = 0;
|
|
+ dsi.update_region.w = w;
|
|
+ dsi.update_region.h = h;
|
|
+ dsi.update_region.bytespp = 3; // XXX
|
|
+#endif
|
|
+
|
|
+ /* the overlay settings may not have been applied, if we were in manual
|
|
+ * mode earlier, so do it here */
|
|
+ display->manager->apply(display->manager);
|
|
+
|
|
+ dispc_set_lcd_size(w, h);
|
|
+
|
|
+ dsi.autoupdate_setup = 0;
|
|
+}
|
|
+
|
|
+static void dsi_update_screen_dispc(struct omap_display *display,
|
|
+ u16 x, u16 y, u16 w, u16 h)
|
|
+{
|
|
+ int bytespp = 3;
|
|
+ int total_len;
|
|
+ int line_packet_len;
|
|
+ u32 l;
|
|
+
|
|
+ if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
|
|
+ DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
|
|
+ x, y, w, h);
|
|
+
|
|
+ /* TODO: one packet could be longer, I think? Max is the line buffer */
|
|
+ line_packet_len = w * bytespp + 1; /* 1 byte for DCS cmd */
|
|
+ total_len = line_packet_len * h;
|
|
+
|
|
+ display->ctrl->setup_update(display, x, y, w, h);
|
|
+
|
|
+ if (0)
|
|
+ dsi_vc_print_status(1);
|
|
+
|
|
+ perf_mark_start();
|
|
+
|
|
+ l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
|
|
+ dsi_write_reg(DSI_VC_TE(1), l);
|
|
+
|
|
+ dsi_vc_write_long_header(1, DSI_DT_DCS_LONG_WRITE, line_packet_len, 0);
|
|
+
|
|
+ if (dsi.use_te)
|
|
+ l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
|
|
+ else
|
|
+ l = FLD_MOD(l, 1, 31, 31); /* TE_START */
|
|
+ dsi_write_reg(DSI_VC_TE(1), l);
|
|
+
|
|
+ dispc_enable_lcd_out(1);
|
|
+
|
|
+ if (dsi.use_te)
|
|
+ dsi_vc_send_bta(1);
|
|
+}
|
|
+
|
|
+static void framedone_callback(void *data, u32 mask)
|
|
+{
|
|
+ if (dsi.framedone_scheduled) {
|
|
+ DSSERR("Framedone already scheduled. Bogus FRAMEDONE IRQ?\n");
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ dsi.framedone_scheduled = 1;
|
|
+
|
|
+ /* We get FRAMEDONE when DISPC has finished sending pixels and turns
|
|
+ * itself off. However, DSI still has the pixels in its buffers, and
|
|
+ * is sending the data. Thus we have to wait until we can do a new
|
|
+ * transfer or turn the clocks off. We do that in a separate work
|
|
+ * func. */
|
|
+ queue_work(dsi.workqueue, &dsi.framedone_work);
|
|
+}
|
|
+
|
|
+static void framedone_worker(struct work_struct *work)
|
|
+{
|
|
+ u32 l;
|
|
+ unsigned long tmo;
|
|
+ int i = 0;
|
|
+
|
|
+ l = REG_GET(DSI_VC_TE(1), 23, 0); /* TE_SIZE */
|
|
+
|
|
+ /* There shouldn't be much stuff in DSI buffers, if any, so we'll
|
|
+ * just busyloop */
|
|
+ if (l > 0) {
|
|
+ tmo = jiffies + msecs_to_jiffies(50);
|
|
+ while (REG_GET(DSI_VC_TE(1), 23, 0) > 0) { /* TE_SIZE */
|
|
+ i++;
|
|
+ if (time_after(jiffies, tmo)) {
|
|
+ DSSERR("timeout waiting TE_SIZE to zero\n");
|
|
+ break;
|
|
+ }
|
|
+ cpu_relax();
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (REG_GET(DSI_VC_TE(1), 30, 30))
|
|
+ DSSERR("TE_EN not zero\n");
|
|
+
|
|
+ if (REG_GET(DSI_VC_TE(1), 31, 31))
|
|
+ DSSERR("TE_START not zero\n");
|
|
+
|
|
+ perf_show("DISPC");
|
|
+
|
|
+ if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
|
|
+ DSSDBG("FRAMEDONE\n");
|
|
+
|
|
+#if 0
|
|
+ if (l)
|
|
+ DSSWARN("FRAMEDONE irq too early, %d bytes, %d loops\n", l, i);
|
|
+#else
|
|
+ if (l > 1024*3)
|
|
+ DSSWARN("FRAMEDONE irq too early, %d bytes, %d loops\n", l, i);
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
|
|
+ dispc_fake_vsync_irq();
|
|
+#endif
|
|
+ dsi.framedone_scheduled = 0;
|
|
+
|
|
+ /* XXX check that fifo is not full. otherwise we would sleep and never
|
|
+ * get to process_cmd_fifo below */
|
|
+ /* We check for target_update_mode, not update_mode. No reason to push
|
|
+ * new updates if we're turning auto update off */
|
|
+ if (dsi.target_update_mode == OMAP_DSS_UPDATE_AUTO)
|
|
+ dsi_push_autoupdate(dsi.vc[1].display);
|
|
+
|
|
+ atomic_set(&dsi.cmd_pending, 0);
|
|
+ dsi_process_cmd_fifo(NULL);
|
|
+}
|
|
+
|
|
+static void dsi_start_auto_update(struct omap_display *display)
|
|
+{
|
|
+ DSSDBG("starting auto update\n");
|
|
+
|
|
+ dsi.autoupdate_setup = 1;
|
|
+
|
|
+ dsi_push_autoupdate(display);
|
|
+}
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+/* FIFO functions */
|
|
+
|
|
+static void dsi_signal_fifo_waiters(void)
|
|
+{
|
|
+ if (atomic_read(&dsi.cmd_fifo_full) > 0) {
|
|
+ DSSDBG("SIGNALING: Fifo not full for waiter!\n");
|
|
+ complete(&dsi.cmd_done);
|
|
+ atomic_dec(&dsi.cmd_fifo_full);
|
|
+ }
|
|
+}
|
|
+
|
|
+/* returns 1 for async op, and 0 for sync op */
|
|
+static int dsi_do_update(struct omap_display *display,
|
|
+ struct dsi_cmd_update *upd)
|
|
+{
|
|
+ int r;
|
|
+ u16 x = upd->x, y = upd->y, w = upd->w, h = upd->h;
|
|
+ u16 dw, dh;
|
|
+
|
|
+ if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
|
|
+ return 0;
|
|
+
|
|
+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
|
|
+ return 0;
|
|
+
|
|
+ display->get_resolution(display, &dw, &dh);
|
|
+ if (x > dw || y > dh)
|
|
+ return 0;
|
|
+
|
|
+ if (x + w > dw)
|
|
+ w = dw - x;
|
|
+
|
|
+ if (y + h > dh)
|
|
+ h = dh - y;
|
|
+
|
|
+ DSSDBGF("%d,%d %dx%d", x, y, w, h);
|
|
+
|
|
+ perf_mark_setup();
|
|
+
|
|
+ if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
|
|
+ dsi_setup_update_dispc(display, x, y, w, h);
|
|
+ dsi_update_screen_dispc(display, x, y, w, h);
|
|
+ return 1;
|
|
+ } else {
|
|
+ r = dsi_update_screen_l4(display, x, y, w, h);
|
|
+ if (r)
|
|
+ DSSERR("L4 update failed\n");
|
|
+ return 0;
|
|
+ }
|
|
+}
|
|
+
|
|
+/* returns 1 for async op, and 0 for sync op */
|
|
+static int dsi_do_autoupdate(struct omap_display *display)
|
|
+{
|
|
+ int r;
|
|
+ u16 w, h;
|
|
+
|
|
+ if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
|
|
+ return 0;
|
|
+
|
|
+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
|
|
+ return 0;
|
|
+
|
|
+ display->get_resolution(display, &w, &h);
|
|
+
|
|
+ perf_mark_setup();
|
|
+
|
|
+ if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
|
|
+ if (dsi.autoupdate_setup)
|
|
+ dsi_setup_autoupdate_dispc(display);
|
|
+ dsi_update_screen_dispc(display, 0, 0, w, h);
|
|
+ return 1;
|
|
+ } else {
|
|
+ r = dsi_update_screen_l4(display, 0, 0, w, h);
|
|
+ if (r)
|
|
+ DSSERR("L4 update failed\n");
|
|
+ return 0;
|
|
+ }
|
|
+}
|
|
+
|
|
+static void dsi_do_cmd_mem_read(struct omap_display *display,
|
|
+ struct dsi_cmd_mem_read *mem_read)
|
|
+{
|
|
+ int r;
|
|
+ r = display->ctrl->memory_read(display,
|
|
+ mem_read->buf,
|
|
+ mem_read->size,
|
|
+ mem_read->x,
|
|
+ mem_read->y,
|
|
+ mem_read->w,
|
|
+ mem_read->h);
|
|
+
|
|
+ *mem_read->ret_size = (size_t)r;
|
|
+ complete(mem_read->completion);
|
|
+}
|
|
+
|
|
+static void dsi_do_cmd_test(struct omap_display *display,
|
|
+ struct dsi_cmd_test *test)
|
|
+{
|
|
+ int r = 0;
|
|
+
|
|
+ DSSDBGF("");
|
|
+
|
|
+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
|
|
+ return;
|
|
+
|
|
+ /* run test first in low speed mode */
|
|
+ dsi_vc_enable_hs(0, 0);
|
|
+
|
|
+ if (display->ctrl->run_test) {
|
|
+ r = display->ctrl->run_test(display, test->test_num);
|
|
+ if (r)
|
|
+ goto end;
|
|
+ }
|
|
+
|
|
+ if (display->panel->run_test) {
|
|
+ r = display->panel->run_test(display, test->test_num);
|
|
+ if (r)
|
|
+ goto end;
|
|
+ }
|
|
+
|
|
+ /* then in high speed */
|
|
+ dsi_vc_enable_hs(0, 1);
|
|
+
|
|
+ if (display->ctrl->run_test) {
|
|
+ r = display->ctrl->run_test(display, test->test_num);
|
|
+ if (r)
|
|
+ goto end;
|
|
+ }
|
|
+
|
|
+ if (display->panel->run_test)
|
|
+ r = display->panel->run_test(display, test->test_num);
|
|
+
|
|
+end:
|
|
+ dsi_vc_enable_hs(0, 1);
|
|
+
|
|
+ *test->result = r;
|
|
+ complete(test->completion);
|
|
+
|
|
+ DSSDBG("test end\n");
|
|
+}
|
|
+
|
|
+static void dsi_do_cmd_set_te(struct omap_display *display, bool enable)
|
|
+{
|
|
+ dsi.use_te = enable;
|
|
+
|
|
+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
|
|
+ return;
|
|
+
|
|
+ display->ctrl->enable_te(display, enable);
|
|
+
|
|
+ if (enable) {
|
|
+ /* disable LP_RX_TO, so that we can receive TE.
|
|
+ * Time to wait for TE is longer than the timer allows */
|
|
+ REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
|
|
+ } else {
|
|
+ REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
|
|
+ }
|
|
+}
|
|
+
|
|
+static void dsi_do_cmd_set_update_mode(struct omap_display *display,
|
|
+ enum omap_dss_update_mode mode)
|
|
+{
|
|
+ dsi.update_mode = mode;
|
|
+
|
|
+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
|
|
+ return;
|
|
+
|
|
+ if (mode == OMAP_DSS_UPDATE_AUTO)
|
|
+ dsi_start_auto_update(display);
|
|
+}
|
|
+
|
|
+static void dsi_process_cmd_fifo(struct work_struct *work)
|
|
+{
|
|
+ int len;
|
|
+ struct dsi_cmd_item p;
|
|
+ unsigned long flags;
|
|
+ struct omap_display *display;
|
|
+ int exit = 0;
|
|
+
|
|
+ if (dsi.debug_process)
|
|
+ DSSDBGF("");
|
|
+
|
|
+ if (atomic_cmpxchg(&dsi.cmd_pending, 0, 1) == 1) {
|
|
+ if (dsi.debug_process)
|
|
+ DSSDBG("cmd pending, skip process\n");
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ while (!exit) {
|
|
+ spin_lock_irqsave(dsi.cmd_fifo->lock, flags);
|
|
+
|
|
+ len = __kfifo_get(dsi.cmd_fifo, (unsigned char *)&p,
|
|
+ sizeof(p));
|
|
+ if (len == 0) {
|
|
+ if (dsi.debug_process)
|
|
+ DSSDBG("nothing more in fifo, atomic clear\n");
|
|
+ atomic_set(&dsi.cmd_pending, 0);
|
|
+ spin_unlock_irqrestore(dsi.cmd_fifo->lock, flags);
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ spin_unlock_irqrestore(dsi.cmd_fifo->lock, flags);
|
|
+
|
|
+ BUG_ON(len != sizeof(p));
|
|
+
|
|
+ display = p.display;
|
|
+
|
|
+ if (dsi.debug_process)
|
|
+ DSSDBG("processing cmd %d\n", p.cmd);
|
|
+
|
|
+ switch (p.cmd) {
|
|
+ case DSI_CMD_UPDATE:
|
|
+ if (dsi_do_update(display, &p.u.r)) {
|
|
+ if (dsi.debug_process)
|
|
+ DSSDBG("async update\n");
|
|
+ exit = 1;
|
|
+ } else {
|
|
+ if (dsi.debug_process)
|
|
+ DSSDBG("sync update\n");
|
|
+ }
|
|
+ break;
|
|
+
|
|
+ case DSI_CMD_AUTOUPDATE:
|
|
+ if (dsi_do_autoupdate(display)) {
|
|
+ if (dsi.debug_process)
|
|
+ DSSDBG("async autoupdate\n");
|
|
+ exit = 1;
|
|
+ } else {
|
|
+ if (dsi.debug_process)
|
|
+ DSSDBG("sync autoupdate\n");
|
|
+ }
|
|
+ break;
|
|
+
|
|
+ case DSI_CMD_SYNC:
|
|
+ if (dsi.debug_process)
|
|
+ DSSDBG("Signaling SYNC done!\n");
|
|
+ complete(p.u.sync);
|
|
+ break;
|
|
+
|
|
+ case DSI_CMD_MEM_READ:
|
|
+ dsi_do_cmd_mem_read(display, &p.u.mem_read);
|
|
+ break;
|
|
+
|
|
+ case DSI_CMD_TEST:
|
|
+ dsi_do_cmd_test(display, &p.u.test);
|
|
+ break;
|
|
+
|
|
+ case DSI_CMD_SET_TE:
|
|
+ dsi_do_cmd_set_te(display, p.u.te);
|
|
+ break;
|
|
+
|
|
+ case DSI_CMD_SET_UPDATE_MODE:
|
|
+ dsi_do_cmd_set_update_mode(display, p.u.update_mode);
|
|
+ break;
|
|
+
|
|
+ case DSI_CMD_SET_ROTATE:
|
|
+ display->ctrl->set_rotate(display, p.u.rotate);
|
|
+ if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO)
|
|
+ dsi.autoupdate_setup = 1;
|
|
+ break;
|
|
+
|
|
+ case DSI_CMD_SET_MIRROR:
|
|
+ display->ctrl->set_mirror(display, p.u.mirror);
|
|
+ break;
|
|
+
|
|
+ default:
|
|
+ BUG();
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (dsi.debug_process)
|
|
+ DSSDBG("exit dsi_process_cmd_fifo\n");
|
|
+
|
|
+ dsi_signal_fifo_waiters();
|
|
+}
|
|
+
|
|
+static void dsi_push_cmd(struct dsi_cmd_item *p)
|
|
+{
|
|
+ int ret;
|
|
+
|
|
+ if (dsi.debug_process)
|
|
+ DSSDBGF("");
|
|
+
|
|
+ while (1) {
|
|
+ unsigned long flags;
|
|
+ unsigned avail, used;
|
|
+
|
|
+ spin_lock_irqsave(dsi.cmd_fifo->lock, flags);
|
|
+ used = __kfifo_len(dsi.cmd_fifo) / sizeof(struct dsi_cmd_item);
|
|
+ avail = DSI_CMD_FIFO_LEN - used;
|
|
+
|
|
+ if (dsi.debug_process)
|
|
+ DSSDBG("%u/%u items left in fifo\n", avail, used);
|
|
+
|
|
+ if (avail == 0) {
|
|
+ if (dsi.debug_process)
|
|
+ DSSDBG("cmd fifo full, waiting...\n");
|
|
+ spin_unlock_irqrestore(dsi.cmd_fifo->lock, flags);
|
|
+ atomic_inc(&dsi.cmd_fifo_full);
|
|
+ wait_for_completion(&dsi.cmd_done);
|
|
+ if (dsi.debug_process)
|
|
+ DSSDBG("cmd fifo not full, woke up\n");
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+ ret = __kfifo_put(dsi.cmd_fifo, (unsigned char *)p,
|
|
+ sizeof(*p));
|
|
+
|
|
+ spin_unlock_irqrestore(dsi.cmd_fifo->lock, flags);
|
|
+
|
|
+ BUG_ON(ret != sizeof(*p));
|
|
+
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ queue_work(dsi.workqueue, &dsi.process_work);
|
|
+}
|
|
+
|
|
+static void dsi_push_update(struct omap_display *display,
|
|
+ int x, int y, int w, int h)
|
|
+{
|
|
+ struct dsi_cmd_item p;
|
|
+
|
|
+ p.display = display;
|
|
+ p.cmd = DSI_CMD_UPDATE;
|
|
+
|
|
+ p.u.r.x = x;
|
|
+ p.u.r.y = y;
|
|
+ p.u.r.w = w;
|
|
+ p.u.r.h = h;
|
|
+
|
|
+ DSSDBG("pushing UPDATE %d,%d %dx%d\n", x, y, w, h);
|
|
+
|
|
+ dsi_push_cmd(&p);
|
|
+}
|
|
+
|
|
+static void dsi_push_autoupdate(struct omap_display *display)
|
|
+{
|
|
+ struct dsi_cmd_item p;
|
|
+
|
|
+ p.display = display;
|
|
+ p.cmd = DSI_CMD_AUTOUPDATE;
|
|
+
|
|
+ dsi_push_cmd(&p);
|
|
+}
|
|
+
|
|
+static void dsi_push_sync(struct omap_display *display,
|
|
+ struct completion *sync_comp)
|
|
+{
|
|
+ struct dsi_cmd_item p;
|
|
+
|
|
+ p.display = display;
|
|
+ p.cmd = DSI_CMD_SYNC;
|
|
+ p.u.sync = sync_comp;
|
|
+
|
|
+ DSSDBG("pushing SYNC\n");
|
|
+
|
|
+ dsi_push_cmd(&p);
|
|
+}
|
|
+
|
|
+static void dsi_push_mem_read(struct omap_display *display,
|
|
+ struct dsi_cmd_mem_read *mem_read)
|
|
+{
|
|
+ struct dsi_cmd_item p;
|
|
+
|
|
+ p.display = display;
|
|
+ p.cmd = DSI_CMD_MEM_READ;
|
|
+ p.u.mem_read = *mem_read;
|
|
+
|
|
+ DSSDBG("pushing MEM_READ\n");
|
|
+
|
|
+ dsi_push_cmd(&p);
|
|
+}
|
|
+
|
|
+static void dsi_push_test(struct omap_display *display, int test_num,
|
|
+ int *result, struct completion *completion)
|
|
+{
|
|
+ struct dsi_cmd_item p;
|
|
+
|
|
+ p.display = display;
|
|
+ p.cmd = DSI_CMD_TEST;
|
|
+ p.u.test.test_num = test_num;
|
|
+ p.u.test.result = result;
|
|
+ p.u.test.completion = completion;
|
|
+
|
|
+ DSSDBG("pushing TEST\n");
|
|
+
|
|
+ dsi_push_cmd(&p);
|
|
+}
|
|
+
|
|
+static void dsi_push_set_te(struct omap_display *display, bool enable)
|
|
+{
|
|
+ struct dsi_cmd_item p;
|
|
+
|
|
+ p.display = display;
|
|
+ p.cmd = DSI_CMD_SET_TE;
|
|
+ p.u.te = enable;
|
|
+
|
|
+ DSSDBG("pushing SET_TE\n");
|
|
+
|
|
+ dsi_push_cmd(&p);
|
|
+}
|
|
+
|
|
+static void dsi_push_set_update_mode(struct omap_display *display,
|
|
+ enum omap_dss_update_mode mode)
|
|
+{
|
|
+ struct dsi_cmd_item p;
|
|
+
|
|
+ p.display = display;
|
|
+ p.cmd = DSI_CMD_SET_UPDATE_MODE;
|
|
+ p.u.update_mode = mode;
|
|
+
|
|
+ DSSDBG("pushing SET_UPDATE_MODE\n");
|
|
+
|
|
+ dsi_push_cmd(&p);
|
|
+}
|
|
+
|
|
+static void dsi_push_set_rotate(struct omap_display *display, int rotate)
|
|
+{
|
|
+ struct dsi_cmd_item p;
|
|
+
|
|
+ p.display = display;
|
|
+ p.cmd = DSI_CMD_SET_ROTATE;
|
|
+ p.u.rotate = rotate;
|
|
+
|
|
+ DSSDBG("pushing SET_ROTATE\n");
|
|
+
|
|
+ dsi_push_cmd(&p);
|
|
+}
|
|
+
|
|
+static void dsi_push_set_mirror(struct omap_display *display, int mirror)
|
|
+{
|
|
+ struct dsi_cmd_item p;
|
|
+
|
|
+ p.display = display;
|
|
+ p.cmd = DSI_CMD_SET_MIRROR;
|
|
+ p.u.mirror = mirror;
|
|
+
|
|
+ DSSDBG("pushing SET_MIRROR\n");
|
|
+
|
|
+ dsi_push_cmd(&p);
|
|
+}
|
|
+
|
|
+static int dsi_wait_sync(struct omap_display *display)
|
|
+{
|
|
+ long wait = msecs_to_jiffies(60000);
|
|
+ struct completion compl;
|
|
+
|
|
+ DSSDBGF("");
|
|
+
|
|
+ init_completion(&compl);
|
|
+ dsi_push_sync(display, &compl);
|
|
+
|
|
+ DSSDBG("Waiting for SYNC to happen...\n");
|
|
+ wait = wait_for_completion_timeout(&compl, wait);
|
|
+ DSSDBG("Released from SYNC\n");
|
|
+
|
|
+ if (wait == 0) {
|
|
+ DSSERR("timeout waiting sync\n");
|
|
+ return -ETIME;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+/* Display funcs */
|
|
+
|
|
+static int dsi_display_init_dispc(struct omap_display *display)
|
|
+{
|
|
+ int r;
|
|
+
|
|
+ r = omap_dispc_register_isr(framedone_callback, NULL,
|
|
+ DISPC_IRQ_FRAMEDONE);
|
|
+ if (r) {
|
|
+ DSSERR("can't get FRAMEDONE irq\n");
|
|
+ return r;
|
|
+ }
|
|
+
|
|
+ dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
|
|
+
|
|
+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI);
|
|
+ dispc_enable_fifohandcheck(1);
|
|
+
|
|
+ dispc_set_tft_data_lines(display->ctrl->pixel_size);
|
|
+
|
|
+ {
|
|
+ struct omap_video_timings timings = {
|
|
+ .hsw = 1,
|
|
+ .hfp = 1,
|
|
+ .hbp = 1,
|
|
+ .vsw = 1,
|
|
+ .vfp = 0,
|
|
+ .vbp = 0,
|
|
+ };
|
|
+
|
|
+ dispc_set_lcd_timings(&timings);
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void dsi_display_uninit_dispc(struct omap_display *display)
|
|
+{
|
|
+ omap_dispc_unregister_isr(framedone_callback, NULL,
|
|
+ DISPC_IRQ_FRAMEDONE);
|
|
+}
|
|
+
|
|
+static int dsi_display_init_dsi(struct omap_display *display)
|
|
+{
|
|
+ struct dsi_clock_info cinfo;
|
|
+ int r;
|
|
+
|
|
+ _dsi_print_reset_status();
|
|
+
|
|
+ r = dsi_pll_init(1, 0);
|
|
+ if (r)
|
|
+ goto err0;
|
|
+
|
|
+ r = dsi_pll_calc_ddrfreq(display->hw_config.u.dsi.ddr_clk_hz, &cinfo);
|
|
+ if (r)
|
|
+ goto err1;
|
|
+
|
|
+ r = dsi_pll_program(&cinfo);
|
|
+ if (r)
|
|
+ goto err1;
|
|
+
|
|
+ DSSDBG("PLL OK\n");
|
|
+
|
|
+ r = dsi_complexio_init(display);
|
|
+ if (r)
|
|
+ goto err1;
|
|
+
|
|
+ _dsi_print_reset_status();
|
|
+
|
|
+ dsi_proto_timings();
|
|
+ dsi_set_lp_clk_divisor();
|
|
+
|
|
+ if (1)
|
|
+ _dsi_print_reset_status();
|
|
+
|
|
+ r = dsi_proto_config(display);
|
|
+ if (r)
|
|
+ goto err2;
|
|
+
|
|
+ /* enable interface */
|
|
+ dsi_vc_enable(0, 1);
|
|
+ dsi_vc_enable(1, 1);
|
|
+ dsi_if_enable(1);
|
|
+ dsi_force_tx_stop_mode_io();
|
|
+
|
|
+ if (display->ctrl && display->ctrl->enable) {
|
|
+ r = display->ctrl->enable(display);
|
|
+ if (r)
|
|
+ goto err3;
|
|
+ }
|
|
+
|
|
+ if (display->panel && display->panel->enable) {
|
|
+ r = display->panel->enable(display);
|
|
+ if (r)
|
|
+ goto err4;
|
|
+ }
|
|
+
|
|
+ /* enable high-speed after initial config */
|
|
+ dsi_vc_enable_hs(0, 1);
|
|
+
|
|
+ return 0;
|
|
+err4:
|
|
+ if (display->ctrl && display->ctrl->disable)
|
|
+ display->ctrl->disable(display);
|
|
+err3:
|
|
+ dsi_if_enable(0);
|
|
+err2:
|
|
+ dsi_complexio_uninit();
|
|
+err1:
|
|
+ dsi_pll_uninit();
|
|
+err0:
|
|
+ return r;
|
|
+}
|
|
+
|
|
+static void dsi_display_uninit_dsi(struct omap_display *display)
|
|
+{
|
|
+ if (display->panel && display->panel->disable)
|
|
+ display->panel->disable(display);
|
|
+ if (display->ctrl && display->ctrl->disable)
|
|
+ display->ctrl->disable(display);
|
|
+
|
|
+ dsi_complexio_uninit();
|
|
+ dsi_pll_uninit();
|
|
+}
|
|
+
|
|
+static int dsi_core_init(void)
|
|
+{
|
|
+ /* Autoidle */
|
|
+ REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
|
|
+
|
|
+ /* ENWAKEUP */
|
|
+ REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
|
|
+
|
|
+ /* SIDLEMODE smart-idle */
|
|
+ REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
|
|
+
|
|
+ _dsi_initialize_irq();
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int dsi_display_enable(struct omap_display *display)
|
|
+{
|
|
+ int r = 0;
|
|
+
|
|
+ DSSDBG("dsi_display_enable\n");
|
|
+
|
|
+ mutex_lock(&dsi.lock);
|
|
+
|
|
+ if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
|
|
+ DSSERR("display already enabled\n");
|
|
+ r = -EINVAL;
|
|
+ goto err0;
|
|
+ }
|
|
+
|
|
+ enable_clocks(1);
|
|
+ dsi_enable_pll_clock(1);
|
|
+
|
|
+ r = _dsi_reset();
|
|
+ if (r)
|
|
+ return r;
|
|
+
|
|
+ dsi_core_init();
|
|
+
|
|
+ r = dsi_display_init_dispc(display);
|
|
+ if (r)
|
|
+ goto err1;
|
|
+
|
|
+ r = dsi_display_init_dsi(display);
|
|
+ if (r)
|
|
+ goto err2;
|
|
+
|
|
+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
|
|
+
|
|
+ if (dsi.use_te)
|
|
+ dsi_push_set_te(display, 1);
|
|
+
|
|
+ dsi_push_set_update_mode(display, dsi.user_update_mode);
|
|
+ dsi.target_update_mode = dsi.user_update_mode;
|
|
+
|
|
+ mutex_unlock(&dsi.lock);
|
|
+
|
|
+ return dsi_wait_sync(display);
|
|
+
|
|
+err2:
|
|
+ dsi_display_uninit_dispc(display);
|
|
+err1:
|
|
+ enable_clocks(0);
|
|
+ dsi_enable_pll_clock(0);
|
|
+err0:
|
|
+ mutex_unlock(&dsi.lock);
|
|
+ DSSDBG("dsi_display_enable FAILED\n");
|
|
+ return r;
|
|
+}
|
|
+
|
|
+static void dsi_display_disable(struct omap_display *display)
|
|
+{
|
|
+ DSSDBG("dsi_display_disable\n");
|
|
+
|
|
+ mutex_lock(&dsi.lock);
|
|
+
|
|
+ if (display->state == OMAP_DSS_DISPLAY_DISABLED ||
|
|
+ display->state == OMAP_DSS_DISPLAY_SUSPENDED)
|
|
+ goto end;
|
|
+
|
|
+ if (dsi.target_update_mode != OMAP_DSS_UPDATE_DISABLED) {
|
|
+ dsi_push_set_update_mode(display, OMAP_DSS_UPDATE_DISABLED);
|
|
+ dsi.target_update_mode = OMAP_DSS_UPDATE_DISABLED;
|
|
+ }
|
|
+
|
|
+ dsi_wait_sync(display);
|
|
+
|
|
+ display->state = OMAP_DSS_DISPLAY_DISABLED;
|
|
+
|
|
+ dsi_display_uninit_dispc(display);
|
|
+
|
|
+ dsi_display_uninit_dsi(display);
|
|
+
|
|
+ enable_clocks(0);
|
|
+ dsi_enable_pll_clock(0);
|
|
+end:
|
|
+ mutex_unlock(&dsi.lock);
|
|
+}
|
|
+
|
|
+static int dsi_display_suspend(struct omap_display *display)
|
|
+{
|
|
+ DSSDBG("dsi_display_suspend\n");
|
|
+
|
|
+ dsi_display_disable(display);
|
|
+
|
|
+ display->state = OMAP_DSS_DISPLAY_SUSPENDED;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int dsi_display_resume(struct omap_display *display)
|
|
+{
|
|
+ DSSDBG("dsi_display_resume\n");
|
|
+
|
|
+ display->state = OMAP_DSS_DISPLAY_DISABLED;
|
|
+ return dsi_display_enable(display);
|
|
+}
|
|
+
|
|
+static int dsi_display_update(struct omap_display *display,
|
|
+ u16 x, u16 y, u16 w, u16 h)
|
|
+{
|
|
+ DSSDBG("dsi_display_update(%d,%d %dx%d)\n", x, y, w, h);
|
|
+
|
|
+ if (w == 0 || h == 0)
|
|
+ return 0;
|
|
+
|
|
+ mutex_lock(&dsi.lock);
|
|
+
|
|
+ if (dsi.target_update_mode == OMAP_DSS_UPDATE_MANUAL)
|
|
+ dsi_push_update(display, x, y, w, h);
|
|
+ /* XXX else return error? */
|
|
+
|
|
+ mutex_unlock(&dsi.lock);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int dsi_display_sync(struct omap_display *display)
|
|
+{
|
|
+ DSSDBGF("");
|
|
+ return dsi_wait_sync(display);
|
|
+}
|
|
+
|
|
+static int dsi_display_set_update_mode(struct omap_display *display,
|
|
+ enum omap_dss_update_mode mode)
|
|
+{
|
|
+ DSSDBGF("%d", mode);
|
|
+
|
|
+ mutex_lock(&dsi.lock);
|
|
+
|
|
+ if (dsi.target_update_mode != mode) {
|
|
+ dsi_push_set_update_mode(display, mode);
|
|
+
|
|
+ dsi.target_update_mode = mode;
|
|
+ dsi.user_update_mode = mode;
|
|
+ }
|
|
+
|
|
+ mutex_unlock(&dsi.lock);
|
|
+
|
|
+ return dsi_wait_sync(display);
|
|
+}
|
|
+
|
|
+static enum omap_dss_update_mode dsi_display_get_update_mode(
|
|
+ struct omap_display *display)
|
|
+{
|
|
+ return dsi.update_mode;
|
|
+}
|
|
+
|
|
+static int dsi_display_enable_te(struct omap_display *display, bool enable)
|
|
+{
|
|
+ DSSDBGF("%d", enable);
|
|
+
|
|
+ if (!display->ctrl->enable_te)
|
|
+ return -ENOENT;
|
|
+
|
|
+ dsi_push_set_te(display, enable);
|
|
+
|
|
+ return dsi_wait_sync(display);
|
|
+}
|
|
+
|
|
+static int dsi_display_get_te(struct omap_display *display)
|
|
+{
|
|
+ return dsi.use_te;
|
|
+}
|
|
+
|
|
+
|
|
+
|
|
+static int dsi_display_set_rotate(struct omap_display *display, u8 rotate)
|
|
+{
|
|
+ DSSDBGF("%d", rotate);
|
|
+
|
|
+ if (!display->ctrl->set_rotate || !display->ctrl->get_rotate)
|
|
+ return -EINVAL;
|
|
+
|
|
+ dsi_push_set_rotate(display, rotate);
|
|
+
|
|
+ return dsi_wait_sync(display);
|
|
+}
|
|
+
|
|
+static u8 dsi_display_get_rotate(struct omap_display *display)
|
|
+{
|
|
+ if (!display->ctrl->set_rotate || !display->ctrl->get_rotate)
|
|
+ return 0;
|
|
+
|
|
+ return display->ctrl->get_rotate(display);
|
|
+}
|
|
+
|
|
+static int dsi_display_set_mirror(struct omap_display *display, bool mirror)
|
|
+{
|
|
+ DSSDBGF("%d", mirror);
|
|
+
|
|
+ if (!display->ctrl->set_mirror || !display->ctrl->get_mirror)
|
|
+ return -EINVAL;
|
|
+
|
|
+ dsi_push_set_mirror(display, mirror);
|
|
+
|
|
+ return dsi_wait_sync(display);
|
|
+}
|
|
+
|
|
+static bool dsi_display_get_mirror(struct omap_display *display)
|
|
+{
|
|
+ if (!display->ctrl->set_mirror || !display->ctrl->get_mirror)
|
|
+ return 0;
|
|
+
|
|
+ return display->ctrl->get_mirror(display);
|
|
+}
|
|
+
|
|
+static int dsi_display_run_test(struct omap_display *display, int test_num)
|
|
+{
|
|
+ long wait = msecs_to_jiffies(60000);
|
|
+ struct completion compl;
|
|
+ int result;
|
|
+
|
|
+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
|
|
+ return -EIO;
|
|
+
|
|
+ DSSDBGF("%d", test_num);
|
|
+
|
|
+ init_completion(&compl);
|
|
+
|
|
+ dsi_push_test(display, test_num, &result, &compl);
|
|
+
|
|
+ DSSDBG("Waiting for SYNC to happen...\n");
|
|
+ wait = wait_for_completion_timeout(&compl, wait);
|
|
+ DSSDBG("Released from SYNC\n");
|
|
+
|
|
+ if (wait == 0) {
|
|
+ DSSERR("timeout waiting test sync\n");
|
|
+ return -ETIME;
|
|
+ }
|
|
+
|
|
+ return result;
|
|
+}
|
|
+
|
|
+static int dsi_display_memory_read(struct omap_display *display,
|
|
+ void *buf, size_t size,
|
|
+ u16 x, u16 y, u16 w, u16 h)
|
|
+{
|
|
+ long wait = msecs_to_jiffies(60000);
|
|
+ struct completion compl;
|
|
+ struct dsi_cmd_mem_read mem_read;
|
|
+ size_t ret_size;
|
|
+
|
|
+ DSSDBGF("");
|
|
+
|
|
+ if (!display->ctrl->memory_read)
|
|
+ return -EINVAL;
|
|
+
|
|
+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
|
|
+ return -EIO;
|
|
+
|
|
+ init_completion(&compl);
|
|
+
|
|
+ mem_read.x = x;
|
|
+ mem_read.y = y;
|
|
+ mem_read.w = w;
|
|
+ mem_read.h = h;
|
|
+ mem_read.buf = buf;
|
|
+ mem_read.size = size;
|
|
+ mem_read.ret_size = &ret_size;
|
|
+ mem_read.completion = &compl;
|
|
+
|
|
+ dsi_push_mem_read(display, &mem_read);
|
|
+
|
|
+ DSSDBG("Waiting for SYNC to happen...\n");
|
|
+ wait = wait_for_completion_timeout(&compl, wait);
|
|
+ DSSDBG("Released from SYNC\n");
|
|
+
|
|
+ if (wait == 0) {
|
|
+ DSSERR("timeout waiting mem read sync\n");
|
|
+ return -ETIME;
|
|
+ }
|
|
+
|
|
+ return ret_size;
|
|
+}
|
|
+
|
|
+static void dsi_configure_overlay(struct omap_overlay *ovl)
|
|
+{
|
|
+ unsigned low, high, size;
|
|
+ enum omap_burst_size burst;
|
|
+ enum omap_plane plane = ovl->id;
|
|
+
|
|
+ burst = OMAP_DSS_BURST_16x32;
|
|
+ size = 16 * 32 / 8;
|
|
+
|
|
+ dispc_set_burst_size(plane, burst);
|
|
+
|
|
+ high = dispc_get_plane_fifo_size(plane) - size;
|
|
+ low = 0;
|
|
+ dispc_setup_plane_fifo(plane, low, high);
|
|
+}
|
|
+
|
|
+void dsi_init_display(struct omap_display *display)
|
|
+{
|
|
+ DSSDBG("DSI init\n");
|
|
+
|
|
+ display->enable = dsi_display_enable;
|
|
+ display->disable = dsi_display_disable;
|
|
+ display->suspend = dsi_display_suspend;
|
|
+ display->resume = dsi_display_resume;
|
|
+ display->update = dsi_display_update;
|
|
+ display->sync = dsi_display_sync;
|
|
+ display->set_update_mode = dsi_display_set_update_mode;
|
|
+ display->get_update_mode = dsi_display_get_update_mode;
|
|
+ display->enable_te = dsi_display_enable_te;
|
|
+ display->get_te = dsi_display_get_te;
|
|
+
|
|
+ display->get_rotate = dsi_display_get_rotate;
|
|
+ display->set_rotate = dsi_display_set_rotate;
|
|
+
|
|
+ display->get_mirror = dsi_display_get_mirror;
|
|
+ display->set_mirror = dsi_display_set_mirror;
|
|
+
|
|
+ display->run_test = dsi_display_run_test;
|
|
+ display->memory_read = dsi_display_memory_read;
|
|
+
|
|
+ display->configure_overlay = dsi_configure_overlay;
|
|
+
|
|
+ display->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
|
|
+
|
|
+ dsi.vc[0].display = display;
|
|
+ dsi.vc[1].display = display;
|
|
+}
|
|
+
|
|
+int dsi_init(void)
|
|
+{
|
|
+ u32 rev;
|
|
+
|
|
+ spin_lock_init(&dsi.cmd_lock);
|
|
+ dsi.cmd_fifo = kfifo_alloc(
|
|
+ DSI_CMD_FIFO_LEN * sizeof(struct dsi_cmd_item),
|
|
+ GFP_KERNEL,
|
|
+ &dsi.cmd_lock);
|
|
+
|
|
+ init_completion(&dsi.cmd_done);
|
|
+ atomic_set(&dsi.cmd_fifo_full, 0);
|
|
+ atomic_set(&dsi.cmd_pending, 0);
|
|
+
|
|
+ init_completion(&dsi.bta_completion);
|
|
+
|
|
+ dsi.workqueue = create_singlethread_workqueue("dsi");
|
|
+ INIT_WORK(&dsi.framedone_work, framedone_worker);
|
|
+ INIT_WORK(&dsi.process_work, dsi_process_cmd_fifo);
|
|
+
|
|
+ mutex_init(&dsi.lock);
|
|
+
|
|
+ dsi.target_update_mode = OMAP_DSS_UPDATE_DISABLED;
|
|
+ dsi.user_update_mode = OMAP_DSS_UPDATE_DISABLED;
|
|
+
|
|
+ dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS);
|
|
+ if (!dsi.base) {
|
|
+ DSSERR("can't ioremap DSI\n");
|
|
+ return -ENOMEM;
|
|
+ }
|
|
+
|
|
+ enable_clocks(1);
|
|
+
|
|
+ rev = dsi_read_reg(DSI_REVISION);
|
|
+ printk(KERN_INFO "OMAP DSI rev %d.%d\n",
|
|
+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
|
|
+
|
|
+ enable_clocks(0);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+void dsi_exit(void)
|
|
+{
|
|
+ flush_workqueue(dsi.workqueue);
|
|
+ destroy_workqueue(dsi.workqueue);
|
|
+
|
|
+ iounmap(dsi.base);
|
|
+
|
|
+ kfifo_free(dsi.cmd_fifo);
|
|
+
|
|
+ DSSDBG("omap_dsi_exit\n");
|
|
+}
|
|
+
|
|
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
|
|
new file mode 100644
|
|
index 0000000..adc1f34
|
|
--- /dev/null
|
|
+++ b/drivers/video/omap2/dss/dss.c
|
|
@@ -0,0 +1,345 @@
|
|
+/*
|
|
+ * linux/drivers/video/omap2/dss/dss.c
|
|
+ *
|
|
+ * Copyright (C) 2009 Nokia Corporation
|
|
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
|
|
+ *
|
|
+ * Some code and ideas taken from drivers/video/omap/ driver
|
|
+ * by Imre Deak.
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published by
|
|
+ * the Free Software Foundation.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful, but WITHOUT
|
|
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
+ * more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License along with
|
|
+ * this program. If not, see <http://www.gnu.org/licenses/>.
|
|
+ */
|
|
+
|
|
+#define DSS_SUBSYS_NAME "DSS"
|
|
+
|
|
+#include <linux/kernel.h>
|
|
+#include <linux/io.h>
|
|
+#include <linux/err.h>
|
|
+#include <linux/delay.h>
|
|
+#include <linux/interrupt.h>
|
|
+#include <linux/seq_file.h>
|
|
+
|
|
+#include <mach/display.h>
|
|
+#include "dss.h"
|
|
+
|
|
+#define DSS_BASE 0x48050000
|
|
+
|
|
+#define DSS_SZ_REGS SZ_512
|
|
+
|
|
+struct dss_reg {
|
|
+ u16 idx;
|
|
+};
|
|
+
|
|
+#define DSS_REG(idx) ((const struct dss_reg) { idx })
|
|
+
|
|
+#define DSS_REVISION DSS_REG(0x0000)
|
|
+#define DSS_SYSCONFIG DSS_REG(0x0010)
|
|
+#define DSS_SYSSTATUS DSS_REG(0x0014)
|
|
+#define DSS_IRQSTATUS DSS_REG(0x0018)
|
|
+#define DSS_CONTROL DSS_REG(0x0040)
|
|
+#define DSS_SDI_CONTROL DSS_REG(0x0044)
|
|
+#define DSS_PLL_CONTROL DSS_REG(0x0048)
|
|
+#define DSS_SDI_STATUS DSS_REG(0x005C)
|
|
+
|
|
+#define REG_GET(idx, start, end) \
|
|
+ FLD_GET(dss_read_reg(idx), start, end)
|
|
+
|
|
+#define REG_FLD_MOD(idx, val, start, end) \
|
|
+ dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
|
|
+
|
|
+static struct {
|
|
+ void __iomem *base;
|
|
+
|
|
+ u32 ctx[DSS_SZ_REGS / sizeof(u32)];
|
|
+} dss;
|
|
+
|
|
+static int _omap_dss_wait_reset(void);
|
|
+
|
|
+static inline void dss_write_reg(const struct dss_reg idx, u32 val)
|
|
+{
|
|
+ __raw_writel(val, dss.base + idx.idx);
|
|
+}
|
|
+
|
|
+static inline u32 dss_read_reg(const struct dss_reg idx)
|
|
+{
|
|
+ return __raw_readl(dss.base + idx.idx);
|
|
+}
|
|
+
|
|
+#define SR(reg) \
|
|
+ dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
|
|
+#define RR(reg) \
|
|
+ dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
|
|
+
|
|
+void dss_save_context(void)
|
|
+{
|
|
+ if (cpu_is_omap24xx())
|
|
+ return;
|
|
+
|
|
+ SR(SYSCONFIG);
|
|
+ SR(CONTROL);
|
|
+
|
|
+#ifdef CONFIG_OMAP2_DSS_SDI
|
|
+ SR(SDI_CONTROL);
|
|
+ SR(PLL_CONTROL);
|
|
+#endif
|
|
+}
|
|
+
|
|
+void dss_restore_context(void)
|
|
+{
|
|
+ if (_omap_dss_wait_reset())
|
|
+ DSSERR("DSS not coming out of reset after sleep\n");
|
|
+
|
|
+ RR(SYSCONFIG);
|
|
+ RR(CONTROL);
|
|
+
|
|
+#ifdef CONFIG_OMAP2_DSS_SDI
|
|
+ RR(SDI_CONTROL);
|
|
+ RR(PLL_CONTROL);
|
|
+#endif
|
|
+}
|
|
+
|
|
+#undef SR
|
|
+#undef RR
|
|
+
|
|
+void dss_sdi_init(u8 datapairs)
|
|
+{
|
|
+ u32 l;
|
|
+
|
|
+ BUG_ON(datapairs > 3 || datapairs < 1);
|
|
+
|
|
+ l = dss_read_reg(DSS_SDI_CONTROL);
|
|
+ l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */
|
|
+ l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */
|
|
+ l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */
|
|
+ dss_write_reg(DSS_SDI_CONTROL, l);
|
|
+
|
|
+ l = dss_read_reg(DSS_PLL_CONTROL);
|
|
+ l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
|
|
+ l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */
|
|
+ l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
|
|
+ dss_write_reg(DSS_PLL_CONTROL, l);
|
|
+}
|
|
+
|
|
+void dss_sdi_enable(void)
|
|
+{
|
|
+ dispc_pck_free_enable(1);
|
|
+
|
|
+ /* Reset SDI PLL */
|
|
+ REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
|
|
+ udelay(1); /* wait 2x PCLK */
|
|
+
|
|
+ /* Lock SDI PLL */
|
|
+ REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
|
|
+
|
|
+ /* Waiting for PLL lock request to complete */
|
|
+ while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6))
|
|
+ ;
|
|
+
|
|
+ /* Clearing PLL_GO bit */
|
|
+ REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
|
|
+
|
|
+ /* Waiting for PLL to lock */
|
|
+ while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5)))
|
|
+ ;
|
|
+
|
|
+ dispc_lcd_enable_signal(1);
|
|
+
|
|
+ /* Waiting for SDI reset to complete */
|
|
+ while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2)))
|
|
+ ;
|
|
+}
|
|
+
|
|
+void dss_sdi_disable(void)
|
|
+{
|
|
+ dispc_lcd_enable_signal(0);
|
|
+
|
|
+ dispc_pck_free_enable(0);
|
|
+
|
|
+ /* Reset SDI PLL */
|
|
+ REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
|
|
+}
|
|
+
|
|
+void dss_dump_regs(struct seq_file *s)
|
|
+{
|
|
+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
|
|
+
|
|
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+
|
|
+ DUMPREG(DSS_REVISION);
|
|
+ DUMPREG(DSS_SYSCONFIG);
|
|
+ DUMPREG(DSS_SYSSTATUS);
|
|
+ DUMPREG(DSS_IRQSTATUS);
|
|
+ DUMPREG(DSS_CONTROL);
|
|
+ DUMPREG(DSS_SDI_CONTROL);
|
|
+ DUMPREG(DSS_PLL_CONTROL);
|
|
+ DUMPREG(DSS_SDI_STATUS);
|
|
+
|
|
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+#undef DUMPREG
|
|
+}
|
|
+
|
|
+void dss_select_clk_source(bool dsi, bool dispc)
|
|
+{
|
|
+ u32 r;
|
|
+ r = dss_read_reg(DSS_CONTROL);
|
|
+ r = FLD_MOD(r, dsi, 1, 1); /* DSI_CLK_SWITCH */
|
|
+ r = FLD_MOD(r, dispc, 0, 0); /* DISPC_CLK_SWITCH */
|
|
+ dss_write_reg(DSS_CONTROL, r);
|
|
+}
|
|
+
|
|
+int dss_get_dsi_clk_source(void)
|
|
+{
|
|
+ return FLD_GET(dss_read_reg(DSS_CONTROL), 1, 1);
|
|
+}
|
|
+
|
|
+int dss_get_dispc_clk_source(void)
|
|
+{
|
|
+ return FLD_GET(dss_read_reg(DSS_CONTROL), 0, 0);
|
|
+}
|
|
+
|
|
+static irqreturn_t dss_irq_handler_omap2(int irq, void *arg)
|
|
+{
|
|
+ dispc_irq_handler();
|
|
+
|
|
+ return IRQ_HANDLED;
|
|
+}
|
|
+
|
|
+static irqreturn_t dss_irq_handler_omap3(int irq, void *arg)
|
|
+{
|
|
+ u32 irqstatus;
|
|
+
|
|
+ irqstatus = dss_read_reg(DSS_IRQSTATUS);
|
|
+
|
|
+ if (irqstatus & (1<<0)) /* DISPC_IRQ */
|
|
+ dispc_irq_handler();
|
|
+#ifdef CONFIG_OMAP2_DSS_DSI
|
|
+ if (irqstatus & (1<<1)) /* DSI_IRQ */
|
|
+ dsi_irq_handler();
|
|
+#endif
|
|
+
|
|
+ return IRQ_HANDLED;
|
|
+}
|
|
+
|
|
+static int _omap_dss_wait_reset(void)
|
|
+{
|
|
+ unsigned timeout = 1000;
|
|
+
|
|
+ while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
|
|
+ udelay(1);
|
|
+ if (!--timeout) {
|
|
+ DSSERR("soft reset failed\n");
|
|
+ return -ENODEV;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int _omap_dss_reset(void)
|
|
+{
|
|
+ /* Soft reset */
|
|
+ REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
|
|
+ return _omap_dss_wait_reset();
|
|
+}
|
|
+
|
|
+void dss_set_venc_output(enum omap_dss_venc_type type)
|
|
+{
|
|
+ int l = 0;
|
|
+
|
|
+ if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
|
|
+ l = 0;
|
|
+ else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
|
|
+ l = 1;
|
|
+ else
|
|
+ BUG();
|
|
+
|
|
+ /* venc out selection. 0 = comp, 1 = svideo */
|
|
+ REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
|
|
+}
|
|
+
|
|
+void dss_set_dac_pwrdn_bgz(bool enable)
|
|
+{
|
|
+ REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
|
|
+}
|
|
+
|
|
+int dss_init(bool skip_init)
|
|
+{
|
|
+ int r;
|
|
+ u32 rev;
|
|
+
|
|
+ dss.base = ioremap(DSS_BASE, DSS_SZ_REGS);
|
|
+ if (!dss.base) {
|
|
+ DSSERR("can't ioremap DSS\n");
|
|
+ r = -ENOMEM;
|
|
+ goto fail0;
|
|
+ }
|
|
+
|
|
+ if (!skip_init) {
|
|
+ /* We need to wait here a bit, otherwise we sometimes start to
|
|
+ * get synclost errors, and after that only power cycle will
|
|
+ * restore DSS functionality. I have no idea why this happens.
|
|
+ * And we have to wait _before_ resetting the DSS, but after
|
|
+ * enabling clocks.
|
|
+ */
|
|
+ msleep(50);
|
|
+
|
|
+ _omap_dss_reset();
|
|
+
|
|
+ }
|
|
+ else
|
|
+ printk("DSS SKIP RESET\n");
|
|
+
|
|
+ /* autoidle */
|
|
+ REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
|
|
+
|
|
+ /* Select DPLL */
|
|
+ REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
|
|
+
|
|
+#ifdef CONFIG_OMAP2_DSS_VENC
|
|
+ REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
|
|
+ REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
|
|
+ REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
|
|
+#endif
|
|
+
|
|
+ r = request_irq(INT_24XX_DSS_IRQ,
|
|
+ cpu_is_omap24xx()
|
|
+ ? dss_irq_handler_omap2
|
|
+ : dss_irq_handler_omap3,
|
|
+ 0, "OMAP DSS", NULL);
|
|
+
|
|
+ if (r < 0) {
|
|
+ DSSERR("omap2 dss: request_irq failed\n");
|
|
+ goto fail1;
|
|
+ }
|
|
+
|
|
+ dss_save_context();
|
|
+
|
|
+ rev = dss_read_reg(DSS_REVISION);
|
|
+ printk(KERN_INFO "OMAP DSS rev %d.%d\n",
|
|
+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
|
|
+
|
|
+ return 0;
|
|
+
|
|
+fail1:
|
|
+ iounmap(dss.base);
|
|
+fail0:
|
|
+ return r;
|
|
+}
|
|
+
|
|
+void dss_exit(void)
|
|
+{
|
|
+ free_irq(INT_24XX_DSS_IRQ, NULL);
|
|
+
|
|
+ iounmap(dss.base);
|
|
+}
|
|
+
|
|
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
|
|
new file mode 100644
|
|
index 0000000..bac5ece
|
|
--- /dev/null
|
|
+++ b/drivers/video/omap2/dss/dss.h
|
|
@@ -0,0 +1,331 @@
|
|
+/*
|
|
+ * linux/drivers/video/omap2/dss/dss.h
|
|
+ *
|
|
+ * Copyright (C) 2009 Nokia Corporation
|
|
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
|
|
+ *
|
|
+ * Some code and ideas taken from drivers/video/omap/ driver
|
|
+ * by Imre Deak.
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published by
|
|
+ * the Free Software Foundation.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful, but WITHOUT
|
|
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
+ * more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License along with
|
|
+ * this program. If not, see <http://www.gnu.org/licenses/>.
|
|
+ */
|
|
+
|
|
+#ifndef __OMAP2_DSS_H
|
|
+#define __OMAP2_DSS_H
|
|
+
|
|
+#ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
|
|
+#define DEBUG
|
|
+#endif
|
|
+
|
|
+#ifdef DEBUG
|
|
+extern unsigned int dss_debug;
|
|
+#ifdef DSS_SUBSYS_NAME
|
|
+#define DSSDBG(format, ...) \
|
|
+ if (dss_debug) \
|
|
+ printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
|
|
+ ## __VA_ARGS__)
|
|
+#else
|
|
+#define DSSDBG(format, ...) \
|
|
+ if (dss_debug) \
|
|
+ printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
|
|
+#endif
|
|
+
|
|
+#ifdef DSS_SUBSYS_NAME
|
|
+#define DSSDBGF(format, ...) \
|
|
+ if (dss_debug) \
|
|
+ printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
|
|
+ ": %s(" format ")\n", \
|
|
+ __func__, \
|
|
+ ## __VA_ARGS__)
|
|
+#else
|
|
+#define DSSDBGF(format, ...) \
|
|
+ if (dss_debug) \
|
|
+ printk(KERN_DEBUG "omapdss: " \
|
|
+ ": %s(" format ")\n", \
|
|
+ __func__, \
|
|
+ ## __VA_ARGS__)
|
|
+#endif
|
|
+
|
|
+#else /* DEBUG */
|
|
+#define DSSDBG(format, ...)
|
|
+#define DSSDBGF(format, ...)
|
|
+#endif
|
|
+
|
|
+
|
|
+#ifdef DSS_SUBSYS_NAME
|
|
+#define DSSERR(format, ...) \
|
|
+ printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
|
|
+ ## __VA_ARGS__)
|
|
+#else
|
|
+#define DSSERR(format, ...) \
|
|
+ printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
|
|
+#endif
|
|
+
|
|
+#ifdef DSS_SUBSYS_NAME
|
|
+#define DSSINFO(format, ...) \
|
|
+ printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
|
|
+ ## __VA_ARGS__)
|
|
+#else
|
|
+#define DSSINFO(format, ...) \
|
|
+ printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
|
|
+#endif
|
|
+
|
|
+#ifdef DSS_SUBSYS_NAME
|
|
+#define DSSWARN(format, ...) \
|
|
+ printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
|
|
+ ## __VA_ARGS__)
|
|
+#else
|
|
+#define DSSWARN(format, ...) \
|
|
+ printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
|
|
+#endif
|
|
+
|
|
+/* OMAP TRM gives bitfields as start:end, where start is the higher bit
|
|
+ number. For example 7:0 */
|
|
+#define FLD_MASK(start, end) (((1 << (start - end + 1)) - 1) << (end))
|
|
+#define FLD_VAL(val, start, end) (((val) << end) & FLD_MASK(start, end))
|
|
+#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
|
|
+#define FLD_MOD(orig, val, start, end) \
|
|
+ (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
|
|
+
|
|
+#define DISPC_MAX_FCK 173000000
|
|
+
|
|
+enum omap_burst_size {
|
|
+ OMAP_DSS_BURST_4x32 = 0,
|
|
+ OMAP_DSS_BURST_8x32 = 1,
|
|
+ OMAP_DSS_BURST_16x32 = 2,
|
|
+};
|
|
+
|
|
+enum omap_parallel_interface_mode {
|
|
+ OMAP_DSS_PARALLELMODE_BYPASS, /* MIPI DPI */
|
|
+ OMAP_DSS_PARALLELMODE_RFBI, /* MIPI DBI */
|
|
+ OMAP_DSS_PARALLELMODE_DSI,
|
|
+};
|
|
+
|
|
+enum dss_clock {
|
|
+ DSS_CLK_ICK = 1 << 0,
|
|
+ DSS_CLK_FCK1 = 1 << 1,
|
|
+ DSS_CLK_FCK2 = 1 << 2,
|
|
+ DSS_CLK_54M = 1 << 3,
|
|
+ DSS_CLK_96M = 1 << 4,
|
|
+};
|
|
+
|
|
+struct dispc_clock_info {
|
|
+ /* rates that we get with dividers below */
|
|
+ unsigned long fck;
|
|
+ unsigned long lck;
|
|
+ unsigned long pck;
|
|
+
|
|
+ /* dividers */
|
|
+ u16 fck_div;
|
|
+ u16 lck_div;
|
|
+ u16 pck_div;
|
|
+};
|
|
+
|
|
+struct dsi_clock_info {
|
|
+ /* rates that we get with dividers below */
|
|
+ unsigned long fint;
|
|
+ unsigned long dsiphy;
|
|
+ unsigned long clkin;
|
|
+ unsigned long dsi1_pll_fclk;
|
|
+ unsigned long dsi2_pll_fclk;
|
|
+ unsigned long lck;
|
|
+ unsigned long pck;
|
|
+
|
|
+ /* dividers */
|
|
+ u16 regn;
|
|
+ u16 regm;
|
|
+ u16 regm3;
|
|
+ u16 regm4;
|
|
+
|
|
+ u16 lck_div;
|
|
+ u16 pck_div;
|
|
+
|
|
+ u8 highfreq;
|
|
+ bool use_dss2_fck;
|
|
+};
|
|
+
|
|
+struct seq_file;
|
|
+struct platform_device;
|
|
+
|
|
+/* core */
|
|
+void dss_clk_enable(enum dss_clock clks);
|
|
+void dss_clk_disable(enum dss_clock clks);
|
|
+unsigned long dss_clk_get_rate(enum dss_clock clk);
|
|
+int dss_need_ctx_restore(void);
|
|
+void dss_dump_clocks(struct seq_file *s);
|
|
+
|
|
+int dss_dsi_power_up(void);
|
|
+void dss_dsi_power_down(void);
|
|
+
|
|
+/* display */
|
|
+void dss_init_displays(struct platform_device *pdev);
|
|
+void dss_uninit_displays(struct platform_device *pdev);
|
|
+int dss_suspend_all_displays(void);
|
|
+int dss_resume_all_displays(void);
|
|
+struct omap_display *dss_get_display(int no);
|
|
+
|
|
+/* manager */
|
|
+int dss_init_overlay_managers(struct platform_device *pdev);
|
|
+void dss_uninit_overlay_managers(struct platform_device *pdev);
|
|
+
|
|
+/* overlay */
|
|
+void dss_init_overlays(struct platform_device *pdev, const char *def_disp_name);
|
|
+void dss_uninit_overlays(struct platform_device *pdev);
|
|
+int dss_check_overlay(struct omap_overlay *ovl, struct omap_display *display);
|
|
+void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
|
|
+
|
|
+/* DSS */
|
|
+int dss_init(bool skip_init);
|
|
+void dss_exit(void);
|
|
+
|
|
+void dss_save_context(void);
|
|
+void dss_restore_context(void);
|
|
+
|
|
+void dss_dump_regs(struct seq_file *s);
|
|
+
|
|
+void dss_sdi_init(u8 datapairs);
|
|
+void dss_sdi_enable(void);
|
|
+void dss_sdi_disable(void);
|
|
+
|
|
+void dss_select_clk_source(bool dsi, bool dispc);
|
|
+int dss_get_dsi_clk_source(void);
|
|
+int dss_get_dispc_clk_source(void);
|
|
+void dss_set_venc_output(enum omap_dss_venc_type type);
|
|
+void dss_set_dac_pwrdn_bgz(bool enable);
|
|
+
|
|
+/* SDI */
|
|
+int sdi_init(bool skip_init);
|
|
+void sdi_exit(void);
|
|
+void sdi_init_display(struct omap_display *display);
|
|
+
|
|
+/* DSI */
|
|
+int dsi_init(void);
|
|
+void dsi_exit(void);
|
|
+
|
|
+void dsi_dump_clocks(struct seq_file *s);
|
|
+void dsi_dump_regs(struct seq_file *s);
|
|
+
|
|
+void dsi_save_context(void);
|
|
+void dsi_restore_context(void);
|
|
+
|
|
+void dsi_init_display(struct omap_display *display);
|
|
+void dsi_irq_handler(void);
|
|
+unsigned long dsi_get_dsi1_pll_rate(void);
|
|
+unsigned long dsi_get_dsi2_pll_rate(void);
|
|
+int dsi_pll_calc_pck(bool is_tft, unsigned long req_pck,
|
|
+ struct dsi_clock_info *cinfo);
|
|
+int dsi_pll_program(struct dsi_clock_info *cinfo);
|
|
+int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv);
|
|
+void dsi_pll_uninit(void);
|
|
+
|
|
+/* DPI */
|
|
+int dpi_init(void);
|
|
+void dpi_exit(void);
|
|
+void dpi_init_display(struct omap_display *display);
|
|
+
|
|
+/* DISPC */
|
|
+int dispc_init(void);
|
|
+void dispc_exit(void);
|
|
+void dispc_dump_clocks(struct seq_file *s);
|
|
+void dispc_dump_regs(struct seq_file *s);
|
|
+void dispc_irq_handler(void);
|
|
+void dispc_fake_vsync_irq(void);
|
|
+
|
|
+void dispc_save_context(void);
|
|
+void dispc_restore_context(void);
|
|
+
|
|
+void dispc_lcd_enable_signal_polarity(bool act_high);
|
|
+void dispc_lcd_enable_signal(bool enable);
|
|
+void dispc_pck_free_enable(bool enable);
|
|
+void dispc_enable_fifohandcheck(bool enable);
|
|
+
|
|
+void dispc_set_lcd_size(u16 width, u16 height);
|
|
+void dispc_set_digit_size(u16 width, u16 height);
|
|
+u32 dispc_get_plane_fifo_size(enum omap_plane plane);
|
|
+void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high);
|
|
+void dispc_enable_fifomerge(bool enable);
|
|
+void dispc_set_burst_size(enum omap_plane plane,
|
|
+ enum omap_burst_size burst_size);
|
|
+
|
|
+void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr);
|
|
+void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr);
|
|
+void dispc_set_plane_pos(enum omap_plane plane, u16 x, u16 y);
|
|
+void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height);
|
|
+
|
|
+int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
|
|
+ u32 paddr, u16 screen_width,
|
|
+ u16 pos_x, u16 pos_y,
|
|
+ u16 width, u16 height,
|
|
+ u16 out_width, u16 out_height,
|
|
+ enum omap_color_mode color_mode,
|
|
+ bool ilace,
|
|
+ u8 rotation, bool mirror);
|
|
+
|
|
+void dispc_go(enum omap_channel channel);
|
|
+void dispc_enable_lcd_out(bool enable);
|
|
+void dispc_enable_digit_out(bool enable);
|
|
+int dispc_enable_plane(enum omap_plane plane, bool enable);
|
|
+
|
|
+void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode);
|
|
+void dispc_set_tft_data_lines(u8 data_lines);
|
|
+void dispc_set_lcd_display_type(enum omap_lcd_display_type type);
|
|
+void dispc_set_loadmode(enum omap_dss_load_mode mode);
|
|
+
|
|
+void dispc_set_default_color(enum omap_channel channel, u32 color);
|
|
+u32 dispc_get_default_color(enum omap_channel channel);
|
|
+void dispc_set_trans_key(enum omap_channel ch,
|
|
+ enum omap_dss_color_key_type type,
|
|
+ u32 trans_key);
|
|
+void dispc_get_trans_key(enum omap_channel ch,
|
|
+ enum omap_dss_color_key_type *type,
|
|
+ u32 *trans_key);
|
|
+void dispc_enable_trans_key(enum omap_channel ch, bool enable);
|
|
+bool dispc_trans_key_enabled(enum omap_channel ch);
|
|
+
|
|
+void dispc_set_lcd_timings(struct omap_video_timings *timings);
|
|
+unsigned long dispc_fclk_rate(void);
|
|
+unsigned long dispc_pclk_rate(void);
|
|
+void dispc_set_pol_freq(struct omap_panel *panel);
|
|
+void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
|
|
+ u16 *lck_div, u16 *pck_div);
|
|
+int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
|
|
+ struct dispc_clock_info *cinfo);
|
|
+int dispc_set_clock_div(struct dispc_clock_info *cinfo);
|
|
+int dispc_get_clock_div(struct dispc_clock_info *cinfo);
|
|
+void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div);
|
|
+
|
|
+void dispc_setup_partial_planes(struct omap_display *display,
|
|
+ u16 *x, u16 *y, u16 *w, u16 *h);
|
|
+void dispc_draw_partial_planes(struct omap_display *display);
|
|
+
|
|
+
|
|
+/* VENC */
|
|
+int venc_init(void);
|
|
+void venc_exit(void);
|
|
+void venc_dump_regs(struct seq_file *s);
|
|
+void venc_init_display(struct omap_display *display);
|
|
+
|
|
+/* RFBI */
|
|
+int rfbi_init(void);
|
|
+void rfbi_exit(void);
|
|
+void rfbi_dump_regs(struct seq_file *s);
|
|
+
|
|
+int rfbi_configure(int rfbi_module, int bpp, int lines);
|
|
+void rfbi_enable_rfbi(bool enable);
|
|
+void rfbi_transfer_area(u16 width, u16 height,
|
|
+ void (callback)(void *data), void *data);
|
|
+void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t);
|
|
+unsigned long rfbi_get_max_tx_rate(void);
|
|
+void rfbi_init_display(struct omap_display *display);
|
|
+
|
|
+#endif
|
|
diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
|
|
new file mode 100644
|
|
index 0000000..b0fee80
|
|
--- /dev/null
|
|
+++ b/drivers/video/omap2/dss/manager.c
|
|
@@ -0,0 +1,576 @@
|
|
+/*
|
|
+ * linux/drivers/video/omap2/dss/manager.c
|
|
+ *
|
|
+ * Copyright (C) 2009 Nokia Corporation
|
|
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
|
|
+ *
|
|
+ * Some code and ideas taken from drivers/video/omap/ driver
|
|
+ * by Imre Deak.
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published by
|
|
+ * the Free Software Foundation.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful, but WITHOUT
|
|
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
+ * more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License along with
|
|
+ * this program. If not, see <http://www.gnu.org/licenses/>.
|
|
+ */
|
|
+
|
|
+#define DSS_SUBSYS_NAME "MANAGER"
|
|
+
|
|
+#include <linux/kernel.h>
|
|
+#include <linux/module.h>
|
|
+#include <linux/platform_device.h>
|
|
+
|
|
+#include <mach/display.h>
|
|
+
|
|
+#include "dss.h"
|
|
+
|
|
+static int num_managers;
|
|
+static struct list_head manager_list;
|
|
+
|
|
+static ssize_t manager_name_show(struct omap_overlay_manager *mgr, char *buf)
|
|
+{
|
|
+ return snprintf(buf, PAGE_SIZE, "%s\n", mgr->name);
|
|
+}
|
|
+
|
|
+static ssize_t manager_display_show(struct omap_overlay_manager *mgr, char *buf)
|
|
+{
|
|
+ return snprintf(buf, PAGE_SIZE, "%s\n",
|
|
+ mgr->display ? mgr->display->name : "<none>");
|
|
+}
|
|
+
|
|
+static ssize_t manager_display_store(struct omap_overlay_manager *mgr, const char *buf, size_t size)
|
|
+{
|
|
+ int r, i;
|
|
+ int len = size;
|
|
+ struct omap_display *display = NULL;
|
|
+
|
|
+ if (buf[size-1] == '\n')
|
|
+ --len;
|
|
+
|
|
+ if (len > 0) {
|
|
+ for (i = 0; i < omap_dss_get_num_displays(); ++i) {
|
|
+ display = dss_get_display(i);
|
|
+
|
|
+ if (strncmp(buf, display->name, len) == 0)
|
|
+ break;
|
|
+
|
|
+ display = NULL;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (len > 0 && display == NULL)
|
|
+ return -EINVAL;
|
|
+
|
|
+ if (display)
|
|
+ DSSDBG("display %s found\n", display->name);
|
|
+
|
|
+ if (mgr->display) {
|
|
+ r = mgr->unset_display(mgr);
|
|
+ if (r) {
|
|
+ DSSERR("failed to unset display\n");
|
|
+ return r;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (display) {
|
|
+ r = mgr->set_display(mgr, display);
|
|
+ if (r) {
|
|
+ DSSERR("failed to set manager\n");
|
|
+ return r;
|
|
+ }
|
|
+
|
|
+ r = mgr->apply(mgr);
|
|
+ if (r) {
|
|
+ DSSERR("failed to apply dispc config\n");
|
|
+ return r;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ return size;
|
|
+}
|
|
+
|
|
+static ssize_t manager_default_color_show(struct omap_overlay_manager *mgr,
|
|
+ char *buf)
|
|
+{
|
|
+ u32 default_color;
|
|
+
|
|
+ default_color = dispc_get_default_color(mgr->id);
|
|
+ return snprintf(buf, PAGE_SIZE, "%d", default_color);
|
|
+}
|
|
+
|
|
+static ssize_t manager_default_color_store(struct omap_overlay_manager *mgr,
|
|
+ const char *buf, size_t size)
|
|
+{
|
|
+ u32 default_color;
|
|
+
|
|
+ if (sscanf(buf, "%d", &default_color) != 1)
|
|
+ return -EINVAL;
|
|
+ dispc_set_default_color(mgr->id, default_color);
|
|
+
|
|
+ return size;
|
|
+}
|
|
+
|
|
+static const char *color_key_type_str[] = {
|
|
+ "gfx-destination",
|
|
+ "video-source",
|
|
+};
|
|
+
|
|
+static ssize_t manager_color_key_type_show(struct omap_overlay_manager *mgr,
|
|
+ char *buf)
|
|
+{
|
|
+ enum omap_dss_color_key_type key_type;
|
|
+
|
|
+ dispc_get_trans_key(mgr->id, &key_type, NULL);
|
|
+ BUG_ON(key_type >= ARRAY_SIZE(color_key_type_str));
|
|
+
|
|
+ return snprintf(buf, PAGE_SIZE, "%s\n", color_key_type_str[key_type]);
|
|
+}
|
|
+
|
|
+static ssize_t manager_color_key_type_store(struct omap_overlay_manager *mgr,
|
|
+ const char *buf, size_t size)
|
|
+{
|
|
+ enum omap_dss_color_key_type key_type;
|
|
+ u32 key_value;
|
|
+
|
|
+ for (key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
|
|
+ key_type < ARRAY_SIZE(color_key_type_str); key_type++) {
|
|
+ if (sysfs_streq(buf, color_key_type_str[key_type]))
|
|
+ break;
|
|
+ }
|
|
+ if (key_type == ARRAY_SIZE(color_key_type_str))
|
|
+ return -EINVAL;
|
|
+ dispc_get_trans_key(mgr->id, NULL, &key_value);
|
|
+ dispc_set_trans_key(mgr->id, key_type, key_value);
|
|
+
|
|
+ return size;
|
|
+}
|
|
+
|
|
+static ssize_t manager_color_key_value_show(struct omap_overlay_manager *mgr,
|
|
+ char *buf)
|
|
+{
|
|
+ u32 key_value;
|
|
+
|
|
+ dispc_get_trans_key(mgr->id, NULL, &key_value);
|
|
+
|
|
+ return snprintf(buf, PAGE_SIZE, "%d\n", key_value);
|
|
+}
|
|
+
|
|
+static ssize_t manager_color_key_value_store(struct omap_overlay_manager *mgr,
|
|
+ const char *buf, size_t size)
|
|
+{
|
|
+ enum omap_dss_color_key_type key_type;
|
|
+ u32 key_value;
|
|
+
|
|
+ if (sscanf(buf, "%d", &key_value) != 1)
|
|
+ return -EINVAL;
|
|
+ dispc_get_trans_key(mgr->id, &key_type, NULL);
|
|
+ dispc_set_trans_key(mgr->id, key_type, key_value);
|
|
+
|
|
+ return size;
|
|
+}
|
|
+
|
|
+static ssize_t manager_color_key_enabled_show(struct omap_overlay_manager *mgr,
|
|
+ char *buf)
|
|
+{
|
|
+ return snprintf(buf, PAGE_SIZE, "%d\n",
|
|
+ dispc_trans_key_enabled(mgr->id));
|
|
+}
|
|
+
|
|
+static ssize_t manager_color_key_enabled_store(struct omap_overlay_manager *mgr,
|
|
+ const char *buf, size_t size)
|
|
+{
|
|
+ int enable;
|
|
+
|
|
+ if (sscanf(buf, "%d", &enable) != 1)
|
|
+ return -EINVAL;
|
|
+
|
|
+ dispc_enable_trans_key(mgr->id, enable);
|
|
+
|
|
+ return size;
|
|
+}
|
|
+
|
|
+
|
|
+struct manager_attribute {
|
|
+ struct attribute attr;
|
|
+ ssize_t (*show)(struct omap_overlay_manager *, char *);
|
|
+ ssize_t (*store)(struct omap_overlay_manager *, const char *, size_t);
|
|
+};
|
|
+
|
|
+#define MANAGER_ATTR(_name, _mode, _show, _store) \
|
|
+ struct manager_attribute manager_attr_##_name = \
|
|
+ __ATTR(_name, _mode, _show, _store)
|
|
+
|
|
+static MANAGER_ATTR(name, S_IRUGO, manager_name_show, NULL);
|
|
+static MANAGER_ATTR(display, S_IRUGO|S_IWUSR,
|
|
+ manager_display_show, manager_display_store);
|
|
+static MANAGER_ATTR(default_color, S_IRUGO|S_IWUSR,
|
|
+ manager_default_color_show, manager_default_color_store);
|
|
+static MANAGER_ATTR(color_key_type, S_IRUGO|S_IWUSR,
|
|
+ manager_color_key_type_show, manager_color_key_type_store);
|
|
+static MANAGER_ATTR(color_key_value, S_IRUGO|S_IWUSR,
|
|
+ manager_color_key_value_show, manager_color_key_value_store);
|
|
+static MANAGER_ATTR(color_key_enabled, S_IRUGO|S_IWUSR,
|
|
+ manager_color_key_enabled_show, manager_color_key_enabled_store);
|
|
+
|
|
+static struct attribute *manager_sysfs_attrs[] = {
|
|
+ &manager_attr_name.attr,
|
|
+ &manager_attr_display.attr,
|
|
+ &manager_attr_default_color.attr,
|
|
+ &manager_attr_color_key_type.attr,
|
|
+ &manager_attr_color_key_value.attr,
|
|
+ &manager_attr_color_key_enabled.attr,
|
|
+ NULL
|
|
+};
|
|
+
|
|
+static ssize_t manager_attr_show(struct kobject *kobj, struct attribute *attr, char *buf)
|
|
+{
|
|
+ struct omap_overlay_manager *manager;
|
|
+ struct manager_attribute *manager_attr;
|
|
+
|
|
+ manager = container_of(kobj, struct omap_overlay_manager, kobj);
|
|
+ manager_attr = container_of(attr, struct manager_attribute, attr);
|
|
+
|
|
+ if (!manager_attr->show)
|
|
+ return -ENOENT;
|
|
+
|
|
+ return manager_attr->show(manager, buf);
|
|
+}
|
|
+
|
|
+static ssize_t manager_attr_store(struct kobject *kobj, struct attribute *attr,
|
|
+ const char *buf, size_t size)
|
|
+{
|
|
+ struct omap_overlay_manager *manager;
|
|
+ struct manager_attribute *manager_attr;
|
|
+
|
|
+ manager = container_of(kobj, struct omap_overlay_manager, kobj);
|
|
+ manager_attr = container_of(attr, struct manager_attribute, attr);
|
|
+
|
|
+ if (!manager_attr->store)
|
|
+ return -ENOENT;
|
|
+
|
|
+ return manager_attr->store(manager, buf, size);
|
|
+}
|
|
+
|
|
+static struct sysfs_ops manager_sysfs_ops = {
|
|
+ .show = manager_attr_show,
|
|
+ .store = manager_attr_store,
|
|
+};
|
|
+
|
|
+static struct kobj_type manager_ktype = {
|
|
+ .sysfs_ops = &manager_sysfs_ops,
|
|
+ .default_attrs = manager_sysfs_attrs,
|
|
+};
|
|
+
|
|
+static int omap_dss_set_display(struct omap_overlay_manager *mgr,
|
|
+ struct omap_display *display)
|
|
+{
|
|
+ int i;
|
|
+ int r;
|
|
+
|
|
+ if (display->manager) {
|
|
+ DSSERR("display '%s' already has a manager '%s'\n",
|
|
+ display->name, display->manager->name);
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ if ((mgr->supported_displays & display->type) == 0) {
|
|
+ DSSERR("display '%s' does not support manager '%s'\n",
|
|
+ display->name, mgr->name);
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ for (i = 0; i < mgr->num_overlays; i++) {
|
|
+ struct omap_overlay *ovl = mgr->overlays[i];
|
|
+
|
|
+ if (ovl->manager != mgr || !ovl->info.enabled)
|
|
+ continue;
|
|
+
|
|
+ r = dss_check_overlay(ovl, display);
|
|
+ if (r)
|
|
+ return r;
|
|
+ }
|
|
+
|
|
+ display->manager = mgr;
|
|
+ mgr->display = display;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int omap_dss_unset_display(struct omap_overlay_manager *mgr)
|
|
+{
|
|
+ if (!mgr->display) {
|
|
+ DSSERR("failed to unset display, display not set.\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ mgr->display->manager = NULL;
|
|
+ mgr->display = NULL;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+
|
|
+static int overlay_enabled(struct omap_overlay *ovl)
|
|
+{
|
|
+ return ovl->info.enabled && ovl->manager && ovl->manager->display;
|
|
+}
|
|
+
|
|
+/* We apply settings to both managers here so that we can use optimizations
|
|
+ * like fifomerge. Shadow registers can be changed first and the non-shadowed
|
|
+ * should be changed last, at the same time with GO */
|
|
+static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
|
|
+{
|
|
+ int i;
|
|
+ int ret = 0;
|
|
+ enum omap_dss_update_mode mode;
|
|
+ struct omap_display *display;
|
|
+ struct omap_overlay *ovl;
|
|
+ bool ilace = 0;
|
|
+ int outw, outh;
|
|
+ int r;
|
|
+ int num_planes_enabled = 0;
|
|
+
|
|
+ DSSDBG("omap_dss_mgr_apply(%s)\n", mgr->name);
|
|
+
|
|
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+
|
|
+ /* Configure normal overlay parameters and disable unused overlays */
|
|
+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
|
|
+ ovl = omap_dss_get_overlay(i);
|
|
+
|
|
+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
|
|
+ continue;
|
|
+
|
|
+ if (!overlay_enabled(ovl)) {
|
|
+ dispc_enable_plane(ovl->id, 0);
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+ display = ovl->manager->display;
|
|
+
|
|
+ if (dss_check_overlay(ovl, display)) {
|
|
+ dispc_enable_plane(ovl->id, 0);
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+ ++num_planes_enabled;
|
|
+
|
|
+ /* On a manual update display, in manual update mode, update()
|
|
+ * handles configuring planes */
|
|
+ mode = OMAP_DSS_UPDATE_AUTO;
|
|
+ if (display->get_update_mode)
|
|
+ mode = display->get_update_mode(mgr->display);
|
|
+
|
|
+ if (display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE &&
|
|
+ mode != OMAP_DSS_UPDATE_AUTO)
|
|
+ continue;
|
|
+
|
|
+ if (display->type == OMAP_DISPLAY_TYPE_VENC)
|
|
+ ilace = 1;
|
|
+
|
|
+ if (ovl->info.out_width == 0)
|
|
+ outw = ovl->info.width;
|
|
+ else
|
|
+ outw = ovl->info.out_width;
|
|
+
|
|
+ if (ovl->info.out_height == 0)
|
|
+ outh = ovl->info.height;
|
|
+ else
|
|
+ outh = ovl->info.out_height;
|
|
+
|
|
+ r = dispc_setup_plane(ovl->id, ovl->manager->id,
|
|
+ ovl->info.paddr,
|
|
+ ovl->info.screen_width,
|
|
+ ovl->info.pos_x,
|
|
+ ovl->info.pos_y,
|
|
+ ovl->info.width,
|
|
+ ovl->info.height,
|
|
+ outw,
|
|
+ outh,
|
|
+ ovl->info.color_mode,
|
|
+ ilace,
|
|
+ ovl->info.rotation,
|
|
+ ovl->info.mirror);
|
|
+
|
|
+ if (r) {
|
|
+ DSSERR("dispc_setup_plane failed for ovl %d\n",
|
|
+ ovl->id);
|
|
+ dispc_enable_plane(ovl->id, 0);
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+ dispc_enable_plane(ovl->id, 1);
|
|
+ }
|
|
+
|
|
+ /* Enable fifo merge if possible */
|
|
+ dispc_enable_fifomerge(num_planes_enabled == 1);
|
|
+
|
|
+ /* Go through overlays again. This time we configure fifos. We have to
|
|
+ * do this after enabling/disabling fifomerge so that we have correct
|
|
+ * knowledge of fifo sizes */
|
|
+ for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
|
|
+ ovl = omap_dss_get_overlay(i);
|
|
+
|
|
+ if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
|
|
+ continue;
|
|
+
|
|
+ if (!overlay_enabled(ovl)) {
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+ ovl->manager->display->configure_overlay(ovl);
|
|
+ }
|
|
+
|
|
+ /* Issue GO for managers */
|
|
+ list_for_each_entry(mgr, &manager_list, list) {
|
|
+ if (!(mgr->caps & OMAP_DSS_OVL_MGR_CAP_DISPC))
|
|
+ continue;
|
|
+
|
|
+ display = mgr->display;
|
|
+
|
|
+ if (!display)
|
|
+ continue;
|
|
+
|
|
+ /* We don't need GO with manual update display. LCD iface will
|
|
+ * always be turned off after frame, and new settings will
|
|
+ * be taken in to use at next update */
|
|
+ if (display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE)
|
|
+ continue;
|
|
+
|
|
+ dispc_go(mgr->id);
|
|
+ }
|
|
+
|
|
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static void omap_dss_mgr_set_def_color(struct omap_overlay_manager *mgr,
|
|
+ u32 color)
|
|
+{
|
|
+ dispc_set_default_color(mgr->id, color);
|
|
+}
|
|
+
|
|
+static void omap_dss_mgr_set_trans_key(struct omap_overlay_manager *mgr,
|
|
+ enum omap_dss_color_key_type type,
|
|
+ u32 trans_key)
|
|
+{
|
|
+ dispc_set_trans_key(mgr->id, type, trans_key);
|
|
+}
|
|
+
|
|
+static void omap_dss_mgr_enable_trans_key(struct omap_overlay_manager *mgr,
|
|
+ bool enable)
|
|
+{
|
|
+ dispc_enable_trans_key(mgr->id, enable);
|
|
+}
|
|
+
|
|
+static void omap_dss_add_overlay_manager(struct omap_overlay_manager *manager)
|
|
+{
|
|
+ ++num_managers;
|
|
+ list_add_tail(&manager->list, &manager_list);
|
|
+}
|
|
+
|
|
+int dss_init_overlay_managers(struct platform_device *pdev)
|
|
+{
|
|
+ int i, r;
|
|
+
|
|
+ INIT_LIST_HEAD(&manager_list);
|
|
+
|
|
+ num_managers = 0;
|
|
+
|
|
+ for (i = 0; i < 2; ++i) {
|
|
+ struct omap_overlay_manager *mgr;
|
|
+ mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
|
|
+
|
|
+ BUG_ON(mgr == NULL);
|
|
+
|
|
+ switch (i) {
|
|
+ case 0:
|
|
+ mgr->name = "lcd";
|
|
+ mgr->id = OMAP_DSS_CHANNEL_LCD;
|
|
+ mgr->supported_displays =
|
|
+ OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
|
|
+ OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI;
|
|
+ break;
|
|
+ case 1:
|
|
+ mgr->name = "tv";
|
|
+ mgr->id = OMAP_DSS_CHANNEL_DIGIT;
|
|
+ mgr->supported_displays = OMAP_DISPLAY_TYPE_VENC;
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ mgr->set_display = &omap_dss_set_display,
|
|
+ mgr->unset_display = &omap_dss_unset_display,
|
|
+ mgr->apply = &omap_dss_mgr_apply,
|
|
+ mgr->set_default_color = &omap_dss_mgr_set_def_color,
|
|
+ mgr->set_trans_key = &omap_dss_mgr_set_trans_key,
|
|
+ mgr->enable_trans_key = &omap_dss_mgr_enable_trans_key,
|
|
+ mgr->caps = OMAP_DSS_OVL_MGR_CAP_DISPC,
|
|
+
|
|
+ dss_overlay_setup_dispc_manager(mgr);
|
|
+
|
|
+ omap_dss_add_overlay_manager(mgr);
|
|
+
|
|
+ r = kobject_init_and_add(&mgr->kobj, &manager_ktype,
|
|
+ &pdev->dev.kobj, "manager%d", i);
|
|
+
|
|
+ if (r) {
|
|
+ DSSERR("failed to create sysfs file\n");
|
|
+ continue;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+void dss_uninit_overlay_managers(struct platform_device *pdev)
|
|
+{
|
|
+ struct omap_overlay_manager *mgr;
|
|
+
|
|
+ while (!list_empty(&manager_list)) {
|
|
+ mgr = list_first_entry(&manager_list,
|
|
+ struct omap_overlay_manager, list);
|
|
+ list_del(&mgr->list);
|
|
+ kobject_del(&mgr->kobj);
|
|
+ kobject_put(&mgr->kobj);
|
|
+ kfree(mgr);
|
|
+ }
|
|
+
|
|
+ num_managers = 0;
|
|
+}
|
|
+
|
|
+int omap_dss_get_num_overlay_managers(void)
|
|
+{
|
|
+ return num_managers;
|
|
+}
|
|
+EXPORT_SYMBOL(omap_dss_get_num_overlay_managers);
|
|
+
|
|
+struct omap_overlay_manager *omap_dss_get_overlay_manager(int num)
|
|
+{
|
|
+ int i = 0;
|
|
+ struct omap_overlay_manager *mgr;
|
|
+
|
|
+ list_for_each_entry(mgr, &manager_list, list) {
|
|
+ if (i++ == num)
|
|
+ return mgr;
|
|
+ }
|
|
+
|
|
+ return NULL;
|
|
+}
|
|
+EXPORT_SYMBOL(omap_dss_get_overlay_manager);
|
|
+
|
|
+#ifdef L4_EXAMPLE
|
|
+static int ovl_mgr_apply_l4(struct omap_overlay_manager *mgr)
|
|
+{
|
|
+ DSSDBG("omap_dss_mgr_apply_l4(%s)\n", mgr->name);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+#endif
|
|
+
|
|
diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
|
|
new file mode 100644
|
|
index 0000000..968edbe
|
|
--- /dev/null
|
|
+++ b/drivers/video/omap2/dss/overlay.c
|
|
@@ -0,0 +1,587 @@
|
|
+/*
|
|
+ * linux/drivers/video/omap2/dss/overlay.c
|
|
+ *
|
|
+ * Copyright (C) 2009 Nokia Corporation
|
|
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
|
|
+ *
|
|
+ * Some code and ideas taken from drivers/video/omap/ driver
|
|
+ * by Imre Deak.
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published by
|
|
+ * the Free Software Foundation.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful, but WITHOUT
|
|
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
+ * more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License along with
|
|
+ * this program. If not, see <http://www.gnu.org/licenses/>.
|
|
+ */
|
|
+
|
|
+#define DSS_SUBSYS_NAME "OVERLAY"
|
|
+
|
|
+#include <linux/kernel.h>
|
|
+#include <linux/module.h>
|
|
+#include <linux/err.h>
|
|
+#include <linux/sysfs.h>
|
|
+#include <linux/kobject.h>
|
|
+#include <linux/platform_device.h>
|
|
+
|
|
+#include <mach/display.h>
|
|
+
|
|
+#include "dss.h"
|
|
+
|
|
+static int num_overlays;
|
|
+static struct list_head overlay_list;
|
|
+
|
|
+static ssize_t overlay_name_show(struct omap_overlay *ovl, char *buf)
|
|
+{
|
|
+ return snprintf(buf, PAGE_SIZE, "%s\n", ovl->name);
|
|
+}
|
|
+
|
|
+static ssize_t overlay_manager_show(struct omap_overlay *ovl, char *buf)
|
|
+{
|
|
+ return snprintf(buf, PAGE_SIZE, "%s\n",
|
|
+ ovl->manager ? ovl->manager->name : "<none>");
|
|
+}
|
|
+
|
|
+static ssize_t overlay_manager_store(struct omap_overlay *ovl, const char *buf, size_t size)
|
|
+{
|
|
+ int i, r;
|
|
+ struct omap_overlay_manager *mgr = NULL;
|
|
+ int len = size;
|
|
+
|
|
+ if (buf[size-1] == '\n')
|
|
+ --len;
|
|
+
|
|
+ if (len > 0) {
|
|
+ for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
|
|
+ mgr = omap_dss_get_overlay_manager(i);
|
|
+
|
|
+ if (strncmp(buf, mgr->name, len) == 0)
|
|
+ break;
|
|
+
|
|
+ mgr = NULL;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (len > 0 && mgr == NULL)
|
|
+ return -EINVAL;
|
|
+
|
|
+ if (mgr)
|
|
+ DSSDBG("manager %s found\n", mgr->name);
|
|
+
|
|
+ if (mgr != ovl->manager) {
|
|
+ /* detach old manager */
|
|
+ if (ovl->manager) {
|
|
+ r = ovl->unset_manager(ovl);
|
|
+ if (r) {
|
|
+ DSSERR("detach failed\n");
|
|
+ return r;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (mgr) {
|
|
+ r = ovl->set_manager(ovl, mgr);
|
|
+ if (r) {
|
|
+ DSSERR("Failed to attach overlay\n");
|
|
+ return r;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
|
|
+ return r;
|
|
+
|
|
+ return size;
|
|
+}
|
|
+
|
|
+static ssize_t overlay_input_size_show(struct omap_overlay *ovl, char *buf)
|
|
+{
|
|
+ return snprintf(buf, PAGE_SIZE, "%d,%d\n",
|
|
+ ovl->info.width, ovl->info.height);
|
|
+}
|
|
+
|
|
+static ssize_t overlay_screen_width_show(struct omap_overlay *ovl, char *buf)
|
|
+{
|
|
+ return snprintf(buf, PAGE_SIZE, "%d\n", ovl->info.screen_width);
|
|
+}
|
|
+
|
|
+static ssize_t overlay_position_show(struct omap_overlay *ovl, char *buf)
|
|
+{
|
|
+ return snprintf(buf, PAGE_SIZE, "%d,%d\n",
|
|
+ ovl->info.pos_x, ovl->info.pos_y);
|
|
+}
|
|
+
|
|
+static ssize_t overlay_position_store(struct omap_overlay *ovl,
|
|
+ const char *buf, size_t size)
|
|
+{
|
|
+ int r;
|
|
+ char *last;
|
|
+ struct omap_overlay_info info;
|
|
+
|
|
+ ovl->get_overlay_info(ovl, &info);
|
|
+
|
|
+ info.pos_x = simple_strtoul(buf, &last, 10);
|
|
+ ++last;
|
|
+ if (last - buf >= size)
|
|
+ return -EINVAL;
|
|
+
|
|
+ info.pos_y = simple_strtoul(last, &last, 10);
|
|
+
|
|
+ if ((r = ovl->set_overlay_info(ovl, &info)))
|
|
+ return r;
|
|
+
|
|
+ if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
|
|
+ return r;
|
|
+
|
|
+ return size;
|
|
+}
|
|
+
|
|
+static ssize_t overlay_output_size_show(struct omap_overlay *ovl, char *buf)
|
|
+{
|
|
+ return snprintf(buf, PAGE_SIZE, "%d,%d\n",
|
|
+ ovl->info.out_width, ovl->info.out_height);
|
|
+}
|
|
+
|
|
+static ssize_t overlay_output_size_store(struct omap_overlay *ovl,
|
|
+ const char *buf, size_t size)
|
|
+{
|
|
+ int r;
|
|
+ char *last;
|
|
+ struct omap_overlay_info info;
|
|
+
|
|
+ ovl->get_overlay_info(ovl, &info);
|
|
+
|
|
+ info.out_width = simple_strtoul(buf, &last, 10);
|
|
+ ++last;
|
|
+ if (last - buf >= size)
|
|
+ return -EINVAL;
|
|
+
|
|
+ info.out_height = simple_strtoul(last, &last, 10);
|
|
+
|
|
+ if ((r = ovl->set_overlay_info(ovl, &info)))
|
|
+ return r;
|
|
+
|
|
+ if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
|
|
+ return r;
|
|
+
|
|
+ return size;
|
|
+}
|
|
+
|
|
+static ssize_t overlay_enabled_show(struct omap_overlay *ovl, char *buf)
|
|
+{
|
|
+ return snprintf(buf, PAGE_SIZE, "%d\n", ovl->info.enabled);
|
|
+}
|
|
+
|
|
+static ssize_t overlay_enabled_store(struct omap_overlay *ovl, const char *buf, size_t size)
|
|
+{
|
|
+ int r;
|
|
+ struct omap_overlay_info info;
|
|
+
|
|
+ ovl->get_overlay_info(ovl, &info);
|
|
+
|
|
+ info.enabled = simple_strtoul(buf, NULL, 10);
|
|
+
|
|
+ if ((r = ovl->set_overlay_info(ovl, &info)))
|
|
+ return r;
|
|
+
|
|
+ if (ovl->manager && (r = ovl->manager->apply(ovl->manager)))
|
|
+ return r;
|
|
+
|
|
+ return size;
|
|
+}
|
|
+
|
|
+struct overlay_attribute {
|
|
+ struct attribute attr;
|
|
+ ssize_t (*show)(struct omap_overlay *, char *);
|
|
+ ssize_t (*store)(struct omap_overlay *, const char *, size_t);
|
|
+};
|
|
+
|
|
+#define OVERLAY_ATTR(_name, _mode, _show, _store) \
|
|
+ struct overlay_attribute overlay_attr_##_name = \
|
|
+ __ATTR(_name, _mode, _show, _store)
|
|
+
|
|
+static OVERLAY_ATTR(name, S_IRUGO, overlay_name_show, NULL);
|
|
+static OVERLAY_ATTR(manager, S_IRUGO|S_IWUSR,
|
|
+ overlay_manager_show, overlay_manager_store);
|
|
+static OVERLAY_ATTR(input_size, S_IRUGO, overlay_input_size_show, NULL);
|
|
+static OVERLAY_ATTR(screen_width, S_IRUGO, overlay_screen_width_show, NULL);
|
|
+static OVERLAY_ATTR(position, S_IRUGO|S_IWUSR,
|
|
+ overlay_position_show, overlay_position_store);
|
|
+static OVERLAY_ATTR(output_size, S_IRUGO|S_IWUSR,
|
|
+ overlay_output_size_show, overlay_output_size_store);
|
|
+static OVERLAY_ATTR(enabled, S_IRUGO|S_IWUSR,
|
|
+ overlay_enabled_show, overlay_enabled_store);
|
|
+
|
|
+static struct attribute *overlay_sysfs_attrs[] = {
|
|
+ &overlay_attr_name.attr,
|
|
+ &overlay_attr_manager.attr,
|
|
+ &overlay_attr_input_size.attr,
|
|
+ &overlay_attr_screen_width.attr,
|
|
+ &overlay_attr_position.attr,
|
|
+ &overlay_attr_output_size.attr,
|
|
+ &overlay_attr_enabled.attr,
|
|
+ NULL
|
|
+};
|
|
+
|
|
+static ssize_t overlay_attr_show(struct kobject *kobj, struct attribute *attr, char *buf)
|
|
+{
|
|
+ struct omap_overlay *overlay;
|
|
+ struct overlay_attribute *overlay_attr;
|
|
+
|
|
+ overlay = container_of(kobj, struct omap_overlay, kobj);
|
|
+ overlay_attr = container_of(attr, struct overlay_attribute, attr);
|
|
+
|
|
+ if (!overlay_attr->show)
|
|
+ return -ENOENT;
|
|
+
|
|
+ return overlay_attr->show(overlay, buf);
|
|
+}
|
|
+
|
|
+static ssize_t overlay_attr_store(struct kobject *kobj, struct attribute *attr,
|
|
+ const char *buf, size_t size)
|
|
+{
|
|
+ struct omap_overlay *overlay;
|
|
+ struct overlay_attribute *overlay_attr;
|
|
+
|
|
+ overlay = container_of(kobj, struct omap_overlay, kobj);
|
|
+ overlay_attr = container_of(attr, struct overlay_attribute, attr);
|
|
+
|
|
+ if (!overlay_attr->store)
|
|
+ return -ENOENT;
|
|
+
|
|
+ return overlay_attr->store(overlay, buf, size);
|
|
+}
|
|
+
|
|
+static struct sysfs_ops overlay_sysfs_ops = {
|
|
+ .show = overlay_attr_show,
|
|
+ .store = overlay_attr_store,
|
|
+};
|
|
+
|
|
+static struct kobj_type overlay_ktype = {
|
|
+ .sysfs_ops = &overlay_sysfs_ops,
|
|
+ .default_attrs = overlay_sysfs_attrs,
|
|
+};
|
|
+
|
|
+/* Check if overlay parameters are compatible with display */
|
|
+int dss_check_overlay(struct omap_overlay *ovl, struct omap_display *display)
|
|
+{
|
|
+ struct omap_overlay_info *info;
|
|
+ u16 outw, outh;
|
|
+ u16 dw, dh;
|
|
+
|
|
+ if (!display)
|
|
+ return 0;
|
|
+
|
|
+ if (!ovl->info.enabled)
|
|
+ return 0;
|
|
+
|
|
+ info = &ovl->info;
|
|
+
|
|
+ display->get_resolution(display, &dw, &dh);
|
|
+
|
|
+ DSSDBG("check_overlay %d: (%d,%d %dx%d -> %dx%d) disp (%dx%d)\n",
|
|
+ ovl->id,
|
|
+ info->pos_x, info->pos_y,
|
|
+ info->width, info->height,
|
|
+ info->out_width, info->out_height,
|
|
+ dw, dh);
|
|
+
|
|
+ if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
|
|
+ outw = info->width;
|
|
+ outh = info->height;
|
|
+ } else {
|
|
+ if (info->out_width == 0)
|
|
+ outw = info->width;
|
|
+ else
|
|
+ outw = info->out_width;
|
|
+
|
|
+ if (info->out_height == 0)
|
|
+ outh = info->height;
|
|
+ else
|
|
+ outh = info->out_height;
|
|
+ }
|
|
+
|
|
+ if (dw < info->pos_x + outw) {
|
|
+ DSSDBG("check_overlay failed 1: %d < %d + %d\n",
|
|
+ dw, info->pos_x, outw);
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ if (dh < info->pos_y + outh) {
|
|
+ DSSDBG("check_overlay failed 2: %d < %d + %d\n",
|
|
+ dh, info->pos_y, outh);
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ if ((ovl->supported_modes & info->color_mode) == 0) {
|
|
+ DSSERR("overlay doesn't support mode %d\n", info->color_mode);
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int dss_ovl_set_overlay_info(struct omap_overlay *ovl,
|
|
+ struct omap_overlay_info *info)
|
|
+{
|
|
+ int r;
|
|
+ struct omap_overlay_info old_info;
|
|
+
|
|
+ old_info = ovl->info;
|
|
+ ovl->info = *info;
|
|
+
|
|
+ if (ovl->manager) {
|
|
+ r = dss_check_overlay(ovl, ovl->manager->display);
|
|
+ if (r) {
|
|
+ ovl->info = old_info;
|
|
+ return r;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void dss_ovl_get_overlay_info(struct omap_overlay *ovl,
|
|
+ struct omap_overlay_info *info)
|
|
+{
|
|
+ *info = ovl->info;
|
|
+}
|
|
+
|
|
+static int omap_dss_set_manager(struct omap_overlay *ovl,
|
|
+ struct omap_overlay_manager *mgr)
|
|
+{
|
|
+ int r;
|
|
+
|
|
+ if (ovl->manager) {
|
|
+ DSSERR("overlay '%s' already has a manager '%s'\n",
|
|
+ ovl->name, ovl->manager->name);
|
|
+ }
|
|
+
|
|
+ r = dss_check_overlay(ovl, mgr->display);
|
|
+ if (r)
|
|
+ return r;
|
|
+
|
|
+ ovl->manager = mgr;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int omap_dss_unset_manager(struct omap_overlay *ovl)
|
|
+{
|
|
+ if (!ovl->manager) {
|
|
+ DSSERR("failed to detach overlay: manager not set\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ ovl->manager = NULL;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+int omap_dss_get_num_overlays(void)
|
|
+{
|
|
+ return num_overlays;
|
|
+}
|
|
+EXPORT_SYMBOL(omap_dss_get_num_overlays);
|
|
+
|
|
+struct omap_overlay *omap_dss_get_overlay(int num)
|
|
+{
|
|
+ int i = 0;
|
|
+ struct omap_overlay *ovl;
|
|
+
|
|
+ list_for_each_entry(ovl, &overlay_list, list) {
|
|
+ if (i++ == num)
|
|
+ return ovl;
|
|
+ }
|
|
+
|
|
+ return NULL;
|
|
+}
|
|
+EXPORT_SYMBOL(omap_dss_get_overlay);
|
|
+
|
|
+static void omap_dss_add_overlay(struct omap_overlay *overlay)
|
|
+{
|
|
+ ++num_overlays;
|
|
+ list_add_tail(&overlay->list, &overlay_list);
|
|
+}
|
|
+
|
|
+static struct omap_overlay *dispc_overlays[3];
|
|
+
|
|
+void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr)
|
|
+{
|
|
+ mgr->num_overlays = 3;
|
|
+ mgr->overlays = dispc_overlays;
|
|
+}
|
|
+
|
|
+void dss_init_overlays(struct platform_device *pdev, const char *def_disp_name)
|
|
+{
|
|
+ int i, r;
|
|
+ struct omap_overlay_manager *lcd_mgr;
|
|
+ struct omap_overlay_manager *tv_mgr;
|
|
+ struct omap_overlay_manager *def_mgr = NULL;
|
|
+
|
|
+ INIT_LIST_HEAD(&overlay_list);
|
|
+
|
|
+ num_overlays = 0;
|
|
+
|
|
+ for (i = 0; i < 3; ++i) {
|
|
+ struct omap_overlay *ovl;
|
|
+ ovl = kzalloc(sizeof(*ovl), GFP_KERNEL);
|
|
+
|
|
+ BUG_ON(ovl == NULL);
|
|
+
|
|
+ switch (i) {
|
|
+ case 0:
|
|
+ ovl->name = "gfx";
|
|
+ ovl->id = OMAP_DSS_GFX;
|
|
+ ovl->supported_modes = OMAP_DSS_COLOR_GFX_OMAP3;
|
|
+ ovl->caps = OMAP_DSS_OVL_CAP_DISPC;
|
|
+ break;
|
|
+ case 1:
|
|
+ ovl->name = "vid1";
|
|
+ ovl->id = OMAP_DSS_VIDEO1;
|
|
+ ovl->supported_modes = OMAP_DSS_COLOR_VID_OMAP3;
|
|
+ ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
|
|
+ OMAP_DSS_OVL_CAP_DISPC;
|
|
+ break;
|
|
+ case 2:
|
|
+ ovl->name = "vid2";
|
|
+ ovl->id = OMAP_DSS_VIDEO2;
|
|
+ ovl->supported_modes = OMAP_DSS_COLOR_VID_OMAP3;
|
|
+ ovl->caps = OMAP_DSS_OVL_CAP_SCALE |
|
|
+ OMAP_DSS_OVL_CAP_DISPC;
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ ovl->set_manager = &omap_dss_set_manager;
|
|
+ ovl->unset_manager = &omap_dss_unset_manager;
|
|
+ ovl->set_overlay_info = &dss_ovl_set_overlay_info;
|
|
+ ovl->get_overlay_info = &dss_ovl_get_overlay_info;
|
|
+
|
|
+ omap_dss_add_overlay(ovl);
|
|
+
|
|
+ r = kobject_init_and_add(&ovl->kobj, &overlay_ktype,
|
|
+ &pdev->dev.kobj, "overlay%d", i);
|
|
+
|
|
+ if (r) {
|
|
+ DSSERR("failed to create sysfs file\n");
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+ dispc_overlays[i] = ovl;
|
|
+ }
|
|
+
|
|
+ lcd_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_LCD);
|
|
+ tv_mgr = omap_dss_get_overlay_manager(OMAP_DSS_OVL_MGR_TV);
|
|
+
|
|
+ if (def_disp_name) {
|
|
+ for (i = 0; i < omap_dss_get_num_displays() ; i++) {
|
|
+ struct omap_display *display = dss_get_display(i);
|
|
+
|
|
+ if (strcmp(display->name, def_disp_name) == 0) {
|
|
+ if (display->type != OMAP_DISPLAY_TYPE_VENC) {
|
|
+ lcd_mgr->set_display(lcd_mgr, display);
|
|
+ def_mgr = lcd_mgr;
|
|
+ } else {
|
|
+ lcd_mgr->set_display(tv_mgr, display);
|
|
+ def_mgr = tv_mgr;
|
|
+ }
|
|
+
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (!def_mgr)
|
|
+ DSSWARN("default display %s not found\n",
|
|
+ def_disp_name);
|
|
+ }
|
|
+
|
|
+ if (def_mgr != lcd_mgr) {
|
|
+ /* connect lcd manager to first non-VENC display found */
|
|
+ for (i = 0; i < omap_dss_get_num_displays(); i++) {
|
|
+ struct omap_display *display = dss_get_display(i);
|
|
+ if (display->type != OMAP_DISPLAY_TYPE_VENC) {
|
|
+ lcd_mgr->set_display(lcd_mgr, display);
|
|
+
|
|
+ if (!def_mgr)
|
|
+ def_mgr = lcd_mgr;
|
|
+
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (def_mgr != tv_mgr) {
|
|
+ /* connect tv manager to first VENC display found */
|
|
+ for (i = 0; i < omap_dss_get_num_displays(); i++) {
|
|
+ struct omap_display *display = dss_get_display(i);
|
|
+ if (display->type == OMAP_DISPLAY_TYPE_VENC) {
|
|
+ tv_mgr->set_display(tv_mgr, display);
|
|
+
|
|
+ if (!def_mgr)
|
|
+ def_mgr = tv_mgr;
|
|
+
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
|
+ /* connect all dispc overlays to def_mgr */
|
|
+ if (def_mgr) {
|
|
+ for (i = 0; i < 3; i++) {
|
|
+ struct omap_overlay *ovl;
|
|
+ ovl = omap_dss_get_overlay(i);
|
|
+ omap_dss_set_manager(ovl, def_mgr);
|
|
+ }
|
|
+ }
|
|
+
|
|
+#ifdef L4_EXAMPLE
|
|
+ /* setup L4 overlay as an example */
|
|
+ {
|
|
+ static struct omap_overlay ovl = {
|
|
+ .name = "l4-ovl",
|
|
+ .supported_modes = OMAP_DSS_COLOR_RGB24U,
|
|
+ .set_manager = &omap_dss_set_manager,
|
|
+ .unset_manager = &omap_dss_unset_manager,
|
|
+ .setup_input = &omap_dss_setup_overlay_input,
|
|
+ .setup_output = &omap_dss_setup_overlay_output,
|
|
+ .enable = &omap_dss_enable_overlay,
|
|
+ };
|
|
+
|
|
+ static struct omap_overlay_manager mgr = {
|
|
+ .name = "l4",
|
|
+ .num_overlays = 1,
|
|
+ .overlays = &ovl,
|
|
+ .set_display = &omap_dss_set_display,
|
|
+ .unset_display = &omap_dss_unset_display,
|
|
+ .apply = &ovl_mgr_apply_l4,
|
|
+ .supported_displays =
|
|
+ OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
|
|
+ };
|
|
+
|
|
+ omap_dss_add_overlay(&ovl);
|
|
+ omap_dss_add_overlay_manager(&mgr);
|
|
+ omap_dss_set_manager(&ovl, &mgr);
|
|
+ }
|
|
+#endif
|
|
+}
|
|
+
|
|
+void dss_uninit_overlays(struct platform_device *pdev)
|
|
+{
|
|
+ struct omap_overlay *ovl;
|
|
+
|
|
+ while (!list_empty(&overlay_list)) {
|
|
+ ovl = list_first_entry(&overlay_list,
|
|
+ struct omap_overlay, list);
|
|
+ list_del(&ovl->list);
|
|
+ kobject_del(&ovl->kobj);
|
|
+ kobject_put(&ovl->kobj);
|
|
+ kfree(ovl);
|
|
+ }
|
|
+
|
|
+ num_overlays = 0;
|
|
+}
|
|
+
|
|
diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c
|
|
new file mode 100644
|
|
index 0000000..3e9ae1e
|
|
--- /dev/null
|
|
+++ b/drivers/video/omap2/dss/rfbi.c
|
|
@@ -0,0 +1,1304 @@
|
|
+/*
|
|
+ * linux/drivers/video/omap2/dss/rfbi.c
|
|
+ *
|
|
+ * Copyright (C) 2009 Nokia Corporation
|
|
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
|
|
+ *
|
|
+ * Some code and ideas taken from drivers/video/omap/ driver
|
|
+ * by Imre Deak.
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published by
|
|
+ * the Free Software Foundation.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful, but WITHOUT
|
|
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
+ * more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License along with
|
|
+ * this program. If not, see <http://www.gnu.org/licenses/>.
|
|
+ */
|
|
+
|
|
+#define DSS_SUBSYS_NAME "RFBI"
|
|
+
|
|
+#include <linux/kernel.h>
|
|
+#include <linux/dma-mapping.h>
|
|
+#include <linux/vmalloc.h>
|
|
+#include <linux/clk.h>
|
|
+#include <linux/io.h>
|
|
+#include <linux/delay.h>
|
|
+#include <linux/kfifo.h>
|
|
+#include <linux/ktime.h>
|
|
+#include <linux/hrtimer.h>
|
|
+#include <linux/seq_file.h>
|
|
+
|
|
+#include <mach/board.h>
|
|
+#include <mach/display.h>
|
|
+#include "dss.h"
|
|
+
|
|
+/*#define MEASURE_PERF*/
|
|
+
|
|
+#define RFBI_BASE 0x48050800
|
|
+
|
|
+struct rfbi_reg { u16 idx; };
|
|
+
|
|
+#define RFBI_REG(idx) ((const struct rfbi_reg) { idx })
|
|
+
|
|
+#define RFBI_REVISION RFBI_REG(0x0000)
|
|
+#define RFBI_SYSCONFIG RFBI_REG(0x0010)
|
|
+#define RFBI_SYSSTATUS RFBI_REG(0x0014)
|
|
+#define RFBI_CONTROL RFBI_REG(0x0040)
|
|
+#define RFBI_PIXEL_CNT RFBI_REG(0x0044)
|
|
+#define RFBI_LINE_NUMBER RFBI_REG(0x0048)
|
|
+#define RFBI_CMD RFBI_REG(0x004c)
|
|
+#define RFBI_PARAM RFBI_REG(0x0050)
|
|
+#define RFBI_DATA RFBI_REG(0x0054)
|
|
+#define RFBI_READ RFBI_REG(0x0058)
|
|
+#define RFBI_STATUS RFBI_REG(0x005c)
|
|
+
|
|
+#define RFBI_CONFIG(n) RFBI_REG(0x0060 + (n)*0x18)
|
|
+#define RFBI_ONOFF_TIME(n) RFBI_REG(0x0064 + (n)*0x18)
|
|
+#define RFBI_CYCLE_TIME(n) RFBI_REG(0x0068 + (n)*0x18)
|
|
+#define RFBI_DATA_CYCLE1(n) RFBI_REG(0x006c + (n)*0x18)
|
|
+#define RFBI_DATA_CYCLE2(n) RFBI_REG(0x0070 + (n)*0x18)
|
|
+#define RFBI_DATA_CYCLE3(n) RFBI_REG(0x0074 + (n)*0x18)
|
|
+
|
|
+#define RFBI_VSYNC_WIDTH RFBI_REG(0x0090)
|
|
+#define RFBI_HSYNC_WIDTH RFBI_REG(0x0094)
|
|
+
|
|
+#define RFBI_CMD_FIFO_LEN_BYTES (16 * sizeof(struct update_param))
|
|
+
|
|
+#define REG_FLD_MOD(idx, val, start, end) \
|
|
+ rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end))
|
|
+
|
|
+/* To work around an RFBI transfer rate limitation */
|
|
+#define OMAP_RFBI_RATE_LIMIT 1
|
|
+
|
|
+enum omap_rfbi_cycleformat {
|
|
+ OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0,
|
|
+ OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1,
|
|
+ OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2,
|
|
+ OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3,
|
|
+};
|
|
+
|
|
+enum omap_rfbi_datatype {
|
|
+ OMAP_DSS_RFBI_DATATYPE_12 = 0,
|
|
+ OMAP_DSS_RFBI_DATATYPE_16 = 1,
|
|
+ OMAP_DSS_RFBI_DATATYPE_18 = 2,
|
|
+ OMAP_DSS_RFBI_DATATYPE_24 = 3,
|
|
+};
|
|
+
|
|
+enum omap_rfbi_parallelmode {
|
|
+ OMAP_DSS_RFBI_PARALLELMODE_8 = 0,
|
|
+ OMAP_DSS_RFBI_PARALLELMODE_9 = 1,
|
|
+ OMAP_DSS_RFBI_PARALLELMODE_12 = 2,
|
|
+ OMAP_DSS_RFBI_PARALLELMODE_16 = 3,
|
|
+};
|
|
+
|
|
+enum update_cmd {
|
|
+ RFBI_CMD_UPDATE = 0,
|
|
+ RFBI_CMD_SYNC = 1,
|
|
+};
|
|
+
|
|
+static int rfbi_convert_timings(struct rfbi_timings *t);
|
|
+static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div);
|
|
+static void process_cmd_fifo(void);
|
|
+
|
|
+static struct {
|
|
+ void __iomem *base;
|
|
+
|
|
+ unsigned long l4_khz;
|
|
+
|
|
+ enum omap_rfbi_datatype datatype;
|
|
+ enum omap_rfbi_parallelmode parallelmode;
|
|
+
|
|
+ enum omap_rfbi_te_mode te_mode;
|
|
+ int te_enabled;
|
|
+
|
|
+ void (*framedone_callback)(void *data);
|
|
+ void *framedone_callback_data;
|
|
+
|
|
+ struct omap_display *display[2];
|
|
+
|
|
+ struct kfifo *cmd_fifo;
|
|
+ spinlock_t cmd_lock;
|
|
+ struct completion cmd_done;
|
|
+ atomic_t cmd_fifo_full;
|
|
+ atomic_t cmd_pending;
|
|
+#ifdef MEASURE_PERF
|
|
+ unsigned perf_bytes;
|
|
+ ktime_t perf_setup_time;
|
|
+ ktime_t perf_start_time;
|
|
+#endif
|
|
+} rfbi;
|
|
+
|
|
+struct update_region {
|
|
+ u16 x;
|
|
+ u16 y;
|
|
+ u16 w;
|
|
+ u16 h;
|
|
+};
|
|
+
|
|
+struct update_param {
|
|
+ u8 rfbi_module;
|
|
+ u8 cmd;
|
|
+
|
|
+ union {
|
|
+ struct update_region r;
|
|
+ struct completion *sync;
|
|
+ } par;
|
|
+};
|
|
+
|
|
+static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val)
|
|
+{
|
|
+ __raw_writel(val, rfbi.base + idx.idx);
|
|
+}
|
|
+
|
|
+static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
|
|
+{
|
|
+ return __raw_readl(rfbi.base + idx.idx);
|
|
+}
|
|
+
|
|
+static void rfbi_enable_clocks(bool enable)
|
|
+{
|
|
+ if (enable)
|
|
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+ else
|
|
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+}
|
|
+
|
|
+void omap_rfbi_write_command(const void *buf, u32 len)
|
|
+{
|
|
+ rfbi_enable_clocks(1);
|
|
+ switch (rfbi.parallelmode) {
|
|
+ case OMAP_DSS_RFBI_PARALLELMODE_8:
|
|
+ {
|
|
+ const u8 *b = buf;
|
|
+ for (; len; len--)
|
|
+ rfbi_write_reg(RFBI_CMD, *b++);
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ case OMAP_DSS_RFBI_PARALLELMODE_16:
|
|
+ {
|
|
+ const u16 *w = buf;
|
|
+ BUG_ON(len & 1);
|
|
+ for (; len; len -= 2)
|
|
+ rfbi_write_reg(RFBI_CMD, *w++);
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ case OMAP_DSS_RFBI_PARALLELMODE_9:
|
|
+ case OMAP_DSS_RFBI_PARALLELMODE_12:
|
|
+ default:
|
|
+ BUG();
|
|
+ }
|
|
+ rfbi_enable_clocks(0);
|
|
+}
|
|
+EXPORT_SYMBOL(omap_rfbi_write_command);
|
|
+
|
|
+void omap_rfbi_read_data(void *buf, u32 len)
|
|
+{
|
|
+ rfbi_enable_clocks(1);
|
|
+ switch (rfbi.parallelmode) {
|
|
+ case OMAP_DSS_RFBI_PARALLELMODE_8:
|
|
+ {
|
|
+ u8 *b = buf;
|
|
+ for (; len; len--) {
|
|
+ rfbi_write_reg(RFBI_READ, 0);
|
|
+ *b++ = rfbi_read_reg(RFBI_READ);
|
|
+ }
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ case OMAP_DSS_RFBI_PARALLELMODE_16:
|
|
+ {
|
|
+ u16 *w = buf;
|
|
+ BUG_ON(len & ~1);
|
|
+ for (; len; len -= 2) {
|
|
+ rfbi_write_reg(RFBI_READ, 0);
|
|
+ *w++ = rfbi_read_reg(RFBI_READ);
|
|
+ }
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ case OMAP_DSS_RFBI_PARALLELMODE_9:
|
|
+ case OMAP_DSS_RFBI_PARALLELMODE_12:
|
|
+ default:
|
|
+ BUG();
|
|
+ }
|
|
+ rfbi_enable_clocks(0);
|
|
+}
|
|
+EXPORT_SYMBOL(omap_rfbi_read_data);
|
|
+
|
|
+void omap_rfbi_write_data(const void *buf, u32 len)
|
|
+{
|
|
+ rfbi_enable_clocks(1);
|
|
+ switch (rfbi.parallelmode) {
|
|
+ case OMAP_DSS_RFBI_PARALLELMODE_8:
|
|
+ {
|
|
+ const u8 *b = buf;
|
|
+ for (; len; len--)
|
|
+ rfbi_write_reg(RFBI_PARAM, *b++);
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ case OMAP_DSS_RFBI_PARALLELMODE_16:
|
|
+ {
|
|
+ const u16 *w = buf;
|
|
+ BUG_ON(len & 1);
|
|
+ for (; len; len -= 2)
|
|
+ rfbi_write_reg(RFBI_PARAM, *w++);
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ case OMAP_DSS_RFBI_PARALLELMODE_9:
|
|
+ case OMAP_DSS_RFBI_PARALLELMODE_12:
|
|
+ default:
|
|
+ BUG();
|
|
+
|
|
+ }
|
|
+ rfbi_enable_clocks(0);
|
|
+}
|
|
+EXPORT_SYMBOL(omap_rfbi_write_data);
|
|
+
|
|
+void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
|
|
+ u16 x, u16 y,
|
|
+ u16 w, u16 h)
|
|
+{
|
|
+ int start_offset = scr_width * y + x;
|
|
+ int horiz_offset = scr_width - w;
|
|
+ int i;
|
|
+
|
|
+ rfbi_enable_clocks(1);
|
|
+
|
|
+ if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
|
|
+ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
|
|
+ const u16 __iomem *pd = buf;
|
|
+ pd += start_offset;
|
|
+
|
|
+ for (; h; --h) {
|
|
+ for (i = 0; i < w; ++i) {
|
|
+ const u8 __iomem *b = (const u8 __iomem *)pd;
|
|
+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
|
|
+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
|
|
+ ++pd;
|
|
+ }
|
|
+ pd += horiz_offset;
|
|
+ }
|
|
+ } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 &&
|
|
+ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
|
|
+ const u32 __iomem *pd = buf;
|
|
+ pd += start_offset;
|
|
+
|
|
+ for (; h; --h) {
|
|
+ for (i = 0; i < w; ++i) {
|
|
+ const u8 __iomem *b = (const u8 __iomem *)pd;
|
|
+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+2));
|
|
+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
|
|
+ rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
|
|
+ ++pd;
|
|
+ }
|
|
+ pd += horiz_offset;
|
|
+ }
|
|
+ } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
|
|
+ rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) {
|
|
+ const u16 __iomem *pd = buf;
|
|
+ pd += start_offset;
|
|
+
|
|
+ for (; h; --h) {
|
|
+ for (i = 0; i < w; ++i) {
|
|
+ rfbi_write_reg(RFBI_PARAM, __raw_readw(pd));
|
|
+ ++pd;
|
|
+ }
|
|
+ pd += horiz_offset;
|
|
+ }
|
|
+ } else {
|
|
+ BUG();
|
|
+ }
|
|
+
|
|
+ rfbi_enable_clocks(0);
|
|
+}
|
|
+EXPORT_SYMBOL(omap_rfbi_write_pixels);
|
|
+
|
|
+#ifdef MEASURE_PERF
|
|
+static void perf_mark_setup(void)
|
|
+{
|
|
+ rfbi.perf_setup_time = ktime_get();
|
|
+}
|
|
+
|
|
+static void perf_mark_start(void)
|
|
+{
|
|
+ rfbi.perf_start_time = ktime_get();
|
|
+}
|
|
+
|
|
+static void perf_show(const char *name)
|
|
+{
|
|
+ ktime_t t, setup_time, trans_time;
|
|
+ u32 total_bytes;
|
|
+ u32 setup_us, trans_us, total_us;
|
|
+
|
|
+ t = ktime_get();
|
|
+
|
|
+ setup_time = ktime_sub(rfbi.perf_start_time, rfbi.perf_setup_time);
|
|
+ setup_us = (u32)ktime_to_us(setup_time);
|
|
+ if (setup_us == 0)
|
|
+ setup_us = 1;
|
|
+
|
|
+ trans_time = ktime_sub(t, rfbi.perf_start_time);
|
|
+ trans_us = (u32)ktime_to_us(trans_time);
|
|
+ if (trans_us == 0)
|
|
+ trans_us = 1;
|
|
+
|
|
+ total_us = setup_us + trans_us;
|
|
+
|
|
+ total_bytes = rfbi.perf_bytes;
|
|
+
|
|
+ DSSINFO("%s update %u us + %u us = %u us (%uHz), %u bytes, "
|
|
+ "%u kbytes/sec\n",
|
|
+ name,
|
|
+ setup_us,
|
|
+ trans_us,
|
|
+ total_us,
|
|
+ 1000*1000 / total_us,
|
|
+ total_bytes,
|
|
+ total_bytes * 1000 / total_us);
|
|
+}
|
|
+#else
|
|
+#define perf_mark_setup()
|
|
+#define perf_mark_start()
|
|
+#define perf_show(x)
|
|
+#endif
|
|
+
|
|
+void rfbi_transfer_area(u16 width, u16 height,
|
|
+ void (callback)(void *data), void *data)
|
|
+{
|
|
+ u32 l;
|
|
+
|
|
+ /*BUG_ON(callback == 0);*/
|
|
+ BUG_ON(rfbi.framedone_callback != NULL);
|
|
+
|
|
+ DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
|
|
+
|
|
+ dispc_set_lcd_size(width, height);
|
|
+
|
|
+ dispc_enable_lcd_out(1);
|
|
+
|
|
+ rfbi.framedone_callback = callback;
|
|
+ rfbi.framedone_callback_data = data;
|
|
+
|
|
+ rfbi_enable_clocks(1);
|
|
+
|
|
+ rfbi_write_reg(RFBI_PIXEL_CNT, width * height);
|
|
+
|
|
+ l = rfbi_read_reg(RFBI_CONTROL);
|
|
+ l = FLD_MOD(l, 1, 0, 0); /* enable */
|
|
+ if (!rfbi.te_enabled)
|
|
+ l = FLD_MOD(l, 1, 4, 4); /* ITE */
|
|
+
|
|
+ perf_mark_start();
|
|
+
|
|
+ rfbi_write_reg(RFBI_CONTROL, l);
|
|
+}
|
|
+
|
|
+static void framedone_callback(void *data, u32 mask)
|
|
+{
|
|
+ void (*callback)(void *data);
|
|
+
|
|
+ DSSDBG("FRAMEDONE\n");
|
|
+
|
|
+ perf_show("DISPC");
|
|
+
|
|
+ REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0);
|
|
+
|
|
+ rfbi_enable_clocks(0);
|
|
+
|
|
+ callback = rfbi.framedone_callback;
|
|
+ rfbi.framedone_callback = NULL;
|
|
+
|
|
+ /*callback(rfbi.framedone_callback_data);*/
|
|
+
|
|
+ atomic_set(&rfbi.cmd_pending, 0);
|
|
+
|
|
+ process_cmd_fifo();
|
|
+}
|
|
+
|
|
+#if 1 /* VERBOSE */
|
|
+static void rfbi_print_timings(void)
|
|
+{
|
|
+ u32 l;
|
|
+ u32 time;
|
|
+
|
|
+ l = rfbi_read_reg(RFBI_CONFIG(0));
|
|
+ time = 1000000000 / rfbi.l4_khz;
|
|
+ if (l & (1 << 4))
|
|
+ time *= 2;
|
|
+
|
|
+ DSSDBG("Tick time %u ps\n", time);
|
|
+ l = rfbi_read_reg(RFBI_ONOFF_TIME(0));
|
|
+ DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, "
|
|
+ "REONTIME %d, REOFFTIME %d\n",
|
|
+ l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f,
|
|
+ (l >> 20) & 0x0f, (l >> 24) & 0x3f);
|
|
+
|
|
+ l = rfbi_read_reg(RFBI_CYCLE_TIME(0));
|
|
+ DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, "
|
|
+ "ACCESSTIME %d\n",
|
|
+ (l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f,
|
|
+ (l >> 22) & 0x3f);
|
|
+}
|
|
+#else
|
|
+static void rfbi_print_timings(void) {}
|
|
+#endif
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+static u32 extif_clk_period;
|
|
+
|
|
+static inline unsigned long round_to_extif_ticks(unsigned long ps, int div)
|
|
+{
|
|
+ int bus_tick = extif_clk_period * div;
|
|
+ return (ps + bus_tick - 1) / bus_tick * bus_tick;
|
|
+}
|
|
+
|
|
+static int calc_reg_timing(struct rfbi_timings *t, int div)
|
|
+{
|
|
+ t->clk_div = div;
|
|
+
|
|
+ t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div);
|
|
+
|
|
+ t->we_on_time = round_to_extif_ticks(t->we_on_time, div);
|
|
+ t->we_off_time = round_to_extif_ticks(t->we_off_time, div);
|
|
+ t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div);
|
|
+
|
|
+ t->re_on_time = round_to_extif_ticks(t->re_on_time, div);
|
|
+ t->re_off_time = round_to_extif_ticks(t->re_off_time, div);
|
|
+ t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div);
|
|
+
|
|
+ t->access_time = round_to_extif_ticks(t->access_time, div);
|
|
+ t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div);
|
|
+ t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div);
|
|
+
|
|
+ DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n",
|
|
+ t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
|
|
+ DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n",
|
|
+ t->we_on_time, t->we_off_time, t->re_cycle_time,
|
|
+ t->we_cycle_time);
|
|
+ DSSDBG("[reg]rdaccess %d cspulse %d\n",
|
|
+ t->access_time, t->cs_pulse_width);
|
|
+
|
|
+ return rfbi_convert_timings(t);
|
|
+}
|
|
+
|
|
+static int calc_extif_timings(struct rfbi_timings *t)
|
|
+{
|
|
+ u32 max_clk_div;
|
|
+ int div;
|
|
+
|
|
+ rfbi_get_clk_info(&extif_clk_period, &max_clk_div);
|
|
+ for (div = 1; div <= max_clk_div; div++) {
|
|
+ if (calc_reg_timing(t, div) == 0)
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ if (div <= max_clk_div)
|
|
+ return 0;
|
|
+
|
|
+ DSSERR("can't setup timings\n");
|
|
+ return -1;
|
|
+}
|
|
+
|
|
+
|
|
+void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t)
|
|
+{
|
|
+ int r;
|
|
+
|
|
+ if (!t->converted) {
|
|
+ r = calc_extif_timings(t);
|
|
+ if (r < 0)
|
|
+ DSSERR("Failed to calc timings\n");
|
|
+ }
|
|
+
|
|
+ BUG_ON(!t->converted);
|
|
+
|
|
+ rfbi_enable_clocks(1);
|
|
+ rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]);
|
|
+ rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]);
|
|
+
|
|
+ /* TIMEGRANULARITY */
|
|
+ REG_FLD_MOD(RFBI_CONFIG(rfbi_module),
|
|
+ (t->tim[2] ? 1 : 0), 4, 4);
|
|
+
|
|
+ rfbi_print_timings();
|
|
+ rfbi_enable_clocks(0);
|
|
+}
|
|
+
|
|
+static int ps_to_rfbi_ticks(int time, int div)
|
|
+{
|
|
+ unsigned long tick_ps;
|
|
+ int ret;
|
|
+
|
|
+ /* Calculate in picosecs to yield more exact results */
|
|
+ tick_ps = 1000000000 / (rfbi.l4_khz) * div;
|
|
+
|
|
+ ret = (time + tick_ps - 1) / tick_ps;
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+#ifdef OMAP_RFBI_RATE_LIMIT
|
|
+unsigned long rfbi_get_max_tx_rate(void)
|
|
+{
|
|
+ unsigned long l4_rate, dss1_rate;
|
|
+ int min_l4_ticks = 0;
|
|
+ int i;
|
|
+
|
|
+ /* According to TI this can't be calculated so make the
|
|
+ * adjustments for a couple of known frequencies and warn for
|
|
+ * others.
|
|
+ */
|
|
+ static const struct {
|
|
+ unsigned long l4_clk; /* HZ */
|
|
+ unsigned long dss1_clk; /* HZ */
|
|
+ unsigned long min_l4_ticks;
|
|
+ } ftab[] = {
|
|
+ { 55, 132, 7, }, /* 7.86 MPix/s */
|
|
+ { 110, 110, 12, }, /* 9.16 MPix/s */
|
|
+ { 110, 132, 10, }, /* 11 Mpix/s */
|
|
+ { 120, 120, 10, }, /* 12 Mpix/s */
|
|
+ { 133, 133, 10, }, /* 13.3 Mpix/s */
|
|
+ };
|
|
+
|
|
+ l4_rate = rfbi.l4_khz / 1000;
|
|
+ dss1_rate = dss_clk_get_rate(DSS_CLK_FCK1) / 1000000;
|
|
+
|
|
+ for (i = 0; i < ARRAY_SIZE(ftab); i++) {
|
|
+ /* Use a window instead of an exact match, to account
|
|
+ * for different DPLL multiplier / divider pairs.
|
|
+ */
|
|
+ if (abs(ftab[i].l4_clk - l4_rate) < 3 &&
|
|
+ abs(ftab[i].dss1_clk - dss1_rate) < 3) {
|
|
+ min_l4_ticks = ftab[i].min_l4_ticks;
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+ if (i == ARRAY_SIZE(ftab)) {
|
|
+ /* Can't be sure, return anyway the maximum not
|
|
+ * rate-limited. This might cause a problem only for the
|
|
+ * tearing synchronisation.
|
|
+ */
|
|
+ DSSERR("can't determine maximum RFBI transfer rate\n");
|
|
+ return rfbi.l4_khz * 1000;
|
|
+ }
|
|
+ return rfbi.l4_khz * 1000 / min_l4_ticks;
|
|
+}
|
|
+#else
|
|
+int rfbi_get_max_tx_rate(void)
|
|
+{
|
|
+ return rfbi.l4_khz * 1000;
|
|
+}
|
|
+#endif
|
|
+
|
|
+static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
|
|
+{
|
|
+ *clk_period = 1000000000 / rfbi.l4_khz;
|
|
+ *max_clk_div = 2;
|
|
+}
|
|
+
|
|
+static int rfbi_convert_timings(struct rfbi_timings *t)
|
|
+{
|
|
+ u32 l;
|
|
+ int reon, reoff, weon, weoff, cson, csoff, cs_pulse;
|
|
+ int actim, recyc, wecyc;
|
|
+ int div = t->clk_div;
|
|
+
|
|
+ if (div <= 0 || div > 2)
|
|
+ return -1;
|
|
+
|
|
+ /* Make sure that after conversion it still holds that:
|
|
+ * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff,
|
|
+ * csoff > cson, csoff >= max(weoff, reoff), actim > reon
|
|
+ */
|
|
+ weon = ps_to_rfbi_ticks(t->we_on_time, div);
|
|
+ weoff = ps_to_rfbi_ticks(t->we_off_time, div);
|
|
+ if (weoff <= weon)
|
|
+ weoff = weon + 1;
|
|
+ if (weon > 0x0f)
|
|
+ return -1;
|
|
+ if (weoff > 0x3f)
|
|
+ return -1;
|
|
+
|
|
+ reon = ps_to_rfbi_ticks(t->re_on_time, div);
|
|
+ reoff = ps_to_rfbi_ticks(t->re_off_time, div);
|
|
+ if (reoff <= reon)
|
|
+ reoff = reon + 1;
|
|
+ if (reon > 0x0f)
|
|
+ return -1;
|
|
+ if (reoff > 0x3f)
|
|
+ return -1;
|
|
+
|
|
+ cson = ps_to_rfbi_ticks(t->cs_on_time, div);
|
|
+ csoff = ps_to_rfbi_ticks(t->cs_off_time, div);
|
|
+ if (csoff <= cson)
|
|
+ csoff = cson + 1;
|
|
+ if (csoff < max(weoff, reoff))
|
|
+ csoff = max(weoff, reoff);
|
|
+ if (cson > 0x0f)
|
|
+ return -1;
|
|
+ if (csoff > 0x3f)
|
|
+ return -1;
|
|
+
|
|
+ l = cson;
|
|
+ l |= csoff << 4;
|
|
+ l |= weon << 10;
|
|
+ l |= weoff << 14;
|
|
+ l |= reon << 20;
|
|
+ l |= reoff << 24;
|
|
+
|
|
+ t->tim[0] = l;
|
|
+
|
|
+ actim = ps_to_rfbi_ticks(t->access_time, div);
|
|
+ if (actim <= reon)
|
|
+ actim = reon + 1;
|
|
+ if (actim > 0x3f)
|
|
+ return -1;
|
|
+
|
|
+ wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div);
|
|
+ if (wecyc < weoff)
|
|
+ wecyc = weoff;
|
|
+ if (wecyc > 0x3f)
|
|
+ return -1;
|
|
+
|
|
+ recyc = ps_to_rfbi_ticks(t->re_cycle_time, div);
|
|
+ if (recyc < reoff)
|
|
+ recyc = reoff;
|
|
+ if (recyc > 0x3f)
|
|
+ return -1;
|
|
+
|
|
+ cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div);
|
|
+ if (cs_pulse > 0x3f)
|
|
+ return -1;
|
|
+
|
|
+ l = wecyc;
|
|
+ l |= recyc << 6;
|
|
+ l |= cs_pulse << 12;
|
|
+ l |= actim << 22;
|
|
+
|
|
+ t->tim[1] = l;
|
|
+
|
|
+ t->tim[2] = div - 1;
|
|
+
|
|
+ t->converted = 1;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/* xxx FIX module selection missing */
|
|
+int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
|
|
+ unsigned hs_pulse_time, unsigned vs_pulse_time,
|
|
+ int hs_pol_inv, int vs_pol_inv, int extif_div)
|
|
+{
|
|
+ int hs, vs;
|
|
+ int min;
|
|
+ u32 l;
|
|
+
|
|
+ hs = ps_to_rfbi_ticks(hs_pulse_time, 1);
|
|
+ vs = ps_to_rfbi_ticks(vs_pulse_time, 1);
|
|
+ if (hs < 2)
|
|
+ return -EDOM;
|
|
+ if (mode == OMAP_DSS_RFBI_TE_MODE_2)
|
|
+ min = 2;
|
|
+ else /* OMAP_DSS_RFBI_TE_MODE_1 */
|
|
+ min = 4;
|
|
+ if (vs < min)
|
|
+ return -EDOM;
|
|
+ if (vs == hs)
|
|
+ return -EINVAL;
|
|
+ rfbi.te_mode = mode;
|
|
+ DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n",
|
|
+ mode, hs, vs, hs_pol_inv, vs_pol_inv);
|
|
+
|
|
+ rfbi_enable_clocks(1);
|
|
+ rfbi_write_reg(RFBI_HSYNC_WIDTH, hs);
|
|
+ rfbi_write_reg(RFBI_VSYNC_WIDTH, vs);
|
|
+
|
|
+ l = rfbi_read_reg(RFBI_CONFIG(0));
|
|
+ if (hs_pol_inv)
|
|
+ l &= ~(1 << 21);
|
|
+ else
|
|
+ l |= 1 << 21;
|
|
+ if (vs_pol_inv)
|
|
+ l &= ~(1 << 20);
|
|
+ else
|
|
+ l |= 1 << 20;
|
|
+ rfbi_enable_clocks(0);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+EXPORT_SYMBOL(omap_rfbi_setup_te);
|
|
+
|
|
+/* xxx FIX module selection missing */
|
|
+int omap_rfbi_enable_te(bool enable, unsigned line)
|
|
+{
|
|
+ u32 l;
|
|
+
|
|
+ DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode);
|
|
+ if (line > (1 << 11) - 1)
|
|
+ return -EINVAL;
|
|
+
|
|
+ rfbi_enable_clocks(1);
|
|
+ l = rfbi_read_reg(RFBI_CONFIG(0));
|
|
+ l &= ~(0x3 << 2);
|
|
+ if (enable) {
|
|
+ rfbi.te_enabled = 1;
|
|
+ l |= rfbi.te_mode << 2;
|
|
+ } else
|
|
+ rfbi.te_enabled = 0;
|
|
+ rfbi_write_reg(RFBI_CONFIG(0), l);
|
|
+ rfbi_write_reg(RFBI_LINE_NUMBER, line);
|
|
+ rfbi_enable_clocks(0);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+EXPORT_SYMBOL(omap_rfbi_enable_te);
|
|
+
|
|
+#if 0
|
|
+static void rfbi_enable_config(int enable1, int enable2)
|
|
+{
|
|
+ u32 l;
|
|
+ int cs = 0;
|
|
+
|
|
+ if (enable1)
|
|
+ cs |= 1<<0;
|
|
+ if (enable2)
|
|
+ cs |= 1<<1;
|
|
+
|
|
+ rfbi_enable_clocks(1);
|
|
+
|
|
+ l = rfbi_read_reg(RFBI_CONTROL);
|
|
+
|
|
+ l = FLD_MOD(l, cs, 3, 2);
|
|
+ l = FLD_MOD(l, 0, 1, 1);
|
|
+
|
|
+ rfbi_write_reg(RFBI_CONTROL, l);
|
|
+
|
|
+
|
|
+ l = rfbi_read_reg(RFBI_CONFIG(0));
|
|
+ l = FLD_MOD(l, 0, 3, 2); /* TRIGGERMODE: ITE */
|
|
+ /*l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
|
|
+ /*l |= FLD_VAL(0, 8, 7); */ /* L4FORMAT, 1pix/L4 */
|
|
+
|
|
+ l = FLD_MOD(l, 0, 16, 16); /* A0POLARITY */
|
|
+ l = FLD_MOD(l, 1, 20, 20); /* TE_VSYNC_POLARITY */
|
|
+ l = FLD_MOD(l, 1, 21, 21); /* HSYNCPOLARITY */
|
|
+
|
|
+ l = FLD_MOD(l, OMAP_DSS_RFBI_PARALLELMODE_8, 1, 0);
|
|
+ rfbi_write_reg(RFBI_CONFIG(0), l);
|
|
+
|
|
+ rfbi_enable_clocks(0);
|
|
+}
|
|
+#endif
|
|
+
|
|
+int rfbi_configure(int rfbi_module, int bpp, int lines)
|
|
+{
|
|
+ u32 l;
|
|
+ int cycle1 = 0, cycle2 = 0, cycle3 = 0;
|
|
+ enum omap_rfbi_cycleformat cycleformat;
|
|
+ enum omap_rfbi_datatype datatype;
|
|
+ enum omap_rfbi_parallelmode parallelmode;
|
|
+
|
|
+ switch (bpp) {
|
|
+ case 12:
|
|
+ datatype = OMAP_DSS_RFBI_DATATYPE_12;
|
|
+ break;
|
|
+ case 16:
|
|
+ datatype = OMAP_DSS_RFBI_DATATYPE_16;
|
|
+ break;
|
|
+ case 18:
|
|
+ datatype = OMAP_DSS_RFBI_DATATYPE_18;
|
|
+ break;
|
|
+ case 24:
|
|
+ datatype = OMAP_DSS_RFBI_DATATYPE_24;
|
|
+ break;
|
|
+ default:
|
|
+ BUG();
|
|
+ return 1;
|
|
+ }
|
|
+ rfbi.datatype = datatype;
|
|
+
|
|
+ switch (lines) {
|
|
+ case 8:
|
|
+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8;
|
|
+ break;
|
|
+ case 9:
|
|
+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9;
|
|
+ break;
|
|
+ case 12:
|
|
+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12;
|
|
+ break;
|
|
+ case 16:
|
|
+ parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16;
|
|
+ break;
|
|
+ default:
|
|
+ BUG();
|
|
+ return 1;
|
|
+ }
|
|
+ rfbi.parallelmode = parallelmode;
|
|
+
|
|
+ if ((bpp % lines) == 0) {
|
|
+ switch (bpp / lines) {
|
|
+ case 1:
|
|
+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1;
|
|
+ break;
|
|
+ case 2:
|
|
+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1;
|
|
+ break;
|
|
+ case 3:
|
|
+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1;
|
|
+ break;
|
|
+ default:
|
|
+ BUG();
|
|
+ return 1;
|
|
+ }
|
|
+ } else if ((2 * bpp % lines) == 0) {
|
|
+ if ((2 * bpp / lines) == 3)
|
|
+ cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2;
|
|
+ else {
|
|
+ BUG();
|
|
+ return 1;
|
|
+ }
|
|
+ } else {
|
|
+ BUG();
|
|
+ return 1;
|
|
+ }
|
|
+
|
|
+ switch (cycleformat) {
|
|
+ case OMAP_DSS_RFBI_CYCLEFORMAT_1_1:
|
|
+ cycle1 = lines;
|
|
+ break;
|
|
+
|
|
+ case OMAP_DSS_RFBI_CYCLEFORMAT_2_1:
|
|
+ cycle1 = lines;
|
|
+ cycle2 = lines;
|
|
+ break;
|
|
+
|
|
+ case OMAP_DSS_RFBI_CYCLEFORMAT_3_1:
|
|
+ cycle1 = lines;
|
|
+ cycle2 = lines;
|
|
+ cycle3 = lines;
|
|
+ break;
|
|
+
|
|
+ case OMAP_DSS_RFBI_CYCLEFORMAT_3_2:
|
|
+ cycle1 = lines;
|
|
+ cycle2 = (lines / 2) | ((lines / 2) << 16);
|
|
+ cycle3 = (lines << 16);
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ rfbi_enable_clocks(1);
|
|
+
|
|
+ REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */
|
|
+
|
|
+ l = 0;
|
|
+ l |= FLD_VAL(parallelmode, 1, 0);
|
|
+ l |= FLD_VAL(0, 3, 2); /* TRIGGERMODE: ITE */
|
|
+ l |= FLD_VAL(0, 4, 4); /* TIMEGRANULARITY */
|
|
+ l |= FLD_VAL(datatype, 6, 5);
|
|
+ /* l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
|
|
+ l |= FLD_VAL(0, 8, 7); /* L4FORMAT, 1pix/L4 */
|
|
+ l |= FLD_VAL(cycleformat, 10, 9);
|
|
+ l |= FLD_VAL(0, 12, 11); /* UNUSEDBITS */
|
|
+ l |= FLD_VAL(0, 16, 16); /* A0POLARITY */
|
|
+ l |= FLD_VAL(0, 17, 17); /* REPOLARITY */
|
|
+ l |= FLD_VAL(0, 18, 18); /* WEPOLARITY */
|
|
+ l |= FLD_VAL(0, 19, 19); /* CSPOLARITY */
|
|
+ l |= FLD_VAL(1, 20, 20); /* TE_VSYNC_POLARITY */
|
|
+ l |= FLD_VAL(1, 21, 21); /* HSYNCPOLARITY */
|
|
+ rfbi_write_reg(RFBI_CONFIG(rfbi_module), l);
|
|
+
|
|
+ rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1);
|
|
+ rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2);
|
|
+ rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3);
|
|
+
|
|
+
|
|
+ l = rfbi_read_reg(RFBI_CONTROL);
|
|
+ l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */
|
|
+ l = FLD_MOD(l, 0, 1, 1); /* clear bypass */
|
|
+ rfbi_write_reg(RFBI_CONTROL, l);
|
|
+
|
|
+
|
|
+ DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n",
|
|
+ bpp, lines, cycle1, cycle2, cycle3);
|
|
+
|
|
+ rfbi_enable_clocks(0);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+EXPORT_SYMBOL(rfbi_configure);
|
|
+
|
|
+static int rfbi_find_display(struct omap_display *disp)
|
|
+{
|
|
+ if (disp == rfbi.display[0])
|
|
+ return 0;
|
|
+
|
|
+ if (disp == rfbi.display[1])
|
|
+ return 1;
|
|
+
|
|
+ BUG();
|
|
+ return -1;
|
|
+}
|
|
+
|
|
+
|
|
+static void signal_fifo_waiters(void)
|
|
+{
|
|
+ if (atomic_read(&rfbi.cmd_fifo_full) > 0) {
|
|
+ /* DSSDBG("SIGNALING: Fifo not full for waiter!\n"); */
|
|
+ complete(&rfbi.cmd_done);
|
|
+ atomic_dec(&rfbi.cmd_fifo_full);
|
|
+ }
|
|
+}
|
|
+
|
|
+/* returns 1 for async op, and 0 for sync op */
|
|
+static int do_update(struct omap_display *display, struct update_region *upd)
|
|
+{
|
|
+ u16 x = upd->x;
|
|
+ u16 y = upd->y;
|
|
+ u16 w = upd->w;
|
|
+ u16 h = upd->h;
|
|
+
|
|
+ perf_mark_setup();
|
|
+
|
|
+ if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
|
|
+ /*display->ctrl->enable_te(display, 1); */
|
|
+ dispc_setup_partial_planes(display, &x, &y, &w, &h);
|
|
+ }
|
|
+
|
|
+#ifdef MEASURE_PERF
|
|
+ rfbi.perf_bytes = w * h * 2; /* XXX always 16bit */
|
|
+#endif
|
|
+
|
|
+ display->ctrl->setup_update(display, x, y, w, h);
|
|
+
|
|
+ if (display->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
|
|
+ rfbi_transfer_area(w, h, NULL, NULL);
|
|
+ return 1;
|
|
+ } else {
|
|
+ struct omap_overlay *ovl;
|
|
+ void __iomem *addr;
|
|
+ int scr_width;
|
|
+
|
|
+ ovl = display->manager->overlays[0];
|
|
+ scr_width = ovl->info.screen_width;
|
|
+ addr = ovl->info.vaddr;
|
|
+
|
|
+ omap_rfbi_write_pixels(addr, scr_width, x, y, w, h);
|
|
+
|
|
+ perf_show("L4");
|
|
+
|
|
+ return 0;
|
|
+ }
|
|
+}
|
|
+
|
|
+static void process_cmd_fifo(void)
|
|
+{
|
|
+ int len;
|
|
+ struct update_param p;
|
|
+ struct omap_display *display;
|
|
+ unsigned long flags;
|
|
+
|
|
+ if (atomic_inc_return(&rfbi.cmd_pending) != 1)
|
|
+ return;
|
|
+
|
|
+ while (true) {
|
|
+ spin_lock_irqsave(rfbi.cmd_fifo->lock, flags);
|
|
+
|
|
+ len = __kfifo_get(rfbi.cmd_fifo, (unsigned char *)&p,
|
|
+ sizeof(struct update_param));
|
|
+ if (len == 0) {
|
|
+ DSSDBG("nothing more in fifo\n");
|
|
+ atomic_set(&rfbi.cmd_pending, 0);
|
|
+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ /* DSSDBG("fifo full %d\n", rfbi.cmd_fifo_full.counter);*/
|
|
+
|
|
+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
|
|
+
|
|
+ BUG_ON(len != sizeof(struct update_param));
|
|
+ BUG_ON(p.rfbi_module > 1);
|
|
+
|
|
+ display = rfbi.display[p.rfbi_module];
|
|
+
|
|
+ if (p.cmd == RFBI_CMD_UPDATE) {
|
|
+ if (do_update(display, &p.par.r))
|
|
+ break; /* async op */
|
|
+ } else if (p.cmd == RFBI_CMD_SYNC) {
|
|
+ DSSDBG("Signaling SYNC done!\n");
|
|
+ complete(p.par.sync);
|
|
+ } else
|
|
+ BUG();
|
|
+ }
|
|
+
|
|
+ signal_fifo_waiters();
|
|
+}
|
|
+
|
|
+static void rfbi_push_cmd(struct update_param *p)
|
|
+{
|
|
+ int ret;
|
|
+
|
|
+ while (1) {
|
|
+ unsigned long flags;
|
|
+ int available;
|
|
+
|
|
+ spin_lock_irqsave(rfbi.cmd_fifo->lock, flags);
|
|
+ available = RFBI_CMD_FIFO_LEN_BYTES -
|
|
+ __kfifo_len(rfbi.cmd_fifo);
|
|
+
|
|
+/* DSSDBG("%d bytes left in fifo\n", available); */
|
|
+ if (available < sizeof(struct update_param)) {
|
|
+ DSSDBG("Going to wait because FIFO FULL..\n");
|
|
+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
|
|
+ atomic_inc(&rfbi.cmd_fifo_full);
|
|
+ wait_for_completion(&rfbi.cmd_done);
|
|
+ /*DSSDBG("Woke up because fifo not full anymore\n");*/
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+ ret = __kfifo_put(rfbi.cmd_fifo, (unsigned char *)p,
|
|
+ sizeof(struct update_param));
|
|
+/* DSSDBG("pushed %d bytes\n", ret);*/
|
|
+
|
|
+ spin_unlock_irqrestore(rfbi.cmd_fifo->lock, flags);
|
|
+
|
|
+ BUG_ON(ret != sizeof(struct update_param));
|
|
+
|
|
+ break;
|
|
+ }
|
|
+}
|
|
+
|
|
+static void rfbi_push_update(int rfbi_module, int x, int y, int w, int h)
|
|
+{
|
|
+ struct update_param p;
|
|
+
|
|
+ p.rfbi_module = rfbi_module;
|
|
+ p.cmd = RFBI_CMD_UPDATE;
|
|
+
|
|
+ p.par.r.x = x;
|
|
+ p.par.r.y = y;
|
|
+ p.par.r.w = w;
|
|
+ p.par.r.h = h;
|
|
+
|
|
+ DSSDBG("RFBI pushed %d,%d %dx%d\n", x, y, w, h);
|
|
+
|
|
+ rfbi_push_cmd(&p);
|
|
+
|
|
+ process_cmd_fifo();
|
|
+}
|
|
+
|
|
+static void rfbi_push_sync(int rfbi_module, struct completion *sync_comp)
|
|
+{
|
|
+ struct update_param p;
|
|
+
|
|
+ p.rfbi_module = rfbi_module;
|
|
+ p.cmd = RFBI_CMD_SYNC;
|
|
+ p.par.sync = sync_comp;
|
|
+
|
|
+ rfbi_push_cmd(&p);
|
|
+
|
|
+ DSSDBG("RFBI sync pushed to cmd fifo\n");
|
|
+
|
|
+ process_cmd_fifo();
|
|
+}
|
|
+
|
|
+void rfbi_dump_regs(struct seq_file *s)
|
|
+{
|
|
+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r))
|
|
+
|
|
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+
|
|
+ DUMPREG(RFBI_REVISION);
|
|
+ DUMPREG(RFBI_SYSCONFIG);
|
|
+ DUMPREG(RFBI_SYSSTATUS);
|
|
+ DUMPREG(RFBI_CONTROL);
|
|
+ DUMPREG(RFBI_PIXEL_CNT);
|
|
+ DUMPREG(RFBI_LINE_NUMBER);
|
|
+ DUMPREG(RFBI_CMD);
|
|
+ DUMPREG(RFBI_PARAM);
|
|
+ DUMPREG(RFBI_DATA);
|
|
+ DUMPREG(RFBI_READ);
|
|
+ DUMPREG(RFBI_STATUS);
|
|
+
|
|
+ DUMPREG(RFBI_CONFIG(0));
|
|
+ DUMPREG(RFBI_ONOFF_TIME(0));
|
|
+ DUMPREG(RFBI_CYCLE_TIME(0));
|
|
+ DUMPREG(RFBI_DATA_CYCLE1(0));
|
|
+ DUMPREG(RFBI_DATA_CYCLE2(0));
|
|
+ DUMPREG(RFBI_DATA_CYCLE3(0));
|
|
+
|
|
+ DUMPREG(RFBI_CONFIG(1));
|
|
+ DUMPREG(RFBI_ONOFF_TIME(1));
|
|
+ DUMPREG(RFBI_CYCLE_TIME(1));
|
|
+ DUMPREG(RFBI_DATA_CYCLE1(1));
|
|
+ DUMPREG(RFBI_DATA_CYCLE2(1));
|
|
+ DUMPREG(RFBI_DATA_CYCLE3(1));
|
|
+
|
|
+ DUMPREG(RFBI_VSYNC_WIDTH);
|
|
+ DUMPREG(RFBI_HSYNC_WIDTH);
|
|
+
|
|
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+#undef DUMPREG
|
|
+}
|
|
+
|
|
+int rfbi_init(void)
|
|
+{
|
|
+ u32 rev;
|
|
+ u32 l;
|
|
+
|
|
+ spin_lock_init(&rfbi.cmd_lock);
|
|
+ rfbi.cmd_fifo = kfifo_alloc(RFBI_CMD_FIFO_LEN_BYTES, GFP_KERNEL,
|
|
+ &rfbi.cmd_lock);
|
|
+ if (IS_ERR(rfbi.cmd_fifo))
|
|
+ return -ENOMEM;
|
|
+
|
|
+ init_completion(&rfbi.cmd_done);
|
|
+ atomic_set(&rfbi.cmd_fifo_full, 0);
|
|
+ atomic_set(&rfbi.cmd_pending, 0);
|
|
+
|
|
+ rfbi.base = ioremap(RFBI_BASE, SZ_256);
|
|
+ if (!rfbi.base) {
|
|
+ DSSERR("can't ioremap RFBI\n");
|
|
+ return -ENOMEM;
|
|
+ }
|
|
+
|
|
+ rfbi_enable_clocks(1);
|
|
+
|
|
+ msleep(10);
|
|
+
|
|
+ rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000;
|
|
+
|
|
+ /* Enable autoidle and smart-idle */
|
|
+ l = rfbi_read_reg(RFBI_SYSCONFIG);
|
|
+ l |= (1 << 0) | (2 << 3);
|
|
+ rfbi_write_reg(RFBI_SYSCONFIG, l);
|
|
+
|
|
+ rev = rfbi_read_reg(RFBI_REVISION);
|
|
+ printk(KERN_INFO "OMAP RFBI rev %d.%d\n",
|
|
+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
|
|
+
|
|
+ rfbi_enable_clocks(0);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+void rfbi_exit(void)
|
|
+{
|
|
+ DSSDBG("rfbi_exit\n");
|
|
+
|
|
+ kfifo_free(rfbi.cmd_fifo);
|
|
+
|
|
+ iounmap(rfbi.base);
|
|
+}
|
|
+
|
|
+/* struct omap_display support */
|
|
+static int rfbi_display_update(struct omap_display *display,
|
|
+ u16 x, u16 y, u16 w, u16 h)
|
|
+{
|
|
+ int rfbi_module;
|
|
+
|
|
+ if (w == 0 || h == 0)
|
|
+ return 0;
|
|
+
|
|
+ rfbi_module = rfbi_find_display(display);
|
|
+
|
|
+ rfbi_push_update(rfbi_module, x, y, w, h);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int rfbi_display_sync(struct omap_display *display)
|
|
+{
|
|
+ struct completion sync_comp;
|
|
+ int rfbi_module;
|
|
+
|
|
+ rfbi_module = rfbi_find_display(display);
|
|
+
|
|
+ init_completion(&sync_comp);
|
|
+ rfbi_push_sync(rfbi_module, &sync_comp);
|
|
+ DSSDBG("Waiting for SYNC to happen...\n");
|
|
+ wait_for_completion(&sync_comp);
|
|
+ DSSDBG("Released from SYNC\n");
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int rfbi_display_enable_te(struct omap_display *display, bool enable)
|
|
+{
|
|
+ display->ctrl->enable_te(display, enable);
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int rfbi_display_enable(struct omap_display *display)
|
|
+{
|
|
+ int r;
|
|
+
|
|
+ BUG_ON(display->panel == NULL || display->ctrl == NULL);
|
|
+
|
|
+ r = omap_dispc_register_isr(framedone_callback, NULL,
|
|
+ DISPC_IRQ_FRAMEDONE);
|
|
+ if (r) {
|
|
+ DSSERR("can't get FRAMEDONE irq\n");
|
|
+ return r;
|
|
+ }
|
|
+
|
|
+ dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
|
|
+
|
|
+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_RFBI);
|
|
+
|
|
+ dispc_set_tft_data_lines(display->ctrl->pixel_size);
|
|
+
|
|
+ rfbi_configure(display->hw_config.u.rfbi.channel,
|
|
+ display->ctrl->pixel_size,
|
|
+ display->hw_config.u.rfbi.data_lines);
|
|
+
|
|
+ rfbi_set_timings(display->hw_config.u.rfbi.channel,
|
|
+ &display->ctrl->timings);
|
|
+
|
|
+
|
|
+ if (display->ctrl && display->ctrl->enable) {
|
|
+ r = display->ctrl->enable(display);
|
|
+ if (r)
|
|
+ goto err;
|
|
+ }
|
|
+
|
|
+ if (display->panel && display->panel->enable) {
|
|
+ r = display->panel->enable(display);
|
|
+ if (r)
|
|
+ goto err;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+err:
|
|
+ return -ENODEV;
|
|
+}
|
|
+
|
|
+static void rfbi_display_disable(struct omap_display *display)
|
|
+{
|
|
+ display->ctrl->disable(display);
|
|
+ omap_dispc_unregister_isr(framedone_callback, NULL,
|
|
+ DISPC_IRQ_FRAMEDONE);
|
|
+}
|
|
+
|
|
+void rfbi_init_display(struct omap_display *display)
|
|
+{
|
|
+ display->enable = rfbi_display_enable;
|
|
+ display->disable = rfbi_display_disable;
|
|
+ display->update = rfbi_display_update;
|
|
+ display->sync = rfbi_display_sync;
|
|
+ display->enable_te = rfbi_display_enable_te;
|
|
+
|
|
+ rfbi.display[display->hw_config.u.rfbi.channel] = display;
|
|
+
|
|
+ display->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
|
|
+}
|
|
diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c
|
|
new file mode 100644
|
|
index 0000000..fbff2b2
|
|
--- /dev/null
|
|
+++ b/drivers/video/omap2/dss/sdi.c
|
|
@@ -0,0 +1,245 @@
|
|
+/*
|
|
+ * linux/drivers/video/omap2/dss/sdi.c
|
|
+ *
|
|
+ * Copyright (C) 2009 Nokia Corporation
|
|
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published by
|
|
+ * the Free Software Foundation.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful, but WITHOUT
|
|
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
+ * more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License along with
|
|
+ * this program. If not, see <http://www.gnu.org/licenses/>.
|
|
+ */
|
|
+
|
|
+#define DSS_SUBSYS_NAME "SDI"
|
|
+
|
|
+#include <linux/kernel.h>
|
|
+#include <linux/clk.h>
|
|
+#include <linux/delay.h>
|
|
+#include <linux/err.h>
|
|
+
|
|
+#include <mach/board.h>
|
|
+#include <mach/display.h>
|
|
+#include "dss.h"
|
|
+
|
|
+
|
|
+static struct {
|
|
+ bool skip_init;
|
|
+ bool update_enabled;
|
|
+} sdi;
|
|
+
|
|
+static void sdi_basic_init(void)
|
|
+{
|
|
+ dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
|
|
+
|
|
+ dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
|
|
+ dispc_set_tft_data_lines(24);
|
|
+ dispc_lcd_enable_signal_polarity(1);
|
|
+}
|
|
+
|
|
+static int sdi_display_enable(struct omap_display *display)
|
|
+{
|
|
+ struct dispc_clock_info cinfo;
|
|
+ u16 lck_div, pck_div;
|
|
+ unsigned long fck;
|
|
+ struct omap_panel *panel = display->panel;
|
|
+ unsigned long pck;
|
|
+ int r;
|
|
+
|
|
+ if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
|
|
+ DSSERR("display already enabled\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ /* In case of skip_init sdi_init has already enabled the clocks */
|
|
+ if (!sdi.skip_init)
|
|
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+
|
|
+ sdi_basic_init();
|
|
+
|
|
+ /* 15.5.9.1.2 */
|
|
+ panel->config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF;
|
|
+
|
|
+ dispc_set_pol_freq(panel);
|
|
+
|
|
+ if (!sdi.skip_init)
|
|
+ r = dispc_calc_clock_div(1, panel->timings.pixel_clock * 1000,
|
|
+ &cinfo);
|
|
+ else
|
|
+ r = dispc_get_clock_div(&cinfo);
|
|
+
|
|
+ if (r)
|
|
+ goto err0;
|
|
+
|
|
+ fck = cinfo.fck;
|
|
+ lck_div = cinfo.lck_div;
|
|
+ pck_div = cinfo.pck_div;
|
|
+
|
|
+ pck = fck / lck_div / pck_div / 1000;
|
|
+
|
|
+ if (pck != panel->timings.pixel_clock) {
|
|
+ DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
|
|
+ "got %lu kHz\n",
|
|
+ panel->timings.pixel_clock, pck);
|
|
+
|
|
+ panel->timings.pixel_clock = pck;
|
|
+ }
|
|
+
|
|
+
|
|
+ dispc_set_lcd_timings(&panel->timings);
|
|
+
|
|
+ r = dispc_set_clock_div(&cinfo);
|
|
+ if (r)
|
|
+ goto err1;
|
|
+
|
|
+ if (!sdi.skip_init) {
|
|
+ dss_sdi_init(display->hw_config.u.sdi.datapairs);
|
|
+ dss_sdi_enable();
|
|
+ mdelay(2);
|
|
+ }
|
|
+
|
|
+ dispc_enable_lcd_out(1);
|
|
+
|
|
+ r = panel->enable(display);
|
|
+ if (r)
|
|
+ goto err2;
|
|
+
|
|
+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
|
|
+
|
|
+ sdi.skip_init = 0;
|
|
+
|
|
+ return 0;
|
|
+err2:
|
|
+ dispc_enable_lcd_out(0);
|
|
+err1:
|
|
+err0:
|
|
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+ return r;
|
|
+}
|
|
+
|
|
+static int sdi_display_resume(struct omap_display *display);
|
|
+
|
|
+static void sdi_display_disable(struct omap_display *display)
|
|
+{
|
|
+ if (display->state == OMAP_DSS_DISPLAY_DISABLED)
|
|
+ return;
|
|
+
|
|
+ if (display->state == OMAP_DSS_DISPLAY_SUSPENDED)
|
|
+ sdi_display_resume(display);
|
|
+
|
|
+ display->panel->disable(display);
|
|
+
|
|
+ dispc_enable_lcd_out(0);
|
|
+
|
|
+ dss_sdi_disable();
|
|
+
|
|
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+
|
|
+ display->state = OMAP_DSS_DISPLAY_DISABLED;
|
|
+}
|
|
+
|
|
+static int sdi_display_suspend(struct omap_display *display)
|
|
+{
|
|
+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
|
|
+ return -EINVAL;
|
|
+
|
|
+ if (display->panel->suspend)
|
|
+ display->panel->suspend(display);
|
|
+
|
|
+ dispc_enable_lcd_out(0);
|
|
+
|
|
+ dss_sdi_disable();
|
|
+
|
|
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+
|
|
+ display->state = OMAP_DSS_DISPLAY_SUSPENDED;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int sdi_display_resume(struct omap_display *display)
|
|
+{
|
|
+ if (display->state != OMAP_DSS_DISPLAY_SUSPENDED)
|
|
+ return -EINVAL;
|
|
+
|
|
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+
|
|
+ dss_sdi_enable();
|
|
+ mdelay(2);
|
|
+
|
|
+ dispc_enable_lcd_out(1);
|
|
+
|
|
+ if (display->panel->resume)
|
|
+ display->panel->resume(display);
|
|
+
|
|
+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int sdi_display_set_update_mode(struct omap_display *display,
|
|
+ enum omap_dss_update_mode mode)
|
|
+{
|
|
+ if (mode == OMAP_DSS_UPDATE_MANUAL)
|
|
+ return -EINVAL;
|
|
+
|
|
+ if (mode == OMAP_DSS_UPDATE_DISABLED) {
|
|
+ dispc_enable_lcd_out(0);
|
|
+ sdi.update_enabled = 0;
|
|
+ } else {
|
|
+ dispc_enable_lcd_out(1);
|
|
+ sdi.update_enabled = 1;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static enum omap_dss_update_mode sdi_display_get_update_mode(
|
|
+ struct omap_display *display)
|
|
+{
|
|
+ return sdi.update_enabled ? OMAP_DSS_UPDATE_AUTO :
|
|
+ OMAP_DSS_UPDATE_DISABLED;
|
|
+}
|
|
+
|
|
+static void sdi_get_timings(struct omap_display *display,
|
|
+ struct omap_video_timings *timings)
|
|
+{
|
|
+ *timings = display->panel->timings;
|
|
+}
|
|
+
|
|
+void sdi_init_display(struct omap_display *display)
|
|
+{
|
|
+ DSSDBG("SDI init\n");
|
|
+
|
|
+ display->enable = sdi_display_enable;
|
|
+ display->disable = sdi_display_disable;
|
|
+ display->suspend = sdi_display_suspend;
|
|
+ display->resume = sdi_display_resume;
|
|
+ display->set_update_mode = sdi_display_set_update_mode;
|
|
+ display->get_update_mode = sdi_display_get_update_mode;
|
|
+ display->get_timings = sdi_get_timings;
|
|
+}
|
|
+
|
|
+int sdi_init(bool skip_init)
|
|
+{
|
|
+ /* we store this for first display enable, then clear it */
|
|
+ sdi.skip_init = skip_init;
|
|
+
|
|
+ /*
|
|
+ * Enable clocks already here, otherwise there would be a toggle
|
|
+ * of them until sdi_display_enable is called.
|
|
+ */
|
|
+ if (skip_init)
|
|
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+void sdi_exit(void)
|
|
+{
|
|
+}
|
|
diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
|
|
new file mode 100644
|
|
index 0000000..aceed9f
|
|
--- /dev/null
|
|
+++ b/drivers/video/omap2/dss/venc.c
|
|
@@ -0,0 +1,600 @@
|
|
+/*
|
|
+ * linux/drivers/video/omap2/dss/venc.c
|
|
+ *
|
|
+ * Copyright (C) 2009 Nokia Corporation
|
|
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
|
|
+ *
|
|
+ * VENC settings from TI's DSS driver
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published by
|
|
+ * the Free Software Foundation.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful, but WITHOUT
|
|
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
+ * more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License along with
|
|
+ * this program. If not, see <http://www.gnu.org/licenses/>.
|
|
+ */
|
|
+
|
|
+#define DSS_SUBSYS_NAME "VENC"
|
|
+
|
|
+#include <linux/kernel.h>
|
|
+#include <linux/module.h>
|
|
+#include <linux/clk.h>
|
|
+#include <linux/err.h>
|
|
+#include <linux/io.h>
|
|
+#include <linux/mutex.h>
|
|
+#include <linux/completion.h>
|
|
+#include <linux/delay.h>
|
|
+#include <linux/string.h>
|
|
+
|
|
+#include <mach/display.h>
|
|
+#include <mach/cpu.h>
|
|
+
|
|
+#include "dss.h"
|
|
+
|
|
+#define VENC_BASE 0x48050C00
|
|
+
|
|
+/* Venc registers */
|
|
+#define VENC_REV_ID 0x00
|
|
+#define VENC_STATUS 0x04
|
|
+#define VENC_F_CONTROL 0x08
|
|
+#define VENC_VIDOUT_CTRL 0x10
|
|
+#define VENC_SYNC_CTRL 0x14
|
|
+#define VENC_LLEN 0x1C
|
|
+#define VENC_FLENS 0x20
|
|
+#define VENC_HFLTR_CTRL 0x24
|
|
+#define VENC_CC_CARR_WSS_CARR 0x28
|
|
+#define VENC_C_PHASE 0x2C
|
|
+#define VENC_GAIN_U 0x30
|
|
+#define VENC_GAIN_V 0x34
|
|
+#define VENC_GAIN_Y 0x38
|
|
+#define VENC_BLACK_LEVEL 0x3C
|
|
+#define VENC_BLANK_LEVEL 0x40
|
|
+#define VENC_X_COLOR 0x44
|
|
+#define VENC_M_CONTROL 0x48
|
|
+#define VENC_BSTAMP_WSS_DATA 0x4C
|
|
+#define VENC_S_CARR 0x50
|
|
+#define VENC_LINE21 0x54
|
|
+#define VENC_LN_SEL 0x58
|
|
+#define VENC_L21__WC_CTL 0x5C
|
|
+#define VENC_HTRIGGER_VTRIGGER 0x60
|
|
+#define VENC_SAVID__EAVID 0x64
|
|
+#define VENC_FLEN__FAL 0x68
|
|
+#define VENC_LAL__PHASE_RESET 0x6C
|
|
+#define VENC_HS_INT_START_STOP_X 0x70
|
|
+#define VENC_HS_EXT_START_STOP_X 0x74
|
|
+#define VENC_VS_INT_START_X 0x78
|
|
+#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
|
|
+#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
|
|
+#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
|
|
+#define VENC_VS_EXT_STOP_Y 0x88
|
|
+#define VENC_AVID_START_STOP_X 0x90
|
|
+#define VENC_AVID_START_STOP_Y 0x94
|
|
+#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
|
|
+#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
|
|
+#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
|
|
+#define VENC_TVDETGP_INT_START_STOP_X 0xB0
|
|
+#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
|
|
+#define VENC_GEN_CTRL 0xB8
|
|
+#define VENC_OUTPUT_CONTROL 0xC4
|
|
+#define VENC_DAC_B__DAC_C 0xC8
|
|
+
|
|
+struct venc_config {
|
|
+ u32 f_control;
|
|
+ u32 vidout_ctrl;
|
|
+ u32 sync_ctrl;
|
|
+ u32 llen;
|
|
+ u32 flens;
|
|
+ u32 hfltr_ctrl;
|
|
+ u32 cc_carr_wss_carr;
|
|
+ u32 c_phase;
|
|
+ u32 gain_u;
|
|
+ u32 gain_v;
|
|
+ u32 gain_y;
|
|
+ u32 black_level;
|
|
+ u32 blank_level;
|
|
+ u32 x_color;
|
|
+ u32 m_control;
|
|
+ u32 bstamp_wss_data;
|
|
+ u32 s_carr;
|
|
+ u32 line21;
|
|
+ u32 ln_sel;
|
|
+ u32 l21__wc_ctl;
|
|
+ u32 htrigger_vtrigger;
|
|
+ u32 savid__eavid;
|
|
+ u32 flen__fal;
|
|
+ u32 lal__phase_reset;
|
|
+ u32 hs_int_start_stop_x;
|
|
+ u32 hs_ext_start_stop_x;
|
|
+ u32 vs_int_start_x;
|
|
+ u32 vs_int_stop_x__vs_int_start_y;
|
|
+ u32 vs_int_stop_y__vs_ext_start_x;
|
|
+ u32 vs_ext_stop_x__vs_ext_start_y;
|
|
+ u32 vs_ext_stop_y;
|
|
+ u32 avid_start_stop_x;
|
|
+ u32 avid_start_stop_y;
|
|
+ u32 fid_int_start_x__fid_int_start_y;
|
|
+ u32 fid_int_offset_y__fid_ext_start_x;
|
|
+ u32 fid_ext_start_y__fid_ext_offset_y;
|
|
+ u32 tvdetgp_int_start_stop_x;
|
|
+ u32 tvdetgp_int_start_stop_y;
|
|
+ u32 gen_ctrl;
|
|
+};
|
|
+
|
|
+/* from TRM */
|
|
+static const struct venc_config venc_config_pal_trm = {
|
|
+ .f_control = 0,
|
|
+ .vidout_ctrl = 1,
|
|
+ .sync_ctrl = 0x40,
|
|
+ .llen = 0x35F, /* 863 */
|
|
+ .flens = 0x270, /* 624 */
|
|
+ .hfltr_ctrl = 0,
|
|
+ .cc_carr_wss_carr = 0x2F7225ED,
|
|
+ .c_phase = 0,
|
|
+ .gain_u = 0x111,
|
|
+ .gain_v = 0x181,
|
|
+ .gain_y = 0x140,
|
|
+ .black_level = 0x3B,
|
|
+ .blank_level = 0x3B,
|
|
+ .x_color = 0x7,
|
|
+ .m_control = 0x2,
|
|
+ .bstamp_wss_data = 0x3F,
|
|
+ .s_carr = 0x2A098ACB,
|
|
+ .line21 = 0,
|
|
+ .ln_sel = 0x01290015,
|
|
+ .l21__wc_ctl = 0x0000F603,
|
|
+ .htrigger_vtrigger = 0,
|
|
+
|
|
+ .savid__eavid = 0x06A70108,
|
|
+ .flen__fal = 0x00180270,
|
|
+ .lal__phase_reset = 0x00040135,
|
|
+ .hs_int_start_stop_x = 0x00880358,
|
|
+ .hs_ext_start_stop_x = 0x000F035F,
|
|
+ .vs_int_start_x = 0x01A70000,
|
|
+ .vs_int_stop_x__vs_int_start_y = 0x000001A7,
|
|
+ .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
|
|
+ .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
|
|
+ .vs_ext_stop_y = 0x00000025,
|
|
+ .avid_start_stop_x = 0x03530083,
|
|
+ .avid_start_stop_y = 0x026C002E,
|
|
+ .fid_int_start_x__fid_int_start_y = 0x0001008A,
|
|
+ .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
|
|
+ .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
|
|
+
|
|
+ .tvdetgp_int_start_stop_x = 0x00140001,
|
|
+ .tvdetgp_int_start_stop_y = 0x00010001,
|
|
+ .gen_ctrl = 0x00FF0000,
|
|
+};
|
|
+
|
|
+/* from TRM */
|
|
+static const struct venc_config venc_config_ntsc_trm = {
|
|
+ .f_control = 0,
|
|
+ .vidout_ctrl = 1,
|
|
+ .sync_ctrl = 0x8040,
|
|
+ .llen = 0x359,
|
|
+ .flens = 0x20C,
|
|
+ .hfltr_ctrl = 0,
|
|
+ .cc_carr_wss_carr = 0x043F2631,
|
|
+ .c_phase = 0,
|
|
+ .gain_u = 0x102,
|
|
+ .gain_v = 0x16C,
|
|
+ .gain_y = 0x12F,
|
|
+ .black_level = 0x43,
|
|
+ .blank_level = 0x38,
|
|
+ .x_color = 0x7,
|
|
+ .m_control = 0x1,
|
|
+ .bstamp_wss_data = 0x38,
|
|
+ .s_carr = 0x21F07C1F,
|
|
+ .line21 = 0,
|
|
+ .ln_sel = 0x01310011,
|
|
+ .l21__wc_ctl = 0x0000F003,
|
|
+ .htrigger_vtrigger = 0,
|
|
+
|
|
+ .savid__eavid = 0x069300F4,
|
|
+ .flen__fal = 0x0016020C,
|
|
+ .lal__phase_reset = 0x00060107,
|
|
+ .hs_int_start_stop_x = 0x008E0350,
|
|
+ .hs_ext_start_stop_x = 0x000F0359,
|
|
+ .vs_int_start_x = 0x01A00000,
|
|
+ .vs_int_stop_x__vs_int_start_y = 0x020701A0,
|
|
+ .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
|
|
+ .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
|
|
+ .vs_ext_stop_y = 0x00000006,
|
|
+ .avid_start_stop_x = 0x03480078,
|
|
+ .avid_start_stop_y = 0x02060024,
|
|
+ .fid_int_start_x__fid_int_start_y = 0x0001008A,
|
|
+ .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
|
|
+ .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
|
|
+
|
|
+ .tvdetgp_int_start_stop_x = 0x00140001,
|
|
+ .tvdetgp_int_start_stop_y = 0x00010001,
|
|
+ .gen_ctrl = 0x00F90000,
|
|
+};
|
|
+
|
|
+static const struct venc_config venc_config_pal_bdghi = {
|
|
+ .f_control = 0,
|
|
+ .vidout_ctrl = 0,
|
|
+ .sync_ctrl = 0,
|
|
+ .hfltr_ctrl = 0,
|
|
+ .x_color = 0,
|
|
+ .line21 = 0,
|
|
+ .ln_sel = 21,
|
|
+ .htrigger_vtrigger = 0,
|
|
+ .tvdetgp_int_start_stop_x = 0x00140001,
|
|
+ .tvdetgp_int_start_stop_y = 0x00010001,
|
|
+ .gen_ctrl = 0x00FB0000,
|
|
+
|
|
+ .llen = 864-1,
|
|
+ .flens = 625-1,
|
|
+ .cc_carr_wss_carr = 0x2F7625ED,
|
|
+ .c_phase = 0xDF,
|
|
+ .gain_u = 0x111,
|
|
+ .gain_v = 0x181,
|
|
+ .gain_y = 0x140,
|
|
+ .black_level = 0x3e,
|
|
+ .blank_level = 0x3e,
|
|
+ .m_control = 0<<2 | 1<<1,
|
|
+ .bstamp_wss_data = 0x42,
|
|
+ .s_carr = 0x2a098acb,
|
|
+ .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
|
|
+ .savid__eavid = 0x06A70108,
|
|
+ .flen__fal = 23<<16 | 624<<0,
|
|
+ .lal__phase_reset = 2<<17 | 310<<0,
|
|
+ .hs_int_start_stop_x = 0x00920358,
|
|
+ .hs_ext_start_stop_x = 0x000F035F,
|
|
+ .vs_int_start_x = 0x1a7<<16,
|
|
+ .vs_int_stop_x__vs_int_start_y = 0x000601A7,
|
|
+ .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
|
|
+ .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
|
|
+ .vs_ext_stop_y = 0x05,
|
|
+ .avid_start_stop_x = 0x03530082,
|
|
+ .avid_start_stop_y = 0x0270002E,
|
|
+ .fid_int_start_x__fid_int_start_y = 0x0005008A,
|
|
+ .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
|
|
+ .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
|
|
+};
|
|
+
|
|
+const struct omap_video_timings omap_dss_pal_timings = {
|
|
+ .x_res = 720,
|
|
+ .y_res = 574,
|
|
+ .pixel_clock = 26181,
|
|
+ .hsw = 32,
|
|
+ .hfp = 80,
|
|
+ .hbp = 48,
|
|
+ .vsw = 7,
|
|
+ .vfp = 3,
|
|
+ .vbp = 6,
|
|
+};
|
|
+EXPORT_SYMBOL(omap_dss_pal_timings);
|
|
+
|
|
+const struct omap_video_timings omap_dss_ntsc_timings = {
|
|
+ .x_res = 720,
|
|
+ .y_res = 482,
|
|
+ .pixel_clock = 22153,
|
|
+ .hsw = 32,
|
|
+ .hfp = 80,
|
|
+ .hbp = 48,
|
|
+ .vsw = 10,
|
|
+ .vfp = 3,
|
|
+ .vbp = 6,
|
|
+};
|
|
+EXPORT_SYMBOL(omap_dss_ntsc_timings);
|
|
+
|
|
+static struct {
|
|
+ void __iomem *base;
|
|
+ struct mutex venc_lock;
|
|
+} venc;
|
|
+
|
|
+static struct omap_panel venc_panel = {
|
|
+ .name = "tv-out",
|
|
+};
|
|
+
|
|
+static inline void venc_write_reg(int idx, u32 val)
|
|
+{
|
|
+ __raw_writel(val, venc.base + idx);
|
|
+}
|
|
+
|
|
+static inline u32 venc_read_reg(int idx)
|
|
+{
|
|
+ u32 l = __raw_readl(venc.base + idx);
|
|
+ return l;
|
|
+}
|
|
+
|
|
+static void venc_write_config(const struct venc_config *config)
|
|
+{
|
|
+ DSSDBG("write venc conf\n");
|
|
+
|
|
+ venc_write_reg(VENC_LLEN, config->llen);
|
|
+ venc_write_reg(VENC_FLENS, config->flens);
|
|
+ venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
|
|
+ venc_write_reg(VENC_C_PHASE, config->c_phase);
|
|
+ venc_write_reg(VENC_GAIN_U, config->gain_u);
|
|
+ venc_write_reg(VENC_GAIN_V, config->gain_v);
|
|
+ venc_write_reg(VENC_GAIN_Y, config->gain_y);
|
|
+ venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
|
|
+ venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
|
|
+ venc_write_reg(VENC_M_CONTROL, config->m_control);
|
|
+ venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data);
|
|
+ venc_write_reg(VENC_S_CARR, config->s_carr);
|
|
+ venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
|
|
+ venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
|
|
+ venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
|
|
+ venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
|
|
+ venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
|
|
+ venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
|
|
+ venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
|
|
+ venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
|
|
+ config->vs_int_stop_x__vs_int_start_y);
|
|
+ venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
|
|
+ config->vs_int_stop_y__vs_ext_start_x);
|
|
+ venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
|
|
+ config->vs_ext_stop_x__vs_ext_start_y);
|
|
+ venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
|
|
+ venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
|
|
+ venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
|
|
+ venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
|
|
+ config->fid_int_start_x__fid_int_start_y);
|
|
+ venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
|
|
+ config->fid_int_offset_y__fid_ext_start_x);
|
|
+ venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
|
|
+ config->fid_ext_start_y__fid_ext_offset_y);
|
|
+
|
|
+ venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
|
|
+ venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
|
|
+ venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
|
|
+ venc_write_reg(VENC_X_COLOR, config->x_color);
|
|
+ venc_write_reg(VENC_LINE21, config->line21);
|
|
+ venc_write_reg(VENC_LN_SEL, config->ln_sel);
|
|
+ venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
|
|
+ venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
|
|
+ config->tvdetgp_int_start_stop_x);
|
|
+ venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
|
|
+ config->tvdetgp_int_start_stop_y);
|
|
+ venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
|
|
+ venc_write_reg(VENC_F_CONTROL, config->f_control);
|
|
+ venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
|
|
+}
|
|
+
|
|
+static void venc_reset(void)
|
|
+{
|
|
+ int t = 1000;
|
|
+
|
|
+ venc_write_reg(VENC_F_CONTROL, 1<<8);
|
|
+ while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
|
|
+ if (--t == 0) {
|
|
+ DSSERR("Failed to reset venc\n");
|
|
+ return;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ /* the magical sleep that makes things work */
|
|
+ msleep(20);
|
|
+}
|
|
+
|
|
+static void venc_enable_clocks(int enable)
|
|
+{
|
|
+ if (enable)
|
|
+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
|
|
+ DSS_CLK_96M);
|
|
+ else
|
|
+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M |
|
|
+ DSS_CLK_96M);
|
|
+}
|
|
+
|
|
+static const struct venc_config *venc_timings_to_config(
|
|
+ struct omap_video_timings *timings)
|
|
+{
|
|
+ if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
|
|
+ return &venc_config_pal_trm;
|
|
+
|
|
+ if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
|
|
+ return &venc_config_ntsc_trm;
|
|
+
|
|
+ BUG();
|
|
+}
|
|
+
|
|
+int venc_init(void)
|
|
+{
|
|
+ u8 rev_id;
|
|
+
|
|
+ mutex_init(&venc.venc_lock);
|
|
+
|
|
+ venc_panel.timings = omap_dss_pal_timings;
|
|
+
|
|
+ venc.base = ioremap(VENC_BASE, SZ_1K);
|
|
+ if (!venc.base) {
|
|
+ DSSERR("can't ioremap VENC\n");
|
|
+ return -ENOMEM;
|
|
+ }
|
|
+
|
|
+ venc_enable_clocks(1);
|
|
+
|
|
+ rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
|
|
+ printk(KERN_INFO "OMAP VENC rev %d\n", rev_id);
|
|
+
|
|
+ venc_enable_clocks(0);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+void venc_exit(void)
|
|
+{
|
|
+ iounmap(venc.base);
|
|
+}
|
|
+
|
|
+static void venc_power_on(struct omap_display *display)
|
|
+{
|
|
+ venc_enable_clocks(1);
|
|
+
|
|
+ venc_reset();
|
|
+ venc_write_config(venc_timings_to_config(&display->panel->timings));
|
|
+
|
|
+ dss_set_venc_output(display->hw_config.u.venc.type);
|
|
+ dss_set_dac_pwrdn_bgz(1);
|
|
+
|
|
+ if (display->hw_config.u.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE) {
|
|
+ if (cpu_is_omap24xx())
|
|
+ venc_write_reg(VENC_OUTPUT_CONTROL, 0x2);
|
|
+ else
|
|
+ venc_write_reg(VENC_OUTPUT_CONTROL, 0xa);
|
|
+ } else { /* S-Video */
|
|
+ venc_write_reg(VENC_OUTPUT_CONTROL, 0xd);
|
|
+ }
|
|
+
|
|
+ dispc_set_digit_size(display->panel->timings.x_res,
|
|
+ display->panel->timings.y_res/2);
|
|
+
|
|
+ if (display->hw_config.panel_enable)
|
|
+ display->hw_config.panel_enable(display);
|
|
+
|
|
+ dispc_enable_digit_out(1);
|
|
+}
|
|
+
|
|
+static void venc_power_off(struct omap_display *display)
|
|
+{
|
|
+ venc_write_reg(VENC_OUTPUT_CONTROL, 0);
|
|
+ dss_set_dac_pwrdn_bgz(0);
|
|
+
|
|
+ dispc_enable_digit_out(0);
|
|
+
|
|
+ if (display->hw_config.panel_disable)
|
|
+ display->hw_config.panel_disable(display);
|
|
+
|
|
+ venc_enable_clocks(0);
|
|
+}
|
|
+
|
|
+static int venc_enable_display(struct omap_display *display)
|
|
+{
|
|
+ int r = 0;
|
|
+
|
|
+ DSSDBG("venc_enable_display\n");
|
|
+
|
|
+ mutex_lock(&venc.venc_lock);
|
|
+
|
|
+ if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
|
|
+ r = -EINVAL;
|
|
+ goto err;
|
|
+ }
|
|
+
|
|
+ venc_power_on(display);
|
|
+
|
|
+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
|
|
+err:
|
|
+ mutex_unlock(&venc.venc_lock);
|
|
+
|
|
+ return r;
|
|
+}
|
|
+
|
|
+static void venc_disable_display(struct omap_display *display)
|
|
+{
|
|
+ DSSDBG("venc_disable_display\n");
|
|
+
|
|
+ mutex_lock(&venc.venc_lock);
|
|
+
|
|
+ if (display->state == OMAP_DSS_DISPLAY_DISABLED)
|
|
+ goto end;
|
|
+
|
|
+ if (display->state == OMAP_DSS_DISPLAY_SUSPENDED) {
|
|
+ /* suspended is the same as disabled with venc */
|
|
+ display->state = OMAP_DSS_DISPLAY_DISABLED;
|
|
+ goto end;
|
|
+ }
|
|
+
|
|
+ venc_power_off(display);
|
|
+
|
|
+ display->state = OMAP_DSS_DISPLAY_DISABLED;
|
|
+end:
|
|
+ mutex_unlock(&venc.venc_lock);
|
|
+}
|
|
+
|
|
+static int venc_display_suspend(struct omap_display *display)
|
|
+{
|
|
+ int r = 0;
|
|
+
|
|
+ DSSDBG("venc_display_suspend\n");
|
|
+
|
|
+ mutex_lock(&venc.venc_lock);
|
|
+
|
|
+ if (display->state != OMAP_DSS_DISPLAY_ACTIVE) {
|
|
+ r = -EINVAL;
|
|
+ goto err;
|
|
+ }
|
|
+
|
|
+ venc_power_off(display);
|
|
+
|
|
+ display->state = OMAP_DSS_DISPLAY_SUSPENDED;
|
|
+err:
|
|
+ mutex_unlock(&venc.venc_lock);
|
|
+
|
|
+ return r;
|
|
+}
|
|
+
|
|
+static int venc_display_resume(struct omap_display *display)
|
|
+{
|
|
+ int r = 0;
|
|
+
|
|
+ DSSDBG("venc_display_resume\n");
|
|
+
|
|
+ mutex_lock(&venc.venc_lock);
|
|
+
|
|
+ if (display->state != OMAP_DSS_DISPLAY_SUSPENDED) {
|
|
+ r = -EINVAL;
|
|
+ goto err;
|
|
+ }
|
|
+
|
|
+ venc_power_on(display);
|
|
+
|
|
+ display->state = OMAP_DSS_DISPLAY_ACTIVE;
|
|
+err:
|
|
+ mutex_unlock(&venc.venc_lock);
|
|
+
|
|
+ return r;
|
|
+}
|
|
+
|
|
+static void venc_get_timings(struct omap_display *display,
|
|
+ struct omap_video_timings *timings)
|
|
+{
|
|
+ *timings = venc_panel.timings;
|
|
+}
|
|
+
|
|
+static void venc_set_timings(struct omap_display *display,
|
|
+ struct omap_video_timings *timings)
|
|
+{
|
|
+ DSSDBG("venc_set_timings\n");
|
|
+ display->panel->timings = *timings;
|
|
+ if (display->state == OMAP_DSS_DISPLAY_ACTIVE) {
|
|
+ /* turn the venc off and on to get new timings to use */
|
|
+ venc_disable_display(display);
|
|
+ venc_enable_display(display);
|
|
+ }
|
|
+}
|
|
+
|
|
+static int venc_check_timings(struct omap_display *display,
|
|
+ struct omap_video_timings *timings)
|
|
+{
|
|
+ DSSDBG("venc_check_timings\n");
|
|
+
|
|
+ if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
|
|
+ return 0;
|
|
+
|
|
+ if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
|
|
+ return 0;
|
|
+
|
|
+ return -EINVAL;
|
|
+}
|
|
+
|
|
+void venc_init_display(struct omap_display *display)
|
|
+{
|
|
+ display->panel = &venc_panel;
|
|
+ display->enable = venc_enable_display;
|
|
+ display->disable = venc_disable_display;
|
|
+ display->suspend = venc_display_suspend;
|
|
+ display->resume = venc_display_resume;
|
|
+ display->get_timings = venc_get_timings;
|
|
+ display->set_timings = venc_set_timings;
|
|
+ display->check_timings = venc_check_timings;
|
|
+}
|
|
--
|
|
1.5.6.5
|
|
|