tremor: add a patch to build with arm thumb
Add IT instructions so that it builds with thumb tunes. ARM mode won't be affected since IT is a pseudo-instruction in ARM mode. (From OE-Core rev: b5187fa61b34ff94513fcf8f64ff5c588c211d06) Signed-off-by: Sen Zhang <sen.zhang@windriver.com> Signed-off-by: Saul Wold <sgw@linux.intel.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
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From: Xin Ouyang <Xin.Ouyang@windriver.com>
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Date: Mon, 16 Jul 2012 13:29:34 +0800
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Subject: [PATCH] tremor: add IT instructions for arm thumb2 tune flags.
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Upstream-Status: Pending
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In Thumb-2, most instructions do not have a built in condition code (except for
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conditional branches). Instead, short sequences of instructions which are to be
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executed conditionally can be preceded by a special "IT instruction" which
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describes the condition and which of the following instructions should be
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executed if the condition is false respectively.
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For the ARM/Thumb IT(If-Then) instruction:
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http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489c/Cjabicci.html
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Signed-off-by: Xin Ouyang <Xin.Ouyang@windriver.com>
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---
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asm_arm.h | 14 ++++++++++++++
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1 file changed, 14 insertions(+)
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diff --git a/asm_arm.h b/asm_arm.h
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index c3bda00..823c54f 100755
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--- a/asm_arm.h
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+++ b/asm_arm.h
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@@ -108,9 +108,11 @@ static inline void XNPROD31(ogg_int32_t a, ogg_int32_t b,
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static inline ogg_int32_t CLIP_TO_15(ogg_int32_t x) {
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int tmp;
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asm volatile("subs %1, %0, #32768\n\t"
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+ "itt pl\n\t"
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"movpl %0, #0x7f00\n\t"
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"orrpl %0, %0, #0xff\n"
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"adds %1, %0, #32768\n\t"
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+ "it mi\n\t"
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"movmi %0, #0x8000"
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: "+r"(x),"=r"(tmp)
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:
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@@ -139,10 +141,12 @@ static inline void lsp_loop_asm(ogg_uint32_t *qip,ogg_uint32_t *pip,
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"ldmdb r0!,{r1,r3};"
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"subs r1,r1,%4;" //ilsp[j]-wi
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+ "it mi;"
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"rsbmi r1,r1,#0;" //labs(ilsp[j]-wi)
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"umull %0,r2,r1,%0;" //qi*=labs(ilsp[j]-wi)
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"subs r1,r3,%4;" //ilsp[j+1]-wi
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+ "it mi;"
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"rsbmi r1,r1,#0;" //labs(ilsp[j+1]-wi)
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"umull %1,r3,r1,%1;" //pi*=labs(ilsp[j+1]-wi)
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@@ -167,6 +171,7 @@ static inline void lsp_loop_asm(ogg_uint32_t *qip,ogg_uint32_t *pip,
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"mov r0,#0x4000;\n"
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"subs r1,r1,%4;\n" //ilsp[j]-wi
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+ "it mi;\n"
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"rsbmi r1,r1,#0;\n" //labs(ilsp[j]-wi)
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"umull %0,r2,r1,%0;\n" //qi*=labs(ilsp[j]-wi)
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"umull %1,r3,r0,%1;\n" //pi*=labs(ilsp[j+1]-wi)
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@@ -190,18 +195,23 @@ static inline void lsp_loop_asm(ogg_uint32_t *qip,ogg_uint32_t *pip,
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"mov r2,#0;"
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"orr r1,%0,%1;"
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"tst r1,#0xff000000;"
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+ "itt ne;"
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"addne r2,r2,#8;"
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"movne r1,r1,lsr #8;"
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"tst r1,#0x00f00000;"
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+ "itt ne;"
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"addne r2,r2,#4;"
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"movne r1,r1,lsr #4;"
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"tst r1,#0x000c0000;"
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+ "itt ne;"
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"addne r2,r2,#2;"
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"movne r1,r1,lsr #2;"
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"tst r1,#0x00020000;"
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+ "itt ne;"
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"addne r2,r2,#1;"
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"movne r1,r1,lsr #1;"
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"tst r1,#0x00010000;"
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+ "it ne;"
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"addne r2,r2,#1;"
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"mov %0,%0,lsr r2;"
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"mov %1,%1,lsr r2;"
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@@ -222,15 +232,19 @@ static inline void lsp_norm_asm(ogg_uint32_t *qip,ogg_int32_t *qexpp){
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ogg_int32_t qexp=*qexpp;
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asm("tst %0,#0x0000ff00;"
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+ "itt eq;"
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"moveq %0,%0,lsl #8;"
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"subeq %1,%1,#8;"
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"tst %0,#0x0000f000;"
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+ "itt eq;"
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"moveq %0,%0,lsl #4;"
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"subeq %1,%1,#4;"
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"tst %0,#0x0000c000;"
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+ "itt eq;"
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"moveq %0,%0,lsl #2;"
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"subeq %1,%1,#2;"
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"tst %0,#0x00008000;"
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+ "itt eq;"
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"moveq %0,%0,lsl #1;"
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"subeq %1,%1,#1;"
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: "+r"(qi),"+r"(qexp)
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--
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1.7.9.5
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@ -10,6 +10,7 @@ PR = "r1"
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SRC_URI = "svn://svn.xiph.org/trunk;module=Tremor;rev=18221;protocol=http \
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file://obsolete_automake_macros.patch;striplevel=0 \
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file://tremor-arm-thumb2.patch \
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"
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S = "${WORKDIR}/Tremor"
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