siteinfo.bbclass: Port over oe.dev logic for site files
In oe.dev we have a sets to pick out hostos/hostarch/etc site files out of and include things like a common-linux site file. This should also help out with adding multilib-specific site files (ie x32). In oe.dev we have an iterator but at Richard's request we continue to return a list of files in siteinfo_get_files(). (From OE-Core rev: cb3d7cd1c0f2bbcd448abbb832074ca965e0af5e) Signed-off-by: Tom Rini <tom_rini@mentor.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This commit is contained in:
Tom Rini
Richard Purdie
parent
fe7db148c2
commit
997b1fc7f7
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@ -15,121 +15,114 @@
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# It is an error for the target not to exist.
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# If 'what' doesn't exist then an empty value is returned
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#
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def get_siteinfo_list(d):
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target = bb.data.getVar('HOST_ARCH', d, 1) + "-" + bb.data.getVar('HOST_OS', d, 1)
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def siteinfo_data(d):
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archinfo = {
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"allarch": "endian-little bit-32", # bogus, but better than special-casing the checks below for allarch
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"arm": "endian-little bit-32 arm-common",
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"armeb": "endian-big bit-32 arm-common",
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"avr32": "endian-big bit-32 avr32-common",
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"bfin": "endian-little bit-32 bfin-common",
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"i386": "endian-little bit-32 ix86-common",
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"i486": "endian-little bit-32 ix86-common",
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"i586": "endian-little bit-32 ix86-common",
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"i686": "endian-little bit-32 ix86-common",
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"ia64": "endian-little bit-64",
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"microblaze": "endian-big bit-32 microblaze-common",
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"microblazeel": "endian-little bit-32 microblaze-common",
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"mips": "endian-big bit-32 mips-common",
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"mips64": "endian-big bit-64 mips64-common",
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"mips64el": "endian-little bit-64 mips64-common",
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"mipsel": "endian-little bit-32 mips-common",
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"powerpc": "endian-big bit-32 powerpc-common",
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"nios2": "endian-little bit-32 nios2-common",
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"powerpc64": "endian-big bit-64 powerpc-common powerpc64-linux",
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"ppc": "endian-big bit-32 powerpc-common",
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"ppc64": "endian-big bit-64 powerpc-common powerpc64-linux",
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"sh3": "endian-little bit-32 sh-common",
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"sh4": "endian-little bit-32 sh-common",
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"sparc": "endian-big bit-32",
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"viac3": "endian-little bit-32 ix86-common",
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"x86_64": "endian-little bit-64",
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}
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osinfo = {
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"darwin": "common-darwin",
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"darwin9": "common-darwin",
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"linux": "common-linux common-glibc",
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"linux-gnueabi": "common-linux common-glibc",
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"linux-gnuspe": "common-linux common-glibc",
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"linux-uclibc": "common-linux common-uclibc",
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"linux-uclibceabi": "common-linux common-uclibc",
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"linux-uclibcspe": "common-linux common-uclibc",
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"uclinux-uclibc": "common-uclibc",
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"cygwin": "common-cygwin",
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"mingw32": "common-mingw",
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}
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targetinfo = {
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"arm-linux-gnueabi": "arm-linux",
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"arm-linux-uclibceabi": "arm-linux-uclibc",
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"armeb-linux-gnueabi": "armeb-linux",
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"armeb-linux-uclibceabi": "armeb-linux-uclibc",
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"powerpc-linux-gnuspe": "powerpc-linux",
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"powerpc-linux-uclibcspe": "powerpc-linux-uclibc",
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}
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targetinfo = {\
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"allarch-linux": "",\
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"armeb-linux": "endian-big bit-32 common-glibc arm-common",\
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"armeb-linux-gnueabi": "endian-big bit-32 common-glibc arm-common armeb-linux",\
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"armeb-linux-uclibc": "endian-big bit-32 common-uclibc arm-common",\
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"armeb-linux-uclibceabi": "endian-big bit-32 common-uclibc arm-common armeb-linux-uclibc",\
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"arm-darwin": "endian-little bit-32 common-darwin",\
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"arm-darwin8": "endian-little bit-32 common-darwin",\
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"arm-linux": "endian-little bit-32 common-glibc arm-common",\
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"arm-linux-gnueabi": "endian-little bit-32 common-glibc arm-common arm-linux",\
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"arm-linux-uclibc": "endian-little bit-32 common-uclibc arm-common",\
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"arm-linux-uclibceabi": "endian-little bit-32 common-uclibc arm-common arm-linux-uclibc",\
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"avr32-linux": "endian-big bit-32 common-glibc avr32-common",\
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"avr32-linux-uclibc": "endian-big bit-32 common-uclibc avr32-common",\
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"bfin-uclinux-uclibc": "endian-little bit-32 common-uclibc bfin-common",\
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"i386-linux": "endian-little bit-32 common-glibc ix86-common",\
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"i486-linux": "endian-little bit-32 common-glibc ix86-common",\
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"i586-linux": "endian-little bit-32 common-glibc ix86-common",\
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"i686-linux": "endian-little bit-32 common-glibc ix86-common",\
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"i386-linux-uclibc": "endian-little bit-32 common-uclibc ix86-common",\
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"i486-linux-uclibc": "endian-little bit-32 common-uclibc ix86-common",\
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"i586-linux-uclibc": "endian-little bit-32 common-uclibc ix86-common",\
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"i686-linux-uclibc": "endian-little bit-32 common-uclibc ix86-common",\
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"microblaze-linux-gnu": "endian-big bit-32 common-glibc microblaze-common",\
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"microblazeel-linux-gnu": "endian-little bit-32 common-glibc microblaze-common",\
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"mipsel-linux": "endian-little bit-32 common-glibc mips-common",\
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"mipsel-linux-uclibc": "endian-little bit-32 common-uclibc mips-common",\
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"mips-linux": "endian-big bit-32 common-glibc mips-common",\
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"mips-linux-uclibc": "endian-big bit-32 common-uclibc mips-common",\
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"powerpc-darwin": "endian-big bit-32 common-darwin",\
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"ppc-linux": "endian-big bit-32 common-glibc powerpc-common",\
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"powerpc-linux": "endian-big bit-32 common-glibc powerpc-common",\
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"powerpc-linux-gnuspe": "endian-big bit-32 common-glibc powerpc-common",\
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"powerpc-linux-uclibc": "endian-big bit-32 common-uclibc powerpc-common",\
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"sh3-linux": "endian-little bit-32 common-glibc sh-common",\
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"sh4-linux": "endian-little bit-32 common-glibc sh-common",\
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"sh4-linux-uclibc": "endian-little bit-32 common-uclibc sh-common",\
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"sparc-linux": "endian-big bit-32 common-glibc",\
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"x86_64-linux": "endian-little bit-64 common-glibc",\
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"x86_64-linux-uclibc": "endian-little bit-64 common-uclibc"}
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if target in targetinfo:
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info = targetinfo[target].split()
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info.append(target)
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info.append("common")
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return info
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else:
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bb.error("Information not available for target '%s'" % target)
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hostarch = d.getVar("HOST_ARCH", True)
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hostos = d.getVar("HOST_OS", True)
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target = "%s-%s" % (hostarch, hostos)
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sitedata = []
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if hostarch in archinfo:
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sitedata.extend(archinfo[hostarch].split())
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if hostos in osinfo:
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sitedata.extend(osinfo[hostos].split())
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if target in targetinfo:
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sitedata.extend(targetinfo[target].split())
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sitedata.append(target)
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sitedata.append("common")
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bb.debug(1, "SITE files %s" % sitedata);
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return sitedata
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python () {
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sitedata = set(siteinfo_data(d))
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if "endian-little" in sitedata:
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d.setVar("SITEINFO_ENDIANESS", "le")
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elif "endian-big" in sitedata:
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d.setVar("SITEINFO_ENDIANESS", "be")
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else:
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bb.error("Unable to determine endianness for architecture '%s'" %
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d.getVar("HOST_ARCH", True))
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bb.fatal("Please add your architecture to siteinfo.bbclass")
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if "bit-32" in sitedata:
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d.setVar("SITEINFO_BITS", "32")
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elif "bit-64" in sitedata:
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d.setVar("SITEINFO_BITS", "64")
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else:
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bb.error("Unable to determine bit size for architecture '%s'" %
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d.getVar("HOST_ARCH", True))
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bb.fatal("Please add your architecture to siteinfo.bbclass")
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}
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#
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# Define which site files to use. We check for several site files and
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# use each one that is found, based on the list returned by get_siteinfo_list()
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#
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# Search for the files in the following directories:
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# 1) ${BBPATH}/site (in reverse) - app specific, then site wide
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# 2) ${FILE_DIRNAME}/site-${PV} - app version specific
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#
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def siteinfo_get_files(d):
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sitefiles = ""
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sitedata = siteinfo_data(d)
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sitefiles = ""
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for path in d.getVar("BBPATH", True).split(":"):
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for element in sitedata:
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filename = os.path.join(path, "site", element)
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if os.path.exists(filename):
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sitefiles += filename + " "
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# Determine which site files to look for
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sites = get_siteinfo_list(d)
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# Now check for siteconfig cache files
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path_siteconfig = bb.data.getVar('SITECONFIG_SYSROOTCACHE', d, 1)
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if os.path.isdir(path_siteconfig):
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for i in os.listdir(path_siteconfig):
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filename = os.path.join(path_siteconfig, i)
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sitefiles += filename + " "
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# Check along bbpath for site files and append in reverse order so
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# the application specific sites files are last and system site
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# files first.
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path_bb = bb.data.getVar('BBPATH', d, 1)
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for p in (path_bb or "").split(':'):
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tmp = ""
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for i in sites:
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fname = os.path.join(p, 'site', i)
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if os.path.exists(fname):
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tmp += fname + " "
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sitefiles = tmp + sitefiles;
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# Now check for the applications version specific site files
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path_pkgv = os.path.join(bb.data.getVar('FILE_DIRNAME', d, 1), "site-" + bb.data.getVar('PV', d, 1))
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for i in sites:
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fname = os.path.join(path_pkgv, i)
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if os.path.exists(fname):
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sitefiles += fname + " "
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# Now check for siteconfig cache files
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path_siteconfig = bb.data.getVar('SITECONFIG_SYSROOTCACHE', d, 1)
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if os.path.isdir(path_siteconfig):
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for i in os.listdir(path_siteconfig):
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fname = os.path.join(path_siteconfig, i)
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sitefiles += fname + " "
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bb.debug(1, "SITE files " + sitefiles);
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return sitefiles
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def siteinfo_get_endianess(d):
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info = get_siteinfo_list(d)
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if 'endian-little' in info:
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return "le"
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elif 'endian-big' in info:
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return "be"
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bb.error("Site info could not determine endianess for target")
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def siteinfo_get_bits(d):
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info = get_siteinfo_list(d)
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if 'bit-32' in info:
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return "32"
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elif 'bit-64' in info:
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return "64"
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bb.error("Site info could not determine bit size for target")
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return sitefiles
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#
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# Make some information available via variables
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#
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SITEINFO_ENDIANESS = "${@siteinfo_get_endianess(d)}"
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SITEINFO_BITS = "${@siteinfo_get_bits(d)}"
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SITECONFIG_SYSROOTCACHE = "${STAGING_DATADIR}/${TARGET_SYS}_config_site.d"
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