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linux-omap2: Add from OE for beagleboard 

git-svn-id: https://svn.o-hand.com/repos/poky/trunk@4869 311d38ba-8fff-0310-9ca6-ca027cbcb966
This commit is contained in:
Richard Purdie 2008-07-18 08:35:45 +00:00
parent e9ebcc4c19
commit 78fc9af3a9
33 changed files with 89332 additions and 0 deletions
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55
meta/packages/linux/linux-omap2-git/beagleboard/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch Normal file
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@ -0,0 +1,55 @@
From a1dbb6dd28e9815a307b87b8d96dcf371d6cfd58 Mon Sep 17 00:00:00 2001
From: Jarkko Nikula <jarkko.nikula@nokia.com>
Date: Mon, 19 May 2008 13:24:41 +0300
Subject: [PATCH] ASoC: OMAP: Add basic support for OMAP34xx in McBSP DAI driver
This adds support for OMAP34xx McBSP port 1 and 2.
Signed-off-by: Jarkko Nikula <jarkko.nikula@nokia.com>
---
sound/soc/omap/omap-mcbsp.c | 20 +++++++++++++++++++-
1 files changed, 19 insertions(+), 1 deletions(-)
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index 40d87e6..8e6ec9d 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -99,6 +99,21 @@ static const unsigned long omap2420_mcbsp_port[][2] = {
static const int omap2420_dma_reqs[][2] = {};
static const unsigned long omap2420_mcbsp_port[][2] = {};
#endif
+#if defined(CONFIG_ARCH_OMAP34XX)
+static const int omap34xx_dma_reqs[][2] = {
+ { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
+ { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
+};
+static const unsigned long omap34xx_mcbsp_port[][2] = {
+ { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR2,
+ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR2 },
+ { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR2,
+ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR2 },
+};
+#else
+static const int omap34xx_dma_reqs[][2] = {};
+static const unsigned long omap34xx_mcbsp_port[][2] = {};
+#endif
static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream)
{
@@ -169,9 +184,12 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
} else if (cpu_is_omap2420()) {
dma = omap2420_dma_reqs[bus_id][substream->stream];
port = omap2420_mcbsp_port[bus_id][substream->stream];
+ } else if (cpu_is_omap343x()) {
+ dma = omap34xx_dma_reqs[bus_id][substream->stream];
+ port = omap34xx_mcbsp_port[bus_id][substream->stream];
} else {
/*
- * TODO: Add support for 2430 and 3430
+ * TODO: Add support for 2430
*/
return -ENODEV;
}
--
1.5.5.1

450
meta/packages/linux/linux-omap2-git/beagleboard/0001-omap3-cpuidle.patch Normal file
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@ -0,0 +1,450 @@
From: "Rajendra Nayak" <rnayak@ti.com>
To: <linux-omap@vger.kernel.org>
Subject: [PATCH 01/02] OMAP3 CPUidle driver
Date: Tue, 10 Jun 2008 12:39:00 +0530
This patch adds the OMAP3 cpuidle driver. Irq enable/disable is done in the core cpuidle driver
before it queries the governor for the next state.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/mach-omap2/Makefile | 2
arch/arm/mach-omap2/cpuidle34xx.c | 293 ++++++++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/cpuidle34xx.h | 51 ++++++
arch/arm/mach-omap2/pm34xx.c | 5
drivers/cpuidle/cpuidle.c | 10 +
5 files changed, 359 insertions(+), 2 deletions(-)
Index: linux-omap-2.6/arch/arm/mach-omap2/Makefile
===================================================================
--- linux-omap-2.6.orig/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:33.855303920 +0530
+++ linux-omap-2.6/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:39.569121361 +0530
@@ -20,7 +20,7 @@ obj-y += pm.o
obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
obj-$(CONFIG_ARCH_OMAP2420) += sleep242x.o
obj-$(CONFIG_ARCH_OMAP2430) += sleep243x.o
-obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
+obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
endif
Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c 2008-06-10 11:41:27.644820323 +0530
@@ -0,0 +1,293 @@
+/*
+ * linux/arch/arm/mach-omap2/cpuidle34xx.c
+ *
+ * OMAP3 CPU IDLE Routines
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Karthik Dasu <karthik-dp@ti.com>
+ *
+ * Copyright (C) 2006 Nokia Corporation
+ * Tony Lindgren <tony@atomide.com>
+ *
+ * Copyright (C) 2005 Texas Instruments, Inc.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/cpuidle.h>
+#include <asm/arch/pm.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/powerdomain.h>
+#include <asm/arch/clockdomain.h>
+#include <asm/arch/irqs.h>
+#include "cpuidle34xx.h"
+
+#ifdef CONFIG_CPU_IDLE
+
+struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
+struct omap3_processor_cx current_cx_state;
+
+static int omap3_idle_bm_check(void)
+{
+ /* Check for omap3_fclks_active() here once available */
+ return 0;
+}
+
+/* omap3_enter_idle - Programs OMAP3 to enter the specified state.
+ * returns the total time during which the system was idle.
+ */
+static int omap3_enter_idle(struct cpuidle_device *dev,
+ struct cpuidle_state *state)
+{
+ struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
+ struct timespec ts_preidle, ts_postidle, ts_idle;
+ struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd;
+ int neon_pwrst;
+
+ current_cx_state = *cx;
+
+ if (cx->type == OMAP3_STATE_C0) {
+ /* Do nothing for C0, not even a wfi */
+ return 0;
+ }
+
+ /* Used to keep track of the total time in idle */
+ getnstimeofday(&ts_preidle);
+
+ mpu_pd = pwrdm_lookup("mpu_pwrdm");
+ core_pd = pwrdm_lookup("core_pwrdm");
+ per_pd = pwrdm_lookup("per_pwrdm");
+ neon_pd = pwrdm_lookup("neon_pwrdm");
+
+ /* Reset previous power state registers */
+ pwrdm_clear_all_prev_pwrst(mpu_pd);
+ pwrdm_clear_all_prev_pwrst(neon_pd);
+ pwrdm_clear_all_prev_pwrst(core_pd);
+ pwrdm_clear_all_prev_pwrst(per_pd);
+
+ if (omap_irq_pending())
+ return 0;
+
+ neon_pwrst = pwrdm_read_pwrst(neon_pd);
+
+ /* Program MPU/NEON to target state */
+ if (cx->mpu_state < PWRDM_POWER_ON) {
+ if (neon_pwrst == PWRDM_POWER_ON) {
+ if (cx->mpu_state == PWRDM_POWER_RET)
+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);
+ else if (cx->mpu_state == PWRDM_POWER_OFF)
+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF);
+ }
+ pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
+ }
+
+ /* Program CORE to target state */
+ if (cx->core_state < PWRDM_POWER_ON)
+ pwrdm_set_next_pwrst(core_pd, cx->core_state);
+
+ /* Execute ARM wfi */
+ omap_sram_idle();
+
+ /* Program MPU/NEON to ON */
+ if (cx->mpu_state < PWRDM_POWER_ON) {
+ if (neon_pwrst == PWRDM_POWER_ON)
+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON);
+ pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON);
+ }
+
+ if (cx->core_state < PWRDM_POWER_ON)
+ pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON);
+
+ getnstimeofday(&ts_postidle);
+ ts_idle = timespec_sub(ts_postidle, ts_preidle);
+ return timespec_to_ns(&ts_idle);
+}
+
+/*
+ * omap3_enter_idle_bm - enter function for states with CPUIDLE_FLAG_CHECK_BM
+ *
+ * This function checks for all the pre-requisites needed for OMAP3 to enter
+ * CORE RET/OFF state. It then calls omap3_enter_idle to program the desired
+ * C state.
+ */
+static int omap3_enter_idle_bm(struct cpuidle_device *dev,
+ struct cpuidle_state *state)
+{
+ struct cpuidle_state *new_state = NULL;
+ int i, j;
+
+ if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
+
+ /* Find current state in list */
+ for (i = 0; i < OMAP3_MAX_STATES; i++)
+ if (state == &dev->states[i])
+ break;
+ BUG_ON(i == OMAP3_MAX_STATES);
+
+ /* Back up to non 'CHECK_BM' state */
+ for (j = i - 1; j > 0; j--) {
+ struct cpuidle_state *s = &dev->states[j];
+
+ if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) {
+ new_state = s;
+ break;
+ }
+ }
+
+ pr_debug("%s: Bus activity: Entering %s (instead of %s)\n",
+ __FUNCTION__, new_state->name, state->name);
+ }
+
+ return omap3_enter_idle(dev, new_state ? : state);
+}
+
+DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
+
+/* omap3_init_power_states - Initialises the OMAP3 specific C states.
+ * Below is the desciption of each C state.
+ *
+ C0 . System executing code
+ C1 . MPU WFI + Core active
+ C2 . MPU CSWR + Core active
+ C3 . MPU OFF + Core active
+ C4 . MPU CSWR + Core CSWR
+ C5 . MPU OFF + Core CSWR
+ C6 . MPU OFF + Core OFF
+ */
+void omap_init_power_states(void)
+{
+ /* C0 . System executing code */
+ omap3_power_states[0].valid = 1;
+ omap3_power_states[0].type = OMAP3_STATE_C0;
+ omap3_power_states[0].sleep_latency = 0;
+ omap3_power_states[0].wakeup_latency = 0;
+ omap3_power_states[0].threshold = 0;
+ omap3_power_states[0].mpu_state = PWRDM_POWER_ON;
+ omap3_power_states[0].core_state = PWRDM_POWER_ON;
+ omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_SHALLOW;
+
+ /* C1 . MPU WFI + Core active */
+ omap3_power_states[1].valid = 1;
+ omap3_power_states[1].type = OMAP3_STATE_C1;
+ omap3_power_states[1].sleep_latency = 10;
+ omap3_power_states[1].wakeup_latency = 10;
+ omap3_power_states[1].threshold = 30;
+ omap3_power_states[1].mpu_state = PWRDM_POWER_ON;
+ omap3_power_states[1].core_state = PWRDM_POWER_ON;
+ omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_SHALLOW;
+
+ /* C2 . MPU CSWR + Core active */
+ omap3_power_states[2].valid = 1;
+ omap3_power_states[2].type = OMAP3_STATE_C2;
+ omap3_power_states[2].sleep_latency = 50;
+ omap3_power_states[2].wakeup_latency = 50;
+ omap3_power_states[2].threshold = 300;
+ omap3_power_states[2].mpu_state = PWRDM_POWER_RET;
+ omap3_power_states[2].core_state = PWRDM_POWER_ON;
+ omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_BALANCED;
+
+ /* C3 . MPU OFF + Core active */
+ omap3_power_states[3].valid = 0;
+ omap3_power_states[3].type = OMAP3_STATE_C3;
+ omap3_power_states[3].sleep_latency = 1500;
+ omap3_power_states[3].wakeup_latency = 1800;
+ omap3_power_states[3].threshold = 4000;
+ omap3_power_states[3].mpu_state = PWRDM_POWER_OFF;
+ omap3_power_states[3].core_state = PWRDM_POWER_RET;
+ omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_BALANCED;
+
+ /* C4 . MPU CSWR + Core CSWR*/
+ omap3_power_states[4].valid = 1;
+ omap3_power_states[4].type = OMAP3_STATE_C4;
+ omap3_power_states[4].sleep_latency = 2500;
+ omap3_power_states[4].wakeup_latency = 7500;
+ omap3_power_states[4].threshold = 12000;
+ omap3_power_states[4].mpu_state = PWRDM_POWER_RET;
+ omap3_power_states[4].core_state = PWRDM_POWER_RET;
+ omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
+
+ /* C5 . MPU OFF + Core CSWR */
+ omap3_power_states[5].valid = 0;
+ omap3_power_states[5].type = OMAP3_STATE_C5;
+ omap3_power_states[5].sleep_latency = 3000;
+ omap3_power_states[5].wakeup_latency = 8500;
+ omap3_power_states[5].threshold = 15000;
+ omap3_power_states[5].mpu_state = PWRDM_POWER_OFF;
+ omap3_power_states[5].core_state = PWRDM_POWER_RET;
+ omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
+
+ /* C6 . MPU OFF + Core OFF */
+ omap3_power_states[6].valid = 0;
+ omap3_power_states[6].type = OMAP3_STATE_C6;
+ omap3_power_states[6].sleep_latency = 10000;
+ omap3_power_states[6].wakeup_latency = 30000;
+ omap3_power_states[6].threshold = 300000;
+ omap3_power_states[6].mpu_state = PWRDM_POWER_OFF;
+ omap3_power_states[6].core_state = PWRDM_POWER_OFF;
+ omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM;
+}
+
+struct cpuidle_driver omap3_idle_driver = {
+ .name = "omap3_idle",
+ .owner = THIS_MODULE,
+};
+/*
+ * omap3_idle_init - Init routine for OMAP3 idle.
+ * Registers the OMAP3 specific cpuidle driver with the cpuidle f/w
+ * with the valid set of states.
+ */
+int omap3_idle_init(void)
+{
+ int i, count = 0;
+ struct omap3_processor_cx *cx;
+ struct cpuidle_state *state;
+ struct cpuidle_device *dev;
+
+ omap_init_power_states();
+ cpuidle_register_driver(&omap3_idle_driver);
+
+ dev = &per_cpu(omap3_idle_dev, smp_processor_id());
+
+ for (i = 0; i < OMAP3_MAX_STATES; i++) {
+ cx = &omap3_power_states[i];
+ state = &dev->states[count];
+
+ if (!cx->valid)
+ continue;
+ cpuidle_set_statedata(state, cx);
+ state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
+ state->target_residency = cx->threshold;
+ state->flags = cx->flags;
+ state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
+ omap3_enter_idle_bm : omap3_enter_idle;
+ sprintf(state->name, "C%d", count+1);
+ count++;
+ }
+
+ if (!count)
+ return -EINVAL;
+ dev->state_count = count;
+
+ if (cpuidle_register_device(dev)) {
+ printk(KERN_ERR "%s: CPUidle register device failed\n",
+ __FUNCTION__);
+ return -EIO;
+ }
+
+ return 0;
+}
+__initcall(omap3_idle_init);
+#endif /* CONFIG_CPU_IDLE */
Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h 2008-06-09 20:15:39.569121361 +0530
@@ -0,0 +1,51 @@
+/*
+ * linux/arch/arm/mach-omap2/cpuidle34xx.h
+ *
+ * OMAP3 cpuidle structure definitions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Written by Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * History:
+ *
+ */
+
+#ifndef ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX
+#define ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX
+
+#define OMAP3_MAX_STATES 7
+#define OMAP3_STATE_C0 0 /* C0 - System executing code */
+#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */
+#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */
+#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */
+#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */
+#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */
+#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */
+
+extern void omap_sram_idle(void);
+extern int omap3_irq_pending(void);
+
+struct omap3_processor_cx {
+ u8 valid;
+ u8 type;
+ u32 sleep_latency;
+ u32 wakeup_latency;
+ u32 mpu_state;
+ u32 core_state;
+ u32 threshold;
+ u32 flags;
+};
+
+void omap_init_power_states(void);
+int omap3_idle_init(void);
+
+#endif /* ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX */
+
Index: linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c
===================================================================
--- linux-omap-2.6.orig/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:15:33.855303920 +0530
+++ linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:16:20.976798343 +0530
@@ -141,7 +141,7 @@ static irqreturn_t prcm_interrupt_handle
return IRQ_HANDLED;
}
-static void omap_sram_idle(void)
+void omap_sram_idle(void)
{
/* Variable to tell what needs to be saved and restored
* in omap_sram_idle*/
@@ -156,6 +156,7 @@ static void omap_sram_idle(void)
mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
switch (mpu_next_state) {
+ case PWRDM_POWER_ON:
case PWRDM_POWER_RET:
/* No need to save context */
save_state = 0;
@@ -386,7 +387,9 @@ int __init omap3_pm_init(void)
prcm_setup_regs();
+#ifndef CONFIG_CPU_IDLE
pm_idle = omap3_pm_idle;
+#endif
err1:
return ret;
Index: linux-omap-2.6/drivers/cpuidle/cpuidle.c
===================================================================
--- linux-omap-2.6.orig/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:33.856303888 +0530
+++ linux-omap-2.6/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:39.570121329 +0530
@@ -58,6 +58,11 @@ static void cpuidle_idle_call(void)
return;
}
+#ifdef CONFIG_ARCH_OMAP3
+ local_irq_disable();
+ local_fiq_disable();
+#endif
+
/* ask the governor for the next state */
next_state = cpuidle_curr_governor->select(dev);
if (need_resched())
@@ -70,6 +75,11 @@ static void cpuidle_idle_call(void)
target_state->time += (unsigned long long)dev->last_residency;
target_state->usage++;
+#ifdef CONFIG_ARCH_OMAP3
+ local_irq_enable();
+ local_fiq_enable();
+#endif
+
/* give the governor an opportunity to reflect on the outcome */
if (cpuidle_curr_governor->reflect)
cpuidle_curr_governor->reflect(dev);
--
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69
meta/packages/linux/linux-omap2-git/beagleboard/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch Normal file
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@ -0,0 +1,69 @@
From 7a444ee080c5f1a62ac5042f1e7926622b3e1ce7 Mon Sep 17 00:00:00 2001
From: Koen Kooi <koen@openembedded.org>
Date: Fri, 30 May 2008 13:43:36 +0200
Subject: [PATCH] ARM: OMAP: omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver
omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver
* on revision A5 and earlier board the two leds can't be controlled seperately, should be fixed in rev. B and C boards.
Signed-off-by: Koen Kooi <koen@openembedded.org>
---
arch/arm/mach-omap2/board-omap3beagle.c | 28 ++++++++++++++++++++++++++++
1 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index c992cc7..83891fc 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -19,6 +19,7 @@
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/leds.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
@@ -72,6 +73,32 @@ static struct omap_lcd_config omap3_beagle_lcd_config __initdata = {
.ctrl_name = "internal",
};
+struct gpio_led gpio_leds[] = {
+ {
+ .name = "beagleboard::led0",
+ .default_trigger = "none",
+ .gpio = 149,
+ },
+ {
+ .name = "beagleboard::led1",
+ .default_trigger = "none",
+ .gpio = 150,
+ },
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+ .leds = gpio_leds,
+ .num_leds = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &gpio_led_info,
+ },
+};
+
static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
{ OMAP_TAG_UART, &omap3_beagle_uart_config },
{ OMAP_TAG_MMC, &omap3beagle_mmc_config },
@@ -83,6 +110,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = {
#ifdef CONFIG_RTC_DRV_TWL4030
&omap3_beagle_twl4030rtc_device,
#endif
+ &leds_gpio,
};
static void __init omap3_beagle_init(void)
--
1.5.4.3

88
meta/packages/linux/linux-omap2-git/beagleboard/0002-omap3-cpuidle.patch Normal file
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@ -0,0 +1,88 @@
From: "Rajendra Nayak" <rnayak@ti.com>
To: <linux-omap@vger.kernel.org>
Subject: [PATCH 02/02] Kconfig changes
Date: Tue, 10 Jun 2008 12:39:02 +0530
Updates the CPUidle Kconfig
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/Kconfig | 10 ++++++++++
drivers/cpuidle/Kconfig | 28 ++++++++++++++++++++++------
2 files changed, 32 insertions(+), 6 deletions(-)
Index: linux-omap-2.6/arch/arm/Kconfig
===================================================================
--- linux-omap-2.6.orig/arch/arm/Kconfig 2008-06-10 11:43:10.790502713 +0530
+++ linux-omap-2.6/arch/arm/Kconfig 2008-06-10 11:43:38.701604549 +0530
@@ -954,6 +954,16 @@ config ATAGS_PROC
endmenu
+if (ARCH_OMAP)
+
+menu "CPUIdle"
+
+source "drivers/cpuidle/Kconfig"
+
+endmenu
+
+endif
+
if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
menu "CPU Frequency scaling"
Index: linux-omap-2.6/drivers/cpuidle/Kconfig
===================================================================
--- linux-omap-2.6.orig/drivers/cpuidle/Kconfig 2008-06-10 11:43:10.790502713 +0530
+++ linux-omap-2.6/drivers/cpuidle/Kconfig 2008-06-10 12:06:36.139332151 +0530
@@ -1,20 +1,36 @@
+menu "CPU idle PM support"
config CPU_IDLE
bool "CPU idle PM support"
- default ACPI
+ default n
help
CPU idle is a generic framework for supporting software-controlled
idle processor power management. It includes modular cross-platform
governors that can be swapped during runtime.
- If you're using an ACPI-enabled platform, you should say Y here.
+ If you're using a mobile platform that supports CPU idle PM (e.g.
+ an ACPI-capable notebook), you should say Y here.
+
+if CPU_IDLE
+
+comment "Governors"
config CPU_IDLE_GOV_LADDER
- bool
+ bool "ladder"
depends on CPU_IDLE
- default y
+ default n
config CPU_IDLE_GOV_MENU
- bool
+ bool "menu"
depends on CPU_IDLE && NO_HZ
- default y
+ default n
+ help
+ This cpuidle governor evaluates all available states and chooses the
+ deepest state that meets all of the following constraints: BM activity,
+ expected time until next timer interrupt, and last break event time
+ delta. It is designed to minimize power consumption. Currently
+ dynticks is required.
+
+endif # CPU_IDLE
+
+endmenu
--
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13
meta/packages/linux/linux-omap2-git/beagleboard/16bpp.patch Normal file
View File

@ -0,0 +1,13 @@
diff --git a/drivers/video/omap/lcd_omap3beagle.c b/drivers/video/omap/lcd_omap3beagle.c
index 69d4e06..c1c4f4c 100644
--- a/drivers/video/omap/lcd_omap3beagle.c
+++ b/drivers/video/omap/lcd_omap3beagle.c
@@ -66,7 +66,7 @@ struct lcd_panel omap3beagle_panel = {
.name = "omap3beagle",
.config = OMAP_LCDC_PANEL_TFT,
- .bpp = 24,
+ .bpp = 16,
.data_lines = 24,
.x_res = LCD_XRES,
.y_res = LCD_YRES,

1965
meta/packages/linux/linux-omap2-git/beagleboard/defconfig Normal file
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File diff suppressed because it is too large Load Diff

558
meta/packages/linux/linux-omap2-git/beagleboard/flash.patch Normal file
View File

@ -0,0 +1,558 @@
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 13d0043..d582b8f 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -44,7 +44,8 @@ obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o \
board-omap3evm-flash.o
obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o \
usb-musb.o usb-ehci.o \
- hsmmc.o
+ hsmmc.o \
+ board-omap3beagle-flash.o
obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \
hsmmc.o \
usb-musb.o
diff --git a/arch/arm/mach-omap2/board-omap3beagle-flash.c b/arch/arm/mach-omap2/board-omap3beagle-flash.c
new file mode 100644
index 0000000..5346df0
--- /dev/null
+++ b/arch/arm/mach-omap2/board-omap3beagle-flash.c
@@ -0,0 +1,119 @@
+/*
+ * board-omap3beagle-flash.c
+ *
+ * Copyright (c) 2008 Texas Instruments
+ *
+ * Modified from board-omap3evm-flash.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand.h>
+#include <linux/types.h>
+#include <linux/io.h>
+
+#include <asm/mach/flash.h>
+#include <asm/arch/board.h>
+#include <asm/arch/gpmc.h>
+#include <asm/arch/nand.h>
+
+#define GPMC_CS0_BASE 0x60
+#define GPMC_CS_SIZE 0x30
+
+static struct mtd_partition omap3beagle_nand_partitions[] = {
+ /* All the partition sizes are listed in terms of NAND block size */
+ {
+ .name = "X-Loader",
+ .offset = 0,
+ .size = 4*(64 * 2048),
+ .mask_flags = MTD_WRITEABLE, /* force read-only */
+ },
+ {
+ .name = "U-Boot",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
+ .size = 15*(64 * 2048),
+ .mask_flags = MTD_WRITEABLE, /* force read-only */
+ },
+ {
+ .name = "U-Boot Env",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
+ .size = 1*(64 * 2048),
+ },
+ {
+ .name = "Kernel",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
+ .size = 32*(64 * 2048),
+ },
+ {
+ .name = "File System",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+static struct omap_nand_platform_data omap3beagle_nand_data = {
+ .parts = omap3beagle_nand_partitions,
+ .nr_parts = ARRAY_SIZE(omap3beagle_nand_partitions),
+ .dma_channel = -1, /* disable DMA in OMAP NAND driver */
+ .nand_setup = NULL,
+ .dev_ready = NULL,
+};
+
+static struct resource omap3beagle_nand_resource = {
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device omap3beagle_nand_device = {
+ .name = "omap2-nand",
+ .id = -1,
+ .dev = {
+ .platform_data = &omap3beagle_nand_data,
+ },
+ .num_resources = 1,
+ .resource = &omap3beagle_nand_resource,
+};
+
+
+void __init omap3beagle_flash_init(void)
+{
+ u8 cs = 0;
+ u8 nandcs = GPMC_CS_NUM + 1;
+
+ u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
+
+ /* find out the chip-select on which NAND exists */
+ while (cs < GPMC_CS_NUM) {
+ u32 ret = 0;
+ ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+
+ if ((ret & 0xC00) == 0x800) {
+ printk(KERN_INFO "Found NAND on CS%d\n", cs);
+ if (nandcs > GPMC_CS_NUM)
+ nandcs = cs;
+ }
+ cs++;
+ }
+
+ if (nandcs > GPMC_CS_NUM) {
+ printk(KERN_INFO "NAND: Unable to find configuration "
+ "in GPMC\n ");
+ return;
+ }
+
+ if (nandcs < GPMC_CS_NUM) {
+ omap3beagle_nand_data.cs = nandcs;
+ omap3beagle_nand_data.gpmc_cs_baseaddr = (void *)(gpmc_base_add +
+ GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
+ omap3beagle_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add);
+
+ printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
+ if (platform_device_register(&omap3beagle_nand_device) < 0)
+ printk(KERN_ERR "Unable to register NAND device\n");
+ }
+}
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index c992cc7..99e042e 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -94,6 +94,7 @@ static void __init omap3_beagle_init(void)
hsmmc_init();
usb_musb_init();
usb_ehci_init();
+ omap3beagle_flash_init();
}
arch_initcall(omap3_beagle_i2c_init);
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 3d5e432..02b9ced 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -71,7 +71,7 @@ config MTD_NAND_AMS_DELTA
config MTD_NAND_OMAP2
tristate "NAND Flash device on OMAP 2420H4/2430SDP boards"
- depends on (ARM && ARCH_OMAP2 && MTD_NAND)
+ depends on ARM && MTD_NAND && (ARCH_OMAP2 || ARCH_OMAP3)
help
Support for NAND flash on Texas Instruments 2430SDP/2420H4 platforms.
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 3b7307c..3aac1d2 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -111,15 +111,6 @@
static const char *part_probes[] = { "cmdlinepart", NULL };
#endif
-static int hw_ecc = 1;
-
-/* new oob placement block for use with hardware ecc generation */
-static struct nand_ecclayout omap_hw_eccoob = {
- .eccbytes = 12,
- .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
- .oobfree = {{16, 32}, {33, 63} },
-};
-
struct omap_nand_info {
struct nand_hw_control controller;
struct omap_nand_platform_data *pdata;
@@ -133,6 +124,13 @@ struct omap_nand_info {
void __iomem *gpmc_cs_baseaddr;
void __iomem *gpmc_baseaddr;
};
+
+/*
+ * omap_nand_wp - This function enable or disable the Write Protect feature on
+ * NAND device
+ * @mtd: MTD device structure
+ * @mode: WP ON/OFF
+ */
static void omap_nand_wp(struct mtd_info *mtd, int mode)
{
struct omap_nand_info *info = container_of(mtd,
@@ -189,11 +187,11 @@ static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
}
/*
-* omap_read_buf - read data from NAND controller into buffer
-* @mtd: MTD device structure
-* @buf: buffer to store date
-* @len: number of bytes to read
-*/
+ * omap_read_buf - read data from NAND controller into buffer
+ * @mtd: MTD device structure
+ * @buf: buffer to store date
+ * @len: number of bytes to read
+ */
static void omap_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
struct omap_nand_info *info = container_of(mtd,
@@ -207,11 +205,11 @@ static void omap_read_buf(struct mtd_info *mtd, u_char *buf, int len)
}
/*
-* omap_write_buf - write buffer to NAND controller
-* @mtd: MTD device structure
-* @buf: data buffer
-* @len: number of bytes to write
-*/
+ * omap_write_buf - write buffer to NAND controller
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
+ */
static void omap_write_buf(struct mtd_info *mtd, const u_char * buf, int len)
{
struct omap_nand_info *info = container_of(mtd,
@@ -250,10 +248,16 @@ static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
return 0;
}
+#ifdef CONFIG_MTD_NAND_OMAP_HWECC
+/*
+ * omap_hwecc_init-Initialize the Hardware ECC for NAND flash in GPMC controller
+ * @mtd: MTD device structure
+ */
static void omap_hwecc_init(struct mtd_info *mtd)
{
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
mtd);
+ register struct nand_chip *chip = mtd->priv;
unsigned long val = 0x0;
/* Read from ECC Control Register */
@@ -264,16 +268,15 @@ static void omap_hwecc_init(struct mtd_info *mtd)
/* Read from ECC Size Config Register */
val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
- /* ECCSIZE1=512 | ECCSIZE0=8bytes | Select eccResultsize[0123] */
- val = ((0x000000FF<<22) | (0x00000003<<12) | (0x0000000F));
+ /* ECCSIZE1=512 | Select eccResultsize[0-3] */
+ val = ((((chip->ecc.size >> 1) - 1) << 22) | (0x0000000F));
__raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
-
-
}
/*
- * This function will generate true ECC value, which can be used
+ * gen_true_ecc - This function will generate true ECC value, which can be used
* when correcting data read from NAND flash memory core
+ * @ecc_buf: buffer to store ecc code
*/
static void gen_true_ecc(u8 *ecc_buf)
{
@@ -289,8 +292,12 @@ static void gen_true_ecc(u8 *ecc_buf)
}
/*
- * This function compares two ECC's and indicates if there is an error.
- * If the error can be corrected it will be corrected to the buffer
+ * omap_compare_ecc - This function compares two ECC's and indicates if there
+ * is an error. If the error can be corrected it will be corrected to the
+ * buffer
+ * @ecc_data1: ecc code from nand spare area
+ * @ecc_data2: ecc code from hardware register obtained from hardware ecc
+ * @page_data: page data
*/
static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
u8 *ecc_data2, /* read from register */
@@ -409,6 +416,14 @@ static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
}
}
+/*
+ * omap_correct_data - Compares the ecc read from nand spare area with ECC
+ * registers values and corrects one bit error if it has occured
+ * @mtd: MTD device structure
+ * @dat: page data
+ * @read_ecc: ecc read from nand flash
+ * @calc_ecc: ecc read from ECC registers
+ */
static int omap_correct_data(struct mtd_info *mtd, u_char * dat,
u_char * read_ecc, u_char * calc_ecc)
{
@@ -436,65 +451,64 @@ static int omap_correct_data(struct mtd_info *mtd, u_char * dat,
}
/*
-** Generate non-inverted ECC bytes.
-**
-** Using noninverted ECC can be considered ugly since writing a blank
-** page ie. padding will clear the ECC bytes. This is no problem as long
-** nobody is trying to write data on the seemingly unused page.
-**
-** Reading an erased page will produce an ECC mismatch between
-** generated and read ECC bytes that has to be dealt with separately.
-*/
+ * omap_calcuate_ecc - Generate non-inverted ECC bytes.
+ * Using noninverted ECC can be considered ugly since writing a blank
+ * page ie. padding will clear the ECC bytes. This is no problem as long
+ * nobody is trying to write data on the seemingly unused page. Reading
+ * an erased page will produce an ECC mismatch between generated and read
+ * ECC bytes that has to be dealt with separately.
+ * @mtd: MTD device structure
+ * @dat: The pointer to data on which ecc is computed
+ * @ecc_code: The ecc_code buffer
+ */
static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u_char *ecc_code)
{
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
mtd);
unsigned long val = 0x0;
- unsigned long reg, n;
-
- /* Ex NAND_ECC_HW12_2048 */
- if ((info->nand.ecc.mode == NAND_ECC_HW) &&
- (info->nand.ecc.size == 2048))
- n = 4;
- else
- n = 1;
+ unsigned long reg;
/* Start Reading from HW ECC1_Result = 0x200 */
reg = (unsigned long)(info->gpmc_baseaddr + GPMC_ECC1_RESULT);
- while (n--) {
- val = __raw_readl(reg);
- *ecc_code++ = val; /* P128e, ..., P1e */
- *ecc_code++ = val >> 16; /* P128o, ..., P1o */
- /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
- *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
- reg += 4;
- }
+ val = __raw_readl(reg);
+ *ecc_code++ = val; /* P128e, ..., P1e */
+ *ecc_code++ = val >> 16; /* P128o, ..., P1o */
+ /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
+ *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
+ reg += 4;
return 0;
-} /* omap_calculate_ecc */
+}
+/*
+ * omap_enable_hwecc - This function enables the hardware ecc functionality
+ * @mtd: MTD device structure
+ * @mode: Read/Write mode
+ */
static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
{
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
mtd);
+ register struct nand_chip *chip = mtd->priv;
+ unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
unsigned long val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONFIG);
switch (mode) {
case NAND_ECC_READ :
__raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
- /* ECC 16 bit col) | ( CS 0 ) | ECC Enable */
- val = (1 << 7) | (0x0) | (0x1) ;
+ /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
+ val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
break;
case NAND_ECC_READSYN :
- __raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
- /* ECC 16 bit col) | ( CS 0 ) | ECC Enable */
- val = (1 << 7) | (0x0) | (0x1) ;
+ __raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
+ /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
+ val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
break;
case NAND_ECC_WRITE :
__raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
- /* ECC 16 bit col) | ( CS 0 ) | ECC Enable */
- val = (1 << 7) | (0x0) | (0x1) ;
+ /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
+ val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
break;
default:
DEBUG(MTD_DEBUG_LEVEL0, "Error: Unrecognized Mode[%d]!\n",
@@ -504,7 +518,38 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
__raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONFIG);
}
+#endif
+/*
+ * omap_wait - Wait function is called during Program and erase
+ * operations and the way it is called from MTD layer, we should wait
+ * till the NAND chip is ready after the programming/erase operation
+ * has completed.
+ * @mtd: MTD device structure
+ * @chip: NAND Chip structure
+ */
+static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
+{
+ register struct nand_chip *this = mtd->priv;
+ struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
+ mtd);
+ int status = 0;
+
+ this->IO_ADDR_W = (void *) info->gpmc_cs_baseaddr +
+ GPMC_CS_NAND_COMMAND;
+ this->IO_ADDR_R = (void *) info->gpmc_cs_baseaddr + GPMC_CS_NAND_DATA;
+
+ while (!(status & 0x40)) {
+ __raw_writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W);
+ status = __raw_readb(this->IO_ADDR_R);
+ }
+ return status;
+}
+
+/*
+ * omap_dev_ready - calls the platform specific dev_ready function
+ * @mtd: MTD device structure
+ */
static int omap_dev_ready(struct mtd_info *mtd)
{
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
@@ -534,7 +579,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
struct omap_nand_info *info;
struct omap_nand_platform_data *pdata;
int err;
- unsigned long val;
+ unsigned long val;
pdata = pdev->dev.platform_data;
@@ -568,15 +613,20 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
}
/* Enable RD PIN Monitoring Reg */
- val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1);
- val |= WR_RD_PIN_MONITORING;
- gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val);
+ if (pdata->dev_ready) {
+ val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1);
+ val |= WR_RD_PIN_MONITORING;
+ gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val);
+ }
val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG7);
val &= ~(0xf << 8);
val |= (0xc & 0xf) << 8;
gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG7, val);
+ /* NAND write protect off */
+ omap_nand_wp(&info->mtd, NAND_WP_OFF);
+
if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
pdev->dev.driver->name)) {
err = -EBUSY;
@@ -597,29 +647,39 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
info->nand.write_buf = omap_write_buf;
info->nand.verify_buf = omap_verify_buf;
- info->nand.dev_ready = omap_dev_ready;
- info->nand.chip_delay = 0;
-
- /* Options */
- info->nand.options = NAND_BUSWIDTH_16;
- info->nand.options |= NAND_SKIP_BBTSCAN;
-
- if (hw_ecc) {
- /* init HW ECC */
- omap_hwecc_init(&info->mtd);
-
- info->nand.ecc.calculate = omap_calculate_ecc;
- info->nand.ecc.hwctl = omap_enable_hwecc;
- info->nand.ecc.correct = omap_correct_data;
- info->nand.ecc.mode = NAND_ECC_HW;
- info->nand.ecc.bytes = 12;
- info->nand.ecc.size = 2048;
- info->nand.ecc.layout = &omap_hw_eccoob;
-
+ /*
+ * If RDY/BSY line is connected to OMAP then use the omap ready funcrtion
+ * and the generic nand_wait function which reads the status register
+ * after monitoring the RDY/BSY line.Otherwise use a standard chip delay
+ * which is slightly more than tR (AC Timing) of the NAND device and read
+ * status register until you get a failure or success
+ */
+ if (pdata->dev_ready) {
+ info->nand.dev_ready = omap_dev_ready;
+ info->nand.chip_delay = 0;
} else {
- info->nand.ecc.mode = NAND_ECC_SOFT;
+ info->nand.waitfunc = omap_wait;
+ info->nand.chip_delay = 50;
}
+ info->nand.options |= NAND_SKIP_BBTSCAN;
+ if ((gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1) & 0x3000)
+ == 0x1000)
+ info->nand.options |= NAND_BUSWIDTH_16;
+
+#ifdef CONFIG_MTD_NAND_OMAP_HWECC
+ info->nand.ecc.bytes = 3;
+ info->nand.ecc.size = 512;
+ info->nand.ecc.calculate = omap_calculate_ecc;
+ info->nand.ecc.hwctl = omap_enable_hwecc;
+ info->nand.ecc.correct = omap_correct_data;
+ info->nand.ecc.mode = NAND_ECC_HW;
+
+ /* init HW ECC */
+ omap_hwecc_init(&info->mtd);
+#else
+ info->nand.ecc.mode = NAND_ECC_SOFT;
+#endif
/* DIP switches on some boards change between 8 and 16 bit
* bus widths for flash. Try the other width if the first try fails.
@@ -636,14 +696,12 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
if (err > 0)
add_mtd_partitions(&info->mtd, info->parts, err);
- else if (err < 0 && pdata->parts)
+ else if (err <= 0 && pdata->parts)
add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
else
#endif
add_mtd_device(&info->mtd);
- omap_nand_wp(&info->mtd, NAND_WP_OFF);
-
platform_set_drvdata(pdev, &info->mtd);
return 0;
diff --git a/include/asm-arm/arch-omap/board-omap3beagle.h b/include/asm-arm/arch-omap/board-omap3beagle.h
index 46dff31..26ecfb8 100644
--- a/include/asm-arm/arch-omap/board-omap3beagle.h
+++ b/include/asm-arm/arch-omap/board-omap3beagle.h
@@ -29,5 +29,7 @@
#ifndef __ASM_ARCH_OMAP3_BEAGLE_H
#define __ASM_ARCH_OMAP3_BEAGLE_H
+extern void omap3beagle_flash_init(void);
+
#endif /* __ASM_ARCH_OMAP3_BEAGLE_H */

73147
meta/packages/linux/linux-omap2-git/beagleboard/logo_linux_clut224.ppm Normal file
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File diff suppressed because it is too large Load Diff

15
meta/packages/linux/linux-omap2-git/beagleboard/no-empty-flash-warnings.patch Normal file
View File

@ -0,0 +1,15 @@
diff --git a/fs/jffs2/scan.c b/fs/jffs2/scan.c
index 1d437de..33b3feb 100644
--- a/fs/jffs2/scan.c
+++ b/fs/jffs2/scan.c
@@ -647,8 +647,8 @@ scan_more:
inbuf_ofs = ofs - buf_ofs;
while (inbuf_ofs < scan_end) {
if (unlikely(*(uint32_t *)(&buf[inbuf_ofs]) != 0xffffffff)) {
- printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n",
- empty_start, ofs);
+// printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n",
+// empty_start, ofs);
if ((err = jffs2_scan_dirty_space(c, jeb, ofs-empty_start)))
return err;
goto scan_more;

11
meta/packages/linux/linux-omap2-git/beagleboard/no-harry-potter.diff Normal file
View File

@ -0,0 +1,11 @@
--- /tmp/Makefile 2008-04-24 14:36:20.509598016 +0200
+++ git/arch/arm/Makefile 2008-04-24 14:36:31.949546584 +0200
@@ -47,7 +47,7 @@
# Note that GCC does not numerically define an architecture version
# macro, but instead defines a whole series of macros which makes
# testing for a specific architecture or later rather impossible.
-arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7a,-march=armv5t -Wa$(comma)-march=armv7a)
+arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
arch-$(CONFIG_CPU_32v6) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
# Only override the compiler option if ARMv6. The ARMv6K extensions are
# always available in ARMv7

114
meta/packages/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch Normal file
View File

@ -0,0 +1,114 @@
From linux-omap-owner@vger.kernel.org Tue Jun 24 09:24:30 2008
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Date: Tue, 24 Jun 2008 01:12:35 -0600 (MDT)
From: Paul Walmsley <paul@pwsan.com>
To: linux-omap@vger.kernel.org
Subject: [PATCH] OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4
Message-ID: <alpine.DEB.1.00.0806240111320.9741@utopia.booyaka.com>
User-Agent: Alpine 1.00 (DEB 882 2007-12-20)
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X-OriginalArrivalTime: 24 Jun 2008 07:13:04.0264 (UTC) FILETIME=[BE950880:01C8D5C9]
OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and
DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this
into the OMAP3 clock framework.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock34xx.h | 20 ++++++++++++++++----
1 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index b4dceea..9605744 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1029,8 +1029,15 @@ static struct clk corex2_fck = {
/* DPLL power domain clock controls */
-static const struct clksel div2_core_clksel[] = {
- { .parent = &core_ck, .rates = div2_rates },
+static const struct clksel_rate div4_rates[] = {
+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+ { .div = 2, .val = 2, .flags = RATE_IN_343X },
+ { .div = 4, .val = 4, .flags = RATE_IN_343X },
+ { .div = 0 }
+};
+
+static const struct clksel div4_core_clksel[] = {
+ { .parent = &core_ck, .rates = div4_rates },
{ .parent = NULL }
};
@@ -1044,7 +1051,7 @@ static struct clk dpll1_fck = {
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
.clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
- .clksel = div2_core_clksel,
+ .clksel = div4_core_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
.recalc = &omap2_clksel_recalc,
@@ -1119,7 +1126,7 @@ static struct clk dpll2_fck = {
.init = &omap2_init_clksel_parent,
.clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
.clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
- .clksel = div2_core_clksel,
+ .clksel = div4_core_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
.recalc = &omap2_clksel_recalc,
@@ -1155,6 +1162,11 @@ static struct clk iva2_ck = {
/* Common interface clocks */
+static const struct clksel div2_core_clksel[] = {
+ { .parent = &core_ck, .rates = div2_rates },
+ { .parent = NULL }
+};
+
static struct clk l3_ick = {
.name = "l3_ick",
.parent = &core_ck,
--
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95
meta/packages/linux/linux-omap2-git/beagleboard/omap3-jitter.patch Normal file
View File

@ -0,0 +1,95 @@
From linux-omap-owner@vger.kernel.org Tue Jun 24 09:24:30 2008
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Date: Tue, 24 Jun 2008 01:11:21 -0600 (MDT)
From: Paul Walmsley <paul@pwsan.com>
To: linux-omap@vger.kernel.org
Subject: [PATCH] OMAP3 clock: fix DPLL jitter correction and rate
programming
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X-OriginalArrivalTime: 24 Jun 2008 07:20:48.0265 (UTC) FILETIME=[D325F790:01C8D5CA]
Fix DPLL jitter correction programming. Previously,
omap3_noncore_dpll_program() stored the FREQSEL jitter correction
parameter to the wrong register. This caused jitter correction to be set
incorrectly and also caused the DPLL divider to be programmed incorrectly.
Also, fix DPLL divider programming. An off-by-one error existed in
omap3_noncore_dpll_program(), causing DPLLs to be programmed with a higher
divider than intended.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/clock34xx.c | 13 ++++++++-----
1 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 408b51a..8fdf8f3 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -346,14 +346,17 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
_omap3_noncore_dpll_bypass(clk);
+ /* Set jitter correction */
+ v = __raw_readl(dd->control_reg);
+ v &= ~dd->freqsel_mask;
+ v |= freqsel << __ffs(dd->freqsel_mask);
+ __raw_writel(v, dd->control_reg);
+
+ /* Set DPLL multiplier, divider */
v = __raw_readl(dd->mult_div1_reg);
v &= ~(dd->mult_mask | dd->div1_mask);
-
- /* Set mult (M), div1 (N), freqsel */
v |= m << __ffs(dd->mult_mask);
- v |= n << __ffs(dd->div1_mask);
- v |= freqsel << __ffs(dd->freqsel_mask);
-
+ v |= (n - 1) << __ffs(dd->div1_mask);
__raw_writel(v, dd->mult_div1_reg);
/* We let the clock framework set the other output dividers later */
--
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611
meta/packages/linux/linux-omap2-git/beagleboard/oprofile-0.9.3.armv7.diff Normal file
View File

@ -0,0 +1,611 @@
Hi,
This patch adds Oprofile support on ARMv7, using the PMNC unit.
Tested on OMAP3430 SDP.
Feedback and comments are welcome.
The patch to user space components is attached for reference. It i applies
against version 0.9.3 of oprofile source
(http://prdownloads.sourceforge.net/oprofile/oprofile-0.9.3.tar.gz).
Regards,
Jean.
---
From: Jean Pihet <jpihet@mvista.com>
Date: Tue, 6 May 2008 17:21:44 +0200
Subject: [PATCH] ARM: Add ARMv7 oprofile support
Add ARMv7 Oprofile support to kernel
Signed-off-by: Jean Pihet <jpihet@mvista.com>
---
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c60a27d..60b50a0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -161,6 +161,11 @@ config OPROFILE_MPCORE
config OPROFILE_ARM11_CORE
bool
+config OPROFILE_ARMV7
+ def_bool y
+ depends on CPU_V7 && !SMP
+ bool
+
endif
config VECTORS_BASE
diff --git a/arch/arm/oprofile/Makefile b/arch/arm/oprofile/Makefile
index e61d0cc..88e31f5 100644
--- a/arch/arm/oprofile/Makefile
+++ b/arch/arm/oprofile/Makefile
@@ -11,3 +11,4 @@ oprofile-$(CONFIG_CPU_XSCALE) += op_model_xscale.o
oprofile-$(CONFIG_OPROFILE_ARM11_CORE) += op_model_arm11_core.o
oprofile-$(CONFIG_OPROFILE_ARMV6) += op_model_v6.o
oprofile-$(CONFIG_OPROFILE_MPCORE) += op_model_mpcore.o
+oprofile-$(CONFIG_OPROFILE_ARMV7) += op_model_v7.o
diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c
index 0a5cf3a..3fcd752 100644
--- a/arch/arm/oprofile/common.c
+++ b/arch/arm/oprofile/common.c
@@ -145,6 +145,10 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
spec = &op_mpcore_spec;
#endif
+#ifdef CONFIG_OPROFILE_ARMV7
+ spec = &op_armv7_spec;
+#endif
+
if (spec) {
ret = spec->init();
if (ret < 0)
diff --git a/arch/arm/oprofile/op_arm_model.h
b/arch/arm/oprofile/op_arm_model.h
index 4899c62..8c4e4f6 100644
--- a/arch/arm/oprofile/op_arm_model.h
+++ b/arch/arm/oprofile/op_arm_model.h
@@ -26,6 +26,7 @@ extern struct op_arm_model_spec op_xscale_spec;
extern struct op_arm_model_spec op_armv6_spec;
extern struct op_arm_model_spec op_mpcore_spec;
+extern struct op_arm_model_spec op_armv7_spec;
extern void arm_backtrace(struct pt_regs * const regs, unsigned int depth);
diff --git a/arch/arm/oprofile/op_model_v7.c b/arch/arm/oprofile/op_model_v7.c
new file mode 100644
index 0000000..a159bc1
--- /dev/null
+++ b/arch/arm/oprofile/op_model_v7.c
@@ -0,0 +1,407 @@
+/**
+ * @file op_model_v7.c
+ * ARM V7 (Cortex A8) Event Monitor Driver
+ *
+ * @remark Copyright 2008 Jean Pihet <jpihet@mvista.com>
+ * @remark Copyright 2004 ARM SMP Development Team
+ */
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/oprofile.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/smp.h>
+
+#include "op_counter.h"
+#include "op_arm_model.h"
+#include "op_model_v7.h"
+
+/* #define DEBUG */
+
+
+/*
+ * ARM V7 PMNC support
+ */
+
+static u32 cnt_en[CNTMAX];
+
+static inline void armv7_pmnc_write(u32 val)
+{
+ val &= PMNC_MASK;
+ asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (val));
+}
+
+static inline u32 armv7_pmnc_read(void)
+{
+ u32 val;
+
+ asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
+ return val;
+}
+
+static inline u32 armv7_pmnc_enable_counter(unsigned int cnt)
+{
+ u32 val;
+
+ if (cnt >= CNTMAX) {
+ printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter"
+ " %d\n", smp_processor_id(), cnt);
+ return -1;
+ }
+
+ if (cnt == CCNT)
+ val = CNTENS_C;
+ else
+ val = (1 << (cnt - CNT0));
+
+ val &= CNTENS_MASK;
+ asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
+
+ return cnt;
+}
+
+static inline u32 armv7_pmnc_disable_counter(unsigned int cnt)
+{
+ u32 val;
+
+ if (cnt >= CNTMAX) {
+ printk(KERN_ERR "oprofile: CPU%u disabling wrong PMNC counter"
+ " %d\n", smp_processor_id(), cnt);
+ return -1;
+ }
+
+ if (cnt == CCNT)
+ val = CNTENC_C;
+ else
+ val = (1 << (cnt - CNT0));
+
+ val &= CNTENC_MASK;
+ asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
+
+ return cnt;
+}
+
+static inline u32 armv7_pmnc_enable_intens(unsigned int cnt)
+{
+ u32 val;
+
+ if (cnt >= CNTMAX) {
+ printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter"
+ " interrupt enable %d\n", smp_processor_id(), cnt);
+ return -1;
+ }
+
+ if (cnt == CCNT)
+ val = INTENS_C;
+ else
+ val = (1 << (cnt - CNT0));
+
+ val &= INTENS_MASK;
+ asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
+
+ return cnt;
+}
+
+static inline u32 armv7_pmnc_getreset_flags(void)
+{
+ u32 val;
+
+ /* Read */
+ asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
+
+ /* Write to clear flags */
+ val &= FLAG_MASK;
+ asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
+
+ return val;
+}
+
+static inline int armv7_pmnc_select_counter(unsigned int cnt)
+{
+ u32 val;
+
+ if ((cnt == CCNT) || (cnt >= CNTMAX)) {
+ printk(KERN_ERR "oprofile: CPU%u selecting wrong PMNC counteri"
+ " %d\n", smp_processor_id(), cnt);
+ return -1;
+ }
+
+ val = (cnt - CNT0) & SELECT_MASK;
+ asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
+
+ return cnt;
+}
+
+static inline void armv7_pmnc_write_evtsel(unsigned int cnt, u32 val)
+{
+ if (armv7_pmnc_select_counter(cnt) == cnt) {
+ val &= EVTSEL_MASK;
+ asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
+ }
+}
+
+static void armv7_pmnc_reset_counter(unsigned int cnt)
+{
+ u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt);
+ u32 val = -(u32)counter_config[cpu_cnt].count;
+
+ switch (cnt) {
+ case CCNT:
+ armv7_pmnc_disable_counter(cnt);
+
+ asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (val));
+
+ if (cnt_en[cnt] != 0)
+ armv7_pmnc_enable_counter(cnt);
+
+ break;
+
+ case CNT0:
+ case CNT1:
+ case CNT2:
+ case CNT3:
+ armv7_pmnc_disable_counter(cnt);
+
+ if (armv7_pmnc_select_counter(cnt) == cnt)
+ asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (val));
+
+ if (cnt_en[cnt] != 0)
+ armv7_pmnc_enable_counter(cnt);
+
+ break;
+
+ default:
+ printk(KERN_ERR "oprofile: CPU%u resetting wrong PMNC counter"
+ " %d\n", smp_processor_id(), cnt);
+ break;
+ }
+}
+
+int armv7_setup_pmnc(void)
+{
+ unsigned int cnt;
+
+ if (armv7_pmnc_read() & PMNC_E) {
+ printk(KERN_ERR "oprofile: CPU%u PMNC still enabled when setup"
+ " new event counter.\n", smp_processor_id());
+ return -EBUSY;
+ }
+
+ /*
+ * Initialize & Reset PMNC: C bit, D bit and P bit.
+ * Note: Using a slower count for CCNT (D bit: divide by 64) results
+ * in a more stable system
+ */
+ armv7_pmnc_write(PMNC_P | PMNC_C | PMNC_D);
+
+
+ for (cnt = CCNT; cnt < CNTMAX; cnt++) {
+ unsigned long event;
+ u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt);
+
+ /*
+ * Disable counter
+ */
+ armv7_pmnc_disable_counter(cnt);
+ cnt_en[cnt] = 0;
+
+ if (!counter_config[cpu_cnt].enabled)
+ continue;
+
+ event = counter_config[cpu_cnt].event & 255;
+
+ /*
+ * Set event (if destined for PMNx counters)
+ * We don't need to set the event if it's a cycle count
+ */
+ if (cnt != CCNT)
+ armv7_pmnc_write_evtsel(cnt, event);
+
+ /*
+ * Enable interrupt for this counter
+ */
+ armv7_pmnc_enable_intens(cnt);
+
+ /*
+ * Reset counter
+ */
+ armv7_pmnc_reset_counter(cnt);
+
+ /*
+ * Enable counter
+ */
+ armv7_pmnc_enable_counter(cnt);
+ cnt_en[cnt] = 1;
+ }
+
+ return 0;
+}
+
+static inline void armv7_start_pmnc(void)
+{
+ armv7_pmnc_write(armv7_pmnc_read() | PMNC_E);
+}
+
+static inline void armv7_stop_pmnc(void)
+{
+ armv7_pmnc_write(armv7_pmnc_read() & ~PMNC_E);
+}
+
+/*
+ * CPU counters' IRQ handler (one IRQ per CPU)
+ */
+static irqreturn_t armv7_pmnc_interrupt(int irq, void *arg)
+{
+ struct pt_regs *regs = get_irq_regs();
+ unsigned int cnt;
+ u32 flags;
+
+
+ /*
+ * Stop IRQ generation
+ */
+ armv7_stop_pmnc();
+
+ /*
+ * Get and reset overflow status flags
+ */
+ flags = armv7_pmnc_getreset_flags();
+
+ /*
+ * Cycle counter
+ */
+ if (flags & FLAG_C) {
+ u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), CCNT);
+ armv7_pmnc_reset_counter(CCNT);
+ oprofile_add_sample(regs, cpu_cnt);
+ }
+
+ /*
+ * PMNC counters 0:3
+ */
+ for (cnt = CNT0; cnt < CNTMAX; cnt++) {
+ if (flags & (1 << (cnt - CNT0))) {
+ u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt);
+ armv7_pmnc_reset_counter(cnt);
+ oprofile_add_sample(regs, cpu_cnt);
+ }
+ }
+
+ /*
+ * Allow IRQ generation
+ */
+ armv7_start_pmnc();
+
+ return IRQ_HANDLED;
+}
+
+int armv7_request_interrupts(int *irqs, int nr)
+{
+ unsigned int i;
+ int ret = 0;
+
+ for (i = 0; i < nr; i++) {
+ ret = request_irq(irqs[i], armv7_pmnc_interrupt,
+ IRQF_DISABLED, "CP15 PMNC", NULL);
+ if (ret != 0) {
+ printk(KERN_ERR "oprofile: unable to request IRQ%u"
+ " for ARMv7\n",
+ irqs[i]);
+ break;
+ }
+ }
+
+ if (i != nr)
+ while (i-- != 0)
+ free_irq(irqs[i], NULL);
+
+ return ret;
+}
+
+void armv7_release_interrupts(int *irqs, int nr)
+{
+ unsigned int i;
+
+ for (i = 0; i < nr; i++)
+ free_irq(irqs[i], NULL);
+}
+
+#ifdef DEBUG
+static void armv7_pmnc_dump_regs(void)
+{
+ u32 val;
+ unsigned int cnt;
+
+ printk(KERN_INFO "PMNC registers dump:\n");
+
+ asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
+ printk(KERN_INFO "PMNC =0x%08x\n", val);
+
+ asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
+ printk(KERN_INFO "CNTENS=0x%08x\n", val);
+
+ asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
+ printk(KERN_INFO "INTENS=0x%08x\n", val);
+
+ asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
+ printk(KERN_INFO "FLAGS =0x%08x\n", val);
+
+ asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
+ printk(KERN_INFO "SELECT=0x%08x\n", val);
+
+ asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
+ printk(KERN_INFO "CCNT =0x%08x\n", val);
+
+ for (cnt = CNT0; cnt < CNTMAX; cnt++) {
+ armv7_pmnc_select_counter(cnt);
+ asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
+ printk(KERN_INFO "CNT[%d] count =0x%08x\n", cnt-CNT0, val);
+ asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
+ printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n", cnt-CNT0, val);
+ }
+}
+#endif
+
+
+static int irqs[] = {
+#ifdef CONFIG_ARCH_OMAP3
+ INT_34XX_BENCH_MPU_EMUL,
+#endif
+};
+
+static void armv7_pmnc_stop(void)
+{
+#ifdef DEBUG
+ armv7_pmnc_dump_regs();
+#endif
+ armv7_stop_pmnc();
+ armv7_release_interrupts(irqs, ARRAY_SIZE(irqs));
+}
+
+static int armv7_pmnc_start(void)
+{
+ int ret;
+
+#ifdef DEBUG
+ armv7_pmnc_dump_regs();
+#endif
+ ret = armv7_request_interrupts(irqs, ARRAY_SIZE(irqs));
+ if (ret >= 0)
+ armv7_start_pmnc();
+
+ return ret;
+}
+
+static int armv7_detect_pmnc(void)
+{
+ return 0;
+}
+
+struct op_arm_model_spec op_armv7_spec = {
+ .init = armv7_detect_pmnc,
+ .num_counters = 5,
+ .setup_ctrs = armv7_setup_pmnc,
+ .start = armv7_pmnc_start,
+ .stop = armv7_pmnc_stop,
+ .name = "arm/armv7",
+};
diff --git a/arch/arm/oprofile/op_model_v7.h b/arch/arm/oprofile/op_model_v7.h
new file mode 100644
index 0000000..08f40ea
--- /dev/null
+++ b/arch/arm/oprofile/op_model_v7.h
@@ -0,0 +1,101 @@
+/**
+ * @file op_model_v7.h
+ * ARM v7 (Cortex A8) Event Monitor Driver
+ *
+ * @remark Copyright 2008 Jean Pihet <jpihet@mvista.com>
+ * @remark Copyright 2004 ARM SMP Development Team
+ * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com>
+ * @remark Copyright 2000-2004 MontaVista Software Inc
+ * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com>
+ * @remark Copyright 2004 Intel Corporation
+ * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk>
+ * @remark Copyright 2004 Oprofile Authors
+ *
+ * @remark Read the file COPYING
+ *
+ * @author Zwane Mwaikambo
+ */
+#ifndef OP_MODEL_V7_H
+#define OP_MODEL_V7_H
+
+/*
+ * Per-CPU PMNC: config reg
+ */
+#define PMNC_E (1 << 0) /* Enable all counters */
+#define PMNC_P (1 << 1) /* Reset all counters */
+#define PMNC_C (1 << 2) /* Cycle counter reset */
+#define PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */
+#define PMNC_X (1 << 4) /* Export to ETM */
+#define PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
+#define PMNC_MASK 0x3f /* Mask for writable bits */
+
+/*
+ * Available counters
+ */
+#define CCNT 0
+#define CNT0 1
+#define CNT1 2
+#define CNT2 3
+#define CNT3 4
+#define CNTMAX 5
+
+#define CPU_COUNTER(cpu, counter) ((cpu) * CNTMAX + (counter))
+
+/*
+ * CNTENS: counters enable reg
+ */
+#define CNTENS_P0 (1 << 0)
+#define CNTENS_P1 (1 << 1)
+#define CNTENS_P2 (1 << 2)
+#define CNTENS_P3 (1 << 3)
+#define CNTENS_C (1 << 31)
+#define CNTENS_MASK 0x8000000f /* Mask for writable bits */
+
+/*
+ * CNTENC: counters disable reg
+ */
+#define CNTENC_P0 (1 << 0)
+#define CNTENC_P1 (1 << 1)
+#define CNTENC_P2 (1 << 2)
+#define CNTENC_P3 (1 << 3)
+#define CNTENC_C (1 << 31)
+#define CNTENC_MASK 0x8000000f /* Mask for writable bits */
+
+/*
+ * INTENS: counters overflow interrupt enable reg
+ */
+#define INTENS_P0 (1 << 0)
+#define INTENS_P1 (1 << 1)
+#define INTENS_P2 (1 << 2)
+#define INTENS_P3 (1 << 3)
+#define INTENS_C (1 << 31)
+#define INTENS_MASK 0x8000000f /* Mask for writable bits */
+
+/*
+ * EVTSEL: Event selection reg
+ */
+#define EVTSEL_MASK 0x7f /* Mask for writable bits */
+
+/*
+ * SELECT: Counter selection reg
+ */
+#define SELECT_MASK 0x1f /* Mask for writable bits */
+
+/*
+ * FLAG: counters overflow flag status reg
+ */
+#define FLAG_P0 (1 << 0)
+#define FLAG_P1 (1 << 1)
+#define FLAG_P2 (1 << 2)
+#define FLAG_P3 (1 << 3)
+#define FLAG_C (1 << 31)
+#define FLAG_MASK 0x8000000f /* Mask for writable bits */
+
+
+int armv7_setup_pmu(void);
+int armv7_start_pmu(void);
+int armv7_stop_pmu(void);
+int armv7_request_interrupts(int *, int);
+void armv7_release_interrupts(int *, int);
+
+#endif
diff --git a/include/asm-arm/arch-omap/irqs.h
b/include/asm-arm/arch-omap/irqs.h
index c80e160..89ca90e 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -297,6 +297,7 @@
#define INT_243X_HS_USB_DMA 93
#define INT_243X_CARKIT_IRQ 94
+#define INT_34XX_BENCH_MPU_EMUL 3
#define INT_34XX_ST_MCBSP2_IRQ 4
#define INT_34XX_ST_MCBSP3_IRQ 5
#define INT_34XX_SYS_NIRQ 7

1173
meta/packages/linux/linux-omap2-git/beagleboard/soc.patch Normal file
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File diff suppressed because it is too large Load Diff

43
meta/packages/linux/linux-omap2-git/beagleboard/timer-suppression.patch Normal file
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@ -0,0 +1,43 @@
diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c
index b854a89..26f5569 100644
--- a/kernel/time/tick-sched.c
+++ b/kernel/time/tick-sched.c
@@ -253,6 +253,16 @@ void tick_nohz_stop_sched_tick(void)
/* Schedule the tick, if we are at least one jiffie off */
if ((long)delta_jiffies >= 1) {
+ /*
+ * calculate the expiry time for the next timer wheel
+ * timer
+ */
+ expires = ktime_add_ns(last_update, tick_period.tv64 *
+ delta_jiffies);
+
+ /* Skip reprogram of event if its not changed */
+ if(ts->tick_stopped && ktime_equal(expires, dev->next_event))
+ goto out2;
if (delta_jiffies > 1)
cpu_set(cpu, nohz_cpu_mask);
@@ -304,12 +314,7 @@ void tick_nohz_stop_sched_tick(void)
goto out;
}
- /*
- * calculate the expiry time for the next timer wheel
- * timer
- */
- expires = ktime_add_ns(last_update, tick_period.tv64 *
- delta_jiffies);
+ /* Mark expiries */
ts->idle_expires = expires;
if (ts->nohz_mode == NOHZ_MODE_HIGHRES) {
@@ -328,6 +333,7 @@ void tick_nohz_stop_sched_tick(void)
tick_do_update_jiffies64(ktime_get());
cpu_clear(cpu, nohz_cpu_mask);
}
+out2:
raise_softirq_irqoff(TIMER_SOFTIRQ);
out:
ts->next_jiffies = next_jiffies;

11
meta/packages/linux/linux-omap2-git/omap-2430-lcd.patch Normal file
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@ -0,0 +1,11 @@
--- git/drivers/video/omap/lcd_2430sdp.c.orig 2007-08-13 14:35:17.000000000 -0700
+++ git/drivers/video/omap/lcd_2430sdp.c 2007-08-13 14:35:55.000000000 -0700
@@ -32,7 +32,7 @@
#define LCD_PANEL_BACKLIGHT_GPIO 91
#define LCD_PANEL_ENABLE_GPIO 154
#define LCD_PIXCLOCK_MAX 5400 /* freq 5.4 MHz */
-#define PM_RECEIVER TWL4030_MODULE_PM_RECIEVER
+#define PM_RECEIVER TWL4030_MODULE_PM_RECEIVER
#define ENABLE_VAUX2_DEDICATED 0x09
#define ENABLE_VAUX2_DEV_GRP 0x20

1303
meta/packages/linux/linux-omap2-git/omap-2430sdp/defconfig Normal file
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1303
meta/packages/linux/linux-omap2-git/omap-2430sdp/defconfig.eabi Normal file
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1119
meta/packages/linux/linux-omap2-git/omap2420h4/defconfig Normal file
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File diff suppressed because it is too large Load Diff

1303
meta/packages/linux/linux-omap2-git/omap2430sdp/defconfig Normal file
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1303
meta/packages/linux/linux-omap2-git/omap2430sdp/defconfig.eabi Normal file
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File diff suppressed because it is too large Load Diff

1002
meta/packages/linux/linux-omap2-git/omap3evm/0001-ARM-OMAP-SmartReflex-driver.patch Normal file
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File diff suppressed because it is too large Load Diff

55
meta/packages/linux/linux-omap2-git/omap3evm/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch Normal file
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@ -0,0 +1,55 @@
From a1dbb6dd28e9815a307b87b8d96dcf371d6cfd58 Mon Sep 17 00:00:00 2001
From: Jarkko Nikula <jarkko.nikula@nokia.com>
Date: Mon, 19 May 2008 13:24:41 +0300
Subject: [PATCH] ASoC: OMAP: Add basic support for OMAP34xx in McBSP DAI driver
This adds support for OMAP34xx McBSP port 1 and 2.
Signed-off-by: Jarkko Nikula <jarkko.nikula@nokia.com>
---
sound/soc/omap/omap-mcbsp.c | 20 +++++++++++++++++++-
1 files changed, 19 insertions(+), 1 deletions(-)
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index 40d87e6..8e6ec9d 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -99,6 +99,21 @@ static const unsigned long omap2420_mcbsp_port[][2] = {
static const int omap2420_dma_reqs[][2] = {};
static const unsigned long omap2420_mcbsp_port[][2] = {};
#endif
+#if defined(CONFIG_ARCH_OMAP34XX)
+static const int omap34xx_dma_reqs[][2] = {
+ { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
+ { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
+};
+static const unsigned long omap34xx_mcbsp_port[][2] = {
+ { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR2,
+ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR2 },
+ { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR2,
+ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR2 },
+};
+#else
+static const int omap34xx_dma_reqs[][2] = {};
+static const unsigned long omap34xx_mcbsp_port[][2] = {};
+#endif
static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream)
{
@@ -169,9 +184,12 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
} else if (cpu_is_omap2420()) {
dma = omap2420_dma_reqs[bus_id][substream->stream];
port = omap2420_mcbsp_port[bus_id][substream->stream];
+ } else if (cpu_is_omap343x()) {
+ dma = omap34xx_dma_reqs[bus_id][substream->stream];
+ port = omap34xx_mcbsp_port[bus_id][substream->stream];
} else {
/*
- * TODO: Add support for 2430 and 3430
+ * TODO: Add support for 2430
*/
return -ENODEV;
}
--
1.5.5.1

450
meta/packages/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch Normal file
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@ -0,0 +1,450 @@
From: "Rajendra Nayak" <rnayak@ti.com>
To: <linux-omap@vger.kernel.org>
Subject: [PATCH 01/02] OMAP3 CPUidle driver
Date: Tue, 10 Jun 2008 12:39:00 +0530
This patch adds the OMAP3 cpuidle driver. Irq enable/disable is done in the core cpuidle driver
before it queries the governor for the next state.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/mach-omap2/Makefile | 2
arch/arm/mach-omap2/cpuidle34xx.c | 293 ++++++++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/cpuidle34xx.h | 51 ++++++
arch/arm/mach-omap2/pm34xx.c | 5
drivers/cpuidle/cpuidle.c | 10 +
5 files changed, 359 insertions(+), 2 deletions(-)
Index: linux-omap-2.6/arch/arm/mach-omap2/Makefile
===================================================================
--- linux-omap-2.6.orig/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:33.855303920 +0530
+++ linux-omap-2.6/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:39.569121361 +0530
@@ -20,7 +20,7 @@ obj-y += pm.o
obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
obj-$(CONFIG_ARCH_OMAP2420) += sleep242x.o
obj-$(CONFIG_ARCH_OMAP2430) += sleep243x.o
-obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
+obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
endif
Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c 2008-06-10 11:41:27.644820323 +0530
@@ -0,0 +1,293 @@
+/*
+ * linux/arch/arm/mach-omap2/cpuidle34xx.c
+ *
+ * OMAP3 CPU IDLE Routines
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Karthik Dasu <karthik-dp@ti.com>
+ *
+ * Copyright (C) 2006 Nokia Corporation
+ * Tony Lindgren <tony@atomide.com>
+ *
+ * Copyright (C) 2005 Texas Instruments, Inc.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/cpuidle.h>
+#include <asm/arch/pm.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/powerdomain.h>
+#include <asm/arch/clockdomain.h>
+#include <asm/arch/irqs.h>
+#include "cpuidle34xx.h"
+
+#ifdef CONFIG_CPU_IDLE
+
+struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
+struct omap3_processor_cx current_cx_state;
+
+static int omap3_idle_bm_check(void)
+{
+ /* Check for omap3_fclks_active() here once available */
+ return 0;
+}
+
+/* omap3_enter_idle - Programs OMAP3 to enter the specified state.
+ * returns the total time during which the system was idle.
+ */
+static int omap3_enter_idle(struct cpuidle_device *dev,
+ struct cpuidle_state *state)
+{
+ struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
+ struct timespec ts_preidle, ts_postidle, ts_idle;
+ struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd;
+ int neon_pwrst;
+
+ current_cx_state = *cx;
+
+ if (cx->type == OMAP3_STATE_C0) {
+ /* Do nothing for C0, not even a wfi */
+ return 0;
+ }
+
+ /* Used to keep track of the total time in idle */
+ getnstimeofday(&ts_preidle);
+
+ mpu_pd = pwrdm_lookup("mpu_pwrdm");
+ core_pd = pwrdm_lookup("core_pwrdm");
+ per_pd = pwrdm_lookup("per_pwrdm");
+ neon_pd = pwrdm_lookup("neon_pwrdm");
+
+ /* Reset previous power state registers */
+ pwrdm_clear_all_prev_pwrst(mpu_pd);
+ pwrdm_clear_all_prev_pwrst(neon_pd);
+ pwrdm_clear_all_prev_pwrst(core_pd);
+ pwrdm_clear_all_prev_pwrst(per_pd);
+
+ if (omap_irq_pending())
+ return 0;
+
+ neon_pwrst = pwrdm_read_pwrst(neon_pd);
+
+ /* Program MPU/NEON to target state */
+ if (cx->mpu_state < PWRDM_POWER_ON) {
+ if (neon_pwrst == PWRDM_POWER_ON) {
+ if (cx->mpu_state == PWRDM_POWER_RET)
+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);
+ else if (cx->mpu_state == PWRDM_POWER_OFF)
+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF);
+ }
+ pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
+ }
+
+ /* Program CORE to target state */
+ if (cx->core_state < PWRDM_POWER_ON)
+ pwrdm_set_next_pwrst(core_pd, cx->core_state);
+
+ /* Execute ARM wfi */
+ omap_sram_idle();
+
+ /* Program MPU/NEON to ON */
+ if (cx->mpu_state < PWRDM_POWER_ON) {
+ if (neon_pwrst == PWRDM_POWER_ON)
+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON);
+ pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON);
+ }
+
+ if (cx->core_state < PWRDM_POWER_ON)
+ pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON);
+
+ getnstimeofday(&ts_postidle);
+ ts_idle = timespec_sub(ts_postidle, ts_preidle);
+ return timespec_to_ns(&ts_idle);
+}
+
+/*
+ * omap3_enter_idle_bm - enter function for states with CPUIDLE_FLAG_CHECK_BM
+ *
+ * This function checks for all the pre-requisites needed for OMAP3 to enter
+ * CORE RET/OFF state. It then calls omap3_enter_idle to program the desired
+ * C state.
+ */
+static int omap3_enter_idle_bm(struct cpuidle_device *dev,
+ struct cpuidle_state *state)
+{
+ struct cpuidle_state *new_state = NULL;
+ int i, j;
+
+ if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
+
+ /* Find current state in list */
+ for (i = 0; i < OMAP3_MAX_STATES; i++)
+ if (state == &dev->states[i])
+ break;
+ BUG_ON(i == OMAP3_MAX_STATES);
+
+ /* Back up to non 'CHECK_BM' state */
+ for (j = i - 1; j > 0; j--) {
+ struct cpuidle_state *s = &dev->states[j];
+
+ if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) {
+ new_state = s;
+ break;
+ }
+ }
+
+ pr_debug("%s: Bus activity: Entering %s (instead of %s)\n",
+ __FUNCTION__, new_state->name, state->name);
+ }
+
+ return omap3_enter_idle(dev, new_state ? : state);
+}
+
+DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
+
+/* omap3_init_power_states - Initialises the OMAP3 specific C states.
+ * Below is the desciption of each C state.
+ *
+ C0 . System executing code
+ C1 . MPU WFI + Core active
+ C2 . MPU CSWR + Core active
+ C3 . MPU OFF + Core active
+ C4 . MPU CSWR + Core CSWR
+ C5 . MPU OFF + Core CSWR
+ C6 . MPU OFF + Core OFF
+ */
+void omap_init_power_states(void)
+{
+ /* C0 . System executing code */
+ omap3_power_states[0].valid = 1;
+ omap3_power_states[0].type = OMAP3_STATE_C0;
+ omap3_power_states[0].sleep_latency = 0;
+ omap3_power_states[0].wakeup_latency = 0;
+ omap3_power_states[0].threshold = 0;
+ omap3_power_states[0].mpu_state = PWRDM_POWER_ON;
+ omap3_power_states[0].core_state = PWRDM_POWER_ON;
+ omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_SHALLOW;
+
+ /* C1 . MPU WFI + Core active */
+ omap3_power_states[1].valid = 1;
+ omap3_power_states[1].type = OMAP3_STATE_C1;
+ omap3_power_states[1].sleep_latency = 10;
+ omap3_power_states[1].wakeup_latency = 10;
+ omap3_power_states[1].threshold = 30;
+ omap3_power_states[1].mpu_state = PWRDM_POWER_ON;
+ omap3_power_states[1].core_state = PWRDM_POWER_ON;
+ omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_SHALLOW;
+
+ /* C2 . MPU CSWR + Core active */
+ omap3_power_states[2].valid = 1;
+ omap3_power_states[2].type = OMAP3_STATE_C2;
+ omap3_power_states[2].sleep_latency = 50;
+ omap3_power_states[2].wakeup_latency = 50;
+ omap3_power_states[2].threshold = 300;
+ omap3_power_states[2].mpu_state = PWRDM_POWER_RET;
+ omap3_power_states[2].core_state = PWRDM_POWER_ON;
+ omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_BALANCED;
+
+ /* C3 . MPU OFF + Core active */
+ omap3_power_states[3].valid = 0;
+ omap3_power_states[3].type = OMAP3_STATE_C3;
+ omap3_power_states[3].sleep_latency = 1500;
+ omap3_power_states[3].wakeup_latency = 1800;
+ omap3_power_states[3].threshold = 4000;
+ omap3_power_states[3].mpu_state = PWRDM_POWER_OFF;
+ omap3_power_states[3].core_state = PWRDM_POWER_RET;
+ omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_BALANCED;
+
+ /* C4 . MPU CSWR + Core CSWR*/
+ omap3_power_states[4].valid = 1;
+ omap3_power_states[4].type = OMAP3_STATE_C4;
+ omap3_power_states[4].sleep_latency = 2500;
+ omap3_power_states[4].wakeup_latency = 7500;
+ omap3_power_states[4].threshold = 12000;
+ omap3_power_states[4].mpu_state = PWRDM_POWER_RET;
+ omap3_power_states[4].core_state = PWRDM_POWER_RET;
+ omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
+
+ /* C5 . MPU OFF + Core CSWR */
+ omap3_power_states[5].valid = 0;
+ omap3_power_states[5].type = OMAP3_STATE_C5;
+ omap3_power_states[5].sleep_latency = 3000;
+ omap3_power_states[5].wakeup_latency = 8500;
+ omap3_power_states[5].threshold = 15000;
+ omap3_power_states[5].mpu_state = PWRDM_POWER_OFF;
+ omap3_power_states[5].core_state = PWRDM_POWER_RET;
+ omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
+
+ /* C6 . MPU OFF + Core OFF */
+ omap3_power_states[6].valid = 0;
+ omap3_power_states[6].type = OMAP3_STATE_C6;
+ omap3_power_states[6].sleep_latency = 10000;
+ omap3_power_states[6].wakeup_latency = 30000;
+ omap3_power_states[6].threshold = 300000;
+ omap3_power_states[6].mpu_state = PWRDM_POWER_OFF;
+ omap3_power_states[6].core_state = PWRDM_POWER_OFF;
+ omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID |
+ CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM;
+}
+
+struct cpuidle_driver omap3_idle_driver = {
+ .name = "omap3_idle",
+ .owner = THIS_MODULE,
+};
+/*
+ * omap3_idle_init - Init routine for OMAP3 idle.
+ * Registers the OMAP3 specific cpuidle driver with the cpuidle f/w
+ * with the valid set of states.
+ */
+int omap3_idle_init(void)
+{
+ int i, count = 0;
+ struct omap3_processor_cx *cx;
+ struct cpuidle_state *state;
+ struct cpuidle_device *dev;
+
+ omap_init_power_states();
+ cpuidle_register_driver(&omap3_idle_driver);
+
+ dev = &per_cpu(omap3_idle_dev, smp_processor_id());
+
+ for (i = 0; i < OMAP3_MAX_STATES; i++) {
+ cx = &omap3_power_states[i];
+ state = &dev->states[count];
+
+ if (!cx->valid)
+ continue;
+ cpuidle_set_statedata(state, cx);
+ state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
+ state->target_residency = cx->threshold;
+ state->flags = cx->flags;
+ state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
+ omap3_enter_idle_bm : omap3_enter_idle;
+ sprintf(state->name, "C%d", count+1);
+ count++;
+ }
+
+ if (!count)
+ return -EINVAL;
+ dev->state_count = count;
+
+ if (cpuidle_register_device(dev)) {
+ printk(KERN_ERR "%s: CPUidle register device failed\n",
+ __FUNCTION__);
+ return -EIO;
+ }
+
+ return 0;
+}
+__initcall(omap3_idle_init);
+#endif /* CONFIG_CPU_IDLE */
Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h 2008-06-09 20:15:39.569121361 +0530
@@ -0,0 +1,51 @@
+/*
+ * linux/arch/arm/mach-omap2/cpuidle34xx.h
+ *
+ * OMAP3 cpuidle structure definitions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Written by Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * History:
+ *
+ */
+
+#ifndef ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX
+#define ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX
+
+#define OMAP3_MAX_STATES 7
+#define OMAP3_STATE_C0 0 /* C0 - System executing code */
+#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */
+#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */
+#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */
+#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */
+#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */
+#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */
+
+extern void omap_sram_idle(void);
+extern int omap3_irq_pending(void);
+
+struct omap3_processor_cx {
+ u8 valid;
+ u8 type;
+ u32 sleep_latency;
+ u32 wakeup_latency;
+ u32 mpu_state;
+ u32 core_state;
+ u32 threshold;
+ u32 flags;
+};
+
+void omap_init_power_states(void);
+int omap3_idle_init(void);
+
+#endif /* ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX */
+
Index: linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c
===================================================================
--- linux-omap-2.6.orig/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:15:33.855303920 +0530
+++ linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:16:20.976798343 +0530
@@ -141,7 +141,7 @@ static irqreturn_t prcm_interrupt_handle
return IRQ_HANDLED;
}
-static void omap_sram_idle(void)
+void omap_sram_idle(void)
{
/* Variable to tell what needs to be saved and restored
* in omap_sram_idle*/
@@ -156,6 +156,7 @@ static void omap_sram_idle(void)
mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
switch (mpu_next_state) {
+ case PWRDM_POWER_ON:
case PWRDM_POWER_RET:
/* No need to save context */
save_state = 0;
@@ -386,7 +387,9 @@ int __init omap3_pm_init(void)
prcm_setup_regs();
+#ifndef CONFIG_CPU_IDLE
pm_idle = omap3_pm_idle;
+#endif
err1:
return ret;
Index: linux-omap-2.6/drivers/cpuidle/cpuidle.c
===================================================================
--- linux-omap-2.6.orig/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:33.856303888 +0530
+++ linux-omap-2.6/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:39.570121329 +0530
@@ -58,6 +58,11 @@ static void cpuidle_idle_call(void)
return;
}
+#ifdef CONFIG_ARCH_OMAP3
+ local_irq_disable();
+ local_fiq_disable();
+#endif
+
/* ask the governor for the next state */
next_state = cpuidle_curr_governor->select(dev);
if (need_resched())
@@ -70,6 +75,11 @@ static void cpuidle_idle_call(void)
target_state->time += (unsigned long long)dev->last_residency;
target_state->usage++;
+#ifdef CONFIG_ARCH_OMAP3
+ local_irq_enable();
+ local_fiq_enable();
+#endif
+
/* give the governor an opportunity to reflect on the outcome */
if (cpuidle_curr_governor->reflect)
cpuidle_curr_governor->reflect(dev);
--
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69
meta/packages/linux/linux-omap2-git/omap3evm/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch Normal file
View File

@ -0,0 +1,69 @@
From 7a444ee080c5f1a62ac5042f1e7926622b3e1ce7 Mon Sep 17 00:00:00 2001
From: Koen Kooi <koen@openembedded.org>
Date: Fri, 30 May 2008 13:43:36 +0200
Subject: [PATCH] ARM: OMAP: omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver
omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver
* on revision A5 and earlier board the two leds can't be controlled seperately, should be fixed in rev. B and C boards.
Signed-off-by: Koen Kooi <koen@openembedded.org>
---
arch/arm/mach-omap2/board-omap3beagle.c | 28 ++++++++++++++++++++++++++++
1 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index c992cc7..83891fc 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -19,6 +19,7 @@
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/leds.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
@@ -72,6 +73,32 @@ static struct omap_lcd_config omap3_beagle_lcd_config __initdata = {
.ctrl_name = "internal",
};
+struct gpio_led gpio_leds[] = {
+ {
+ .name = "beagleboard::led0",
+ .default_trigger = "none",
+ .gpio = 149,
+ },
+ {
+ .name = "beagleboard::led1",
+ .default_trigger = "none",
+ .gpio = 150,
+ },
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+ .leds = gpio_leds,
+ .num_leds = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &gpio_led_info,
+ },
+};
+
static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
{ OMAP_TAG_UART, &omap3_beagle_uart_config },
{ OMAP_TAG_MMC, &omap3beagle_mmc_config },
@@ -83,6 +110,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = {
#ifdef CONFIG_RTC_DRV_TWL4030
&omap3_beagle_twl4030rtc_device,
#endif
+ &leds_gpio,
};
static void __init omap3_beagle_init(void)
--
1.5.4.3

278
meta/packages/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch Normal file
View File

@ -0,0 +1,278 @@
From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
To: linux-omap@vger.kernel.org
Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
Subject: [PATCH 2/3] ARM: OMAP: SmartReflex driver: added required register and bit definitions.
Date: Fri, 6 Jun 2008 12:49:48 +0300
Added new register and bit definitions to enable Smartreflex driver integration.
Also PRM_VC_SMPS_SA bit definitions' naming was changed to match the naming of
other similar bit definitions.
Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
---
arch/arm/mach-omap2/prm-regbits-34xx.h | 27 ++++++--
arch/arm/mach-omap2/smartreflex.h | 124 ++++++++++++++++++++++++++++++-
include/asm-arm/arch-omap/control.h | 19 +++++
include/asm-arm/arch-omap/omap34xx.h | 2 +
4 files changed, 163 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index c6a7940..f82b5a7 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -435,10 +435,10 @@
/* PM_PWSTST_EMU specific bits */
/* PRM_VC_SMPS_SA */
-#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16
-#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16)
-#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0
-#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0)
+#define OMAP3430_SMPS_SA1_SHIFT 16
+#define OMAP3430_SMPS_SA1_MASK (0x7f << 16)
+#define OMAP3430_SMPS_SA0_SHIFT 0
+#define OMAP3430_SMPS_SA0_MASK (0x7f << 0)
/* PRM_VC_SMPS_VOL_RA */
#define OMAP3430_VOLRA1_SHIFT 16
@@ -452,7 +452,7 @@
#define OMAP3430_CMDRA0_SHIFT 0
#define OMAP3430_CMDRA0_MASK (0xff << 0)
-/* PRM_VC_CMD_VAL_0 specific bits */
+/* PRM_VC_CMD_VAL */
#define OMAP3430_VC_CMD_ON_SHIFT 24
#define OMAP3430_VC_CMD_ON_MASK (0xFF << 24)
#define OMAP3430_VC_CMD_ONLP_SHIFT 16
@@ -462,7 +462,17 @@
#define OMAP3430_VC_CMD_OFF_SHIFT 0
#define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0)
+/* PRM_VC_CMD_VAL_0 specific bits */
+#define OMAP3430_VC_CMD_VAL0_ON (0x3 << 4)
+#define OMAP3430_VC_CMD_VAL0_ONLP (0x3 << 3)
+#define OMAP3430_VC_CMD_VAL0_RET (0x3 << 3)
+#define OMAP3430_VC_CMD_VAL0_OFF (0x3 << 3)
+
/* PRM_VC_CMD_VAL_1 specific bits */
+#define OMAP3430_VC_CMD_VAL1_ON (0xB << 2)
+#define OMAP3430_VC_CMD_VAL1_ONLP (0x3 << 3)
+#define OMAP3430_VC_CMD_VAL1_RET (0x3 << 3)
+#define OMAP3430_VC_CMD_VAL1_OFF (0x3 << 3)
/* PRM_VC_CH_CONF */
#define OMAP3430_CMD1 (1 << 20)
@@ -521,6 +531,13 @@
#define OMAP3430_AUTO_RET (1 << 1)
#define OMAP3430_AUTO_SLEEP (1 << 0)
+/* Constants to define setup durations */
+#define OMAP3430_CLKSETUP_DURATION 0xff
+#define OMAP3430_VOLTSETUP_TIME2 0xfff
+#define OMAP3430_VOLTSETUP_TIME1 0xfff
+#define OMAP3430_VOLTOFFSET_DURATION 0xff
+#define OMAP3430_VOLTSETUP2_DURATION 0xff
+
/* PRM_SRAM_PCHARGE */
#define OMAP3430_PCHARGE_TIME_SHIFT 0
#define OMAP3430_PCHARGE_TIME_MASK (0xff << 0)
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index 62907ef..2091a15 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -1,5 +1,10 @@
+#ifndef __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
+#define __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
/*
- * linux/arch/arm/mach-omap3/smartreflex.h
+ * linux/arch/arm/mach-omap2/smartreflex.h
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
*
* Copyright (C) 2007 Texas Instruments, Inc.
* Lesly A M <x0080970@ti.com>
@@ -9,6 +14,21 @@
* published by the Free Software Foundation.
*/
+#define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
+#define PHY_TO_OFF_PM_RECIEVER(p) (p - 0x5b)
+#define PHY_TO_OFF_PM_INT(p) (p - 0x2e)
+
+/* SMART REFLEX REG ADDRESS OFFSET */
+#define SRCONFIG 0x00
+#define SRSTATUS 0x04
+#define SENVAL 0x08
+#define SENMIN 0x0C
+#define SENMAX 0x10
+#define SENAVG 0x14
+#define AVGWEIGHT 0x18
+#define NVALUERECIPROCAL 0x1C
+#define SENERROR 0x20
+#define ERRCONFIG 0x24
/* SR Modules */
#define SR1 1
@@ -127,10 +147,106 @@
#define SR2_ERRMAXLIMIT (0x02 << 8)
#define SR2_ERRMINLIMIT (0xF9 << 0)
+/* T2 SMART REFLEX */
+#define R_SRI2C_SLAVE_ADDR 0x12
+#define R_VDD1_SR_CONTROL 0x00
+#define R_VDD2_SR_CONTROL 0x01
+#define T2_SMPS_UPDATE_DELAY 360 /* In uSec */
+
+/* Vmode control */
+#define R_DCDC_GLOBAL_CFG PHY_TO_OFF_PM_RECIEVER(0x61)
+
+#define R_VDD1_VSEL PHY_TO_OFF_PM_RECIEVER(0xb9)
+#define R_VDD1_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xba)
+#define R_VDD1_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xbb)
+#define R_VDD1_VROOF PHY_TO_OFF_PM_RECIEVER(0xbc)
+#define R_VDD1_STEP PHY_TO_OFF_PM_RECIEVER(0xbd)
+
+#define R_VDD2_VSEL PHY_TO_OFF_PM_RECIEVER(0xc7)
+#define R_VDD2_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xc8)
+#define R_VDD2_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xc9)
+#define R_VDD2_VROOF PHY_TO_OFF_PM_RECIEVER(0xca)
+#define R_VDD2_STEP PHY_TO_OFF_PM_RECIEVER(0xcb)
+
+/* R_DCDC_GLOBAL_CFG register, SMARTREFLEX_ENABLE valuws */
+#define DCDC_GLOBAL_CFG_ENABLE_SRFLX 0x08
+
+/* VDDs*/
+#define PRCM_VDD1 1
+#define PRCM_VDD2 2
+#define PRCM_MAX_SYSC_REGS 30
+
+/* XXX: These should be removed/moved from here once we have a working DVFS
+ implementation in place */
+#define AT_3430 1 /*3430 ES 1.0 */
+#define AT_3430_ES2 2 /*3430 ES 2.0 */
+
+#define ID_OPP 0xE2 /*OPP*/
+
+/* DEVICE ID/DPLL ID/CLOCK ID: bits 28-31 for OMAP type */
+#define OMAP_TYPE_SHIFT 28
+#define OMAP_TYPE_MASK 0xF
+/* OPP ID: bits: 0-4 for OPP number */
+#define OPP_NO_POS 0
+#define OPP_NO_MASK 0x1F
+/* OPP ID: bits: 5-6 for VDD */
+#define VDD_NO_POS 5
+#define VDD_NO_MASK 0x3
+/* Other IDs: bits 20-27 for ID type */
+/* These IDs have bits 25,26,27 as 1 */
+#define OTHER_ID_TYPE_SHIFT 20
+#define OTHER_ID_TYPE_MASK 0xFF
+
+#define OTHER_ID_TYPE(X) ((X & OTHER_ID_TYPE_MASK) << OTHER_ID_TYPE_SHIFT)
+#define ID_OPP_NO(X) ((X & OPP_NO_MASK) << OPP_NO_POS)
+#define ID_VDD(X) ((X & VDD_NO_MASK) << VDD_NO_POS)
+#define OMAP(X) ((X >> OMAP_TYPE_SHIFT) & OMAP_TYPE_MASK)
+#define get_opp_no(X) ((X >> OPP_NO_POS) & OPP_NO_MASK)
+#define get_vdd(X) ((X >> VDD_NO_POS) & VDD_NO_MASK)
+
+/* VDD1 OPPs */
+#define PRCM_VDD1_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x1))
+#define PRCM_VDD1_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x2))
+#define PRCM_VDD1_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x3))
+#define PRCM_VDD1_OPP4 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x4))
+#define PRCM_VDD1_OPP5 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x5))
+#define PRCM_NO_VDD1_OPPS 5
+
+
+/* VDD2 OPPs */
+#define PRCM_VDD2_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x1))
+#define PRCM_VDD2_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x2))
+#define PRCM_VDD2_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x3))
+#define PRCM_NO_VDD2_OPPS 3
+/* XXX: end remove/move */
+
+
+/* XXX: find more appropriate place for these once DVFS is in place */
extern u32 current_vdd1_opp;
extern u32 current_vdd2_opp;
-extern struct kset power_subsys;
-extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay);
-extern void omap_udelay(u32 udelay);
+/*
+ * Smartreflex module enable/disable interface.
+ * NOTE: if smartreflex is not enabled from sysfs, these functions will not
+ * do anything.
+ */
+#if defined(CONFIG_ARCH_OMAP34XX) && defined(CONFIG_TWL4030_CORE)
+void enable_smartreflex(int srid);
+void disable_smartreflex(int srid);
+#else
+static inline void enable_smartreflex(int srid) {}
+static inline void disable_smartreflex(int srid) {}
+#endif
+
+
+#endif
+
diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
index 12bc22a..6e64fe7 100644
--- a/include/asm-arm/arch-omap/control.h
+++ b/include/asm-arm/arch-omap/control.h
@@ -138,6 +138,15 @@
#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
+#define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
+#define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
+#define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
+#define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c)
+#define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
+#define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124)
+#define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
+#define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)
+#define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130)
#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4)
@@ -172,6 +181,16 @@
#define OMAP2_SYSBOOT_1_MASK (1 << 1)
#define OMAP2_SYSBOOT_0_MASK (1 << 0)
+/* CONTROL_FUSE_SR bits */
+#define OMAP343X_SR2_SENNENABLE_MASK (0x3 << 10)
+#define OMAP343X_SR2_SENNENABLE_SHIFT 10
+#define OMAP343X_SR2_SENPENABLE_MASK (0x3 << 8)
+#define OMAP343X_SR2_SENPENABLE_SHIFT 8
+#define OMAP343X_SR1_SENNENABLE_MASK (0x3 << 2)
+#define OMAP343X_SR1_SENNENABLE_SHIFT 2
+#define OMAP343X_SR1_SENPENABLE_MASK (0x3 << 0)
+#define OMAP343X_SR1_SENPENABLE_SHIFT 0
+
#ifndef __ASSEMBLY__
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
extern void __iomem *omap_ctrl_base_get(void);
diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h
index 6a0459a..3667fd6 100644
--- a/include/asm-arm/arch-omap/omap34xx.h
+++ b/include/asm-arm/arch-omap/omap34xx.h
@@ -54,6 +54,8 @@
#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
#define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000)
#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
+#define OMAP34XX_SR1_BASE 0x480C9000
+#define OMAP34XX_SR2_BASE 0x480CB000
#if defined(CONFIG_ARCH_OMAP3430)
--
1.5.4.3

88
meta/packages/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch Normal file
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@ -0,0 +1,88 @@
From: "Rajendra Nayak" <rnayak@ti.com>
To: <linux-omap@vger.kernel.org>
Subject: [PATCH 02/02] Kconfig changes
Date: Tue, 10 Jun 2008 12:39:02 +0530
Updates the CPUidle Kconfig
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
arch/arm/Kconfig | 10 ++++++++++
drivers/cpuidle/Kconfig | 28 ++++++++++++++++++++++------
2 files changed, 32 insertions(+), 6 deletions(-)
Index: linux-omap-2.6/arch/arm/Kconfig
===================================================================
--- linux-omap-2.6.orig/arch/arm/Kconfig 2008-06-10 11:43:10.790502713 +0530
+++ linux-omap-2.6/arch/arm/Kconfig 2008-06-10 11:43:38.701604549 +0530
@@ -954,6 +954,16 @@ config ATAGS_PROC
endmenu
+if (ARCH_OMAP)
+
+menu "CPUIdle"
+
+source "drivers/cpuidle/Kconfig"
+
+endmenu
+
+endif
+
if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
menu "CPU Frequency scaling"
Index: linux-omap-2.6/drivers/cpuidle/Kconfig
===================================================================
--- linux-omap-2.6.orig/drivers/cpuidle/Kconfig 2008-06-10 11:43:10.790502713 +0530
+++ linux-omap-2.6/drivers/cpuidle/Kconfig 2008-06-10 12:06:36.139332151 +0530
@@ -1,20 +1,36 @@
+menu "CPU idle PM support"
config CPU_IDLE
bool "CPU idle PM support"
- default ACPI
+ default n
help
CPU idle is a generic framework for supporting software-controlled
idle processor power management. It includes modular cross-platform
governors that can be swapped during runtime.
- If you're using an ACPI-enabled platform, you should say Y here.
+ If you're using a mobile platform that supports CPU idle PM (e.g.
+ an ACPI-capable notebook), you should say Y here.
+
+if CPU_IDLE
+
+comment "Governors"
config CPU_IDLE_GOV_LADDER
- bool
+ bool "ladder"
depends on CPU_IDLE
- default y
+ default n
config CPU_IDLE_GOV_MENU
- bool
+ bool "menu"
depends on CPU_IDLE && NO_HZ
- default y
+ default n
+ help
+ This cpuidle governor evaluates all available states and chooses the
+ deepest state that meets all of the following constraints: BM activity,
+ expected time until next timer interrupt, and last break event time
+ delta. It is designed to minimize power consumption. Currently
+ dynticks is required.
+
+endif # CPU_IDLE
+
+endmenu
--
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1001
meta/packages/linux/linux-omap2-git/omap3evm/0003-ARM-OMAP-SmartReflex-driver.patch Normal file
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File diff suppressed because it is too large Load Diff

1567
meta/packages/linux/linux-omap2-git/omap3evm/defconfig Normal file
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File diff suppressed because it is too large Load Diff

15
meta/packages/linux/linux-omap2-git/omap3evm/no-empty-flash-warnings.patch Normal file
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@ -0,0 +1,15 @@
diff --git a/fs/jffs2/scan.c b/fs/jffs2/scan.c
index 1d437de..33b3feb 100644
--- a/fs/jffs2/scan.c
+++ b/fs/jffs2/scan.c
@@ -647,8 +647,8 @@ scan_more:
inbuf_ofs = ofs - buf_ofs;
while (inbuf_ofs < scan_end) {
if (unlikely(*(uint32_t *)(&buf[inbuf_ofs]) != 0xffffffff)) {
- printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n",
- empty_start, ofs);
+// printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n",
+// empty_start, ofs);
if ((err = jffs2_scan_dirty_space(c, jeb, ofs-empty_start)))
return err;
goto scan_more;

11
meta/packages/linux/linux-omap2-git/omap3evm/no-harry-potter.diff Normal file
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@ -0,0 +1,11 @@
--- /tmp/Makefile 2008-04-24 14:36:20.509598016 +0200
+++ git/arch/arm/Makefile 2008-04-24 14:36:31.949546584 +0200
@@ -47,7 +47,7 @@
# Note that GCC does not numerically define an architecture version
# macro, but instead defines a whole series of macros which makes
# testing for a specific architecture or later rather impossible.
-arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7a,-march=armv5t -Wa$(comma)-march=armv7a)
+arch-$(CONFIG_CPU_32v7) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
arch-$(CONFIG_CPU_32v6) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
# Only override the compiler option if ARMv6. The ARMv6K extensions are
# always available in ARMv7

7
meta/packages/linux/linux-omap2.inc Normal file
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@ -0,0 +1,7 @@
require linux.inc
DESCRIPTION = "Linux kernel for OMAP processors"
KERNEL_IMAGETYPE = "uImage"
module_autoload_ohci-hcd_omap5912osk = "ohci-hcd"

40
meta/packages/linux/linux-omap2_git.bb Normal file
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@ -0,0 +1,40 @@
require linux-omap2.inc
FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/linux-omap2-git/${MACHINE}"
SRCREV = "c32c81d59d2d8a66e63f82c9732db256d302068e"
PV = "2.6.25+2.6.26-rc8+${PR}+git${SRCREV}"
PR = "r38"
SRC_URI = "git://source.mvista.com/git/linux-omap-2.6.git;protocol=git \
file://defconfig"
SRC_URI_append_beagleboard = " file://no-harry-potter.diff;patch=1 \
file://0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch;patch=1 \
file://flash.patch;patch=1 \
file://0001-omap3-cpuidle.patch;patch=1 \
file://0002-omap3-cpuidle.patch;patch=1 \
file://timer-suppression.patch;patch=1 \
file://soc.patch;patch=1 \
file://16bpp.patch;patch=1 \
file://no-empty-flash-warnings.patch;patch=1 \
file://logo_linux_clut224.ppm \
file://oprofile-0.9.3.armv7.diff;patch=1 \
"
SRC_URI_append_omap3evm = " file://no-harry-potter.diff;patch=1 \
file://0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch;patch=1 \
file://0001-omap3-cpuidle.patch;patch=1 \
file://0002-omap3-cpuidle.patch;patch=1 \
file://timer-suppression.patch;patch=1 \
file://soc.patch;patch=1 \
file://no-empty-flash-warnings.patch;patch=1 \
file://touchscreen.patch;patch=1 \
"
COMPATIBLE_MACHINE = "omap2430sdp|omap2420h4|beagleboard|omap3evm"
S = "${WORKDIR}/git"