diff --git a/recipes-qt/qt5/qtjsbackend/0001-Fix-hardfloat-detection.patch b/recipes-qt/qt5/qtjsbackend/0001-Fix-hardfloat-detection.patch deleted file mode 100644 index 3d86fbf1b2..0000000000 --- a/recipes-qt/qt5/qtjsbackend/0001-Fix-hardfloat-detection.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 05a87fccb76447ce3cb4b926128af929f26469bb Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Eric=20B=C3=A9nard?= -Date: Wed, 22 May 2013 18:50:01 +0200 -Subject: [PATCH] Fix hardfloat detection - -based on the same patch for nodejs which says : - -gcc has a builtin define to denote hard abi when in use, e.g. when -using -mfloat-abi=hard it will define __ARM_PCS_VFP to 1 and therefore -we should check that to determine which calling convention is in use -and not __VFP_FP__ which merely indicates presence of VFP unit - -The fix has been provided by Khem Raj ---- - src/3rdparty/v8/src/platform-linux.cc | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/3rdparty/v8/src/platform-linux.cc b/src/3rdparty/v8/src/platform-linux.cc -index f6db423..8ae2249 100644 ---- a/src/3rdparty/v8/src/platform-linux.cc -+++ b/src/3rdparty/v8/src/platform-linux.cc -@@ -167,7 +167,7 @@ bool OS::ArmCpuHasFeature(CpuFeature feature) { - // calling this will return 1.0 and otherwise 0.0. - static void ArmUsingHardFloatHelper() { - asm("mov r0, #0":::"r0"); --#if defined(__VFP_FP__) && !defined(__SOFTFP__) -+#if defined(__ARM_PCS_VFP) && !defined(__SOFTFP__) - // Load 0x3ff00000 into r1 using instructions available in both ARM - // and Thumb mode. - asm("mov r1, #3":::"r1"); --- -1.7.10.4 - diff --git a/recipes-qt/qt5/qtjsbackend/0003-V8-Cleanup-hardfp-ABI-detection.-This-work-was-trigg.patch b/recipes-qt/qt5/qtjsbackend/0003-V8-Cleanup-hardfp-ABI-detection.-This-work-was-trigg.patch new file mode 100644 index 0000000000..a1f141411e --- /dev/null +++ b/recipes-qt/qt5/qtjsbackend/0003-V8-Cleanup-hardfp-ABI-detection.-This-work-was-trigg.patch @@ -0,0 +1,190 @@ +From d8a3566b013ba581e638cf2b960a8488d5fc9d64 Mon Sep 17 00:00:00 2001 +From: Sergio Martins +Date: Wed, 20 Feb 2013 22:34:46 +0000 +Subject: [PATCH 3/3] [V8] Cleanup hardfp ABI detection. This work was + triggered by issue 2140. + +Upstream Patch: https://chromiumcodereview.appspot.com/10713009 + +Task-Number: QTBUG-28890 +Change-Id: Id073388fbbffa2ad9b1cea0ab42e1d6e47862a36 +Reviewed-by: Sean Harmer +Reviewed-by: Simon Hausmann +--- + src/3rdparty/v8/src/platform-linux.cc | 70 ++++++++++++++++------------------ + src/3rdparty/v8/src/platform-qnx.cc | 71 ++++++++++++++++------------------- + 2 files changed, 65 insertions(+), 76 deletions(-) + +diff --git a/src/3rdparty/v8/src/platform-linux.cc b/src/3rdparty/v8/src/platform-linux.cc +index f6db423..18f59dd 100644 +--- a/src/3rdparty/v8/src/platform-linux.cc ++++ b/src/3rdparty/v8/src/platform-linux.cc +@@ -161,47 +161,41 @@ bool OS::ArmCpuHasFeature(CpuFeature feature) { + } + + +-// Simple helper function to detect whether the C code is compiled with +-// option -mfloat-abi=hard. The register d0 is loaded with 1.0 and the register +-// pair r0, r1 is loaded with 0.0. If -mfloat-abi=hard is pased to GCC then +-// calling this will return 1.0 and otherwise 0.0. +-static void ArmUsingHardFloatHelper() { +- asm("mov r0, #0":::"r0"); +-#if defined(__VFP_FP__) && !defined(__SOFTFP__) +- // Load 0x3ff00000 into r1 using instructions available in both ARM +- // and Thumb mode. +- asm("mov r1, #3":::"r1"); +- asm("mov r2, #255":::"r2"); +- asm("lsl r1, r1, #8":::"r1"); +- asm("orr r1, r1, r2":::"r1"); +- asm("lsl r1, r1, #20":::"r1"); +- // For vmov d0, r0, r1 use ARM mode. +-#ifdef __thumb__ +- asm volatile( +- "@ Enter ARM Mode \n\t" +- " adr r3, 1f \n\t" +- " bx r3 \n\t" +- " .ALIGN 4 \n\t" +- " .ARM \n" +- "1: vmov d0, r0, r1 \n\t" +- "@ Enter THUMB Mode\n\t" +- " adr r3, 2f+1 \n\t" +- " bx r3 \n\t" +- " .THUMB \n" +- "2: \n\t":::"r3"); ++bool OS::ArmUsingHardFloat() { ++ // GCC versions 4.6 and above define __ARM_PCS or __ARM_PCS_VFP to specify ++ // the Floating Point ABI used (PCS stands for Procedure Call Standard). ++ // We use these as well as a couple of other defines to statically determine ++ // what FP ABI used. ++ // GCC versions 4.4 and below don't support hard-fp. ++ // GCC versions 4.5 may support hard-fp without defining __ARM_PCS or ++ // __ARM_PCS_VFP. ++ ++#define GCC_VERSION (__GNUC__ * 10000 \ ++ + __GNUC_MINOR__ * 100 \ ++ + __GNUC_PATCHLEVEL__) ++#if GCC_VERSION >= 40600 ++#if defined(__ARM_PCS_VFP) ++ return true; + #else +- asm("vmov d0, r0, r1"); +-#endif // __thumb__ +-#endif // defined(__VFP_FP__) && !defined(__SOFTFP__) +- asm("mov r1, #0":::"r1"); +-} ++ return false; ++#endif + ++#elif GCC_VERSION < 40500 ++ return false; + +-bool OS::ArmUsingHardFloat() { +- // Cast helper function from returning void to returning double. +- typedef double (*F)(); +- F f = FUNCTION_CAST(FUNCTION_ADDR(ArmUsingHardFloatHelper)); +- return f() == 1.0; ++#else ++#if defined(__ARM_PCS_VFP) ++ return true; ++#elif defined(__ARM_PCS) || defined(__SOFTFP) || !defined(__VFP_FP__) ++ return false; ++#else ++#error "Your version of GCC does not report the FP ABI compiled for." \ ++ "Please report it on this issue" \ ++ "http://code.google.com/p/v8/issues/detail?id=2140" ++ ++#endif ++#endif ++#undef GCC_VERSION + } + #endif // def __arm__ + +diff --git a/src/3rdparty/v8/src/platform-qnx.cc b/src/3rdparty/v8/src/platform-qnx.cc +index bf9f5ba..46d69b8 100644 +--- a/src/3rdparty/v8/src/platform-qnx.cc ++++ b/src/3rdparty/v8/src/platform-qnx.cc +@@ -139,48 +139,43 @@ bool OS::ArmCpuHasFeature(CpuFeature feature) { + } + + +-// Simple helper function to detect whether the C code is compiled with +-// option -mfloat-abi=hard. The register d0 is loaded with 1.0 and the register +-// pair r0, r1 is loaded with 0.0. If -mfloat-abi=hard is pased to GCC then +-// calling this will return 1.0 and otherwise 0.0. +-static void ArmUsingHardFloatHelper() { +- asm("mov r0, #0"); +-#if defined(__VFP_FP__) && !defined(__SOFTFP__) +- // Load 0x3ff00000 into r1 using instructions available in both ARM +- // and Thumb mode. +- asm("mov r1, #3"); +- asm("mov r2, #255"); +- asm("lsl r1, r1, #8"); +- asm("orr r1, r1, r2"); +- asm("lsl r1, r1, #20"); +- // For vmov d0, r0, r1 use ARM mode. +-#ifdef __thumb__ +- asm volatile( +- "@ Enter ARM Mode \n\t" +- " adr r3, 1f \n\t" +- " bx r3 \n\t" +- " .ALIGN 4 \n\t" +- " .ARM \n" +- "1: vmov d0, r0, r1 \n\t" +- "@ Enter THUMB Mode\n\t" +- " adr r3, 2f+1 \n\t" +- " bx r3 \n\t" +- " .THUMB \n" +- "2: \n\t"); ++bool OS::ArmUsingHardFloat() { ++ // GCC versions 4.6 and above define __ARM_PCS or __ARM_PCS_VFP to specify ++ // the Floating Point ABI used (PCS stands for Procedure Call Standard). ++ // We use these as well as a couple of other defines to statically determine ++ // what FP ABI used. ++ // GCC versions 4.4 and below don't support hard-fp. ++ // GCC versions 4.5 may support hard-fp without defining __ARM_PCS or ++ // __ARM_PCS_VFP. ++ ++#define GCC_VERSION (__GNUC__ * 10000 \ ++ + __GNUC_MINOR__ * 100 \ ++ + __GNUC_PATCHLEVEL__) ++#if GCC_VERSION >= 40600 ++#if defined(__ARM_PCS_VFP) ++ return true; + #else +- asm("vmov d0, r0, r1"); +-#endif // __thumb__ +-#endif // defined(__VFP_FP__) && !defined(__SOFTFP__) +- asm("mov r1, #0"); +-} ++ return false; ++#endif + ++#elif GCC_VERSION < 40500 ++ return false; + +-bool OS::ArmUsingHardFloat() { +- // Cast helper function from returning void to returning double. +- typedef double (*F)(); +- F f = FUNCTION_CAST(FUNCTION_ADDR(ArmUsingHardFloatHelper)); +- return f() == 1.0; ++#else ++#if defined(__ARM_PCS_VFP) ++ return true; ++#elif defined(__ARM_PCS) || defined(__SOFTFP) || !defined(__VFP_FP__) ++ return false; ++#else ++#error "Your version of GCC does not report the FP ABI compiled for." \ ++ "Please report it on this issue" \ ++ "http://code.google.com/p/v8/issues/detail?id=2140" ++ ++#endif ++#endif ++#undef GCC_VERSION + } ++ + #endif // def __arm__ + + +-- +1.8.2.1 + diff --git a/recipes-qt/qt5/qtjsbackend_5.0.2.bb b/recipes-qt/qt5/qtjsbackend_5.0.2.bb index 0f8638ebbc..b536da3257 100644 --- a/recipes-qt/qt5/qtjsbackend_5.0.2.bb +++ b/recipes-qt/qt5/qtjsbackend_5.0.2.bb @@ -4,8 +4,8 @@ require ${PN}.inc PR = "${INC_PR}.0" SRC_URI += " \ - file://0001-Fix-hardfloat-detection.patch \ - " + file://0003-V8-Cleanup-hardfp-ABI-detection.-This-work-was-trigg.patch \ +" SRC_URI[md5sum] = "610f011757755888153cb2004c04446f" SRC_URI[sha256sum] = "65071ab9ab7d9024b7ba6d128a1c97ac09cf1b37818affb4238e4ba7d6665cc0"