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gcc: Drop 4.2.3 as its unused 

Signed-off-by: Richard Purdie <rpurdie@linux.intel.com>
This commit is contained in:
Richard Purdie 2010-06-08 21:03:12 +01:00
parent 47e5d86aad
commit 3a8ee5864d
80 changed files with 0 additions and 8033 deletions
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75
meta/packages/gcc/gcc-4.2.3.inc
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@ -1,75 +0,0 @@
require gcc-common.inc
DEPENDS =+ "mpfr gmp"
NATIVEDEPS = "mpfr-native gmp-native gettext-native"
SRC_URI = "ftp://ftp.gnu.org/pub/gnu/gcc/gcc-${PV}/gcc-${PV}.tar.bz2 \
file://100-uclibc-conf.patch;patch=1 \
file://103-uclibc-conf-noupstream.patch;patch=1 \
file://200-uclibc-locale.patch;patch=1 \
file://203-uclibc-locale-no__x.patch;patch=1 \
file://204-uclibc-locale-wchar_fix.patch;patch=1 \
file://205-uclibc-locale-update.patch;patch=1 \
file://300-libstdc++-pic.patch;patch=1 \
file://301-missing-execinfo_h.patch;patch=1 \
file://302-c99-snprintf.patch;patch=1 \
file://303-c99-complex-ugly-hack.patch;patch=1 \
file://304-index_macro.patch;patch=1 \
file://305-libmudflap-susv3-legacy.patch;patch=1 \
file://306-libstdc++-namespace.patch;patch=1 \
file://307-locale_facets.patch;patch=1 \
file://402-libbackend_dep_gcov-iov.h.patch;patch=1 \
file://602-sdk-libstdc++-includes.patch;patch=1 \
file://740-sh-pr24836.patch;patch=1 \
file://800-arm-bigendian.patch;patch=1 \
file://801-arm-bigendian-eabi.patch;patch=1 \
file://904-flatten-switch-stmt-00.patch;patch=1 \
file://arm-nolibfloat.patch;patch=1 \
file://arm-softfloat.patch;patch=1 \
file://gcc41-configure.in.patch;patch=1 \
file://arm-thumb.patch;patch=1 \
file://arm-thumb-cache.patch;patch=1 \
file://ldflags.patch;patch=1 \
file://zecke-xgcc-cpp.patch;patch=1 \
file://unbreak-armv4t.patch;patch=1 \
file://cache-amnesia.patch;patch=1 \
file://gfortran.patch;patch=1 \
file://gcc-4.0.2-e300c2c3.patch;patch=1 \
file://fortran-static-linking.patch;patch=1 \
file://intermask-bigendian.patch;patch=1 \
"
SRC_URI_append_ep93xx = " \
file://arm-crunch-saveregs.patch;patch=1 \
file://arm-crunch-20000320.patch;patch=1 \
file://arm-crunch-compare.patch;patch=1 \
file://arm-crunch-compare-unordered.patch;patch=1 \
file://arm-crunch-compare-geu.patch;patch=1 \
file://arm-crunch-eabi-ieee754.patch;patch=1 \
file://arm-crunch-eabi-ieee754-div.patch;patch=1 \
file://arm-crunch-64bit-disable0.patch;patch=1 \
file://arm-crunch-offset.patch;patch=1 \
file://arm-crunch-fp_consts.patch;patch=1 \
file://arm-crunch-neg2.patch;patch=1 \
file://arm-crunch-predicates3.patch;patch=1 \
file://arm-crunch-cfcvtds-disable.patch;patch=1 \
file://arm-crunch-floatsi-disable.patch;patch=1 \
file://arm-crunch-truncsi-disable.patch;patch=1 \
file://arm-crunch-cfcvt64-disable.patch;patch=1 \
file://arm-crunch-cirrus-bugfixes.patch;patch=1 \
"
PACKAGE_ARCH_ep93xx = "${MACHINE_ARCH}"
SRC_URI_append_sh3 = " file://sh3-installfix-fixheaders.patch;patch=1 "
# Language Overrides
FORTRAN = ""
FORTRAN_linux-gnueabi = ",fortran"
JAVA = ""
EXTRA_OECONF_BASE += " --disable-libssp --disable-bootstrap --disable-libgomp --disable-libmudflap"
EXTRA_OECONF_INITIAL = "--disable-libmudflap --disable-libgomp --disable-libssp"
EXTRA_OECONF_INTERMEDIATE = "--disable-libmudflap --disable-libgomp --disable-libssp"
ARM_INSTRUCTION_SET = "arm"

200
meta/packages/gcc/gcc-4.2.3/100-uclibc-conf.patch vendored
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@ -1,200 +0,0 @@
--- gcc/libgomp/configure
+++ gcc/libgomp/configure
@@ -3771,7 +3771,7 @@
;;
# This must be Linux ELF.
-linux-gnu*)
+linux*)
lt_cv_deplibs_check_method=pass_all
;;
--- gcc/gcc/config/cris/linux.h
+++ gcc/gcc/config/cris/linux.h
@@ -74,7 +74,11 @@
#define CRIS_DEFAULT_CPU_VERSION CRIS_CPU_NG
#undef CRIS_SUBTARGET_VERSION
-#define CRIS_SUBTARGET_VERSION " - cris-axis-linux-gnu"
+#if UCLIBC_DEFAULT
+# define CRIS_SUBTARGET_VERSION " - cris-axis-linux-uclibc"
+#else
+# define CRIS_SUBTARGET_VERSION " - cris-axis-linux-gnu"
+#endif
#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
--- gcc/libstdc++-v3/configure
+++ gcc/libstdc++-v3/configure
@@ -4276,7 +4276,7 @@
;;
# This must be Linux ELF.
-linux-gnu*)
+linux*)
lt_cv_deplibs_check_method=pass_all
;;
--- gcc/zlib/configure
+++ gcc/zlib/configure
@@ -3422,7 +3422,7 @@
;;
# This must be Linux ELF.
-linux-gnu*)
+linux*)
lt_cv_deplibs_check_method=pass_all
;;
--- gcc/libobjc/configure
+++ gcc/libobjc/configure
@@ -3309,7 +3309,7 @@
;;
# This must be Linux ELF.
-linux-gnu*)
+linux*)
lt_cv_deplibs_check_method=pass_all
;;
--- gcc/libgfortran/configure
+++ gcc/libgfortran/configure
@@ -3695,7 +3695,7 @@
;;
# This must be Linux ELF.
-linux-gnu*)
+linux*)
lt_cv_deplibs_check_method=pass_all
;;
--- gcc/libmudflap/configure
+++ gcc/libmudflap/configure
@@ -5378,7 +5378,7 @@
;;
# This must be Linux ELF.
-linux-gnu*)
+linux*)
lt_cv_deplibs_check_method=pass_all
;;
--- gcc/boehm-gc/configure
+++ gcc/boehm-gc/configure
@@ -4316,7 +4316,7 @@
;;
# This must be Linux ELF.
-linux-gnu*)
+linux*)
lt_cv_deplibs_check_method=pass_all
;;
--- gcc/libffi/configure
+++ gcc/libffi/configure
@@ -3453,7 +3453,7 @@
;;
# This must be Linux ELF.
-linux-gnu*)
+linux*)
lt_cv_deplibs_check_method=pass_all
;;
--- gcc/libssp/configure
+++ gcc/libssp/configure
@@ -4409,7 +4409,7 @@
;;
# This must be Linux ELF.
-linux-gnu*)
+linux*)
lt_cv_deplibs_check_method=pass_all
;;
--- gcc/contrib/regression/objs-gcc.sh
+++ gcc/contrib/regression/objs-gcc.sh
@@ -105,6 +105,10 @@
then
make all-gdb all-dejagnu all-ld || exit 1
make install-gdb install-dejagnu install-ld || exit 1
+elif [ $H_REAL_TARGET = $H_REAL_HOST -a $H_REAL_TARGET = i686-pc-linux-uclibc ]
+ then
+ make all-gdb all-dejagnu all-ld || exit 1
+ make install-gdb install-dejagnu install-ld || exit 1
elif [ $H_REAL_TARGET = $H_REAL_HOST ] ; then
make bootstrap || exit 1
make install || exit 1
--- gcc/libjava/classpath/ltconfig
+++ gcc/libjava/classpath/ltconfig
@@ -603,7 +603,7 @@
# Transform linux* to *-*-linux-gnu*, to support old configure scripts.
case $host_os in
-linux-gnu*) ;;
+linux-gnu*|linux-uclibc*) ;;
linux*) host=`echo $host | sed 's/^\(.*-.*-linux\)\(.*\)$/\1-gnu\2/'`
esac
@@ -1251,7 +1251,7 @@
;;
# This must be Linux ELF.
-linux-gnu*)
+linux*)
version_type=linux
need_lib_prefix=no
need_version=no
--- gcc/libjava/classpath/configure
+++ gcc/libjava/classpath/configure
@@ -4665,7 +4665,7 @@
;;
# This must be Linux ELF.
-linux-gnu*)
+linux*)
lt_cv_deplibs_check_method=pass_all
;;
--- gcc/libjava/configure
+++ gcc/libjava/configure
@@ -5212,7 +5212,7 @@
;;
# This must be Linux ELF.
-linux-gnu*)
+linux*)
lt_cv_deplibs_check_method=pass_all
;;
--- gcc/libtool.m4
+++ gcc/libtool.m4
@@ -739,7 +739,7 @@
;;
# This must be Linux ELF.
-linux-gnu*)
+linux*)
lt_cv_deplibs_check_method=pass_all
;;
--- gcc/ltconfig
+++ gcc/ltconfig
@@ -603,7 +603,7 @@
# Transform linux* to *-*-linux-gnu*, to support old configure scripts.
case $host_os in
-linux-gnu*) ;;
+linux-gnu*|linux-uclibc*) ;;
linux*) host=`echo $host | sed 's/^\(.*-.*-linux\)\(.*\)$/\1-gnu\2/'`
esac
@@ -1251,7 +1251,7 @@
;;
# This must be Linux ELF.
-linux-gnu*)
+linux*)
version_type=linux
need_lib_prefix=no
need_version=no

11
meta/packages/gcc/gcc-4.2.3/103-uclibc-conf-noupstream.patch vendored
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@ -1,11 +0,0 @@
--- gcc/gcc/config.gcc.uclibc100-sh~ 2006-03-06 20:46:56 +0100
+++ gcc/gcc/config.gcc 2006-03-10 15:02:41 +0100
@@ -1905,7 +1905,7 @@
;;
sh-*-elf* | sh[12346l]*-*-elf* | sh*-*-kaos* | \
sh-*-symbianelf* | sh[12346l]*-*-symbianelf* | \
- sh-*-linux* | sh[346lbe]*-*-linux* | \
+ sh*-*-linux* | sh[346lbe]*-*-linux* | \
sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \
sh64-*-netbsd* | sh64l*-*-netbsd*)
tmake_file="${tmake_file} sh/t-sh sh/t-elf"

27
meta/packages/gcc/gcc-4.2.3/110-arm-eabi.patch vendored
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@ -1,27 +0,0 @@
--- gcc-2005q3-1.orig/gcc/config.gcc 2005-10-31 19:02:54.000000000 +0300
+++ gcc-2005q3-1/gcc/config.gcc 2006-01-27 01:09:09.000000000 +0300
@@ -674,7 +674,7 @@
tm_file="dbxelf.h elfos.h linux.h arm/elf.h arm/linux-gas.h arm/linux-elf.h"
tmake_file="t-slibgcc-elf-ver t-linux arm/t-arm"
case ${target} in
- arm*-*-linux-gnueabi)
+ arm*-*-linux-gnueabi | arm*-*-linux-uclibcgnueabi)
tm_file="$tm_file arm/bpabi.h arm/linux-eabi.h"
tmake_file="$tmake_file arm/t-arm-elf arm/t-bpabi arm/t-linux-eabi"
# The BPABI long long divmod functions return a 128-bit value in
diff -urN gcc-2005q3-2/gcc/config/arm/linux-eabi.h gcc-2005q3-2.new/gcc/config/arm/linux-eabi.h
--- gcc-2005q3-2/gcc/config/arm/linux-eabi.h 2005-12-07 23:14:16.000000000 +0300
+++ gcc-2005q3-2.new/gcc/config/arm/linux-eabi.h 2006-03-29 19:02:34.000000000 +0400
@@ -53,7 +53,11 @@
/* Use ld-linux.so.3 so that it will be possible to run "classic"
GNU/Linux binaries on an EABI system. */
#undef LINUX_TARGET_INTERPRETER
+#ifdef USE_UCLIBC
+#define LINUX_TARGET_INTERPRETER "/lib/ld-uClibc.so.0"
+#else
#define LINUX_TARGET_INTERPRETER "/lib/ld-linux.so.3"
+#endif
/* At this point, bpabi.h will have clobbered LINK_SPEC. We want to
use the GNU/Linux version, not the generic BPABI version. */

2790
meta/packages/gcc/gcc-4.2.3/200-uclibc-locale.patch vendored
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213
meta/packages/gcc/gcc-4.2.3/203-uclibc-locale-no__x.patch vendored
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@ -1,213 +0,0 @@
--- gcc/libstdc++-v3/config/locale/uclibc/c++locale_internal.h.uclibc200no__x~ 2006-03-10 15:06:17 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/c++locale_internal.h 2006-03-10 15:32:37 +0100
@@ -60,4 +60,49 @@
extern "C" __typeof(wctype_l) __wctype_l;
#endif
+# define __nl_langinfo_l nl_langinfo_l
+# define __strcoll_l strcoll_l
+# define __strftime_l strftime_l
+# define __strtod_l strtod_l
+# define __strtof_l strtof_l
+# define __strtold_l strtold_l
+# define __strxfrm_l strxfrm_l
+# define __newlocale newlocale
+# define __freelocale freelocale
+# define __duplocale duplocale
+# define __uselocale uselocale
+
+# ifdef _GLIBCXX_USE_WCHAR_T
+# define __iswctype_l iswctype_l
+# define __towlower_l towlower_l
+# define __towupper_l towupper_l
+# define __wcscoll_l wcscoll_l
+# define __wcsftime_l wcsftime_l
+# define __wcsxfrm_l wcsxfrm_l
+# define __wctype_l wctype_l
+# endif
+
+#else
+# define __nl_langinfo_l(N, L) nl_langinfo((N))
+# define __strcoll_l(S1, S2, L) strcoll((S1), (S2))
+# define __strtod_l(S, E, L) strtod((S), (E))
+# define __strtof_l(S, E, L) strtof((S), (E))
+# define __strtold_l(S, E, L) strtold((S), (E))
+# define __strxfrm_l(S1, S2, N, L) strxfrm((S1), (S2), (N))
+# warning should dummy __newlocale check for C|POSIX ?
+# define __newlocale(a, b, c) NULL
+# define __freelocale(a) ((void)0)
+# define __duplocale(a) __c_locale()
+//# define __uselocale ?
+//
+# ifdef _GLIBCXX_USE_WCHAR_T
+# define __iswctype_l(C, M, L) iswctype((C), (M))
+# define __towlower_l(C, L) towlower((C))
+# define __towupper_l(C, L) towupper((C))
+# define __wcscoll_l(S1, S2, L) wcscoll((S1), (S2))
+//# define __wcsftime_l(S, M, F, T, L) wcsftime((S), (M), (F), (T))
+# define __wcsxfrm_l(S1, S2, N, L) wcsxfrm((S1), (S2), (N))
+# define __wctype_l(S, L) wctype((S))
+# endif
+
#endif // GLIBC 2.3 and later
--- gcc/libstdc++-v3/config/locale/uclibc/c_locale.cc.uclibc200no__x~ 2006-03-10 15:06:17 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/c_locale.cc 2006-03-10 15:32:37 +0100
@@ -39,20 +39,6 @@
#include <langinfo.h>
#include <bits/c++locale_internal.h>
-#ifndef __UCLIBC_HAS_XLOCALE__
-#define __strtol_l(S, E, B, L) strtol((S), (E), (B))
-#define __strtoul_l(S, E, B, L) strtoul((S), (E), (B))
-#define __strtoll_l(S, E, B, L) strtoll((S), (E), (B))
-#define __strtoull_l(S, E, B, L) strtoull((S), (E), (B))
-#define __strtof_l(S, E, L) strtof((S), (E))
-#define __strtod_l(S, E, L) strtod((S), (E))
-#define __strtold_l(S, E, L) strtold((S), (E))
-#warning should dummy __newlocale check for C|POSIX ?
-#define __newlocale(a, b, c) NULL
-#define __freelocale(a) ((void)0)
-#define __duplocale(a) __c_locale()
-#endif
-
namespace std
{
template<>
--- gcc/libstdc++-v3/config/locale/uclibc/collate_members.cc.uclibc200no__x~ 2006-03-10 15:06:17 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/collate_members.cc 2006-03-10 15:32:37 +0100
@@ -36,13 +36,6 @@
#include <locale>
#include <bits/c++locale_internal.h>
-#ifndef __UCLIBC_HAS_XLOCALE__
-#define __strcoll_l(S1, S2, L) strcoll((S1), (S2))
-#define __strxfrm_l(S1, S2, N, L) strxfrm((S1), (S2), (N))
-#define __wcscoll_l(S1, S2, L) wcscoll((S1), (S2))
-#define __wcsxfrm_l(S1, S2, N, L) wcsxfrm((S1), (S2), (N))
-#endif
-
namespace std
{
// These are basically extensions to char_traits, and perhaps should
--- gcc/libstdc++-v3/config/locale/uclibc/monetary_members.cc.uclibc200no__x~ 2006-03-10 15:06:17 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/monetary_members.cc 2006-03-10 15:32:37 +0100
@@ -43,10 +43,6 @@
#warning tailor for stub locale support
#endif
-#ifndef __UCLIBC_HAS_XLOCALE__
-#define __nl_langinfo_l(N, L) nl_langinfo((N))
-#endif
-
namespace std
{
// Construct and return valid pattern consisting of some combination of:
--- gcc/libstdc++-v3/config/locale/uclibc/numeric_members.cc.uclibc200no__x~ 2006-03-10 15:06:17 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/numeric_members.cc 2006-03-10 15:32:37 +0100
@@ -41,9 +41,6 @@
#ifdef __UCLIBC_MJN3_ONLY__
#warning tailor for stub locale support
#endif
-#ifndef __UCLIBC_HAS_XLOCALE__
-#define __nl_langinfo_l(N, L) nl_langinfo((N))
-#endif
namespace std
{
--- gcc/libstdc++-v3/config/locale/uclibc/time_members.cc.uclibc200no__x~ 2006-03-10 15:06:17 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/time_members.cc 2006-03-10 15:32:37 +0100
@@ -40,9 +40,6 @@
#ifdef __UCLIBC_MJN3_ONLY__
#warning tailor for stub locale support
#endif
-#ifndef __UCLIBC_HAS_XLOCALE__
-#define __nl_langinfo_l(N, L) nl_langinfo((N))
-#endif
namespace std
{
--- gcc/libstdc++-v3/config/locale/uclibc/ctype_members.cc.uclibc200no__x~ 2006-03-10 15:06:17 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/ctype_members.cc 2006-03-10 15:32:37 +0100
@@ -38,13 +38,6 @@
#undef _LIBC
#include <bits/c++locale_internal.h>
-#ifndef __UCLIBC_HAS_XLOCALE__
-#define __wctype_l(S, L) wctype((S))
-#define __towupper_l(C, L) towupper((C))
-#define __towlower_l(C, L) towlower((C))
-#define __iswctype_l(C, M, L) iswctype((C), (M))
-#endif
-
namespace std
{
// NB: The other ctype<char> specializations are in src/locale.cc and
--- gcc/libstdc++-v3/config/locale/uclibc/messages_members.cc.uclibc200no__x~ 2006-03-10 15:06:17 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/messages_members.cc 2006-03-10 15:32:37 +0100
@@ -39,13 +39,10 @@
#ifdef __UCLIBC_MJN3_ONLY__
#warning fix gettext stuff
#endif
-#ifdef __UCLIBC_HAS_GETTEXT_AWARENESS__
-extern "C" char *__dcgettext(const char *domainname,
- const char *msgid, int category);
#undef gettext
-#define gettext(msgid) __dcgettext(NULL, msgid, LC_MESSAGES)
+#ifdef __UCLIBC_HAS_GETTEXT_AWARENESS__
+#define gettext(msgid) dcgettext(NULL, msgid, LC_MESSAGES)
#else
-#undef gettext
#define gettext(msgid) (msgid)
#endif
--- gcc/libstdc++-v3/config/locale/uclibc/messages_members.h.uclibc200no__x~ 2006-03-10 15:06:17 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/messages_members.h 2006-03-10 15:32:37 +0100
@@ -36,15 +36,11 @@
#ifdef __UCLIBC_MJN3_ONLY__
#warning fix prototypes for *textdomain funcs
#endif
-#ifdef __UCLIBC_HAS_GETTEXT_AWARENESS__
-extern "C" char *__textdomain(const char *domainname);
-extern "C" char *__bindtextdomain(const char *domainname,
- const char *dirname);
-#else
-#undef __textdomain
-#undef __bindtextdomain
-#define __textdomain(D) ((void)0)
-#define __bindtextdomain(D,P) ((void)0)
+#ifndef __UCLIBC_HAS_GETTEXT_AWARENESS__
+#undef textdomain
+#undef bindtextdomain
+#define textdomain(D) ((void)0)
+#define bindtextdomain(D,P) ((void)0)
#endif
// Non-virtual member functions.
@@ -70,7 +66,7 @@
messages<_CharT>::open(const basic_string<char>& __s, const locale& __loc,
const char* __dir) const
{
- __bindtextdomain(__s.c_str(), __dir);
+ bindtextdomain(__s.c_str(), __dir);
return this->do_open(__s, __loc);
}
@@ -90,7 +86,7 @@
{
// No error checking is done, assume the catalog exists and can
// be used.
- __textdomain(__s.c_str());
+ textdomain(__s.c_str());
return 0;
}
--- gcc/libstdc++-v3/config/locale/uclibc/c_locale.h.uclibc200no__x~ 2006-03-10 15:06:17 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/c_locale.h 2006-03-10 15:32:37 +0100
@@ -68,6 +68,7 @@
{
extern "C" __typeof(uselocale) __uselocale;
}
+#define __uselocale uselocale
#endif
namespace std

48
meta/packages/gcc/gcc-4.2.3/204-uclibc-locale-wchar_fix.patch vendored
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@ -1,48 +0,0 @@
--- gcc/libstdc++-v3/config/locale/uclibc/monetary_members.cc.uclibc200_wchar~ 2006-03-10 15:32:37 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/monetary_members.cc 2006-03-10 15:37:27 +0100
@@ -401,7 +401,7 @@
# ifdef __UCLIBC_HAS_XLOCALE__
_M_data->_M_decimal_point = __cloc->decimal_point_wc;
_M_data->_M_thousands_sep = __cloc->thousands_sep_wc;
-# else
+# elif defined __UCLIBC_HAS_LOCALE__
_M_data->_M_decimal_point = __global_locale->decimal_point_wc;
_M_data->_M_thousands_sep = __global_locale->thousands_sep_wc;
# endif
@@ -556,7 +556,7 @@
# ifdef __UCLIBC_HAS_XLOCALE__
_M_data->_M_decimal_point = __cloc->decimal_point_wc;
_M_data->_M_thousands_sep = __cloc->thousands_sep_wc;
-# else
+# elif defined __UCLIBC_HAS_LOCALE__
_M_data->_M_decimal_point = __global_locale->decimal_point_wc;
_M_data->_M_thousands_sep = __global_locale->thousands_sep_wc;
# endif
--- gcc/libstdc++-v3/config/locale/uclibc/numeric_members.cc.uclibc200_wchar~ 2006-03-10 15:32:37 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/numeric_members.cc 2006-03-10 15:37:27 +0100
@@ -127,12 +127,25 @@
{
// Named locale.
// NB: In the GNU model wchar_t is always 32 bit wide.
+#ifdef __UCLIBC_MJN3_ONLY__
+#warning fix this... should be numeric
+#endif
+#ifdef __UCLIBC__
+# ifdef __UCLIBC_HAS_XLOCALE__
+ _M_data->_M_decimal_point = __cloc->decimal_point_wc;
+ _M_data->_M_thousands_sep = __cloc->thousands_sep_wc;
+# elif defined __UCLIBC_HAS_LOCALE__
+ _M_data->_M_decimal_point = __global_locale->decimal_point_wc;
+ _M_data->_M_thousands_sep = __global_locale->thousands_sep_wc;
+# endif
+#else
union { char *__s; wchar_t __w; } __u;
__u.__s = __nl_langinfo_l(_NL_NUMERIC_DECIMAL_POINT_WC, __cloc);
_M_data->_M_decimal_point = __u.__w;
__u.__s = __nl_langinfo_l(_NL_NUMERIC_THOUSANDS_SEP_WC, __cloc);
_M_data->_M_thousands_sep = __u.__w;
+#endif
if (_M_data->_M_thousands_sep == L'\0')
_M_data->_M_grouping = "";

347
meta/packages/gcc/gcc-4.2.3/205-uclibc-locale-update.patch vendored
View File

@ -1,347 +0,0 @@
--- gcc/libstdc++-v3/config/locale/uclibc/c_locale.cc.uclibc200_update~ 2006-03-10 15:32:37 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/c_locale.cc 2006-03-10 15:39:14 +0100
@@ -46,16 +47,13 @@
__convert_to_v(const char* __s, float& __v, ios_base::iostate& __err,
const __c_locale& __cloc)
{
- if (!(__err & ios_base::failbit))
- {
- char* __sanity;
- errno = 0;
- float __f = __strtof_l(__s, &__sanity, __cloc);
- if (__sanity != __s && errno != ERANGE)
- __v = __f;
- else
- __err |= ios_base::failbit;
- }
+ char* __sanity;
+ errno = 0;
+ float __f = __strtof_l(__s, &__sanity, __cloc);
+ if (__sanity != __s && errno != ERANGE)
+ __v = __f;
+ else
+ __err |= ios_base::failbit;
}
template<>
@@ -63,16 +61,13 @@
__convert_to_v(const char* __s, double& __v, ios_base::iostate& __err,
const __c_locale& __cloc)
{
- if (!(__err & ios_base::failbit))
- {
- char* __sanity;
- errno = 0;
- double __d = __strtod_l(__s, &__sanity, __cloc);
- if (__sanity != __s && errno != ERANGE)
- __v = __d;
- else
- __err |= ios_base::failbit;
- }
+ char* __sanity;
+ errno = 0;
+ double __d = __strtod_l(__s, &__sanity, __cloc);
+ if (__sanity != __s && errno != ERANGE)
+ __v = __d;
+ else
+ __err |= ios_base::failbit;
}
template<>
@@ -80,16 +75,13 @@
__convert_to_v(const char* __s, long double& __v, ios_base::iostate& __err,
const __c_locale& __cloc)
{
- if (!(__err & ios_base::failbit))
- {
- char* __sanity;
- errno = 0;
- long double __ld = __strtold_l(__s, &__sanity, __cloc);
- if (__sanity != __s && errno != ERANGE)
- __v = __ld;
- else
- __err |= ios_base::failbit;
- }
+ char* __sanity;
+ errno = 0;
+ long double __ld = __strtold_l(__s, &__sanity, __cloc);
+ if (__sanity != __s && errno != ERANGE)
+ __v = __ld;
+ else
+ __err |= ios_base::failbit;
}
void
@@ -110,7 +102,7 @@
void
locale::facet::_S_destroy_c_locale(__c_locale& __cloc)
{
- if (_S_get_c_locale() != __cloc)
+ if (__cloc && _S_get_c_locale() != __cloc)
__freelocale(__cloc);
}
--- gcc/libstdc++-v3/config/locale/uclibc/ctype_members.cc.uclibc200_update~ 2006-03-10 15:32:37 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/ctype_members.cc 2006-03-10 15:39:14 +0100
@@ -33,9 +33,14 @@
// Written by Benjamin Kosnik <bkoz@redhat.com>
+#include <features.h>
+#ifdef __UCLIBC_HAS_LOCALE__
#define _LIBC
#include <locale>
#undef _LIBC
+#else
+#include <locale>
+#endif
#include <bits/c++locale_internal.h>
namespace std
@@ -138,20 +143,34 @@
ctype<wchar_t>::
do_is(mask __m, wchar_t __c) const
{
- // Highest bitmask in ctype_base == 10, but extra in "C"
- // library for blank.
+ // The case of __m == ctype_base::space is particularly important,
+ // due to its use in many istream functions. Therefore we deal with
+ // it first, exploiting the knowledge that on GNU systems _M_bit[5]
+ // is the mask corresponding to ctype_base::space. NB: an encoding
+ // change would not affect correctness!
bool __ret = false;
- const size_t __bitmasksize = 11;
- for (size_t __bitcur = 0; __bitcur <= __bitmasksize; ++__bitcur)
- if (__m & _M_bit[__bitcur]
- && __iswctype_l(__c, _M_wmask[__bitcur], _M_c_locale_ctype))
- {
- __ret = true;
- break;
- }
+ if (__m == _M_bit[5])
+ __ret = __iswctype_l(__c, _M_wmask[5], _M_c_locale_ctype);
+ else
+ {
+ // Highest bitmask in ctype_base == 10, but extra in "C"
+ // library for blank.
+ const size_t __bitmasksize = 11;
+ for (size_t __bitcur = 0; __bitcur <= __bitmasksize; ++__bitcur)
+ if (__m & _M_bit[__bitcur])
+ {
+ if (__iswctype_l(__c, _M_wmask[__bitcur], _M_c_locale_ctype))
+ {
+ __ret = true;
+ break;
+ }
+ else if (__m == _M_bit[__bitcur])
+ break;
+ }
+ }
return __ret;
}
-
+
const wchar_t*
ctype<wchar_t>::
do_is(const wchar_t* __lo, const wchar_t* __hi, mask* __vec) const
--- gcc/libstdc++-v3/config/locale/uclibc/messages_members.h.uclibc200_update~ 2006-03-10 15:32:37 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/messages_members.h 2006-03-10 15:39:14 +0100
@@ -47,18 +47,21 @@
template<typename _CharT>
messages<_CharT>::messages(size_t __refs)
: facet(__refs), _M_c_locale_messages(_S_get_c_locale()),
- _M_name_messages(_S_get_c_name())
+ _M_name_messages(_S_get_c_name())
{ }
template<typename _CharT>
messages<_CharT>::messages(__c_locale __cloc, const char* __s,
size_t __refs)
- : facet(__refs), _M_c_locale_messages(_S_clone_c_locale(__cloc)),
- _M_name_messages(__s)
+ : facet(__refs), _M_c_locale_messages(NULL), _M_name_messages(NULL)
{
- char* __tmp = new char[std::strlen(__s) + 1];
- std::strcpy(__tmp, __s);
+ const size_t __len = std::strlen(__s) + 1;
+ char* __tmp = new char[__len];
+ std::memcpy(__tmp, __s, __len);
_M_name_messages = __tmp;
+
+ // Last to avoid leaking memory if new throws.
+ _M_c_locale_messages = _S_clone_c_locale(__cloc);
}
template<typename _CharT>
--- gcc/libstdc++-v3/config/locale/uclibc/monetary_members.cc.uclibc200_update~ 2006-03-10 15:37:27 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/monetary_members.cc 2006-03-10 15:39:14 +0100
@@ -33,9 +33,14 @@
// Written by Benjamin Kosnik <bkoz@redhat.com>
+#include <features.h>
+#ifdef __UCLIBC_HAS_LOCALE__
#define _LIBC
#include <locale>
#undef _LIBC
+#else
+#include <locale>
+#endif
#include <bits/c++locale_internal.h>
#ifdef __UCLIBC_MJN3_ONLY__
@@ -206,7 +211,7 @@
}
break;
default:
- ;
+ __ret = pattern();
}
return __ret;
}
--- gcc/libstdc++-v3/config/locale/uclibc/numeric_members.cc.uclibc200_update~ 2006-03-10 15:37:27 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/numeric_members.cc 2006-03-10 15:39:14 +0100
@@ -33,9 +33,14 @@
// Written by Benjamin Kosnik <bkoz@redhat.com>
+#include <features.h>
+#ifdef __UCLIBC_HAS_LOCALE__
#define _LIBC
#include <locale>
#undef _LIBC
+#else
+#include <locale>
+#endif
#include <bits/c++locale_internal.h>
#ifdef __UCLIBC_MJN3_ONLY__
--- gcc/libstdc++-v3/config/locale/uclibc/time_members.h.uclibc200_update~ 2006-03-10 15:06:17 +0100
+++ gcc/libstdc++-v3/config/locale/uclibc/time_members.h 2006-03-10 15:39:14 +0100
@@ -37,25 +37,33 @@
template<typename _CharT>
__timepunct<_CharT>::__timepunct(size_t __refs)
: facet(__refs), _M_data(NULL), _M_c_locale_timepunct(NULL),
- _M_name_timepunct(_S_get_c_name())
+ _M_name_timepunct(_S_get_c_name())
{ _M_initialize_timepunct(); }
template<typename _CharT>
__timepunct<_CharT>::__timepunct(__cache_type* __cache, size_t __refs)
: facet(__refs), _M_data(__cache), _M_c_locale_timepunct(NULL),
- _M_name_timepunct(_S_get_c_name())
+ _M_name_timepunct(_S_get_c_name())
{ _M_initialize_timepunct(); }
template<typename _CharT>
__timepunct<_CharT>::__timepunct(__c_locale __cloc, const char* __s,
size_t __refs)
: facet(__refs), _M_data(NULL), _M_c_locale_timepunct(NULL),
- _M_name_timepunct(__s)
+ _M_name_timepunct(NULL)
{
- char* __tmp = new char[std::strlen(__s) + 1];
- std::strcpy(__tmp, __s);
+ const size_t __len = std::strlen(__s) + 1;
+ char* __tmp = new char[__len];
+ std::memcpy(__tmp, __s, __len);
_M_name_timepunct = __tmp;
- _M_initialize_timepunct(__cloc);
+
+ try
+ { _M_initialize_timepunct(__cloc); }
+ catch(...)
+ {
+ delete [] _M_name_timepunct;
+ __throw_exception_again;
+ }
}
template<typename _CharT>
--- gcc-4.2/libstdc++-v3/config/locale/uclibc/c_locale.h.old 2006-09-28 11:39:00.000000000 +0200
+++ gcc-4.2/libstdc++-v3/config/locale/uclibc/c_locale.h 2006-09-28 12:10:41.000000000 +0200
@@ -39,21 +39,23 @@
#pragma GCC system_header
#include <cstring> // get std::strlen
-#include <cstdio> // get std::snprintf or std::sprintf
+#include <cstdio> // get std::vsnprintf or std::vsprintf
#include <clocale>
#include <langinfo.h> // For codecvt
#ifdef __UCLIBC_MJN3_ONLY__
#warning fix this
#endif
-#ifdef __UCLIBC_HAS_LOCALE__
+#ifdef _GLIBCXX_USE_ICONV
#include <iconv.h> // For codecvt using iconv, iconv_t
#endif
-#ifdef __UCLIBC_HAS_GETTEXT_AWARENESS__
-#include <libintl.h> // For messages
+#ifdef HAVE_LIBINTL_H
+#include <libintl.h> // For messages
#endif
+#include <cstdarg>
#ifdef __UCLIBC_MJN3_ONLY__
#warning what is _GLIBCXX_C_LOCALE_GNU for
+// psm: used in os/gnu-linux/ctype_noninline.h
#endif
#define _GLIBCXX_C_LOCALE_GNU 1
@@ -62,7 +64,7 @@
#endif
// #define _GLIBCXX_NUM_CATEGORIES 6
#define _GLIBCXX_NUM_CATEGORIES 0
-
+
#ifdef __UCLIBC_HAS_XLOCALE__
namespace __gnu_cxx
{
@@ -79,22 +81,24 @@
typedef int* __c_locale;
#endif
- // Convert numeric value of type _Tv to string and return length of
- // string. If snprintf is available use it, otherwise fall back to
- // the unsafe sprintf which, in general, can be dangerous and should
+ // Convert numeric value of type double to string and return length of
+ // string. If vsnprintf is available use it, otherwise fall back to
+ // the unsafe vsprintf which, in general, can be dangerous and should
// be avoided.
- template<typename _Tv>
- int
- __convert_from_v(char* __out,
- const int __size __attribute__ ((__unused__)),
- const char* __fmt,
-#ifdef __UCLIBC_HAS_XCLOCALE__
- _Tv __v, const __c_locale& __cloc, int __prec)
+ inline int
+ __convert_from_v(const __c_locale&
+#ifndef __UCLIBC_HAS_XCLOCALE__
+ __cloc __attribute__ ((__unused__))
+#endif
+ ,
+ char* __out,
+ const int __size,
+ const char* __fmt, ...)
{
+ va_list __args;
+#ifdef __UCLIBC_HAS_XCLOCALE__
__c_locale __old = __gnu_cxx::__uselocale(__cloc);
#else
- _Tv __v, const __c_locale&, int __prec)
- {
# ifdef __UCLIBC_HAS_LOCALE__
char* __old = std::setlocale(LC_ALL, NULL);
char* __sav = new char[std::strlen(__old) + 1];
@@ -103,7 +107,9 @@
# endif
#endif
- const int __ret = std::snprintf(__out, __size, __fmt, __prec, __v);
+ va_start(__args, __fmt);
+ const int __ret = std::vsnprintf(__out, __size, __fmt, __args);
+ va_end(__args);
#ifdef __UCLIBC_HAS_XCLOCALE__
__gnu_cxx::__uselocale(__old);

46
meta/packages/gcc/gcc-4.2.3/300-libstdc++-pic.patch vendored
View File

@ -1,46 +0,0 @@
# DP: Build and install libstdc++_pic.a library.
--- gcc-4.1.0/libstdc++-v3/src/Makefile.am 2004-11-15 17:33:05.000000000 -0600
+++ gcc-4.1.0-patched/libstdc++-v3/src/Makefile.am 2005-04-25 20:05:59.186930896 -0500
@@ -214,6 +214,10 @@
$(OPT_LDFLAGS) $(SECTION_LDFLAGS) $(AM_CXXFLAGS) $(LDFLAGS) -o $@
+install-exec-local:
+ $(AR) cru libstdc++_pic.a .libs/*.o $(top_builddir)/libsupc++/*.o
+ $(INSTALL_DATA) libstdc++_pic.a $(DESTDIR)$(toolexeclibdir)
+
# Added bits to build debug library.
if GLIBCXX_BUILD_DEBUG
all-local: build_debug
--- gcc-4.1.0/libstdc++-v3/src/Makefile.in 2005-04-11 19:13:08.000000000 -0500
+++ gcc-4.1.0-patched/libstdc++-v3/src/Makefile.in 2005-04-25 20:12:33.284316275 -0500
@@ -627,7 +627,7 @@
install-data-am: install-data-local
-install-exec-am: install-toolexeclibLTLIBRARIES
+install-exec-am: install-toolexeclibLTLIBRARIES install-exec-local
install-info: install-info-am
@@ -660,6 +660,7 @@
distclean-libtool distclean-tags distdir dvi dvi-am html \
html-am info info-am install install-am install-data \
install-data-am install-data-local install-exec \
+ install-exec-local \
install-exec-am install-info install-info-am install-man \
install-strip install-toolexeclibLTLIBRARIES installcheck \
installcheck-am installdirs maintainer-clean \
@@ -745,6 +746,11 @@
install_debug:
(cd ${debugdir} && $(MAKE) \
toolexeclibdir=$(glibcxx_toolexeclibdir)/debug install)
+
+install-exec-local:
+ $(AR) cru libstdc++_pic.a .libs/*.o $(top_builddir)/libsupc++/*.o
+ $(INSTALL_DATA) libstdc++_pic.a $(DESTDIR)$(toolexeclibdir)
+
# Tell versions [3.59,3.63) of GNU make to not export all variables.
# Otherwise a system limit (for SysV at least) may be exceeded.
.NOEXPORT:

11
meta/packages/gcc/gcc-4.2.3/301-missing-execinfo_h.patch vendored
View File

@ -1,11 +0,0 @@
--- gcc-4.0.0/boehm-gc/include/gc.h-orig 2005-04-28 22:28:57.000000000 -0500
+++ gcc-4.0.0/boehm-gc/include/gc.h 2005-04-28 22:30:38.000000000 -0500
@@ -500,7 +500,7 @@
#ifdef __linux__
# include <features.h>
# if (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 1 || __GLIBC__ > 2) \
- && !defined(__ia64__)
+ && !defined(__ia64__) && !defined(__UCLIBC__)
# ifndef GC_HAVE_BUILTIN_BACKTRACE
# define GC_HAVE_BUILTIN_BACKTRACE
# endif

11
meta/packages/gcc/gcc-4.2.3/302-c99-snprintf.patch vendored
View File

@ -1,11 +0,0 @@
--- gcc-4.0.0/libstdc++-v3/include/c_std/std_cstdio.h-orig 2005-04-29 00:08:41.000000000 -0500
+++ gcc-4.0.0/libstdc++-v3/include/c_std/std_cstdio.h 2005-04-29 00:08:45.000000000 -0500
@@ -142,7 +142,7 @@
using ::vsprintf;
}
-#if _GLIBCXX_USE_C99
+#if _GLIBCXX_USE_C99 || defined(__UCLIBC__)
#undef snprintf
#undef vfscanf

12
meta/packages/gcc/gcc-4.2.3/303-c99-complex-ugly-hack.patch vendored
View File

@ -1,12 +0,0 @@
--- gcc-4.0.0/libstdc++-v3/configure-old 2005-04-30 22:04:48.061603912 -0500
+++ gcc-4.0.0/libstdc++-v3/configure 2005-04-30 22:06:13.678588152 -0500
@@ -7194,6 +7194,9 @@
cat >>conftest.$ac_ext <<_ACEOF
/* end confdefs.h. */
#include <complex.h>
+#ifdef __UCLIBC__
+#error ugly hack to make sure configure test fails here for cross until uClibc supports the complex funcs
+#endif
int
main ()
{

24
meta/packages/gcc/gcc-4.2.3/304-index_macro.patch vendored
View File

@ -1,24 +0,0 @@
--- gcc-4.1.0/libstdc++-v3/include/ext/rope.mps 2006-03-24 01:49:51 +0100
+++ gcc-4.1.0/libstdc++-v3/include/ext/rope 2006-03-24 01:49:37 +0100
@@ -59,6 +59,9 @@
#include <bits/allocator.h>
#include <ext/hash_fun.h>
+/* cope w/ index defined as macro, SuSv3 proposal */
+#undef index
+
# ifdef __GC
# define __GC_CONST const
# else
--- gcc-4.1.0/libstdc++-v3/include/ext/ropeimpl.h.mps 2006-03-24 01:50:04 +0100
+++ gcc-4.1.0/libstdc++-v3/include/ext/ropeimpl.h 2006-03-24 01:50:28 +0100
@@ -53,6 +53,9 @@
#include <ext/memory> // For uninitialized_copy_n
#include <ext/numeric> // For power
+/* cope w/ index defined as macro, SuSv3 proposal */
+#undef index
+
_GLIBCXX_BEGIN_NAMESPACE(__gnu_cxx)
using std::size_t;

49
meta/packages/gcc/gcc-4.2.3/305-libmudflap-susv3-legacy.patch vendored
View File

@ -1,49 +0,0 @@
Index: gcc-4.2/libmudflap/mf-hooks2.c
===================================================================
--- gcc-4.2/libmudflap/mf-hooks2.c (revision 119834)
+++ gcc-4.2/libmudflap/mf-hooks2.c (working copy)
@@ -427,7 +427,7 @@
{
TRACE ("%s\n", __PRETTY_FUNCTION__);
MF_VALIDATE_EXTENT(s, n, __MF_CHECK_WRITE, "bzero region");
- bzero (s, n);
+ memset (s, 0, n);
}
@@ -437,7 +437,7 @@
TRACE ("%s\n", __PRETTY_FUNCTION__);
MF_VALIDATE_EXTENT(src, n, __MF_CHECK_READ, "bcopy src");
MF_VALIDATE_EXTENT(dest, n, __MF_CHECK_WRITE, "bcopy dest");
- bcopy (src, dest, n);
+ memmove (dest, src, n);
}
@@ -447,7 +447,7 @@
TRACE ("%s\n", __PRETTY_FUNCTION__);
MF_VALIDATE_EXTENT(s1, n, __MF_CHECK_READ, "bcmp 1st arg");
MF_VALIDATE_EXTENT(s2, n, __MF_CHECK_READ, "bcmp 2nd arg");
- return bcmp (s1, s2, n);
+ return n == 0 ? 0 : memcmp (s1, s2, n);
}
@@ -456,7 +456,7 @@
size_t n = strlen (s);
TRACE ("%s\n", __PRETTY_FUNCTION__);
MF_VALIDATE_EXTENT(s, CLAMPADD(n, 1), __MF_CHECK_READ, "index region");
- return index (s, c);
+ return strchr (s, c);
}
@@ -465,7 +465,7 @@
size_t n = strlen (s);
TRACE ("%s\n", __PRETTY_FUNCTION__);
MF_VALIDATE_EXTENT(s, CLAMPADD(n, 1), __MF_CHECK_READ, "rindex region");
- return rindex (s, c);
+ return strrchr (s, c);
}
/* XXX: stpcpy, memccpy */

36
meta/packages/gcc/gcc-4.2.3/306-libstdc++-namespace.patch vendored
View File

@ -1,36 +0,0 @@
diff -rup gcc-4.2.orig/libstdc++-v3/config/locale/uclibc/messages_members.h gcc-4.2/libstdc++-v3/config/locale/uclibc/messages_members.h
--- gcc-4.2.orig/libstdc++-v3/config/locale/uclibc/messages_members.h 2006-12-22 13:06:56.000000000 +0100
+++ gcc-4.2/libstdc++-v3/config/locale/uclibc/messages_members.h 2006-12-22 15:23:41.000000000 +0100
@@ -32,7 +32,8 @@
//
// Written by Benjamin Kosnik <bkoz@redhat.com>
-
+namespace std
+{
#ifdef __UCLIBC_MJN3_ONLY__
#warning fix prototypes for *textdomain funcs
#endif
@@ -115,3 +116,4 @@
this->_S_create_c_locale(this->_M_c_locale_messages, __s);
}
}
+}
diff -rup gcc-4.2.orig/libstdc++-v3/config/locale/uclibc/time_members.h gcc-4.2/libstdc++-v3/config/locale/uclibc/time_members.h
--- gcc-4.2.orig/libstdc++-v3/config/locale/uclibc/time_members.h 2006-12-22 13:06:56.000000000 +0100
+++ gcc-4.2/libstdc++-v3/config/locale/uclibc/time_members.h 2006-12-22 15:20:31.000000000 +0100
@@ -33,7 +33,8 @@
//
// Written by Benjamin Kosnik <bkoz@redhat.com>
-
+namespace std
+{
template<typename _CharT>
__timepunct<_CharT>::__timepunct(size_t __refs)
: facet(__refs), _M_data(NULL), _M_c_locale_timepunct(NULL),
@@ -74,3 +75,4 @@
delete _M_data;
_S_destroy_c_locale(_M_c_locale_timepunct);
}
+}

26
meta/packages/gcc/gcc-4.2.3/307-locale_facets.patch vendored
View File

@ -1,26 +0,0 @@
This patch fixes a bug into ostream::operator<<(double) due to the wrong size
passed into the __convert_from_v method. The wrong size is then passed to
std::snprintf function, that, on uClibc, doens't handle sized 0 buffer.
Signed-off-by: Carmelo Amoroso <carmelo.amoroso@st.com>
--- gcc-4.2.1/libstdc++-v3/include/bits/locale_facets.tcc 2006-10-17 18:43:47.000000000 +0200
+++ gcc-4.2.1-st/libstdc++-v3/include/bits/locale_facets.tcc 2007-08-22 18:54:23.000000000 +0200
@@ -1143,7 +1143,7 @@ _GLIBCXX_BEGIN_LDBL_NAMESPACE
const int __cs_size = __fixed ? __max_exp + __prec + 4
: __max_digits * 2 + __prec;
char* __cs = static_cast<char*>(__builtin_alloca(__cs_size));
- __len = std::__convert_from_v(_S_get_c_locale(), __cs, 0, __fbuf,
+ __len = std::__convert_from_v(_S_get_c_locale(), __cs, __cs_size, __fbuf,
__prec, __v);
#endif
@@ -1777,7 +1777,7 @@ _GLIBCXX_BEGIN_LDBL_NAMESPACE
// max_exponent10 + 1 for the integer part, + 2 for sign and '\0'.
const int __cs_size = numeric_limits<long double>::max_exponent10 + 3;
char* __cs = static_cast<char*>(__builtin_alloca(__cs_size));
- int __len = std::__convert_from_v(_S_get_c_locale(), __cs, 0, "%.*Lf",
+ int __len = std::__convert_from_v(_S_get_c_locale(), __cs, __cs_size, "%.*Lf",
0, __units);
#endif
string_type __digits(__len, char_type());

13
meta/packages/gcc/gcc-4.2.3/402-libbackend_dep_gcov-iov.h.patch vendored
View File

@ -1,13 +0,0 @@
Index: gcc-4.2/gcc/Makefile.in
===================================================================
--- gcc-4.2/gcc/Makefile.in (revision 121758)
+++ gcc-4.2/gcc/Makefile.in (working copy)
@@ -2658,7 +2658,7 @@ mips-tdump.o : mips-tdump.c $(CONFIG_H)
# FIXME: writing proper dependencies for this is a *LOT* of work.
libbackend.o : $(OBJS-common:.o=.c) $(out_file) \
insn-config.h insn-flags.h insn-codes.h insn-constants.h \
- insn-attr.h $(DATESTAMP) $(BASEVER) $(DEVPHASE)
+ insn-attr.h $(DATESTAMP) $(BASEVER) $(DEVPHASE) gcov-iov.h
$(CC) $(ALL_CFLAGS) $(ALL_CPPFLAGS) \
-DTARGET_NAME=\"$(target_noncanonical)\" \
-DLOCALEDIR=\"$(localedir)\" \

20
meta/packages/gcc/gcc-4.2.3/602-sdk-libstdc++-includes.patch vendored
View File

@ -1,20 +0,0 @@
--- gcc-4.1.0/libstdc++-v3/fragment.am 2005-03-21 11:40:14.000000000 -0600
+++ gcc-4.1.0-patched/libstdc++-v3/fragment.am 2005-04-25 20:14:39.856251785 -0500
@@ -21,5 +21,5 @@
$(WARN_FLAGS) $(WERROR) -fdiagnostics-show-location=once
# -I/-D flags to pass when compiling.
-AM_CPPFLAGS = $(GLIBCXX_INCLUDES)
+AM_CPPFLAGS = $(GLIBCXX_INCLUDES) -I$(toplevel_srcdir)/include
--- gcc-4.1.0/libstdc++-v3/libmath/Makefile.am 2005-03-21 11:40:18.000000000 -0600
+++ gcc-4.1.0-patched/libstdc++-v3/libmath/Makefile.am 2005-04-25 20:14:39.682280735 -0500
@@ -35,7 +35,7 @@
libmath_la_SOURCES = stubs.c
-AM_CPPFLAGS = $(CANADIAN_INCLUDES)
+AM_CPPFLAGS = $(CANADIAN_INCLUDES) -I$(toplevel_srcdir)/include
# Only compiling "C" sources in this directory.
LIBTOOL = @LIBTOOL@ --tag CC

25
meta/packages/gcc/gcc-4.2.3/740-sh-pr24836.patch vendored
View File

@ -1,25 +0,0 @@
http://sourceforge.net/mailarchive/forum.php?thread_id=8959304&forum_id=5348
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=24836
--- gcc/gcc/configure.ac (revision 106699)
+++ gcc/gcc/configure.ac (working copy)
@@ -2446,7 +2446,7 @@
tls_first_minor=14
tls_as_opt="-m64 -Aesame --fatal-warnings"
;;
- sh-*-* | sh[34]-*-*)
+ sh-*-* | sh[34]*-*-*)
conftest_s='
.section ".tdata","awT",@progbits
foo: .long 25
--- gcc/gcc/configure
+++ gcc/gcc/configure
@@ -14846,7 +14846,7 @@
tls_first_minor=14
tls_as_opt="-m64 -Aesame --fatal-warnings"
;;
- sh-*-* | sh[34]-*-*)
+ sh-*-* | sh[34]*-*-*)
conftest_s='
.section ".tdata","awT",@progbits
foo: .long 25

67
meta/packages/gcc/gcc-4.2.3/800-arm-bigendian.patch vendored
View File

@ -1,67 +0,0 @@
By Lennert Buytenhek <buytenh@wantstofly.org>
Adds support for arm*b-linux* big-endian ARM targets
See http://gcc.gnu.org/PR16350
--- gcc-4.2.0/gcc/config/arm/linux-elf.h
+++ gcc-4.2.0/gcc/config/arm/linux-elf.h
@@ -28,19 +28,33 @@
#undef TARGET_VERSION
#define TARGET_VERSION fputs (" (ARM GNU/Linux with ELF)", stderr);
+/*
+ * 'config.gcc' defines TARGET_BIG_ENDIAN_DEFAULT as 1 for arm*b-*
+ * (big endian) configurations.
+ */
+#if TARGET_BIG_ENDIAN_DEFAULT
+#define TARGET_ENDIAN_DEFAULT MASK_BIG_END
+#define TARGET_ENDIAN_OPTION "mbig-endian"
+#define TARGET_LINKER_EMULATION "armelfb_linux"
+#else
+#define TARGET_ENDIAN_DEFAULT 0
+#define TARGET_ENDIAN_OPTION "mlittle-endian"
+#define TARGET_LINKER_EMULATION "armelf_linux"
+#endif
+
#undef TARGET_DEFAULT_FLOAT_ABI
#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_HARD
#undef TARGET_DEFAULT
-#define TARGET_DEFAULT (0)
+#define TARGET_DEFAULT (TARGET_ENDIAN_DEFAULT)
#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm6
-#define SUBTARGET_EXTRA_LINK_SPEC " -m armelf_linux -p"
+#define SUBTARGET_EXTRA_LINK_SPEC " -m " TARGET_LINKER_EMULATION " -p"
#undef MULTILIB_DEFAULTS
#define MULTILIB_DEFAULTS \
- { "marm", "mlittle-endian", "mhard-float", "mno-thumb-interwork" }
+ { "marm", TARGET_ENDIAN_OPTION, "mhard-float", "mno-thumb-interwork" }
/* Now we define the strings used to build the spec file. */
#undef LIB_SPEC
@@ -61,7 +75,7 @@
%{rdynamic:-export-dynamic} \
%{!dynamic-linker:-dynamic-linker " LINUX_DYNAMIC_LINKER "} \
-X \
- %{mbig-endian:-EB}" \
+ %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
SUBTARGET_EXTRA_LINK_SPEC
#undef LINK_SPEC
--- gcc-4.2.0/gcc/config.gcc.orig 2006-09-22 14:53:41.000000000 +0200
+++ gcc-4.2.0/gcc/config.gcc 2006-09-25 10:45:21.000000000 +0200
@@ -696,6 +696,11 @@
tm_file="dbxelf.h elfos.h linux.h arm/elf.h arm/linux-gas.h arm/linux-elf.h"
tmake_file="${tmake_file} t-linux arm/t-arm"
case ${target} in
+ arm*b-*)
+ tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
+ ;;
+ esac
+ case ${target} in
arm*-*-linux-*eabi)
tm_file="$tm_file arm/bpabi.h arm/linux-eabi.h"
tmake_file="$tmake_file arm/t-arm-elf arm/t-bpabi arm/t-linux-eabi"

14
meta/packages/gcc/gcc-4.2.3/801-arm-bigendian-eabi.patch vendored
View File

@ -1,14 +0,0 @@
Index: gcc-4.1.1/gcc/config/arm/linux-eabi.h
===================================================================
--- gcc-4.1.1.orig/gcc/config/arm/linux-eabi.h 2007-02-20 14:51:33.416193250 +0100
+++ gcc-4.1.1/gcc/config/arm/linux-eabi.h 2007-02-20 14:52:11.622581000 +0100
@@ -48,7 +48,8 @@
#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm9tdmi
#undef SUBTARGET_EXTRA_LINK_SPEC
-#define SUBTARGET_EXTRA_LINK_SPEC " -m armelf_linux_eabi"
+#define SUBTARGET_EXTRA_LINK_SPEC \
+ " %{mbig-endian:-m armelfb_linux_eabi} %{mlittle-endian:-m armelf_linux_eabi} "
/* Use ld-linux.so.3 so that it will be possible to run "classic"
GNU/Linux binaries on an EABI system. */

153
meta/packages/gcc/gcc-4.2.3/904-flatten-switch-stmt-00.patch vendored
View File

@ -1,153 +0,0 @@
Hi,
The attached patch makes sure that we create smaller object code for
simple switch statements. We just make sure to flatten the switch
statement into an if-else chain, basically.
This fixes a size-regression as compared to gcc-3.4, as can be seen
below.
2007-04-15 Bernhard Fischer <..>
* stmt.c (expand_case): Do not create a complex binary tree when
optimizing for size but rather use the simple ordered list.
(emit_case_nodes): do not emit jumps to the default_label when
optimizing for size.
Not regtested so far.
Comments?
Attached is the test switch.c mentioned below.
$ for i in 2.95 3.3 3.4 4.0 4.1 4.2.orig-HEAD 4.3.orig-HEAD 4.3-HEAD;do
gcc-$i -DCHAIN -Os -o switch-CHAIN-$i.o -c switch.c ;done
$ for i in 2.95 3.3 3.4 4.0 4.1 4.2.orig-HEAD 4.3.orig-HEAD 4.3-HEAD;do
gcc-$i -UCHAIN -Os -o switch-$i.o -c switch.c ;done
$ size switch-*.o
text data bss dec hex filename
169 0 0 169 a9 switch-2.95.o
115 0 0 115 73 switch-3.3.o
103 0 0 103 67 switch-3.4.o
124 0 0 124 7c switch-4.0.o
124 0 0 124 7c switch-4.1.o
124 0 0 124 7c switch-4.2.orig-HEAD.o
95 0 0 95 5f switch-4.3-HEAD.o
124 0 0 124 7c switch-4.3.orig-HEAD.o
166 0 0 166 a6 switch-CHAIN-2.95.o
111 0 0 111 6f switch-CHAIN-3.3.o
95 0 0 95 5f switch-CHAIN-3.4.o
95 0 0 95 5f switch-CHAIN-4.0.o
95 0 0 95 5f switch-CHAIN-4.1.o
95 0 0 95 5f switch-CHAIN-4.2.orig-HEAD.o
95 0 0 95 5f switch-CHAIN-4.3-HEAD.o
95 0 0 95 5f switch-CHAIN-4.3.orig-HEAD.o
Content-Type: text/x-diff; charset=us-ascii
Content-Disposition: attachment; filename="gcc-4.3.gcc-flatten-switch-stmt.00.diff"
Index: gcc-4.2.0/gcc/stmt.c
===================================================================
--- gcc-4.2.0.orig/gcc/stmt.c (revision 123843)
+++ gcc-4.2.0/gcc/stmt.c (working copy)
@@ -2517,7 +2517,11 @@ expand_case (tree exp)
use_cost_table
= (TREE_CODE (orig_type) != ENUMERAL_TYPE
&& estimate_case_costs (case_list));
- balance_case_nodes (&case_list, NULL);
+ /* When optimizing for size, we want a straight list to avoid
+ jumps as much as possible. This basically creates an if-else
+ chain. */
+ if (!optimize_size)
+ balance_case_nodes (&case_list, NULL);
emit_case_nodes (index, case_list, default_label, index_type);
emit_jump (default_label);
}
@@ -3075,6 +3079,7 @@ emit_case_nodes (rtx index, case_node_pt
{
if (!node_has_low_bound (node, index_type))
{
+ if (!optimize_size) /* don't jl to the .default_label. */
emit_cmp_and_jump_insns (index,
convert_modes
(mode, imode,
Content-Type: text/x-csrc; charset=us-ascii
Content-Disposition: attachment; filename="switch.c"
int
commutative_tree_code (int code)
{
#define CASE(val, ret) case val:/* __asm__("# val="#val ",ret="#ret);*/ return ret;
#ifndef CHAIN
switch (code)
{
# if 1
CASE(1,3)
CASE(3,2)
CASE(5,8)
CASE(7,1)
CASE(33,4)
CASE(44,9)
CASE(55,10)
CASE(66,-1)
CASE(77,99)
CASE(666,0)
# else
case 1:
return 3;
case 3:
return 2;
case 5:
return 8;
case 7:
return 1;
case 33:
return 4;
case 44:
return 9;
case 55:
return 10;
case 66:
return -1;
case 77:
return 99;
case 666:
return 0;
# endif
default:
break;
}
return 4711;
#else
if (code == 1)
return 3;
else if (code == 3)
return 2;
else if (code == 5)
return 8;
else if (code == 7)
return 1;
else if (code == 33)
return 4;
else if (code == 44)
return 9;
else if (code == 55)
return 10;
else if (code == 66)
return -1;
else if (code == 77)
return 99;
else if (code == 666)
return 0;
else
return 4711;
#endif
}
--AhhlLboLdkugWU4S--

4
meta/packages/gcc/gcc-4.2.3/README vendored
View File

@ -1,4 +0,0 @@
The numbered patches come from
http://www.uclibc.org/cgi-bin/viewcvs.cgi/trunk/buildroot/toolchain/gcc/4.1.1/
Other patches are locally added to fix things (mostly inherited and reapplied
from gcc 3.4.4 where applicable)

11
meta/packages/gcc/gcc-4.2.3/arm-crunch-20000320.patch vendored
View File

@ -1,11 +0,0 @@
--- gcc-4.1.2/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c.original 2007-06-07 16:33:44.000000000 +1000
+++ gcc-4.1.2/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c 2007-06-07 16:34:05.000000000 +1000
@@ -49,7 +49,7 @@
exit (0);
c(0x3690000000000000ULL, 0x00000000U);
-#if (defined __arm__ || defined __thumb__) && ! (defined __ARMEB__ || defined __VFP_FP__)
+#if (defined __arm__ || defined __thumb__) && ! (defined __ARMEB__ || defined __VFP_FP__) && ! (defined __MAVERICK__)
/* The ARM always stores FP numbers in big-wordian format,
even when running in little-byteian mode. */
c(0x0000000136900000ULL, 0x00000001U);

85
meta/packages/gcc/gcc-4.2.3/arm-crunch-32bit-disable.patch vendored
View File

@ -1,85 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/cirrus.md-integer 2007-06-15 09:01:37.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-15 09:04:45.000000000 +1000
@@ -149,7 +149,7 @@
(match_operand:SI 1 "cirrus_fp_register" "0")
(mult:SI (match_operand:SI 2 "cirrus_fp_register" "v")
(match_operand:SI 3 "cirrus_fp_register" "v"))))]
- "0 && TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "0 && TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfmsc32%?\\t%V0, %V2, %V3"
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "normal")]
@@ -305,7 +305,7 @@
[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
(float:SF (match_operand:SI 1 "s_register_operand" "r")))
(clobber (match_scratch:DF 2 "=v"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2"
[(set_attr "length" "8")
(set_attr "cirrus" "move")]
@@ -315,7 +315,7 @@
[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
(float:DF (match_operand:SI 1 "s_register_operand" "r")))
(clobber (match_scratch:DF 2 "=v"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2"
[(set_attr "length" "8")
(set_attr "cirrus" "move")]
@@ -339,7 +339,7 @@
[(set (match_operand:SI 0 "s_register_operand" "=r")
(fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v"))))
(clobber (match_scratch:DF 2 "=v"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
[(set_attr "length" "8")
(set_attr "cirrus" "normal")]
@@ -349,7 +349,7 @@
[(set (match_operand:SI 0 "s_register_operand" "=r")
(fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register" "v"))))
(clobber (match_scratch:DF 2 "=v"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
[(set_attr "length" "8")
(set_attr "cirrus" "normal")]
--- gcc-4.1.2/gcc/config/arm/arm.md-trunc 2007-06-15 10:56:13.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-15 11:01:22.000000000 +1000
@@ -3130,7 +3130,7 @@
(float:SF (match_operand:SI 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"
- if (TARGET_MAVERICK)
+ if (TARGET_MAVERICK && 0)
{
emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1]));
DONE;
@@ -3142,7 +3142,7 @@
(float:DF (match_operand:SI 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"
- if (TARGET_MAVERICK)
+ if (TARGET_MAVERICK && 0)
{
emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1]));
DONE;
@@ -3154,7 +3154,7 @@
(fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"
- if (TARGET_MAVERICK)
+ if (TARGET_MAVERICK && 0)
{
if (!cirrus_fp_register (operands[0], SImode))
operands[0] = force_reg (SImode, operands[0]);
@@ -3170,7 +3170,7 @@
(fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"
- if (TARGET_MAVERICK)
+ if (TARGET_MAVERICK && 0)
{
if (!cirrus_fp_register (operands[1], DFmode))
operands[1] = force_reg (DFmode, operands[0]);

169
meta/packages/gcc/gcc-4.2.3/arm-crunch-64bit-disable-4.2.0.patch vendored
View File

@ -1,169 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/cirrus.md-integer 2007-06-15 09:01:37.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-15 09:04:45.000000000 +1000
@@ -34,7 +34,7 @@
[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
(plus:DI (match_operand:DI 1 "cirrus_fp_register" "v")
(match_operand:DI 2 "cirrus_fp_register" "v")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfadd64%?\\t%V0, %V1, %V2"
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "normal")]
@@ -74,7 +74,7 @@
[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
(minus:DI (match_operand:DI 1 "cirrus_fp_register" "v")
(match_operand:DI 2 "cirrus_fp_register" "v")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfsub64%?\\t%V0, %V1, %V2"
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "normal")]
@@ -124,7 +124,7 @@
[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
(mult:DI (match_operand:DI 2 "cirrus_fp_register" "v")
(match_operand:DI 1 "cirrus_fp_register" "v")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfmul64%?\\t%V0, %V1, %V2"
[(set_attr "type" "mav_dmult")
(set_attr "cirrus" "normal")]
@@ -206,7 +206,7 @@
[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
(ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v")
(match_operand:SI 2 "register_operand" "r")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfrshl64%?\\t%V1, %V0, %s2"
[(set_attr "cirrus" "normal")]
)
@@ -215,7 +215,7 @@
[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
(ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v")
(match_operand:SI 2 "cirrus_shift_const" "")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfsh64%?\\t%V0, %V1, #%s2"
[(set_attr "cirrus" "normal")]
)
@@ -224,7 +224,7 @@
[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
(ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register" "v")
(match_operand:SI 2 "cirrus_shift_const" "")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfsh64%?\\t%V0, %V1, #-%s2"
[(set_attr "cirrus" "normal")]
)
@@ -232,7 +232,7 @@
(define_insn "*cirrus_absdi2"
[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
(abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfabs64%?\\t%V0, %V1"
[(set_attr "cirrus" "normal")]
)
@@ -238,11 +238,12 @@
)
;; This doesn't really clobber ``cc''. Fixme: aldyh.
+;; maybe buggy?
(define_insn "*cirrus_negdi2"
[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
(neg:DI (match_operand:DI 1 "cirrus_fp_register" "v")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfneg64%?\\t%V0, %V1"
[(set_attr "cirrus" "normal")]
)
@@ -324,14 +324,14 @@
(define_insn "floatdisf2"
[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
(float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfcvt64s%?\\t%V0, %V1"
[(set_attr "cirrus" "normal")])
(define_insn "floatdidf2"
[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
(float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfcvt64d%?\\t%V0, %V1"
[(set_attr "cirrus" "normal")])
@@ -376,7 +376,7 @@
(define_insn "*cirrus_arm_movdi"
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v")
(match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"*
{
switch (which_alternative)
--- gcc-4.1.2/gcc/config/arm/arm.md-64 2007-06-15 11:37:42.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-15 11:40:45.000000000 +1000
@@ -357,7 +357,7 @@
(clobber (reg:CC CC_REGNUM))])]
"TARGET_EITHER"
"
- if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
+ if (TARGET_HARD_FLOAT && TARGET_MAVERICK && 0)
{
if (!cirrus_fp_register (operands[0], DImode))
operands[0] = force_reg (DImode, operands[0]);
@@ -393,7 +393,7 @@
(plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0")
(match_operand:DI 2 "s_register_operand" "r, 0")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
+ "TARGET_ARM"
"#"
"TARGET_ARM && reload_completed"
[(parallel [(set (reg:CC_C CC_REGNUM)
@@ -421,7 +421,7 @@
(match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:DI 1 "s_register_operand" "r,0")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
+ "TARGET_ARM"
"#"
"TARGET_ARM && reload_completed"
[(parallel [(set (reg:CC_C CC_REGNUM)
@@ -450,7 +450,7 @@
(match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:DI 1 "s_register_operand" "r,0")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
+ "TARGET_ARM"
"#"
"TARGET_ARM && reload_completed"
[(parallel [(set (reg:CC_C CC_REGNUM)
@@ -838,7 +838,7 @@
if (TARGET_HARD_FLOAT && TARGET_MAVERICK
&& TARGET_ARM
&& cirrus_fp_register (operands[0], DImode)
- && cirrus_fp_register (operands[1], DImode))
+ && cirrus_fp_register (operands[1], DImode) && 0)
{
emit_insn (gen_cirrus_subdi3 (operands[0], operands[1], operands[2]));
DONE;
@@ -2599,7 +2599,7 @@
values to iwmmxt regs and back. */
FAIL;
}
- else if (!TARGET_REALLY_IWMMXT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK))
+ else if (!TARGET_REALLY_IWMMXT)
FAIL;
"
)
@@ -4215,7 +4215,6 @@
[(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,l,>,l, m,*r")
(match_operand:DI 1 "general_operand" "l, I,J,>,l,mi,l,*r"))]
"TARGET_THUMB
- && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)
&& ( register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))"
"*

47
meta/packages/gcc/gcc-4.2.3/arm-crunch-64bit-disable0.patch vendored
View File

@ -1,47 +0,0 @@
diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.md gcc-4.1.2/gcc/config/arm/arm.md
--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.md 2006-09-28 03:10:22.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-15 09:53:21.000000000 +1000
@@ -6865,10 +6877,12 @@
)
;; Cirrus DI compare instruction
+;; This is disabled and left go through ARM core registers, because currently
+;; Crunch coprocessor does only signed comparison.
(define_expand "cmpdi"
[(match_operand:DI 0 "cirrus_fp_register" "")
(match_operand:DI 1 "cirrus_fp_register" "")]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0"
"{
arm_compare_op0 = operands[0];
arm_compare_op1 = operands[1];
@@ -6879,7 +6893,7 @@
[(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:DI 0 "cirrus_fp_register" "v")
(match_operand:DI 1 "cirrus_fp_register" "v")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0"
"cfcmp64%?\\tr15, %V0, %V1"
[(set_attr "type" "mav_farith")
(set_attr "cirrus" "compare")]
@@ -10105,6 +10119,7 @@
[(unspec:SI [(match_operand:SI 0 "register_operand" "")] UNSPEC_PROLOGUE_USE)]
""
"%@ %0 needed for prologue"
+ [(set_attr "length" "0")]
)
diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/cirrus.md gcc-4.1.2/gcc/config/arm/cirrus.md
--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/cirrus.md 2005-06-25 11:22:41.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-05-15 09:55:29.000000000 +1000
@@ -348,7 +348,8 @@
(clobber (match_scratch:DF 2 "=v"))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
"cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
- [(set_attr "length" "8")]
+ [(set_attr "length" "8")
+ (set_attr "cirrus" "normal")]
)
(define_insn "*cirrus_truncdfsf2"

67
meta/packages/gcc/gcc-4.2.3/arm-crunch-and-or.patch vendored
View File

@ -1,67 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-13 17:16:38.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-13 17:35:19.000000000 +1000
@@ -8455,7 +8455,7 @@
(and:SI (match_operator:SI 1 "arm_comparison_operator"
[(match_operand 3 "cc_register" "") (const_int 0)])
(match_operand:SI 2 "s_register_operand" "r")))]
- "TARGET_ARM"
+ "TARGET_ARM && !TARGET_MAVERICK"
"mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1"
[(set_attr "conds" "use")
(set_attr "length" "8")]
@@ -8466,7 +8466,7 @@
(ior:SI (match_operator:SI 2 "arm_comparison_operator"
[(match_operand 3 "cc_register" "") (const_int 0)])
(match_operand:SI 1 "s_register_operand" "0,?r")))]
- "TARGET_ARM"
+ "TARGET_ARM && !TARGET_MAVERICK"
"@
orr%d2\\t%0, %1, #1
mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1"
@@ -8734,7 +8734,8 @@
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM
&& (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_OR_Y)
- != CCmode)"
+ != CCmode)
+ && !TARGET_MAVERICK"
"#"
"TARGET_ARM && reload_completed"
[(set (match_dup 7)
@@ -8765,7 +8766,7 @@
(set (match_operand:SI 7 "s_register_operand" "=r")
(ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
(match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
- "TARGET_ARM"
+ "TARGET_ARM && !TARGET_MAVERICK"
"#"
"TARGET_ARM && reload_completed"
[(set (match_dup 0)
@@ -8790,7 +8791,8 @@
(clobber (reg:CC CC_REGNUM))]
"TARGET_ARM
&& (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
- != CCmode)"
+ != CCmode)
+ && !TARGET_MAVERICK"
"#"
"TARGET_ARM && reload_completed
&& (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
@@ -8823,7 +8825,7 @@
(set (match_operand:SI 7 "s_register_operand" "=r")
(and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
(match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
- "TARGET_ARM"
+ "TARGET_ARM && !TARGET_MAVERICK"
"#"
"TARGET_ARM && reload_completed"
[(set (match_dup 0)
@@ -8850,7 +8852,7 @@
[(match_operand:SI 4 "s_register_operand" "r,r,r")
(match_operand:SI 5 "arm_add_operand" "rIL,rIL,rIL")])))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_ARM
+ "TARGET_ARM && !TARGET_MAVERICK
&& (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
== CCmode)"
"#"

19
meta/packages/gcc/gcc-4.2.3/arm-crunch-cfcvt64-disable.patch vendored
View File

@ -1,19 +0,0 @@
--- gcc-4.2.0/gcc/config/arm/cirrus.md-original 2007-06-25 15:32:01.000000000 +1000
+++ gcc-4.2.0/gcc/config/arm/cirrus.md 2007-06-25 15:32:14.000000000 +1000
@@ -325,14 +325,14 @@
(define_insn "floatdisf2"
[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
(float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfcvt64s%?\\t%V0, %V1"
[(set_attr "cirrus" "normal")])
(define_insn "floatdidf2"
[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
(float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfcvt64d%?\\t%V0, %V1"
[(set_attr "cirrus" "normal")])

32
meta/packages/gcc/gcc-4.2.3/arm-crunch-cfcvtds-disable.patch vendored
View File

@ -1,32 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-15 10:06:24.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-15 10:07:21.000000000 +1000
@@ -355,11 +355,12 @@
(set_attr "cirrus" "normal")]
)
+; appears to be buggy - causes 20000320-1.c to fail in execute/ieee
(define_insn "*cirrus_truncdfsf2"
[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
(float_truncate:SF
(match_operand:DF 1 "cirrus_fp_register" "v")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfcvtds%?\\t%V0, %V1"
[(set_attr "cirrus" "normal")]
)
--- gcc-4.1.2/gcc/config/arm/arm.md-truncdfsf2 2007-06-15 10:25:43.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-15 10:27:01.000000000 +1000
@@ -3181,11 +3181,12 @@
;; Truncation insns
+;; Maverick Crunch truncdfsf2 is buggy - see cirrus.md
(define_expand "truncdfsf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(float_truncate:SF
(match_operand:DF 1 "s_register_operand" "")))]
- "TARGET_ARM && TARGET_HARD_FLOAT"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
""
)

573
meta/packages/gcc/gcc-4.2.3/arm-crunch-cirrus-bugfixes.patch vendored
View File

@ -1,573 +0,0 @@
diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c gcc-4.1.2/gcc/config/arm/arm.c
--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c 2007-05-09 16:32:29.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-15 09:39:41.000000000 +1000
@@ -4,6 +4,7 @@
Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
and Martin Simmons (@harleqn.co.uk).
More major hacks by Richard Earnshaw (rearnsha@arm.com).
+ Cirrus Crunch bugfixes by Vladimir Ivanov (vladit@nucleusys.com)
This file is part of GCC.
@@ -131,9 +132,17 @@
static bool arm_xscale_rtx_costs (rtx, int, int, int *);
static bool arm_9e_rtx_costs (rtx, int, int, int *);
static int arm_address_cost (rtx);
-static bool arm_memory_load_p (rtx);
+// static bool arm_memory_load_p (rtx);
static bool arm_cirrus_insn_p (rtx);
-static void cirrus_reorg (rtx);
+// static void cirrus_reorg (rtx);
+static bool arm_mem_access_p (rtx);
+static bool cirrus_dest_regn_p (rtx, int);
+static rtx cirrus_prev_next_mach_insn (rtx, int *, int);
+static rtx cirrus_prev_mach_insn (rtx, int *);
+static rtx cirrus_next_mach_insn (rtx, int *);
+static void cirrus_reorg_branch (rtx);
+static void cirrus_reorg_bug1 (rtx);
+static void cirrus_reorg_bug10_12 (rtx);
static void arm_init_builtins (void);
static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
static void arm_init_iwmmxt_builtins (void);
@@ -5399,41 +5412,6 @@
|| TREE_CODE (valtype) == COMPLEX_TYPE));
}
-/* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
- Use by the Cirrus Maverick code which has to workaround
- a hardware bug triggered by such instructions. */
-static bool
-arm_memory_load_p (rtx insn)
-{
- rtx body, lhs, rhs;;
-
- if (insn == NULL_RTX || GET_CODE (insn) != INSN)
- return false;
-
- body = PATTERN (insn);
-
- if (GET_CODE (body) != SET)
- return false;
-
- lhs = XEXP (body, 0);
- rhs = XEXP (body, 1);
-
- lhs = REG_OR_SUBREG_RTX (lhs);
-
- /* If the destination is not a general purpose
- register we do not have to worry. */
- if (GET_CODE (lhs) != REG
- || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
- return false;
-
- /* As well as loads from memory we also have to react
- to loads of invalid constants which will be turned
- into loads from the minipool. */
- return (GET_CODE (rhs) == MEM
- || GET_CODE (rhs) == SYMBOL_REF
- || note_invalid_constants (insn, -1, false));
-}
-
/* Return TRUE if INSN is a Cirrus instruction. */
static bool
arm_cirrus_insn_p (rtx insn)
@@ -5452,124 +5433,218 @@
return attr != CIRRUS_NOT;
}
-/* Cirrus reorg for invalid instruction combinations. */
-static void
-cirrus_reorg (rtx first)
+/* Return TRUE if ISN does memory access. */
+static bool
+arm_mem_access_p (rtx insn)
{
- enum attr_cirrus attr;
- rtx body = PATTERN (first);
- rtx t;
- int nops;
+ enum attr_type attr;
- /* Any branch must be followed by 2 non Cirrus instructions. */
- if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
- {
- nops = 0;
- t = next_nonnote_insn (first);
+ /* get_attr aborts on USE and CLOBBER. */
+ if (!insn
+ || GET_CODE (insn) != INSN
+ || GET_CODE (PATTERN (insn)) == USE
+ || GET_CODE (PATTERN (insn)) == CLOBBER)
+ return 0;
- if (arm_cirrus_insn_p (t))
- ++ nops;
+ attr = get_attr_type (insn);
- if (arm_cirrus_insn_p (next_nonnote_insn (t)))
- ++ nops;
+ return attr == TYPE_LOAD_BYTE
+ || attr == TYPE_LOAD1 || attr == TYPE_LOAD2 || attr == TYPE_LOAD3 || attr == TYPE_LOAD4
+ || attr == TYPE_F_CVT
+ || attr == TYPE_F_MEM_R || attr == TYPE_R_MEM_F || attr == TYPE_F_2_R || attr == TYPE_R_2_F
+ || attr == TYPE_F_LOAD || attr == TYPE_F_LOADS || attr == TYPE_F_LOADD
+ || attr == TYPE_F_STORE || attr == TYPE_F_STORES || attr == TYPE_F_STORED
+ || attr == TYPE_STORE1 || attr == TYPE_STORE2 || attr == TYPE_STORE3 || attr == TYPE_STORE4;
+
+}
- while (nops --)
- emit_insn_after (gen_nop (), first);
+/* Return TRUE if destination is certain Cirrus register. */
+static bool
+cirrus_dest_regn_p (rtx body, int regn)
+{
+ rtx lhs;
+ int reg;
+ lhs = XEXP (body, 0);
+ if (GET_CODE (lhs) != REG)
+ return 0;
- return;
- }
+ reg = REGNO (lhs);
+ if (REGNO_REG_CLASS (reg) != CIRRUS_REGS)
+ return 0;
- /* (float (blah)) is in parallel with a clobber. */
- if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
- body = XVECEXP (body, 0, 0);
+ return reg == regn;
+}
+
+/* Get previous/next machine instruction during Cirrus workaround scans.
+ Assume worst case (for the purpose of Cirrus workarounds)
+ for JUMP / CALL instructions. */
+static rtx
+cirrus_prev_next_mach_insn (rtx insn, int *len, int next)
+{
+ rtx t;
+ int l = 0;
- if (GET_CODE (body) == SET)
+ /* It seems that we can count only on INSN length. */
+ for ( ; ; )
{
- rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
+ if (next)
+ insn = NEXT_INSN (insn);
+ else
+ insn = PREV_INSN (insn);
+ if (!insn)
+ break;
- /* cfldrd, cfldr64, cfstrd, cfstr64 must
- be followed by a non Cirrus insn. */
- if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
- {
- if (arm_cirrus_insn_p (next_nonnote_insn (first)))
- emit_insn_after (gen_nop (), first);
+ if (GET_CODE (insn) == INSN)
+ {
+ l = get_attr_length (insn) / 4;
+ if (l)
+ break;
+ }
+ else if (GET_CODE (insn) == JUMP_INSN)
+ {
+ l = 1;
+ t = is_jump_table (insn);
+ if (t)
+ l += get_jump_table_size (t) / 4;
+ break;
+ }
+ else if (GET_CODE (insn) == CALL_INSN)
+ {
+ l = 1;
+ break;
+ }
+ }
- return;
- }
- else if (arm_memory_load_p (first))
- {
- unsigned int arm_regno;
+ if (len)
+ *len = l;
- /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
- ldr/cfmv64hr combination where the Rd field is the same
- in both instructions must be split with a non Cirrus
- insn. Example:
-
- ldr r0, blah
- nop
- cfmvsr mvf0, r0. */
-
- /* Get Arm register number for ldr insn. */
- if (GET_CODE (lhs) == REG)
- arm_regno = REGNO (lhs);
- else
- {
- gcc_assert (GET_CODE (rhs) == REG);
- arm_regno = REGNO (rhs);
- }
+ return insn;
+}
- /* Next insn. */
- first = next_nonnote_insn (first);
+static rtx
+cirrus_prev_mach_insn (rtx insn, int *len)
+{
+ return cirrus_prev_next_mach_insn (insn, len, 0);
+}
- if (! arm_cirrus_insn_p (first))
- return;
+static rtx
+cirrus_next_mach_insn (rtx insn, int *len)
+{
+ return cirrus_prev_next_mach_insn (insn, len, 1);
+}
- body = PATTERN (first);
+/* Cirrus reorg for branch slots. */
+static void
+cirrus_reorg_branch (rtx insn)
+{
+ rtx t;
+ int nops, l;
- /* (float (blah)) is in parallel with a clobber. */
- if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
- body = XVECEXP (body, 0, 0);
-
- if (GET_CODE (body) == FLOAT)
- body = XEXP (body, 0);
-
- if (get_attr_cirrus (first) == CIRRUS_MOVE
- && GET_CODE (XEXP (body, 1)) == REG
- && arm_regno == REGNO (XEXP (body, 1)))
- emit_insn_after (gen_nop (), first);
+ /* TODO: handle jump-tables. */
+ t = is_jump_table (insn);
+ if (t)
+ return;
+
+ /* Any branch must be followed by 2 non Cirrus instructions. */
+ t = insn;
+ for (nops = 2; nops > 0; )
+ {
+ if (!cirrus_next_mach_insn (t, 0))
+ {
+ insn = t;
+ break;
+ }
+ t = cirrus_next_mach_insn (t, &l);
+ if (arm_cirrus_insn_p (t))
+ break;
+ nops -= l;
- return;
- }
}
- /* get_attr cannot accept USE or CLOBBER. */
- if (!first
- || GET_CODE (first) != INSN
- || GET_CODE (PATTERN (first)) == USE
- || GET_CODE (PATTERN (first)) == CLOBBER)
- return;
+ while (nops-- > 0)
+ emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */
+}
- attr = get_attr_cirrus (first);
+/* Cirrus reorg for bug #1 (cirrus + cfcmpxx). */
+static void
+cirrus_reorg_bug1 (rtx insn)
+{
+ rtx body = PATTERN (insn), body2;
+ rtx t;
+ int i, nops, l;
+ enum attr_cirrus attr;
- /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
- must be followed by a non-coprocessor instruction. */
- if (attr == CIRRUS_COMPARE)
+ /* Check if destination or clobber is Cirrus register. */
+ if (GET_CODE (body) == PARALLEL)
{
- nops = 0;
-
- t = next_nonnote_insn (first);
+ for (i = 0; i < XVECLEN (body, 0); i++)
+ {
+ body2 = XVECEXP (body, 0, i);
+ if (GET_CODE (body2) == SET)
+ {
+ if (cirrus_dest_regn_p (body2, LAST_CIRRUS_FP_REGNUM))
+ {
+ nops = 5;
+ goto fix;
+ }
+ }
+ else if (GET_CODE (body2) == CLOBBER)
+ {
+ if (cirrus_dest_regn_p (body2, LAST_CIRRUS_FP_REGNUM))
+ {
+ nops = 4;
+ goto fix;
+ }
+ }
+ }
+ }
+ else if (GET_CODE (body) == SET)
+ {
+ if (cirrus_dest_regn_p (body, LAST_CIRRUS_FP_REGNUM))
+ {
+ nops = 5;
+ goto fix;
+ }
+ }
+ return;
- if (arm_cirrus_insn_p (t))
- ++ nops;
+fix:
+ t = insn;
+ for ( ; nops > 0; )
+ {
+ t = cirrus_next_mach_insn (t, &l);
+ if (!t)
+ break;
+ if (GET_CODE (t) == JUMP_INSN
+ || GET_CODE (t) == CALL_INSN)
+ {
+ nops -= l;
+ break;
+ }
+ else if (arm_cirrus_insn_p (t))
+ {
+ attr = get_attr_cirrus (t);
+ if (attr == CIRRUS_COMPARE)
+ break;
+ }
+ nops -= l;
+ }
- if (arm_cirrus_insn_p (next_nonnote_insn (t)))
- ++ nops;
+ while (nops-- > 0)
+ emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */
+}
- while (nops --)
- emit_insn_after (gen_nop (), first);
+/* Cirrus reorg for bugs #10 and #12 (data aborts). */
+static void
+cirrus_reorg_bug10_12 (rtx insn)
+{
+ rtx t;
- return;
- }
+ t = cirrus_next_mach_insn (insn, 0);
+ if (arm_cirrus_insn_p (t))
+ if (TARGET_CIRRUS_D0 ||
+ get_attr_cirrus (t) == CIRRUS_DOUBLE)
+ emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */
}
/* Return TRUE if X references a SYMBOL_REF. */
@@ -7727,7 +7796,7 @@
{
Mnode * mp;
Mnode * nmp;
- int align64 = 0;
+ int align64 = 0, stuffnop = 0;
if (ARM_DOUBLEWORD_ALIGN)
for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
@@ -7742,8 +7811,27 @@
";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
+ /* Check if branch before minipool is already stuffed with nops. */
+ if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1)
+ {
+ rtx t;
+
+ t = prev_active_insn (scan);
+ if (GET_CODE (t) != INSN
+ || PATTERN (t) != const0_rtx)
+ stuffnop = 1;
+ }
scan = emit_label_after (gen_label_rtx (), scan);
scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
+ /* Last instruction was branch, so put two non-Cirrus opcodes. */
+ if (stuffnop)
+ {
+#if TARGET_CIRRUS /* This is doubling up on nops, so I don't think this is a good idea */
+ emit_insn_before (gen_nop (), scan); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */
+ emit_insn_before (gen_nop (), scan); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */
+#endif
+ }
+
scan = emit_label_after (minipool_vector_label, scan);
for (mp = minipool_vector_head; mp != NULL; mp = nmp)
@@ -8151,15 +8239,38 @@
gcc_assert (GET_CODE (insn) == NOTE);
minipool_pad = 0;
+#if TARGET_CIRRUS /* I think this is a double-up */
+ /* Scan all the insn and fix Cirrus issues. */
+ if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1)
+ {
+ rtx t, s;
+
+ for (t = cirrus_next_mach_insn (insn, 0); t; t = cirrus_next_mach_insn (t, 0))
+ if (arm_mem_access_p (t))
+ cirrus_reorg_bug10_12 (t);
+
+ if (TARGET_CIRRUS_D0)
+ for (t = cirrus_next_mach_insn (insn, 0); t; t = cirrus_next_mach_insn (t, 0))
+ if (arm_cirrus_insn_p (t))
+ cirrus_reorg_bug1 (t);
+
+ /* Find last insn. */
+ for (t = insn; ; t = s)
+ {
+ s = cirrus_next_mach_insn (t, 0);
+ if (!s)
+ break;
+ }
+ /* Scan backward and fix branches. - WARNING: appears to cause "bad immediate value for offset" problems! */
+ for ( ; t; t = cirrus_prev_mach_insn (t, 0))
+ if (GET_CODE (t) == JUMP_INSN
+ || GET_CODE (t) == CALL_INSN)
+ cirrus_reorg_branch (t);
+ }
+#endif
/* Scan all the insns and record the operands that will need fixing. */
for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
{
- if (TARGET_CIRRUS_FIX_INVALID_INSNS
- && (arm_cirrus_insn_p (insn)
- || GET_CODE (insn) == JUMP_INSN
- || arm_memory_load_p (insn)))
- cirrus_reorg (insn);
-
if (GET_CODE (insn) == BARRIER)
push_minipool_barrier (insn, address);
else if (INSN_P (insn))
@@ -11755,16 +11910,10 @@
|| get_attr_conds (this_insn) != CONDS_NOCOND)
fail = TRUE;
- /* A conditional cirrus instruction must be followed by
- a non Cirrus instruction. However, since we
- conditionalize instructions in this function and by
- the time we get here we can't add instructions
- (nops), because shorten_branches() has already been
- called, we will disable conditionalizing Cirrus
- instructions to be safe. */
- if (GET_CODE (scanbody) != USE
- && GET_CODE (scanbody) != CLOBBER
- && get_attr_cirrus (this_insn) != CIRRUS_NOT)
+ /* To avoid erratic behaviour, we avoid conditional Cirrus
+ instructions when doing workarounds. */
+ if (arm_cirrus_insn_p(this_insn)
+ && (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1))
fail = TRUE;
break;
diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.h gcc-4.1.2/gcc/config/arm/arm.h
--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.h 2005-11-05 01:02:51.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.h 2007-05-15 10:15:05.000000000 +1000
@@ -5,6 +5,7 @@
and Martin Simmons (@harleqn.co.uk).
More major hacks by Richard Earnshaw (rearnsha@arm.com)
Minor hacks by Nick Clifton (nickc@cygnus.com)
+ Cirrus Crunch fixes by Vladimir Ivanov (vladitx@nucleusys.com)
This file is part of GCC.
@@ -140,7 +141,9 @@
%{msoft-float:%{mhard-float: \
%e-msoft-float and -mhard_float may not be used together}} \
%{mbig-endian:%{mlittle-endian: \
- %e-mbig-endian and -mlittle-endian may not be used together}}"
+ %e-mbig-endian and -mlittle-endian may not be used together}} \
+%{mfix-crunch-d0:%{mfix-crunch-d1: \
+ %e-mfix-crunch-d0 and -mfix-crunch-d1 may not be used together}}"
#ifndef CC1_SPEC
#define CC1_SPEC ""
@@ -179,6 +182,9 @@
#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
#define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
#define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
+#define TARGET_CIRRUS (arm_arch_cirrus)
+#define TARGET_CIRRUS_D0 0 /* (target_flags & ARM_FLAG_CIRRUS_D0) */
+#define TARGET_CIRRUS_D1 1 /* (target_flags & ARM_FLAG_CIRRUS_D1) */
#define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
#define TARGET_IWMMXT (arm_arch_iwmmxt)
#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.opt gcc-4.1.2/gcc/config/arm/arm.opt
--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.opt 2005-11-05 01:02:51.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.opt 2007-05-15 10:09:31.000000000 +1000
@@ -68,6 +68,14 @@
Target Report Mask(CIRRUS_FIX_INVALID_INSNS)
Cirrus: Place NOPs to avoid invalid instruction combinations
+fix-crunch-d0
+Target Report Mask(ARM_FLAG_CIRRUS_D0)
+Cirrus: workarounds for Crunch coprocessor revision D0
+
+fix-crunch-d1
+Target Report Mask(ARM_FLAG_CIRRUS_D1)
+Cirrus: workarounds for Crunch coprocessor revision D1
+
mcpu=
Target RejectNegative Joined
Specify the name of the target CPU
diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/doc/invoke.texi gcc-4.1.2/gcc/doc/invoke.texi
--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/doc/invoke.texi 2006-09-26 07:21:58.000000000 +1000
+++ gcc-4.1.2/gcc/doc/invoke.texi 2007-05-15 10:07:04.000000000 +1000
@@ -408,7 +408,7 @@
-msingle-pic-base -mno-single-pic-base @gol
-mpic-register=@var{reg} @gol
-mnop-fun-dllimport @gol
--mcirrus-fix-invalid-insns -mno-cirrus-fix-invalid-insns @gol
+-mfix-crunch-d0 -mfix-crunch-d1 @gol
-mpoke-function-name @gol
-mthumb -marm @gol
-mtpcs-frame -mtpcs-leaf-frame @gol
@@ -7435,17 +7435,12 @@
Specify the register to be used for PIC addressing. The default is R10
unless stack-checking is enabled, when R9 is used.
-@item -mcirrus-fix-invalid-insns
-@opindex mcirrus-fix-invalid-insns
-@opindex mno-cirrus-fix-invalid-insns
-Insert NOPs into the instruction stream to in order to work around
-problems with invalid Maverick instruction combinations. This option
-is only valid if the @option{-mcpu=ep9312} option has been used to
-enable generation of instructions for the Cirrus Maverick floating
-point co-processor. This option is not enabled by default, since the
-problem is only present in older Maverick implementations. The default
-can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns}
-switch.
+@item -mfix-crunch-d0
+@itemx -mfix-crunch-d1
+@opindex mfix-crunch-d0
+@opindex mfix-crunch-d1
+Enable workarounds for the Cirrus MaverickCrunch coprocessor revisions
+D0 and D1 respectively.
@item -mpoke-function-name
@opindex mpoke-function-name

48
meta/packages/gcc/gcc-4.2.3/arm-crunch-compare-geu.patch vendored
View File

@ -1,48 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-08 06:39:41.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-08 06:41:00.000000000 +1000
@@ -7125,6 +7125,22 @@
(set_attr "length" "8")]
)
+; Special pattern to match GEU for MAVERICK.
+(define_insn "*arm_bgeu"
+ [(set (pc)
+ (if_then_else (geu (match_operand 1 "cc_register" "") (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_ARM && (TARGET_MAVERICK)"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+ if (get_attr_cirrus (prev_active_insn(insn)) == CIRRUS_COMPARE)
+ return \"beq\\t%l0\;bvs\\t%l0\"; else return \"bge\\t%l0\;nop\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "8")]
+)
+
; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0.
(define_insn "*arm_bunlt"
[(set (pc)
@@ -7240,6 +7256,22 @@
(set_attr "length" "8")]
)
+; Special pattern to match reversed GEU for MAVERICK.
+(define_insn "*arm_bgeu_reversed"
+ [(set (pc)
+ (if_then_else (geu (match_operand 1 "cc_register" "") (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ "TARGET_ARM && (TARGET_MAVERICK)"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+
+ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "12")]
+)
+
; Special pattern to match reversed UNLT for MAVERICK.
(define_insn "*arm_bunlt_reversed"
[(set (pc)

98
meta/packages/gcc/gcc-4.2.3/arm-crunch-compare-unordered.patch vendored
View File

@ -1,98 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-07 14:45:22.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-07 15:13:58.000000000 +1000
@@ -7001,16 +7001,16 @@
(if_then_else (unordered (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0,
arm_compare_op1);"
)
(define_expand "bordered"
[(set (pc)
(if_then_else (ordered (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0,
arm_compare_op1);"
@@ -7141,6 +7141,38 @@
(set_attr "length" "8")]
)
+; Special pattern to match UNORDERED for MAVERICK - UGLY since we need to test for Z=0 && N=0.
+(define_insn "*arm_bunordered"
+ [(set (pc)
+ (if_then_else (unordered (match_operand:CCFP 1 "cc_register" "") (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+
+ return \"beq\\t.+12\;bmi\\t.+8\;b\\t%l0\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "12")]
+)
+
+; Special pattern to match ORDERED for MAVERICK.
+(define_insn "*arm_bordered"
+ [(set (pc)
+ (if_then_else (ordered (match_operand:CCFP 1 "cc_register" "") (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+
+ return \"beq\\t%l0\;bmi\\t%l0\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "8")]
+)
+
(define_insn "*arm_cond_branch"
[(set (pc)
(if_then_else (match_operator 1 "arm_comparison_operator"
@@ -7224,6 +7256,37 @@
(set_attr "length" "8")]
)
+; Special pattern to match reversed UNORDERED for MAVERICK.
+(define_insn "*arm_bunordered_reversed"
+ [(set (pc)
+ (if_then_else (unordered (match_operand:CCFP 1 "cc_register" "") (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+
+ return \"beq\\t%l0\;bmi\\t%l0\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "8")]
+)
+
+; Special pattern to match reversed ORDERED for MAVERICK - UGLY since we need to test for Z=0 && N=0.
+(define_insn "*arm_bordered_reversed"
+ [(set (pc)
+ (if_then_else (ordered (match_operand:CCFP 1 "cc_register" "") (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+
+ return \"beq\\t.+12\;bmi\\t.+8\;b\\t%l0\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "12")]
+)
(define_insn "*arm_cond_branch_reversed"
[(set (pc)

98
meta/packages/gcc/gcc-4.2.3/arm-crunch-compare-unordered.patch-z-eq vendored
View File

@ -1,98 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-07 14:45:22.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-07 15:13:58.000000000 +1000
@@ -7001,16 +7001,16 @@
(if_then_else (unordered (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0,
arm_compare_op1);"
)
(define_expand "bordered"
[(set (pc)
(if_then_else (ordered (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0,
arm_compare_op1);"
@@ -7141,6 +7141,38 @@
(set_attr "length" "8")]
)
+; Special pattern to match UNORDERED for MAVERICK - UGLY since we need to test for C=0 && N=0
+(define_insn "*arm_bunordered"
+ [(set (pc)
+ (if_then_else (unordered (match_operand 1 "cc_register" "") (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+
+ return \"bcs\\t.+12\;bmi\\t.+8\;b\\t%l0\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "12")]
+)
+
+; Special pattern to match ORDERED for MAVERICK.
+(define_insn "*arm_bordered"
+ [(set (pc)
+ (if_then_else (ordered (match_operand 1 "cc_register" "") (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+
+ return \"bcs\\t%l0\;bmi\\t%l0\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "8")]
+)
+
(define_insn "*arm_cond_branch"
[(set (pc)
(if_then_else (match_operator 1 "arm_comparison_operator"
@@ -7224,6 +7256,37 @@
(set_attr "length" "8")]
)
+; Special pattern to match reversed UNORDERED for MAVERICK.
+(define_insn "*arm_bunordered_reversed"
+ [(set (pc)
+ (if_then_else (unordered (match_operand 1 "cc_register" "") (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+
+ return \"bcs\\t%l0\;bmi\\t%l0\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "8")]
+)
+
+; Special pattern to match reversed ORDERED for MAVERICK - UGLY since we need to test for C=0 && N=0
+(define_insn "*arm_bordered_reversed"
+ [(set (pc)
+ (if_then_else (ordered (match_operand 1 "cc_register" "") (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+
+ return \"bcs\\t.+12\;bmi\\t.+8\;b\\t%l0\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "12")]
+)
(define_insn "*arm_cond_branch_reversed"
[(set (pc)

400
meta/packages/gcc/gcc-4.2.3/arm-crunch-compare.patch vendored
View File

@ -1,400 +0,0 @@
diff -urN gcc-4.1.2/gcc/config/arm/arm.c ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.c
--- gcc-4.1.2/gcc/config/arm/arm.c 2007-05-31 12:39:48.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-29 17:19:38.000000000 +1000
@@ -11427,26 +11427,53 @@
/* These encodings assume that AC=1 in the FPA system control
byte. This allows us to handle all cases except UNEQ and
LTGT. */
- switch (comp_code)
- {
- case GE: return ARM_GE;
- case GT: return ARM_GT;
- case LE: return ARM_LS;
- case LT: return ARM_MI;
- case NE: return ARM_NE;
- case EQ: return ARM_EQ;
- case ORDERED: return ARM_VC;
- case UNORDERED: return ARM_VS;
- case UNLT: return ARM_LT;
- case UNLE: return ARM_LE;
- case UNGT: return ARM_HI;
- case UNGE: return ARM_PL;
- /* UNEQ and LTGT do not have a representation. */
- case UNEQ: /* Fall through. */
- case LTGT: /* Fall through. */
- default: gcc_unreachable ();
- }
-
+ if (!TARGET_MAVERICK)
+ {
+ switch (comp_code)
+ {
+ case GE: return ARM_GE;
+ case GT: return ARM_GT;
+ case LE: return ARM_LS;
+ case LT: return ARM_MI;
+ case NE: return ARM_NE;
+ case EQ: return ARM_EQ;
+ case ORDERED: return ARM_VC;
+ case UNORDERED: return ARM_VS;
+ case UNLT: return ARM_LT;
+ case UNLE: return ARM_LE;
+ case UNGT: return ARM_HI;
+ case UNGE: return ARM_PL;
+ /* UNEQ and LTGT do not have a representation. */
+ case UNEQ: /* Fall through. */
+ case LTGT: /* Fall through. */
+ default: gcc_unreachable ();
+ }
+ }
+ else
+ {
+ /* CIRRUS */
+ switch (comp_code)
+ {
+#if 1
+ case GT: return ARM_VS;
+ case LE: return ARM_LE;
+ case LT: return ARM_LT;
+ case NE: return ARM_NE;
+ case EQ: return ARM_EQ;
+ case UNLE: return ARM_VC;
+ case UNGT: return ARM_GT;
+ case UNGE: return ARM_GE;
+ case UNEQ: return ARM_PL;
+ case LTGT: return ARM_MI;
+ /* These do not have a representation. */
+ case GE: /* Fall through. -UNGE wrong atm */
+ case UNLT: /* Fall through. -LT wrong atm */
+ case ORDERED: /* Fall through. -AL wrong atm */
+ case UNORDERED: /* Fall through. -AL wrong atm */
+#endif
+ default: gcc_unreachable ();
+ }
+ }
case CC_SWPmode:
switch (comp_code)
{
diff -urN gcc-4.1.2/gcc/config/arm/arm.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.md
--- gcc-4.1.2/gcc/config/arm/arm.md 2007-05-31 12:39:48.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-29 15:17:18.000000000 +1000
@@ -6952,10 +6952,11 @@
"operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);"
)
+;broken on cirrus
(define_expand "bge"
[(set (pc)
(if_then_else (ge (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM"
+ "TARGET_ARM" ;; && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)
"operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
@@ -6988,6 +6989,7 @@
"operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);"
)
+; broken on cirrus?
(define_expand "bgeu"
[(set (pc)
(if_then_else (geu (match_dup 1) (const_int 0))
@@ -7031,14 +7033,15 @@
(if_then_else (ungt (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);"
)
-(define_expand "bunlt"
+; broken for cirrus
+(define_expand "bunlt"
[(set (pc)
(if_then_else (unlt (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);"
@@ -7049,7 +7052,7 @@
(if_then_else (unge (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);"
)
@@ -7058,7 +7061,7 @@
(if_then_else (unle (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);"
)
@@ -7069,7 +7072,7 @@
(if_then_else (uneq (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);"
)
@@ -7078,7 +7081,7 @@
(if_then_else (ltgt (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);"
)
@@ -7086,7 +7089,7 @@
;; Patterns to match conditional branch insns.
;;
-; Special pattern to match UNEQ.
+; Special pattern to match UNEQ for FPA and VFP.
(define_insn "*arm_buneq"
[(set (pc)
(if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0))
@@ -7102,7 +7105,7 @@
(set_attr "length" "8")]
)
-; Special pattern to match LTGT.
+; Special pattern to match LTGT for FPA and VFP.
(define_insn "*arm_bltgt"
[(set (pc)
(if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0))
@@ -7118,6 +7121,38 @@
(set_attr "length" "8")]
)
+; Special pattern to match GE for MAVERICK.
+(define_insn "*arm_bge"
+ [(set (pc)
+ (if_then_else (ge (match_operand:CCFP 1 "cc_register" "") (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+
+ return \"beq\\t%l0\;bvs\\t%l0\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "8")]
+)
+
+; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0.
+(define_insn "*arm_bunlt"
+ [(set (pc)
+ (if_then_else (unlt (match_operand:CCFP 1 "cc_register" "") (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+
+ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "12")]
+)
+
(define_insn "*arm_cond_branch"
[(set (pc)
(if_then_else (match_operator 1 "arm_comparison_operator"
@@ -7137,7 +7172,7 @@
(set_attr "type" "branch")]
)
-; Special pattern to match reversed UNEQ.
+; Special pattern to match reversed UNEQ for FPA and VFP.
(define_insn "*arm_buneq_reversed"
[(set (pc)
(if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0))
@@ -7153,7 +7188,7 @@
(set_attr "length" "8")]
)
-; Special pattern to match reversed LTGT.
+; Special pattern to match reversed LTGT for FPA and VFP.
(define_insn "*arm_bltgt_reversed"
[(set (pc)
(if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0))
@@ -7169,6 +7204,39 @@
(set_attr "length" "8")]
)
+; Special pattern to match reversed GE for MAVERICK - UGLY since we need to tst for Z=0 && N=0.
+(define_insn "*arm_bge_reversed"
+ [(set (pc)
+ (if_then_else (ge (match_operand:CCFP 1 "cc_register" "") (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+
+ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "12")]
+)
+
+; Special pattern to match reversed UNLT for MAVERICK.
+(define_insn "*arm_bunlt_reversed"
+ [(set (pc)
+ (if_then_else (unlt (match_operand:CCFP 1 "cc_register" "") (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+
+ return \"beq\\t%l0\;bvs\\t%l0\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "8")]
+)
+
+
(define_insn "*arm_cond_branch_reversed"
[(set (pc)
(if_then_else (match_operator 1 "arm_comparison_operator"
@@ -7220,8 +7288,9 @@
"operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);"
)
+;; broken for cirrus - definitely
(define_expand "sge"
[(set (match_operand:SI 0 "s_register_operand" "")
(ge:SI (match_dup 1) (const_int 0)))]
- "TARGET_ARM"
+ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
@@ -7227,6 +7296,14 @@
"operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
)
+;;; DO NOT add patterns for SGE these can not be represented with MAVERICK
+; (define_expand "sge"
+; [(set (match_operand:SI 0 "s_register_operand" "")
+; (ge:SI (match_dup 1) (const_int 0)))]
+; "TARGET_ARM && (TARGET_MAVERICK)"
+; "gcc_unreachable ();"
+; )
+
(define_expand "slt"
[(set (match_operand:SI 0 "s_register_operand" "")
(lt:SI (match_dup 1) (const_int 0)))]
@@ -7248,6 +7325,7 @@
"operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);"
)
+;; broken for cirrus - maybe
(define_expand "sgeu"
[(set (match_operand:SI 0 "s_register_operand" "")
(geu:SI (match_dup 1) (const_int 0)))]
@@ -7255,6 +7333,14 @@
"operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);"
)
+;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK?
+; (define_expand "sgeu"
+; [(set (match_operand:SI 0 "s_register_operand" "")
+; (ge:SI (match_dup 1) (const_int 0)))]
+; "TARGET_ARM && (TARGET_MAVERICK)"
+; "gcc_unreachable ();"
+; )
+
(define_expand "sltu"
[(set (match_operand:SI 0 "s_register_operand" "")
(ltu:SI (match_dup 1) (const_int 0)))]
@@ -7281,7 +7367,7 @@
(define_expand "sungt"
[(set (match_operand:SI 0 "s_register_operand" "")
(ungt:SI (match_dup 1) (const_int 0)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0,
arm_compare_op1);"
)
@@ -7289,23 +7375,32 @@
(define_expand "sunge"
[(set (match_operand:SI 0 "s_register_operand" "")
(unge:SI (match_dup 1) (const_int 0)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0,
arm_compare_op1);"
)
+; broken for cirrus
(define_expand "sunlt"
[(set (match_operand:SI 0 "s_register_operand" "")
(unlt:SI (match_dup 1) (const_int 0)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0,
arm_compare_op1);"
)
+;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK
+; (define_expand "sunlt"
+; [(set (match_operand:SI 0 "s_register_operand" "")
+; (unlt:SI (match_dup 1) (const_int 0)))]
+; "TARGET_ARM && (TARGET_MAVERICK)"
+; "gcc_unreachable ();"
+; )
+
(define_expand "sunle"
[(set (match_operand:SI 0 "s_register_operand" "")
(unle:SI (match_dup 1) (const_int 0)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0,
arm_compare_op1);"
)
@@ -7371,7 +7466,7 @@
enum rtx_code code = GET_CODE (operands[1]);
rtx ccreg;
- if (code == UNEQ || code == LTGT)
+ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED)))
FAIL;
ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1);
@@ -7390,7 +7485,8 @@
enum rtx_code code = GET_CODE (operands[1]);
rtx ccreg;
- if (code == UNEQ || code == LTGT)
+ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED)))
+
FAIL;
/* When compiling for SOFT_FLOAT, ensure both arms are in registers.
@@ -7409,13 +7505,13 @@
(if_then_else:DF (match_operand 1 "arm_comparison_operator" "")
(match_operand:DF 2 "s_register_operand" "")
(match_operand:DF 3 "arm_float_add_operand" "")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"
{
enum rtx_code code = GET_CODE (operands[1]);
rtx ccreg;
- if (code == UNEQ || code == LTGT)
+ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code==GE || code == UNLT || code == ORDERED || code == UNORDERED)))
FAIL;
ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1);

400
meta/packages/gcc/gcc-4.2.3/arm-crunch-compare.patch-z-eq vendored
View File

@ -1,400 +0,0 @@
diff -urN gcc-4.1.2/gcc/config/arm/arm.c ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.c
--- gcc-4.1.2/gcc/config/arm/arm.c 2007-05-31 12:39:48.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-29 17:19:38.000000000 +1000
@@ -11427,26 +11427,53 @@
/* These encodings assume that AC=1 in the FPA system control
byte. This allows us to handle all cases except UNEQ and
LTGT. */
- switch (comp_code)
- {
- case GE: return ARM_GE;
- case GT: return ARM_GT;
- case LE: return ARM_LS;
- case LT: return ARM_MI;
- case NE: return ARM_NE;
- case EQ: return ARM_EQ;
- case ORDERED: return ARM_VC;
- case UNORDERED: return ARM_VS;
- case UNLT: return ARM_LT;
- case UNLE: return ARM_LE;
- case UNGT: return ARM_HI;
- case UNGE: return ARM_PL;
- /* UNEQ and LTGT do not have a representation. */
- case UNEQ: /* Fall through. */
- case LTGT: /* Fall through. */
- default: gcc_unreachable ();
- }
-
+ if (!TARGET_MAVERICK)
+ {
+ switch (comp_code)
+ {
+ case GE: return ARM_GE;
+ case GT: return ARM_GT;
+ case LE: return ARM_LS;
+ case LT: return ARM_MI;
+ case NE: return ARM_NE;
+ case EQ: return ARM_EQ;
+ case ORDERED: return ARM_VC;
+ case UNORDERED: return ARM_VS;
+ case UNLT: return ARM_LT;
+ case UNLE: return ARM_LE;
+ case UNGT: return ARM_HI;
+ case UNGE: return ARM_PL;
+ /* UNEQ and LTGT do not have a representation. */
+ case UNEQ: /* Fall through. */
+ case LTGT: /* Fall through. */
+ default: gcc_unreachable ();
+ }
+ }
+ else
+ {
+ /* CIRRUS */
+ switch (comp_code)
+ {
+#if 1
+ case GT: return ARM_VS;
+ case LE: return ARM_LE;
+ case LT: return ARM_LT;
+ case NE: return ARM_NE;
+ case EQ: return ARM_EQ;
+ case UNLE: return ARM_VC;
+ case UNGT: return ARM_GT;
+ case UNGE: return ARM_GE;
+ case UNEQ: return ARM_PL;
+ case LTGT: return ARM_MI;
+ /* These do not have a representation. */
+ case GE: /* Fall through. -UNGE wrong atm */
+ case UNLT: /* Fall through. -LT wrong atm */
+ case ORDERED: /* Fall through. -AL wrong atm */
+ case UNORDERED: /* Fall through. -AL wrong atm */
+#endif
+ default: gcc_unreachable ();
+ }
+ }
case CC_SWPmode:
switch (comp_code)
{
diff -urN gcc-4.1.2/gcc/config/arm/arm.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.md
--- gcc-4.1.2/gcc/config/arm/arm.md 2007-05-31 12:39:48.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-29 15:17:18.000000000 +1000
@@ -6952,10 +6952,11 @@
"operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);"
)
+;broken on cirrus
(define_expand "bge"
[(set (pc)
(if_then_else (ge (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM"
+ "TARGET_ARM"
"operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
@@ -6988,6 +6989,7 @@
"operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);"
)
+; broken on cirrus?
(define_expand "bgeu"
[(set (pc)
(if_then_else (geu (match_dup 1) (const_int 0))
@@ -7031,14 +7033,15 @@
(if_then_else (ungt (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);"
)
-(define_expand "bunlt"
+; broken for cirrus
+(define_expand "bunlt"
[(set (pc)
(if_then_else (unlt (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);"
@@ -7049,7 +7052,7 @@
(if_then_else (unge (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);"
)
@@ -7058,7 +7061,7 @@
(if_then_else (unle (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);"
)
@@ -7069,7 +7072,7 @@
(if_then_else (uneq (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK
"operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);"
)
@@ -7078,7 +7081,7 @@
(if_then_else (ltgt (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK
"operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);"
)
@@ -7086,7 +7089,7 @@
;; Patterns to match conditional branch insns.
;;
-; Special pattern to match UNEQ.
+; Special pattern to match UNEQ for FPA and VFP.
(define_insn "*arm_buneq"
[(set (pc)
(if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0))
@@ -7102,7 +7105,7 @@
(set_attr "length" "8")]
)
-; Special pattern to match LTGT.
+; Special pattern to match LTGT for FPA and VFP.
(define_insn "*arm_bltgt"
[(set (pc)
(if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0))
@@ -7118,6 +7121,38 @@
(set_attr "length" "8")]
)
+; Special pattern to match GE for MAVERICK.
+(define_insn "*arm_bge"
+ [(set (pc)
+ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_ARM && (TARGET_MAVERICK)"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+
+ return \"beq\\t%l0\;bvs\\t%l0\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "8")]
+)
+
+; Special pattern to match UNLT for MAVERICK.
+(define_insn "*arm_bunlt"
+ [(set (pc)
+ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0))
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_ARM && (TARGET_MAVERICK)"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+
+ return \"bne\\t%l0\;bvc\\t%l0\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "8")]
+)
+
(define_insn "*arm_cond_branch"
[(set (pc)
(if_then_else (match_operator 1 "arm_comparison_operator"
@@ -7137,7 +7172,7 @@
(set_attr "type" "branch")]
)
-; Special pattern to match reversed UNEQ.
+; Special pattern to match reversed UNEQ for FPA and VFP.
(define_insn "*arm_buneq_reversed"
[(set (pc)
(if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0))
@@ -7153,7 +7188,7 @@
(set_attr "length" "8")]
)
-; Special pattern to match reversed LTGT.
+; Special pattern to match reversed LTGT for FPA and VFP.
(define_insn "*arm_bltgt_reversed"
[(set (pc)
(if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0))
@@ -7169,6 +7204,39 @@
(set_attr "length" "8")]
)
+; Special pattern to match reversed GE for MAVERICK.
+(define_insn "*arm_bge_reversed"
+ [(set (pc)
+ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ "TARGET_ARM && (TARGET_MAVERICK)"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+
+ return \"bne\\t%l0\;bvc\\t%l0\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "8")]
+)
+
+; Special pattern to match reversed UNLT for MAVERICK.
+(define_insn "*arm_bunlt_reversed"
+ [(set (pc)
+ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ "TARGET_ARM && (TARGET_MAVERICK)"
+ "*
+ gcc_assert (!arm_ccfsm_state);
+
+ return \"beq\\t%l0\;bvs\\t%l0\";
+ "
+ [(set_attr "conds" "jump_clob")
+ (set_attr "length" "8")]
+)
+
+
(define_insn "*arm_cond_branch_reversed"
[(set (pc)
(if_then_else (match_operator 1 "arm_comparison_operator"
@@ -7220,8 +7288,9 @@
"operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);"
)
+;; broken for cirrus - definitely
(define_expand "sge"
[(set (match_operand:SI 0 "s_register_operand" "")
(ge:SI (match_dup 1) (const_int 0)))]
- "TARGET_ARM"
+ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
@@ -7227,6 +7296,14 @@
"operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
)
+;;; DO NOT add patterns for SGE these can not be represented with MAVERICK
+; (define_expand "sge"
+; [(set (match_operand:SI 0 "s_register_operand" "")
+; (ge:SI (match_dup 1) (const_int 0)))]
+; "TARGET_ARM && (TARGET_MAVERICK)"
+; "gcc_unreachable ();"
+; )
+
(define_expand "slt"
[(set (match_operand:SI 0 "s_register_operand" "")
(lt:SI (match_dup 1) (const_int 0)))]
@@ -7248,6 +7325,7 @@
"operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);"
)
+;; broken for cirrus - maybe
(define_expand "sgeu"
[(set (match_operand:SI 0 "s_register_operand" "")
(geu:SI (match_dup 1) (const_int 0)))]
@@ -7255,6 +7333,14 @@
"operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);"
)
+;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK?
+; (define_expand "sgeu"
+; [(set (match_operand:SI 0 "s_register_operand" "")
+; (ge:SI (match_dup 1) (const_int 0)))]
+; "TARGET_ARM && (TARGET_MAVERICK)"
+; "gcc_unreachable ();"
+; )
+
(define_expand "sltu"
[(set (match_operand:SI 0 "s_register_operand" "")
(ltu:SI (match_dup 1) (const_int 0)))]
@@ -7281,7 +7367,7 @@
(define_expand "sungt"
[(set (match_operand:SI 0 "s_register_operand" "")
(ungt:SI (match_dup 1) (const_int 0)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0,
arm_compare_op1);"
)
@@ -7289,23 +7375,32 @@
(define_expand "sunge"
[(set (match_operand:SI 0 "s_register_operand" "")
(unge:SI (match_dup 1) (const_int 0)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0,
arm_compare_op1);"
)
+; broken for cirrus
(define_expand "sunlt"
[(set (match_operand:SI 0 "s_register_operand" "")
(unlt:SI (match_dup 1) (const_int 0)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0,
arm_compare_op1);"
)
+;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK
+; (define_expand "sunlt"
+; [(set (match_operand:SI 0 "s_register_operand" "")
+; (unlt:SI (match_dup 1) (const_int 0)))]
+; "TARGET_ARM && (TARGET_MAVERICK)"
+; "gcc_unreachable ();"
+; )
+
(define_expand "sunle"
[(set (match_operand:SI 0 "s_register_operand" "")
(unle:SI (match_dup 1) (const_int 0)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0,
arm_compare_op1);"
)
@@ -7371,7 +7466,7 @@
enum rtx_code code = GET_CODE (operands[1]);
rtx ccreg;
- if (code == UNEQ || code == LTGT)
+ if (code == UNEQ || code == LTGT || code == GE || code == UNLT || code == ORDERED || code == UNORDERED)
FAIL;
ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1);
@@ -7390,7 +7485,8 @@
enum rtx_code code = GET_CODE (operands[1]);
rtx ccreg;
- if (code == UNEQ || code == LTGT)
+ if (code == UNEQ || code == LTGT || code == GE || code == UNLT || code == ORDERED || code == UNORDERED)
+
FAIL;
/* When compiling for SOFT_FLOAT, ensure both arms are in registers.
@@ -7409,13 +7505,13 @@
(if_then_else:DF (match_operand 1 "arm_comparison_operator" "")
(match_operand:DF 2 "s_register_operand" "")
(match_operand:DF 3 "arm_float_add_operand" "")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"
{
enum rtx_code code = GET_CODE (operands[1]);
rtx ccreg;
- if (code == UNEQ || code == LTGT)
+ if (code == UNEQ || code == LTGT || code == GE || code == UNLT || code == ORDERED || code == UNORDERED)
FAIL;
ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1);

12
meta/packages/gcc/gcc-4.2.3/arm-crunch-dominance.patch vendored
View File

@ -1,12 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/arm.c-original 2007-06-13 11:50:10.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.c 2007-06-13 11:50:56.000000000 +1000
@@ -6556,6 +6556,9 @@
enum rtx_code cond1, cond2;
int swapped = 0;
+ if (TARGET_MAVERICK) // Simple hack for MAVERICK
+ return CCmode;
+
/* Currently we will probably get the wrong result if the individual
comparisons are not simple. This also ensures that it is safe to
reverse a comparison if necessary. */

139
meta/packages/gcc/gcc-4.2.3/arm-crunch-eabi-ieee754-div.patch vendored
View File

@ -1,139 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/ieee754-df-original.S 2007-06-25 10:22:06.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/ieee754-df.S 2007-06-25 10:27:17.000000000 +1000
@@ -717,6 +717,10 @@
cmn r4, #(53 + 1)
movle xl, #0
bicle xh, xh, #0x7fffffff
+#ifdef __MAVERICK__
+ cfmvdlr mvd0, xl
+ cfmvdhr mvd0, xh
+#endif
RETLDM "r4, r5, r6" le
@ Find out proper shift value.
@@ -738,6 +742,10 @@
adc xh, r2, xh, lsr r4
orrs lr, lr, r3, lsl #1
biceq xl, xl, r3, lsr #31
+#ifdef __MAVERICK__
+ cfmvdlr mvd0, xl
+ cfmvdhr mvd0, xh
+#endif
RETLDM "r4, r5, r6"
@ shift result right of 21 to 31 bits, or left 11 to 1 bits after
@@ -752,6 +760,10 @@
adc xh, xh, #0
orrs lr, lr, r3, lsl #1
biceq xl, xl, r3, lsr #31
+#ifdef __MAVERICK__
+ cfmvdlr mvd0, xl
+ cfmvdhr mvd0, xh
+#endif
RETLDM "r4, r5, r6"
@ Shift value right of 32 to 64 bits, or 0 to 32 bits after a switch
@@ -766,6 +778,10 @@
add xl, xl, r3, lsr #31
orrs lr, lr, r3, lsl #1
biceq xl, xl, r3, lsr #31
+#ifdef __MAVERICK__
+ cfmvdlr mvd0, xl
+ cfmvdhr mvd0, xh
+#endif
RETLDM "r4, r5, r6"
@ One or both arguments are denormalized.
@@ -808,6 +824,10 @@
eor xh, xh, yh
bic xh, xh, #0x7fffffff
mov xl, #0
+#ifdef __MAVERICK__
+ cfmvdlr mvd0, xl
+ cfmvdhr mvd0, xh
+#endif
RETLDM "r4, r5, r6"
1: @ One or both args are INF or NAN.
@@ -837,12 +857,20 @@
orr xh, xh, #0x7f000000
orr xh, xh, #0x00f00000
mov xl, #0
+#ifdef __MAVERICK__
+ cfmvdlr mvd0, xl
+ cfmvdhr mvd0, xh
+#endif
RETLDM "r4, r5, r6"
@ Return a quiet NAN.
LSYM(Lml_n):
orr xh, xh, #0x7f000000
orr xh, xh, #0x00f80000
+#ifdef __MAVERICK__
+ cfmvdlr mvd0, xl
+ cfmvdhr mvd0, xh
+#endif
RETLDM "r4, r5, r6"
FUNC_END aeabi_dmul
--- gcc-4.1.2/gcc/config/arm/ieee754-sf-original.S 2007-06-25 10:18:52.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/ieee754-sf.S 2007-06-25 10:40:25.000000000 +1000
@@ -518,6 +518,9 @@
@ Check if denormalized result is possible, otherwise return signed 0.
cmn r2, #(24 + 1)
bicle r0, r0, #0x7fffffff
+#ifdef __MAVERICK__
+ cfmvsr mvf0, r0
+#endif
RETc(le)
@ Shift value right, round, etc.
@@ -530,6 +533,9 @@
adc r0, r0, #0
orrs r3, r3, ip, lsl #1
biceq r0, r0, ip, lsr #31
+#ifdef __MAVERICK__
+ cfmvsr mvf0, r0
+#endif
RET
@ One or both arguments are denormalized.
@@ -567,6 +573,9 @@
LSYM(Lml_z):
eor r0, r0, r1
bic r0, r0, #0x7fffffff
+#ifdef __MAVERICK__
+ cfmvsr mvf0, r0
+#endif
RET
1: @ One or both args are INF or NAN.
@@ -595,12 +604,18 @@
and r0, r0, #0x80000000
orr r0, r0, #0x7f000000
orr r0, r0, #0x00800000
+#ifdef __MAVERICK__
+ cfmvsr mvf0, r0
+#endif
RET
@ Return a quiet NAN.
LSYM(Lml_n):
orr r0, r0, #0x7f000000
orr r0, r0, #0x00c00000
+#ifdef __MAVERICK__
+ cfmvsr mvf0, r0
+#endif
RET
FUNC_END aeabi_fmul
@@ -677,6 +692,9 @@
adds r2, r2, #127
rsbgts r3, r2, #255
orrgt r0, r0, r2, lsl #23
+#ifdef __MAVERICK__
+ cfmvsr mvf0, r0
+#endif
RETc(gt)
orr r0, r0, #0x00800000

100
meta/packages/gcc/gcc-4.2.3/arm-crunch-eabi-ieee754.patch vendored
View File

@ -1,100 +0,0 @@
--- ../gcc-cross-4.1.2-r4-unpatched/gcc-4.1.2/gcc/config/arm/ieee754-df.S 2007-06-07 13:06:52.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/ieee754-df.S 2007-06-07 13:15:49.000000000 +1000
@@ -42,8 +42,9 @@
@ For FPA, float words are always big-endian.
+@ For MAVERICK, float words are always little-endian.
@ For VFP, floats words follow the memory system mode.
-#if defined(__VFP_FP__) && !defined(__ARMEB__)
+#if ((defined(__VFP_FP__) && !defined(__ARMEB__)) || defined(__MAVERICK__))
#define xl r0
#define xh r1
#define yl r2
@@ -451,8 +452,13 @@
orrs r2, r0, r1
#if !defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPA_FP__)
mvfeqd f0, #0.0
#endif
+#if defined (__MAVERICK__)
+ cfstrd mvd0, #0.0
+#endif
+#endif
RETc(eq)
#if !defined (__VFP_FP__) && !defined(__SOFTFP__)
@@ -473,8 +479,13 @@
orrs r2, r0, r1
#if !defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPA_FP__)
mvfeqd f0, #0.0
#endif
+#if defined (__MAVERICK__)
+ cfstrd mvd0, #0.0
+#endif
+#endif
RETc(eq)
#if !defined (__VFP_FP__) && !defined(__SOFTFP__)
@@ -526,8 +537,14 @@
@ Legacy code expects the result to be returned in f0. Copy it
@ there as well.
LSYM(f0_ret):
+#if defined (__FPA_FP__)
stmfd sp!, {r0, r1}
ldfd f0, [sp], #8
+#endif
+#if defined (__MAVERICK__)
+ cfmvdlr mvd0, xl
+ cfmvdhr mvd0, xh
+#endif
RETLDM
#endif
--- ../gcc-cross-4.1.2-r4-unpatched/gcc-4.1.2/gcc/config/arm/ieee754-sf.S 2007-06-07 13:06:52.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/ieee754-sf.S 2007-06-07 13:21:43.000000000 +1000
@@ -302,8 +302,13 @@
orrs r2, r0, r1
#if !defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPA_FP__)
mvfeqs f0, #0.0
#endif
+#if defined (__MAVERICK__)
+ cfmvsr mvf0, #0.0
+#endif
+#endif
RETc(eq)
mov r3, #0
@@ -314,8 +319,13 @@
orrs r2, r0, r1
#if !defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPA_FP__)
mvfeqs f0, #0.0
#endif
+#if defined (__MAVERICK__)
+ cfmvsr mvf0, #0.0
+#endif
+#endif
RETc(eq)
ands r3, ah, #0x80000000 @ sign bit in r3
@@ -387,8 +397,13 @@
#if !defined (__VFP_FP__) && !defined(__SOFTFP__)
LSYM(f0_ret):
+#if defined (__FPA_FP__)
str r0, [sp, #-4]!
ldfs f0, [sp], #4
+#endif
+#if defined (__MAVERICK__)
+ cfmvsr mvf0, r0
+#endif
RETLDM
#endif

64
meta/packages/gcc/gcc-4.2.3/arm-crunch-eabi.patch vendored
View File

@ -1,64 +0,0 @@
--- /home/hwilliams/original/gcc-4.1.2/gcc/config/arm/t-linux-eabi 2005-10-10 11:04:31.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/t-linux-eabi 2007-05-15 13:53:05.000000000 +1000
@@ -1,11 +1,21 @@
# These functions are included in shared libraries.
TARGET_LIBGCC2_CFLAGS = -fPIC
+TARGET_LIBGCC2_CFLAGS += -mcpu=ep9312 -mfpu=maverick
+LIBGCC2_DEBUG_CFLAGS = -g0
# We do not build a Thumb multilib for Linux because the definition of
# CLEAR_INSN_CACHE in linux-gas.h does not work in Thumb mode.
MULTILIB_OPTIONS =
MULTILIB_DIRNAMES =
+LIB1ASMSRC = arm/lib1funcs.asm
+LIB1ASMFUNCS += _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx \
+ _negdf2 _addsubdf3 _muldivdf3 _cmpdf2 _unorddf2 _fixdfsi _fixunsdfsi \
+ _truncdfsf2 _negsf2 _addsubsf3 _muldivsf3 _cmpsf2 _unordsf2 \
+ _fixsfsi _fixunssfsi
+
+CRTSTUFF_T_CFLAGS += -mcpu=ep9312 -mfpu=maverick
+
# Use a version of div0 which raises SIGFPE.
LIB1ASMFUNCS := $(filter-out _dvmd_tls,$(LIB1ASMFUNCS)) _dvmd_lnx
diff -ruN arm/elf.h gcc-3.4.3/gcc/config/arm/elf.h
--- ../gcc-4.1.2-orig/gcc/config/arm/elf.h 2004-02-24 16:25:22.000000000 +0200
+++ gcc-4.1.2/gcc/config/arm/elf.h 2005-02-10 00:31:28.000000000 +0200
@@ -46,7 +46,7 @@
#ifndef SUBTARGET_ASM_FLOAT_SPEC
#define SUBTARGET_ASM_FLOAT_SPEC "\
-%{mapcs-float:-mfloat}"
+%{mapcs-float:-mfloat} %{msoft-float:-mfpu=softfpa} %{mcpu=ep9312:-mfpu=maverick}"
#endif
#ifndef ASM_SPEC
diff -ruN t-linux gcc-4.1.2/gcc/config/arm/t-linux
--- t-linux 2007-05-09 16:32:28.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/t-linux 2007-05-25 11:02:17.000000000 +1000
@@ -1,19 +1,22 @@
# Just for these, we omit the frame pointer since it makes such a big
# difference. It is then pointless adding debugging.
TARGET_LIBGCC2_CFLAGS = -fomit-frame-pointer -fPIC
+TARGET_LIBGCC2_CFLAGS += -mcpu=ep9312 -mfpu=maverick -mfloat-abi=softfp -D__MAVERICK__
LIBGCC2_DEBUG_CFLAGS = -g0
LIB1ASMSRC = arm/lib1funcs.asm
LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx \
_negdf2 _addsubdf3 _muldivdf3 _cmpdf2 _unorddf2 _fixdfsi _fixunsdfsi \
_truncdfsf2 _negsf2 _addsubsf3 _muldivsf3 _cmpsf2 _unordsf2 \
- _call_via_rX \
- _fixsfsi _fixunssfsi _floatdidf _floatdisf
+ _fixsfsi _fixunssfsi
# MULTILIB_OPTIONS = mhard-float/msoft-float
# MULTILIB_DIRNAMES = hard-float soft-float
# EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
+# EXTRA_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o
+CRTSTUFF_T_CFLAGS += -mcpu=ep9312 -mfpu=maverick -mfloat-abi=softfp -D__MAVERICK__
+
# LIBGCC = stmp-multilib
# INSTALL_LIBGCC = install-multilib

38
meta/packages/gcc/gcc-4.2.3/arm-crunch-floatsi-disable-single.patch vendored
View File

@ -1,38 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-25 12:12:39.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-25 12:16:13.000000000 +1000
@@ -301,13 +301,14 @@
)
;; Convert Cirrus-SI to Cirrus-SF
+; appears to be buggy
(define_insn "cirrus_floatsisf2"
[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
(float:SF (match_operand:SI 1 "s_register_operand" "r")))
(clobber (match_scratch:DF 2 "=v"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2"
[(set_attr "length" "8")
(set_attr "cirrus" "move")]
)
--- gcc-4.1.2/gcc/config/arm/arm.md-cfcvt 2007-06-25 12:16:53.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-25 12:18:20.000000000 +1000
@@ -3125,14 +3125,15 @@
;; Fixed <--> Floating conversion insns
+;; Maverick Crunch floatsisf2 is buggy - see cirrus.md
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(float:SF (match_operand:SI 1 "s_register_operand" "")))]
- "TARGET_ARM && TARGET_HARD_FLOAT"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"
- if (TARGET_MAVERICK)
+ if (TARGET_MAVERICK && 0)
{
emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1]));
DONE;
}
")

61
meta/packages/gcc/gcc-4.2.3/arm-crunch-floatsi-disable.patch vendored
View File

@ -1,61 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-25 12:12:39.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-25 12:16:13.000000000 +1000
@@ -301,21 +301,23 @@
)
;; Convert Cirrus-SI to Cirrus-SF
+; appears to be buggy
(define_insn "cirrus_floatsisf2"
[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
(float:SF (match_operand:SI 1 "s_register_operand" "r")))
(clobber (match_scratch:DF 2 "=v"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2"
[(set_attr "length" "8")
(set_attr "cirrus" "move")]
)
+;appears to be buggy
(define_insn "cirrus_floatsidf2"
[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
(float:DF (match_operand:SI 1 "s_register_operand" "r")))
(clobber (match_scratch:DF 2 "=v"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2"
[(set_attr "length" "8")
(set_attr "cirrus" "move")]
--- gcc-4.1.2/gcc/config/arm/arm.md-cfcvt 2007-06-25 12:16:53.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-25 12:18:20.000000000 +1000
@@ -3125,24 +3125,26 @@
;; Fixed <--> Floating conversion insns
+;; Maverick Crunch floatsisf2 is buggy - see cirrus.md
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(float:SF (match_operand:SI 1 "s_register_operand" "")))]
- "TARGET_ARM && TARGET_HARD_FLOAT"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"
- if (TARGET_MAVERICK)
+ if (TARGET_MAVERICK && 0)
{
emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1]));
DONE;
}
")
+;; Maverick Crunch floatsidf2 is buggy - see cirrus.md
(define_expand "floatsidf2"
[(set (match_operand:DF 0 "s_register_operand" "")
(float:DF (match_operand:SI 1 "s_register_operand" "")))]
- "TARGET_ARM && TARGET_HARD_FLOAT"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"
- if (TARGET_MAVERICK)
+ if (TARGET_MAVERICK && 0)
{
emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1]));
DONE;

37
meta/packages/gcc/gcc-4.2.3/arm-crunch-floatunsidf.patch vendored
View File

@ -1,37 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/ieee754-df-original.S 2007-06-25 14:05:35.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/ieee754-df.S 2007-06-25 14:08:03.000000000 +1000
@@ -382,6 +382,8 @@
FUNC_END aeabi_dadd
FUNC_END adddf3
+#ifndef __MAVERICK__ /* THIS IS A BAD HACK */
+
ARM_FUNC_START floatunsidf
ARM_FUNC_ALIAS aeabi_ui2d floatunsidf
@@ -401,8 +403,14 @@
FUNC_END aeabi_ui2d
FUNC_END floatunsidf
+#endif
+
ARM_FUNC_START floatsidf
ARM_FUNC_ALIAS aeabi_i2d floatsidf
+#ifdef __MAVERICK__ /* THIS IS A BAD HACK */
+ARM_FUNC_ALIAS floatunsidf floatsidf
+ARM_FUNC_ALIAS aeabi_ui2d floatsidf
+#endif
teq r0, #0
moveq r1, #0
@@ -418,6 +426,10 @@
mov xh, #0
b LSYM(Lad_l)
+#ifdef __MAVERICK__ /* THIS IS A BAD HACK */
+ FUNC_END aeabi_ui2d floatsidf
+ FUNC_END floatunsidf floatsidf
+#endif
FUNC_END aeabi_i2d
FUNC_END floatsidf

13
meta/packages/gcc/gcc-4.2.3/arm-crunch-fp_consts.patch vendored
View File

@ -1,13 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/arm.c-original 2007-06-12 16:17:14.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.c 2007-06-12 16:17:28.000000000 +1000
@@ -5218,7 +5218,9 @@
int i;
REAL_VALUE_TYPE r;
+ if (TARGET_MAVERICK)
+ fp_consts_inited = 0;
- if (TARGET_VFP)
+ else if (TARGET_VFP)
fp_consts_inited = 1;
else
fp_consts_inited = 8;

30
meta/packages/gcc/gcc-4.2.3/arm-crunch-neg.patch vendored
View File

@ -1,30 +0,0 @@
WARNING: adding this patch causes copysign1.c and mzero3.c to fail...
diff -urN gcc-4.1.2/gcc/config/arm/arm.md-original gcc-4.1.2/gcc/config/arm/arm.md
--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-12 12:48:14.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-12 12:49:53.000000000 +1000
@@ -2985,14 +2985,14 @@
(define_expand "negsf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(neg:SF (match_operand:SF 1 "s_register_operand" "")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
""
)
(define_expand "negdf2"
[(set (match_operand:DF 0 "s_register_operand" "")
(neg:DF (match_operand:DF 1 "s_register_operand" "")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"")
;; abssi2 doesn't really clobber the condition codes if a different register
@@ -4097,7 +4097,7 @@
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m")
(match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))]
"TARGET_ARM
- && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP))
+ && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP || TARGET_MAVERICK))
&& !TARGET_IWMMXT"
"*
switch (which_alternative)

25
meta/packages/gcc/gcc-4.2.3/arm-crunch-neg2.patch vendored
View File

@ -1,25 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/cirrus.md-original 2007-06-12 17:01:24.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-12 17:03:26.000000000 +1000
@@ -255,18 +256,20 @@
[(set_attr "cirrus" "normal")]
)
+;; appears to be buggy: neg 0 != -0
(define_insn "*cirrus_negsf2"
[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
(neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfnegs%?\\t%V0, %V1"
[(set_attr "cirrus" "normal")]
)
+;; appears to be buggy: neg 0 != -0
(define_insn "*cirrus_negdf2"
[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
(neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfnegd%?\\t%V0, %V1"
[(set_attr "cirrus" "normal")]
)

20
meta/packages/gcc/gcc-4.2.3/arm-crunch-offset.patch vendored
View File

@ -1,20 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/arm.c-original 2007-06-12 14:46:20.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.c 2007-06-12 14:48:06.000000000 +1000
@@ -3460,7 +3460,7 @@
use_ldrd = (TARGET_LDRD
&& (mode == DImode
- || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
+ || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_MAVERICK || TARGET_VFP))));
if (code == POST_INC || code == PRE_DEC
|| ((code == PRE_INC || code == POST_DEC)
@@ -3960,7 +3960,7 @@
/* VFP addressing modes actually allow greater offsets, but for
now we just stick with the lowest common denominator. */
if (mode == DImode
- || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
+ || ((TARGET_SOFT_FLOAT || TARGET_MAVERICK || TARGET_VFP) && mode == DFmode))
{
low_n = n & 0x0f;
n &= ~0x0f;

20
meta/packages/gcc/gcc-4.2.3/arm-crunch-predicates.patch vendored
View File

@ -1,20 +0,0 @@
diff -urN gcc-4.1.2/gcc/config/arm/predicates.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/predicates.md
--- gcc-4.1.2/gcc/config/arm/predicates.md 2005-09-11 17:38:02.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/predicates.md 2007-05-30 12:15:54.000000000 +1000
@@ -171,8 +171,14 @@
(match_code "eq,ne"))
;; True for comparisons other than LTGT or UNEQ.
+(define_special_predicate "arm_comparison_operator"
+; (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt")) ;; original - no LTGT or UNEQ
+; (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltgt,ltu,unordered,ordered,uneq,unlt,unle,unge,ungt")) ;; everything?
+;; True for comparisons other than GE, GEU, UNLT, unordered or ordered. - Cirrus Version - must include ge?
-(define_special_predicate "arm_comparison_operator"
+;(define_special_predicate "arm_comparison_operator"
- (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt"))
+(match_code "eq,ne,le,lt,ge,geu,gt,gtu,leu,ltgt,ltu,uneq,unle,unge,ungt")) ;; bad codes removed?
+;(match_code "eq,ne,le,lt,gt,gtu,leu,ltgt,ltu,uneq,unle,unge,ungt")) ;; bad codes removed + ge / geu removed
+
(define_special_predicate "minmax_operator"
(and (match_code "smin,smax,umin,umax")

10
meta/packages/gcc/gcc-4.2.3/arm-crunch-predicates2.patch vendored
View File

@ -1,10 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/predicates.md-original 2007-06-13 12:25:35.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/predicates.md 2007-06-13 12:25:42.000000000 +1000
@@ -206,7 +206,6 @@
|| mode == CC_DEQmode
|| mode == CC_DLEmode
|| mode == CC_DLTmode
- || mode == CC_DGEmode
|| mode == CC_DGTmode
|| mode == CC_DLEUmode
|| mode == CC_DLTUmode

116
meta/packages/gcc/gcc-4.2.3/arm-crunch-predicates3.patch vendored
View File

@ -1,116 +0,0 @@
diff -urN ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/arm.md gcc-4.1.2/gcc/config/arm/arm.md
--- ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/arm.md 2007-06-14 11:50:53.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-14 11:43:17.000000000 +1000
@@ -7488,6 +7488,22 @@
arm_compare_op1);"
)
+;(define_expand "suneq"
+; [(set (match_operand:SI 0 "s_register_operand" "")
+; (uneq:SI (match_dup 1) (const_int 0)))]
+; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
+; "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0,
+; arm_compare_op1);"
+;)
+
+;(define_expand "sltgt"
+; [(set (match_operand:SI 0 "s_register_operand" "")
+; (ltgt:SI (match_dup 1) (const_int 0)))]
+; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
+; "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0,
+; arm_compare_op1);"
+;)
+
;;; DO NOT add patterns for SUNEQ or SLTGT, these can't be represented with
;;; simple ARM instructions.
;
@@ -10284,13 +10284,73 @@
"TARGET_ARM && arm_arch5e"
"pld\\t%a0")
+;; Special predication pattern for Maverick Crunch floating-point
+
+(define_cond_exec
+ [(match_operator 0 "maverick_comparison_operator"
+ [(match_operand:CCFP 1 "cc_register" "")
+ (const_int 0)])]
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ ""
+)
+
+;; Special predication pattern for Maverick Crunch - !CCFP
+
+(define_cond_exec
+ [(match_operator 0 "arm_comparison_operator"
+ [(match_operand:CC_NOOV 1 "cc_register" "")
+ (const_int 0)])]
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ ""
+)
+
+(define_cond_exec
+ [(match_operator 0 "arm_comparison_operator"
+ [(match_operand:CC_Z 1 "cc_register" "")
+ (const_int 0)])]
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ ""
+)
+
+(define_cond_exec
+ [(match_operator 0 "arm_comparison_operator"
+ [(match_operand:CC_SWP 1 "cc_register" "")
+ (const_int 0)])]
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ ""
+)
+
+(define_cond_exec
+ [(match_operator 0 "arm_comparison_operator"
+ [(match_operand:CC_C 1 "cc_register" "")
+ (const_int 0)])]
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ ""
+)
+
+(define_cond_exec
+ [(match_operator 0 "arm_comparison_operator"
+ [(match_operand:CC_N 1 "cc_register" "")
+ (const_int 0)])]
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ ""
+)
+
+(define_cond_exec
+ [(match_operator 0 "arm_comparison_operator"
+ [(match_operand:CC 1 "cc_register" "")
+ (const_int 0)])]
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ ""
+)
+
;; General predication pattern
(define_cond_exec
[(match_operator 0 "arm_comparison_operator"
[(match_operand 1 "cc_register" "")
(const_int 0)])]
- "TARGET_ARM"
+ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
""
)
diff -urN ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/predicates.md gcc-4.1.2/gcc/config/arm/predicates.md
--- ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/predicates.md 2005-09-11 17:38:02.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/predicates.md 2007-06-14 11:46:13.000000000 +1000
@@ -172,7 +172,11 @@
;; True for comparisons other than LTGT or UNEQ.
(define_special_predicate "arm_comparison_operator"
(match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt"))
+
+;; True for comparisons other than GE, GEU, UNLT, UNORDERED or ORDERED - TODO add LTGT and UNEQ - needs extra support elsewhere
+(define_special_predicate "maverick_comparison_operator"
+(match_code "eq,ne,le,lt,gt,gtu,leu,ltu,unle,unge,ungt"))
(define_special_predicate "minmax_operator"
(and (match_code "smin,smax,umin,umax")

153
meta/packages/gcc/gcc-4.2.3/arm-crunch-saveregs.patch vendored
View File

@ -1,153 +0,0 @@
diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c gcc-4.1.2/gcc/config/arm/arm.c
--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c 2007-05-09 16:32:29.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-15 09:39:41.000000000 +1000
@@ -426,7 +435,7 @@
#define FL_STRONG (1 << 8) /* StrongARM */
#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
#define FL_XSCALE (1 << 10) /* XScale */
-#define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
+#define FL_CIRRUS (1 << 11) /* Cirrus Crunch coprocessor. */
#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
media instructions. */
#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
@@ -490,7 +499,7 @@
/* Nonzero if this chip is a StrongARM. */
int arm_tune_strongarm = 0;
-/* Nonzero if this chip is a Cirrus variant. */
+/* Nonzero if this chip supports Cirrus Crunch coprocessor. */
int arm_arch_cirrus = 0;
/* Nonzero if this chip supports Intel Wireless MMX technology. */
@@ -1184,7 +1193,8 @@
else
*/
if (arm_arch_cirrus)
- arm_fpu_arch = FPUTYPE_MAVERICK;
+ /* Cirrus crunch coprocessor still requires soft-float division. */
+ arm_fpu_arch = FPUTYPE_MAVERICK;
else
arm_fpu_arch = FPUTYPE_FPA_EMU2;
#endif
@@ -1567,6 +1577,9 @@
if (regs_ever_live[regno] && !call_used_regs[regno])
return 0;
+ if (TARGET_MAVERICK)
+ return 0;
+
if (TARGET_REALLY_IWMMXT)
for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
if (regs_ever_live[regno] && ! call_used_regs [regno])
@@ -9775,7 +9886,19 @@
/* This variable is for the Virtual Frame Pointer, not VFP regs. */
int vfp_offset = offsets->frame;
- if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
+ if (arm_fpu_arch == FPUTYPE_MAVERICK)
+ {
+ for (reg = LAST_CIRRUS_FP_REGNUM; reg >= FIRST_CIRRUS_FP_REGNUM; reg--)
+ if (regs_ever_live[reg] && !call_used_regs[reg])
+ {
+ floats_offset += 8; /* more problems - futaris? */
+ /* if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1) */
+ asm_fprintf (f, "\tnop\n");
+ asm_fprintf (f, "\tcfldrd\tmvd%d, [%r, #-%d]\n",
+ reg - FIRST_CIRRUS_FP_REGNUM, FP_REGNUM, floats_offset - vfp_offset);
+ }
+ }
+ else if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
{
for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
if (regs_ever_live[reg] && !call_used_regs[reg])
@@ -9924,7 +10047,18 @@
output_add_immediate (operands);
}
- if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
+ if (arm_fpu_arch == FPUTYPE_MAVERICK)
+ { /* order changed - futaris */
+ for (reg = FIRST_CIRRUS_FP_REGNUM; reg <= LAST_CIRRUS_FP_REGNUM; reg++)
+ if (regs_ever_live[reg] && !call_used_regs[reg])
+ {
+ /* if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1) */
+ asm_fprintf (f, "\tnop\n");
+ asm_fprintf (f, "\tcfldrd\tmvd%u, [%r], #8\n",
+ reg - FIRST_CIRRUS_FP_REGNUM, SP_REGNUM);
+ } /* reg problems - futaris */
+ }
+ else if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
{
for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
if (regs_ever_live[reg] && !call_used_regs[reg])
@@ -10429,9 +10563,19 @@
if (! IS_VOLATILE (func_type))
{
+ /* Space for saved MAVERICK registers. */
+ if (arm_fpu_arch == FPUTYPE_MAVERICK)
+ {
+ for (regno = FIRST_CIRRUS_FP_REGNUM; regno <= LAST_CIRRUS_FP_REGNUM; regno++)
+ if (regs_ever_live[regno] && !call_used_regs[regno])
+ saved += 8; // 8 in 3.4.3 patch - futaris;
+ }
+ else
/* Space for saved FPA registers. */
+ {
for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
if (regs_ever_live[regno] && ! call_used_regs[regno])
saved += 12;
+ }
/* Space for saved VFP registers. */
if (TARGET_HARD_FLOAT && TARGET_VFP)
@@ -10739,7 +10882,19 @@
/* Save any floating point call-saved registers used by this
function. */
- if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
+ if (arm_fpu_arch == FPUTYPE_MAVERICK)
+ {
+ for (reg = LAST_CIRRUS_FP_REGNUM; reg >= FIRST_CIRRUS_FP_REGNUM; reg--)
+ if (regs_ever_live[reg] && !call_used_regs[reg])
+ {
+ insn = gen_rtx_PRE_DEC (DFmode, stack_pointer_rtx); /* think these causes problems */
+ insn = gen_rtx_MEM (DFmode, insn);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
+ gen_rtx_REG (DFmode, reg)));
+ RTX_FRAME_RELATED_P (insn) = 1; saved_regs += 8; /* added by futaris */
+ }
+ }
+ else if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
{
for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
if (regs_ever_live[reg] && !call_used_regs[reg])
@@ -15179,6 +15331,9 @@
if (IS_FPA_REGNUM (regno))
return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
+ if (IS_CIRRUS_REGNUM (regno))
+ return 28 + regno - FIRST_CIRRUS_FP_REGNUM;
+
if (IS_VFP_REGNUM (regno))
return 64 + regno - FIRST_VFP_REGNUM;
--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-28 15:42:36.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-28 15:42:48.000000000 +1000
@@ -9800,7 +9800,7 @@
return arm_output_epilogue (next_nonnote_insn (insn));
"
;; Length is absolute worst case
- [(set_attr "length" "44")
+ [(set_attr "length" "108")
(set_attr "type" "block")
;; We don't clobber the conditions, but the potential length of this
;; operation is sufficient to make conditionalizing the sequence
@@ -9818,7 +9818,7 @@
return thumb_unexpanded_epilogue ();
"
; Length is absolute worst case
- [(set_attr "length" "44")
+ [(set_attr "length" "108")
(set_attr "type" "block")
;; We don't clobber the conditions, but the potential length of this
;; operation is sufficient to make conditionalizing the sequence

38
meta/packages/gcc/gcc-4.2.3/arm-crunch-scc.patch vendored
View File

@ -1,38 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-13 12:38:06.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-13 12:40:07.000000000 +1000
@@ -7375,7 +7375,7 @@
(define_expand "sge"
[(set (match_operand:SI 0 "s_register_operand" "")
(ge:SI (match_dup 1) (const_int 0)))]
- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
+ "TARGET_ARM"
"operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
)
@@ -7434,7 +7434,7 @@
(define_expand "sunordered"
[(set (match_operand:SI 0 "s_register_operand" "")
(unordered:SI (match_dup 1) (const_int 0)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0,
arm_compare_op1);"
)
@@ -7442,7 +7442,7 @@
(define_expand "sordered"
[(set (match_operand:SI 0 "s_register_operand" "")
(ordered:SI (match_dup 1) (const_int 0)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0,
arm_compare_op1);"
)
@@ -7467,7 +7467,7 @@
(define_expand "sunlt"
[(set (match_operand:SI 0 "s_register_operand" "")
(unlt:SI (match_dup 1) (const_int 0)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
"operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0,
arm_compare_op1);"
)

33
meta/packages/gcc/gcc-4.2.3/arm-crunch-truncsi-disable-new.patch vendored
View File

@ -1,33 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-25 12:46:22.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-25 12:46:41.000000000 +1000
@@ -337,13 +337,14 @@
"cfcvt64d%?\\t%V0, %V1"
[(set_attr "cirrus" "normal")])
+; appears to be buggy
(define_insn "cirrus_truncsfsi2"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v"))))
(clobber (match_scratch:DF 2 "=v"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
[(set_attr "length" "8")
(set_attr "cirrus" "normal")]
)
--- gcc-4.1.2/gcc/config/arm/arm.md-cfcvt 2007-06-25 12:46:56.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-25 12:48:08.000000000 +1000
@@ -3151,10 +3151,11 @@
}
")
+; appears to be buggy for MAVERICK
(define_expand "fix_truncsfsi2"
[(set (match_operand:SI 0 "s_register_operand" "")
(fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))]
- "TARGET_ARM && TARGET_HARD_FLOAT"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"
if (TARGET_MAVERICK)
{

56
meta/packages/gcc/gcc-4.2.3/arm-crunch-truncsi-disable.patch vendored
View File

@ -1,56 +0,0 @@
--- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-25 12:46:22.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-25 12:46:41.000000000 +1000
@@ -337,21 +337,23 @@
"cfcvt64d%?\\t%V0, %V1"
[(set_attr "cirrus" "normal")])
+; appears to be buggy
(define_insn "cirrus_truncsfsi2"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v"))))
(clobber (match_scratch:DF 2 "=v"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
[(set_attr "length" "8")
(set_attr "cirrus" "normal")]
)
+; appears to be buggy
(define_insn "cirrus_truncdfsi2"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register" "v"))))
(clobber (match_scratch:DF 2 "=v"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
[(set_attr "length" "8")
(set_attr "cirrus" "normal")]
--- gcc-4.1.2/gcc/config/arm/arm.md-cfcvt 2007-06-25 12:46:56.000000000 +1000
+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-25 12:48:08.000000000 +1000
@@ -3151,10 +3151,11 @@
}
")
+; appears to be buggy for MAVERICK
(define_expand "fix_truncsfsi2"
[(set (match_operand:SI 0 "s_register_operand" "")
(fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))]
- "TARGET_ARM && TARGET_HARD_FLOAT"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"
if (TARGET_MAVERICK)
{
@@ -3167,10 +3168,11 @@
}
")
+; appears to be buggy for MAVERICK
(define_expand "fix_truncdfsi2"
[(set (match_operand:SI 0 "s_register_operand" "")
(fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))]
- "TARGET_ARM && TARGET_HARD_FLOAT"
+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"
if (TARGET_MAVERICK)
{

24
meta/packages/gcc/gcc-4.2.3/arm-nolibfloat.patch vendored
View File

@ -1,24 +0,0 @@
# Dimitry Andric <dimitry@andric.com>, 2004-05-01
#
# * Removed the extra -lfloat option from LIBGCC_SPEC, since it isn't needed
# anymore. (The required functions are now in libgcc.)
#
# Fixes errors like
# arm-softfloat-linux-gnu/3.4.0/../../../../arm-softfloat-linux-gnu/bin/ld: cannot find -lfloat
# collect2: ld returned 1 exit status
# make[2]: *** [arm-softfloat-linux-gnu/gcc-3.4.0-glibc-2.3.2/build-glibc/iconvdata/ISO8859-1.so] Error 1
# when building glibc-2.3.3 with gcc-3.4.0 for arm-softfloat
Index: gcc-4.0.2/gcc/config/arm/linux-elf.h
===================================================================
--- gcc-4.0.2.orig/gcc/config/arm/linux-elf.h 2005-03-04 16:14:01.000000000 +0000
+++ gcc-4.0.2/gcc/config/arm/linux-elf.h 2005-11-11 18:02:54.000000000 +0000
@@ -56,7 +56,7 @@
%{shared:-lc} \
%{!shared:%{profile:-lc_p}%{!profile:-lc}}"
-#define LIBGCC_SPEC "%{msoft-float:-lfloat} %{mfloat-abi=soft*:-lfloat} -lgcc"
+#define LIBGCC_SPEC "-lgcc"
/* Provide a STARTFILE_SPEC appropriate for GNU/Linux. Here we add
the GNU/Linux magical crtbegin.o file (see crtstuff.c) which

16
meta/packages/gcc/gcc-4.2.3/arm-softfloat.patch vendored
View File

@ -1,16 +0,0 @@
Index: gcc-4.0.2/gcc/config/arm/t-linux
===================================================================
--- gcc-4.0.2.orig/gcc/config/arm/t-linux 2004-05-15 12:41:35.000000000 +0000
+++ gcc-4.0.2/gcc/config/arm/t-linux 2005-11-11 16:07:53.000000000 +0000
@@ -4,7 +4,10 @@
LIBGCC2_DEBUG_CFLAGS = -g0
LIB1ASMSRC = arm/lib1funcs.asm
-LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx
+LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx \
+ _negdf2 _addsubdf3 _muldivdf3 _cmpdf2 _unorddf2 _fixdfsi _fixunsdfsi \
+ _truncdfsf2 _negsf2 _addsubsf3 _muldivsf3 _cmpsf2 _unordsf2 \
+ _fixsfsi _fixunssfsi _floatdidf _floatdisf _floatundisf _floatundidf
# MULTILIB_OPTIONS = mhard-float/msoft-float
# MULTILIB_DIRNAMES = hard-float soft-float

29
meta/packages/gcc/gcc-4.2.3/arm-thumb-cache.patch vendored
View File

@ -1,29 +0,0 @@
--- gcc-4.1.1/gcc/config/arm/linux-gas.h- 2005-06-25 03:22:41.000000000 +0200
+++ gcc-4.1.1/gcc/config/arm/linux-gas.h 2006-06-18 10:23:46.000000000 +0200
@@ -44,6 +44,7 @@
/* Clear the instruction cache from `beg' to `end'. This makes an
inline system call to SYS_cacheflush. */
+#if !defined(__thumb__)
#define CLEAR_INSN_CACHE(BEG, END) \
{ \
register unsigned long _beg __asm ("a1") = (unsigned long) (BEG); \
@@ -53,3 +54,18 @@
: "=r" (_beg) \
: "0" (_beg), "r" (_end), "r" (_flg)); \
}
+#else
+#define CLEAR_INSN_CACHE(BEG, END) \
+{ \
+ register unsigned long _beg __asm ("a1") = (unsigned long) (BEG); \
+ register unsigned long _end __asm ("a2") = (unsigned long) (END); \
+ register unsigned long _flg __asm ("a3") = 0; \
+ register unsigned long _swi __asm ("a4") = 0xf0002; \
+ __asm __volatile ("push {r7}\n" \
+ " mov r7,a4\n" \
+ " swi 0 @ sys_cacheflush\n" \
+ " pop {r7}\n" \
+ : "=r" (_beg) \
+ : "0" (_beg), "r" (_end), "r" (_flg), "r" (_swi)); \
+}
+#endif

64
meta/packages/gcc/gcc-4.2.3/arm-thumb.patch vendored
View File

@ -1,64 +0,0 @@
#
# Patch managed by http://www.holgerschurig.de/patcher.html
#
--- gcc-4.1.1/gcc/config/arm/lib1funcs.asm~gcc
+++ gcc-4.1.1/gcc/config/arm/lib1funcs.asm
@@ -995,10 +995,24 @@
.code 32
FUNC_START div0
+#if ! defined __thumb__
stmfd sp!, {r1, lr}
mov r0, #SIGFPE
bl SYM(raise) __PLT__
RETLDM r1
+#else
+ push {r1, lr}
+ mov r0, #SIGFPE
+ bl SYM(raise) __PLT__
+#if __ARM_ARCH__ > 4
+ pop {r1, pc}
+#else
+ @ on 4T that won't work
+ pop {r1}
+ pop {r3}
+ bx r3
+#endif
+#endif
FUNC_END div0
@@ -1141,11 +1155,12 @@
code here switches to the correct mode before executing the function. */
.text
- .align 0
+ .align 1
.force_thumb
.macro call_via register
THUMB_FUNC_START _call_via_\register
+ .hidden SYM (_call_via_\register)
bx \register
nop
@@ -1242,6 +1257,7 @@
.code 16
THUMB_FUNC_START _interwork_call_via_\register
+ .hidden SYM (_interwork_call_via_\register)
bx pc
nop
--- gcc-4.1.1/gcc/config/arm/t-linux~gcc
+++ gcc-4.1.1/gcc/config/arm/t-linux
@@ -7,6 +7,7 @@
LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx \
_negdf2 _addsubdf3 _muldivdf3 _cmpdf2 _unorddf2 _fixdfsi _fixunsdfsi \
_truncdfsf2 _negsf2 _addsubsf3 _muldivsf3 _cmpsf2 _unordsf2 \
+ _call_via_rX \
_fixsfsi _fixunssfsi _floatdidf _floatdisf _floatundisf _floatundidf
# MULTILIB_OPTIONS = mhard-float/msoft-float

13
meta/packages/gcc/gcc-4.2.3/cache-amnesia.patch vendored
View File

@ -1,13 +0,0 @@
diff --git a/gcc/configure b/gcc/configure
index 44620ab..6e1830c 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -12272,7 +12272,7 @@ else
esac
saved_CFLAGS="${CFLAGS}"
CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \
- ${realsrcdir}/configure \
+ CONFIG_SITE= ${realsrcdir}/configure --cache-file=./other.cache \
--enable-languages=${enable_languages-all} \
--target=$target_alias --host=$build_alias --build=$build_alias
CFLAGS="${saved_CFLAGS}"

30
meta/packages/gcc/gcc-4.2.3/fortran-cross-compile-hack.patch vendored
View File

@ -1,30 +0,0 @@
* Fortran would have searched for arm-angstrom-gnueabi-gfortran but would have used
used gfortan. For gcc_4.2.2.bb we want to use the gfortran compiler from our cross
directory.
diff --git a/libgfortran/configure b/libgfortran/configure
index f7d86fb..d0966ec 100755
--- a/libgfortran/configure
+++ b/libgfortran/configure
@@ -4475,6 +4475,6 @@ exec 5>>./config.log
# We need gfortran to compile parts of the library
#AC_PROG_FC(gfortran)
-FC="$GFORTRAN"
+#FC="$GFORTRAN"
ac_ext=${FC_SRCEXT-f}
ac_compile='$FC -c $FCFLAGS $FCFLAGS_SRCEXT conftest.$ac_ext >&5'
\ No newline at end of file
diff --git a/libgfortran/configure.ac b/libgfortran/configure.ac
index 4661306..9f83e55 100644
--- a/libgfortran/configure.ac
+++ b/libgfortran/configure.ac
@@ -140,7 +140,7 @@ AC_SUBST(enable_static)
# We need gfortran to compile parts of the library
#AC_PROG_FC(gfortran)
-FC="$GFORTRAN"
+#FC="$GFORTRAN"
AC_PROG_FC(gfortran)
# extra LD Flags which are required for targets

48
meta/packages/gcc/gcc-4.2.3/fortran-static-linking.patch vendored
View File

@ -1,48 +0,0 @@
f951 (fortran) links to MPFR and GMP of our staging area but when executing
the command the libs can not be found. Use rpath like all the other apps in
our staging bin/ directory.
Patch the configure to avoid the regeneration...
Index: gcc-4.2.2/configure
===================================================================
--- gcc-4.2.2.orig/configure 2008-01-15 23:23:41.000000000 +0100
+++ gcc-4.2.2/configure 2008-01-15 23:25:20.000000000 +0100
@@ -2278,14 +2278,14 @@
if test "x$with_mpfr" != x; then
- gmplibs="-L$with_mpfr/lib $gmplibs"
+ gmplibs="-static -L$with_mpfr/lib $gmplibs"
gmpinc="-I$with_mpfr/include"
fi
if test "x$with_mpfr_include" != x; then
gmpinc="-I$with_mpfr_include"
fi
if test "x$with_mpfr_lib" != x; then
- gmplibs="-L$with_mpfr_lib $gmplibs"
+ gmplibs="-static -L$with_mpfr_lib $gmplibs"
fi
# Specify a location for gmp
Index: gcc-4.2.2/configure.in
===================================================================
--- gcc-4.2.2.orig/configure.in 2008-01-15 23:23:41.000000000 +0100
+++ gcc-4.2.2/configure.in 2008-01-15 23:24:36.000000000 +0100
@@ -1066,14 +1066,14 @@
AC_ARG_WITH(mpfr_lib, [ --with-mpfr-lib=PATH Specify the directory for the installed MPFR library])
if test "x$with_mpfr" != x; then
- gmplibs="-L$with_mpfr/lib $gmplibs"
+ gmplibs="-static -L$with_mpfr/lib $gmplibs"
gmpinc="-I$with_mpfr/include"
fi
if test "x$with_mpfr_include" != x; then
gmpinc="-I$with_mpfr_include"
fi
if test "x$with_mpfr_lib" != x; then
- gmplibs="-L$with_mpfr_lib $gmplibs"
+ gmplibs="-static -L$with_mpfr_lib $gmplibs"
fi
# Specify a location for gmp

311
meta/packages/gcc/gcc-4.2.3/gcc-4.0.2-e300c2c3.patch vendored
View File

@ -1,311 +0,0 @@
Adds support for Freescale Power architecture e300c2 and e300c3 cores.
http://www.bitshrine.org/gpp/tc-fsl-x86lnx-e300c3-nptl-4.0.2-2.src.rpm
Leon Woestenberg <leonw@mailcan.com>
Index: gcc-4.1.2/gcc/config/rs6000/e300c2c3.md
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ gcc-4.1.2/gcc/config/rs6000/e300c2c3.md 2007-10-18 15:32:51.000000000 +0200
@@ -0,0 +1,189 @@
+;; Pipeline description for Motorola PowerPC e300c3 core.
+;; Copyright (C) 2003 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to the
+;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+;; MA 02111-1307, USA.
+
+(define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire")
+(define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most")
+
+;; We don't simulate general issue queue (GIC). If we have SU insn
+;; and then SU1 insn, they can not be issued on the same cycle
+;; (although SU1 insn and then SU insn can be issued) because the SU
+;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
+;; multipass insn scheduling will find the situation and issue the SU1
+;; insn and then the SU insn.
+(define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1" "ppce300c3_most")
+
+;; We could describe completion buffers slots in combination with the
+;; retirement units and the order of completion but the result
+;; automaton would behave in the same way because we can not describe
+;; real latency time with taking in order completion into account.
+;; Actually we could define the real latency time by querying reserved
+;; automaton units but the current scheduler uses latency time before
+;; issuing insns and making any reservations.
+;;
+;; So our description is aimed to achieve a insn schedule in which the
+;; insns would not wait in the completion buffer.
+(define_cpu_unit "ppce300c3_retire_0,ppce300c3_retire_1" "ppce300c3_retire")
+
+;; Branch unit:
+(define_cpu_unit "ppce300c3_bu" "ppce300c3_most")
+
+;; IU:
+(define_cpu_unit "ppce300c3_iu0_stage0,ppce300c3_iu1_stage0" "ppce300c3_most")
+
+;; IU: This used to describe non-pipelined division.
+(define_cpu_unit "ppce300c3_mu_div" "ppce300c3_long")
+
+;; SRU:
+(define_cpu_unit "ppce300c3_sru_stage0" "ppce300c3_most")
+
+;; Here we simplified LSU unit description not describing the stages.
+(define_cpu_unit "ppce300c3_lsu" "ppce300c3_most")
+
+;; FPU:
+(define_cpu_unit "ppce300c3_fpu" "ppce300c3_most")
+
+;; The following units are used to make automata deterministic
+(define_cpu_unit "present_ppce300c3_decode_0" "ppce300c3_most")
+(define_cpu_unit "present_ppce300c3_issue_0" "ppce300c3_most")
+(define_cpu_unit "present_ppce300c3_retire_0" "ppce300c3_retire")
+(define_cpu_unit "present_ppce300c3_iu0_stage0" "ppce300c3_most")
+
+;; The following sets to make automata deterministic when option ndfa is used.
+(presence_set "present_ppce300c3_decode_0" "ppce300c3_decode_0")
+(presence_set "present_ppce300c3_issue_0" "ppce300c3_issue_0")
+(presence_set "present_ppce300c3_retire_0" "ppce300c3_retire_0")
+(presence_set "present_ppce300c3_iu0_stage0" "ppce300c3_iu0_stage0")
+
+;; Some useful abbreviations.
+(define_reservation "ppce300c3_decode"
+ "ppce300c3_decode_0|ppce300c3_decode_1+present_ppce300c3_decode_0")
+(define_reservation "ppce300c3_issue"
+ "ppce300c3_issue_0|ppce300c3_issue_1+present_ppce300c3_issue_0")
+(define_reservation "ppce300c3_retire"
+ "ppce300c3_retire_0|ppce300c3_retire_1+present_ppce300c3_retire_0")
+(define_reservation "ppce300c3_iu_stage0"
+ "ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0")
+
+;; Compares can be executed either one of the IU or SRU
+(define_insn_reservation "ppce300c3_cmp" 1
+ (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
+ +ppce300c3_retire")
+
+;; Other one cycle IU insns
+(define_insn_reservation "ppce300c3_iu" 1
+ (and (eq_attr "type" "integer,insert_word")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
+
+;; Branch. Actually this latency time is not used by the scheduler.
+(define_insn_reservation "ppce300c3_branch" 1
+ (and (eq_attr "type" "jmpreg,branch")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_bu,ppce300c3_retire")
+
+;; Multiply is non-pipelined but can be executed in any IU
+(define_insn_reservation "ppce300c3_multiply" 2
+ (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \
+ ppce300c3_iu_stage0+ppce300c3_retire")
+
+;; Divide. We use the average latency time here. We omit reserving a
+;; retire unit because of the result automata will be huge.
+(define_insn_reservation "ppce300c3_divide" 20
+ (and (eq_attr "type" "idiv")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\
+ ppce300c3_mu_div*19")
+
+;; CR logical
+(define_insn_reservation "ppce300c3_cr_logical" 1
+ (and (eq_attr "type" "cr_logical,delayed_cr")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
+
+;; Mfcr
+(define_insn_reservation "ppce300c3_mfcr" 1
+ (and (eq_attr "type" "mfcr")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
+
+;; Mtcrf
+(define_insn_reservation "ppce300c3_mtcrf" 1
+ (and (eq_attr "type" "mtcr")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
+
+;; Mtjmpr
+(define_insn_reservation "ppce300c3_mtjmpr" 1
+ (and (eq_attr "type" "mtjmpr,mfjmpr")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
+
+;; Float point instructions
+(define_insn_reservation "ppce300c3_fpcompare" 3
+ (and (eq_attr "type" "fpcompare")
+ (eq_attr "cpu" "ppce300c3"))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
+
+(define_insn_reservation "ppce300c3_fp" 3
+ (and (eq_attr "type" "fp")
+ (eq_attr "cpu" "ppce300c3"))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
+
+(define_insn_reservation "ppce300c3_dmul" 4
+ (and (eq_attr "type" "dmul")
+ (eq_attr "cpu" "ppce300c3"))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu,nothing,ppce300c3_retire")
+
+; Divides are not pipelined
+(define_insn_reservation "ppce300c3_sdiv" 18
+ (and (eq_attr "type" "sdiv")
+ (eq_attr "cpu" "ppce300c3"))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*17")
+
+(define_insn_reservation "ppce300c3_ddiv" 33
+ (and (eq_attr "type" "ddiv")
+ (eq_attr "cpu" "ppce300c3"))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32")
+
+;; Loads
+(define_insn_reservation "ppce300c3_load" 2
+ (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
+
+(define_insn_reservation "ppce300c3_fpload" 2
+ (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
+ (eq_attr "cpu" "ppce300c3"))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
+
+;; Stores.
+(define_insn_reservation "ppce300c3_store" 2
+ (and (eq_attr "type" "store,store_ux,store_u")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
+
+(define_insn_reservation "ppce300c3_fpstore" 2
+ (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
+ (eq_attr "cpu" "ppce300c3"))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
Index: gcc-4.1.2/gcc/config/rs6000/rs6000.c
===================================================================
--- gcc-4.1.2.orig/gcc/config/rs6000/rs6000.c 2006-12-16 20:24:56.000000000 +0100
+++ gcc-4.1.2/gcc/config/rs6000/rs6000.c 2007-10-18 15:34:26.000000000 +0200
@@ -557,6 +557,21 @@
COSTS_N_INSNS (29), /* ddiv */
};
+/* Instruction costs on E300C2 and E300C3 cores. */
+static const
+struct processor_costs ppce300c2c3_cost = {
+ COSTS_N_INSNS (4), /* mulsi */
+ COSTS_N_INSNS (4), /* mulsi_const */
+ COSTS_N_INSNS (4), /* mulsi_const9 */
+ COSTS_N_INSNS (4), /* muldi */
+ COSTS_N_INSNS (19), /* divsi */
+ COSTS_N_INSNS (19), /* divdi */
+ COSTS_N_INSNS (3), /* fp */
+ COSTS_N_INSNS (4), /* dmul */
+ COSTS_N_INSNS (18), /* sdiv */
+ COSTS_N_INSNS (33), /* ddiv */
+};
+
/* Instruction costs on POWER4 and POWER5 processors. */
static const
struct processor_costs power4_cost = {
@@ -1140,6 +1155,8 @@
/* 8548 has a dummy entry for now. */
{"8548", PROCESSOR_PPC8540,
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_STRICT_ALIGN},
+ {"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
+ {"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK},
{"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
{"970", PROCESSOR_POWER4,
POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
@@ -1529,6 +1546,11 @@
rs6000_cost = &ppc8540_cost;
break;
+ case PROCESSOR_PPCE300C2:
+ case PROCESSOR_PPCE300C3:
+ rs6000_cost = &ppce300c2c3_cost;
+ break;
+
case PROCESSOR_POWER4:
case PROCESSOR_POWER5:
rs6000_cost = &power4_cost;
@@ -16647,6 +16669,8 @@
case CPU_PPC750:
case CPU_PPC7400:
case CPU_PPC8540:
+ case CPU_PPCE300C2:
+ case CPU_PPCE300C3:
return 2;
case CPU_RIOS2:
case CPU_PPC604:
Index: gcc-4.1.2/gcc/config/rs6000/rs6000.h
===================================================================
--- gcc-4.1.2.orig/gcc/config/rs6000/rs6000.h 2006-11-18 01:25:49.000000000 +0100
+++ gcc-4.1.2/gcc/config/rs6000/rs6000.h 2007-10-18 15:32:51.000000000 +0200
@@ -111,6 +111,8 @@
%{mcpu=970: -mpower4 -maltivec} \
%{mcpu=G5: -mpower4 -maltivec} \
%{mcpu=8540: -me500} \
+%{mcpu=e300c2: -mppc} \
+%{mcpu=e300c3: -mppc -mpmr} \
%{maltivec: -maltivec} \
-many"
@@ -211,6 +213,8 @@
PROCESSOR_PPC7400,
PROCESSOR_PPC7450,
PROCESSOR_PPC8540,
+ PROCESSOR_PPCE300C2,
+ PROCESSOR_PPCE300C3,
PROCESSOR_POWER4,
PROCESSOR_POWER5
};
Index: gcc-4.1.2/gcc/config/rs6000/rs6000.md
===================================================================
--- gcc-4.1.2.orig/gcc/config/rs6000/rs6000.md 2006-12-16 20:24:56.000000000 +0100
+++ gcc-4.1.2/gcc/config/rs6000/rs6000.md 2007-10-18 15:32:51.000000000 +0200
@@ -103,7 +103,7 @@
;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in rs6000.h.
-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
+(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,power4,power5"
(const (symbol_ref "rs6000_cpu_attr")))
(automata_option "ndfa")
@@ -119,6 +119,7 @@
(include "7xx.md")
(include "7450.md")
(include "8540.md")
+(include "e300c2c3.md")
(include "power4.md")
(include "power5.md")
Index: gcc-4.1.2/gcc/config.gcc
===================================================================
--- gcc-4.1.2.orig/gcc/config.gcc 2007-10-18 15:26:23.000000000 +0200
+++ gcc-4.1.2/gcc/config.gcc 2007-10-18 15:32:51.000000000 +0200
@@ -2710,7 +2710,7 @@
| rios | rios1 | rios2 | rsc | rsc1 | rs64a \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 505 \
| 601 | 602 | 603 | 603e | ec603e | 604 \
- | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \
+ | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 | e300c[23] \
| 854[08] | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5)
# OK
;;

22
meta/packages/gcc/gcc-4.2.3/gcc41-configure.in.patch vendored
View File

@ -1,22 +0,0 @@
--- gcc-3.4.4/configure.in.orig 2005-08-09 19:57:51.504323183 -0700
+++ gcc-3.4.4/configure.in 2005-08-09 20:00:12.073168623 -0700
@@ -1907,7 +1907,7 @@
*) gxx_include_dir=${with_gxx_include_dir} ;;
esac
-FLAGS_FOR_TARGET=
+FLAGS_FOR_TARGET="$ARCH_FLAGS_FOR_TARGET"
case " $target_configdirs " in
*" newlib "*)
case " $target_configargs " in
--- gcc-3.4.4/configure.orig 2005-08-09 21:02:29.668360660 -0700
+++ gcc-3.4.4/configure 2005-08-09 21:02:50.157649970 -0700
@@ -2669,7 +2669,7 @@
*) gxx_include_dir=${with_gxx_include_dir} ;;
esac
-FLAGS_FOR_TARGET=
+FLAGS_FOR_TARGET="$ARCH_FLAGS_FOR_TARGET"
case " $target_configdirs " in
*" newlib "*)
case " $target_configargs " in

40
meta/packages/gcc/gcc-4.2.3/gfortran.patch vendored
View File

@ -1,40 +0,0 @@
The patch below fixes a crash building libgfortran on arm-linux-gnueabi.
This target doesn't really have a 128-bit integer type, however it does use
TImode to represent the return value of certain special ABI defined library
functions. This results in type_for_size(TImode) being called.
Because TImode deosn't correspond to any gfortran integer kind
gfc_type_for_size returns NULL and we segfault shortly after.
The patch below fixes this by making gfc_type_for_size handle TImode in the
same way as the C frontend.
Tested on x86_64-linux and arm-linux-gnueabi.
Applied to trunk.
Paul
2007-05-15 Paul Brook <paul@codesourcery.com>
gcc/fortran/
* trans-types.c (gfc_type_for_size): Handle signed TImode.
Index: gcc-4.2.1/gcc/fortran/trans-types.c
===================================================================
--- gcc-4.2.1/gcc/fortran/trans-types.c (revision 170435)
+++ gcc-4.2.1/gcc/fortran/trans-types.c (working copy)
@@ -1800,6 +1800,13 @@ gfc_type_for_size (unsigned bits, int un
if (type && bits == TYPE_PRECISION (type))
return type;
}
+
+ /* Handle TImode as a special case because it is used by some backends
+ (eg. ARM) even though it is not available for normal use. */
+#if HOST_BITS_PER_WIDE_INT >= 64
+ if (bits == TYPE_PRECISION (intTI_type_node))
+ return intTI_type_node;
+#endif
}
else
{

24
meta/packages/gcc/gcc-4.2.3/intermask-bigendian.patch vendored
View File

@ -1,24 +0,0 @@
--- gcc-4.2.0/gcc/config/arm/bpabi.h
+++ gcc-4.2.0/gcc/config/arm/bpabi.h
@@ -33,9 +33,19 @@
#undef FPUTYPE_DEFAULT
#define FPUTYPE_DEFAULT FPUTYPE_VFP
+/*
+ * 'config.gcc' defines TARGET_BIG_ENDIAN_DEFAULT as 1 for arm*b-*
+ * (big endian) configurations.
+ */
+#if TARGET_BIG_ENDIAN_DEFAULT
+#define TARGET_ENDIAN_DEFAULT MASK_BIG_END
+#else
+#define TARGET_ENDIAN_DEFAULT 0
+#endif
+
/* EABI targets should enable interworking by default. */
#undef TARGET_DEFAULT
-#define TARGET_DEFAULT MASK_INTERWORK
+#define TARGET_DEFAULT (MASK_INTERWORK | TARGET_ENDIAN_DEFAULT)
/* The ARM BPABI functions return a boolean; they use no special
calling convention. */

22
meta/packages/gcc/gcc-4.2.3/ldflags.patch vendored
View File

@ -1,22 +0,0 @@
--- /tmp/Makefile.in 2006-02-23 20:56:01.399758728 +0100
+++ gcc-4.1-20060217/Makefile.in 2006-02-23 20:56:16.874406224 +0100
@@ -334,7 +334,7 @@
CXXFLAGS_FOR_TARGET = $(CXXFLAGS) $(SYSROOT_CFLAGS_FOR_TARGET)
LIBCFLAGS_FOR_TARGET = $(CFLAGS_FOR_TARGET)
LIBCXXFLAGS_FOR_TARGET = $(CXXFLAGS_FOR_TARGET) -fno-implicit-templates
-LDFLAGS_FOR_TARGET =
+LDFLAGS_FOR_TARGET = @LDFLAGS@
PICFLAG_FOR_TARGET =
# ------------------------------------
--- /tmp/Makefile.tpl 2006-02-23 20:50:34.077519272 +0100
+++ gcc-4.1-20060217/Makefile.tpl 2006-02-23 21:04:31.092273688 +0100
@@ -337,7 +337,7 @@
CXXFLAGS_FOR_TARGET = $(CXXFLAGS) $(SYSROOT_CFLAGS_FOR_TARGET)
LIBCFLAGS_FOR_TARGET = $(CFLAGS_FOR_TARGET)
LIBCXXFLAGS_FOR_TARGET = $(CXXFLAGS_FOR_TARGET) -fno-implicit-templates
-LDFLAGS_FOR_TARGET =
+LDFLAGS_FOR_TARGET = @LDFLAGS@
PICFLAG_FOR_TARGET =
# ------------------------------------

22
meta/packages/gcc/gcc-4.2.3/sdk-libstdc++-includes.patch vendored
View File

@ -1,22 +0,0 @@
--- gcc-3.4.1/libstdc++-v3/libmath/Makefile.am~ 2003-08-27 22:29:42.000000000 +0100
+++ gcc-3.4.1/libstdc++-v3/libmath/Makefile.am 2004-07-22 16:41:45.152130128 +0100
@@ -32,7 +32,7 @@
libmath_la_SOURCES = stubs.c
-AM_CPPFLAGS = $(CANADIAN_INCLUDES)
+AM_CPPFLAGS = $(CANADIAN_INCLUDES) -I$(toplevel_srcdir)/include
# Only compiling "C" sources in this directory.
LIBTOOL = @LIBTOOL@ --tag CC
--- gcc-3.4.1/libstdc++-v3/fragment.am.old 2004-07-22 18:24:58.024083656 +0100
+++ gcc-3.4.1/libstdc++-v3/fragment.am 2004-07-22 18:24:59.019932264 +0100
@@ -18,7 +18,7 @@
$(WARN_FLAGS) $(WERROR) -fdiagnostics-show-location=once
# -I/-D flags to pass when compiling.
-AM_CPPFLAGS = $(GLIBCXX_INCLUDES)
+AM_CPPFLAGS = $(GLIBCXX_INCLUDES) -I$(toplevel_srcdir)/include

11
meta/packages/gcc/gcc-4.2.3/sh3-installfix-fixheaders.patch vendored
View File

@ -1,11 +0,0 @@
--- gcc-4.1.1/gcc/Makefile.in_orig 2007-01-31 21:24:23.000000000 +0000
+++ gcc-4.1.1/gcc/Makefile.in 2007-01-31 21:24:43.000000000 +0000
@@ -3772,8 +3772,6 @@
$(INSTALL_SCRIPT) $(mkinstalldirs) \
$(DESTDIR)$(itoolsdir)/mkinstalldirs ; \
$(INSTALL_SCRIPT) $(srcdir)/fixproto $(DESTDIR)$(itoolsdir)/fixproto ; \
- $(INSTALL_PROGRAM) build/fix-header$(build_exeext) \
- $(DESTDIR)$(itoolsdir)/fix-header$(build_exeext) ; \
else :; fi
echo 'SYSTEM_HEADER_DIR="'"$(SYSTEM_HEADER_DIR)"'"' \
> $(DESTDIR)$(itoolsdatadir)/mkheaders.conf

12
meta/packages/gcc/gcc-4.2.3/unbreak-armv4t.patch vendored
View File

@ -1,12 +0,0 @@
diff -urN gcc-4.1.1/gcc/config/arm/linux-eabi.h gcc-4.1.1-arm9tdmi/gcc/config/arm/linux-eabi.h
--- gcc-4.1.1/gcc/config/arm/linux-eabi.h 2006-10-22 11:11:49.000000000 -0700
+++ gcc-4.1.1-arm9tdmi/gcc/config/arm/linux-eabi.h 2006-10-24 21:34:01.000000000 -0700
@@ -45,7 +45,7 @@
The ARM10TDMI core is the default for armv5t, so set
SUBTARGET_CPU_DEFAULT to achieve this. */
#undef SUBTARGET_CPU_DEFAULT
-#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm10tdmi
+#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm9tdmi
#undef SUBTARGET_EXTRA_LINK_SPEC
#define SUBTARGET_EXTRA_LINK_SPEC " -m armelf_linux_eabi"

31
meta/packages/gcc/gcc-4.2.3/zecke-no-host-includes.patch vendored
View File

@ -1,31 +0,0 @@
Index: gcc-4.0.2/gcc/c-incpath.c
===================================================================
--- gcc-4.0.2.orig/gcc/c-incpath.c 2005-01-23 16:05:27.000000000 +0100
+++ gcc-4.0.2/gcc/c-incpath.c 2006-05-15 21:23:02.000000000 +0200
@@ -350,6 +350,26 @@
p->construct = 0;
p->user_supplied_p = user_supplied_p;
+#ifdef CROSS_COMPILE
+ /* A common error when cross compiling is including
+ host headers. This code below will try to fail fast
+ for cross compiling. Currently we consider /usr/include,
+ /opt/include and /sw/include as harmful. */
+ {
+ /* printf("Adding Path: %s\n", p->name ); */
+ if( strstr(p->name, "/usr/include" ) == p->name ) {
+ fprintf(stderr, _("BUILD ISOLATION FAILURE: /usr/include in INCLUDEPATH: %s\n Please fix the flags passed to the compiler to use the correct prefix.\n"), p->name);
+ abort();
+ } else if( strstr(p->name, "/sw/include") == p->name ) {
+ fprintf(stderr, _("BUILD ISOLATION FAILURE: /sw/include in INCLUDEPATH: %s\n Please fix the flags passed to the compiler to use the correct prefix.\n"), p->name);
+ abort();
+ } else if( strstr(p->name, "/opt/include") == p->name ) {
+ fprintf(stderr, _("BUILD ISOLATION FAILURE: /opt/include in INCLUDEPATH: %s\n Please fix the flags passed to the compiler to use the correct prefix.\n"), p->name);
+ abort();
+ }
+ }
+#endif
+
add_cpp_dir_path (p, chain);
}

16
meta/packages/gcc/gcc-4.2.3/zecke-xgcc-cpp.patch vendored
View File

@ -1,16 +0,0 @@
upstream: n/a
comment: Use the preprocessor we have just compiled instead the one of
the system. There might be incompabilities between us and them.
Index: gcc-4.1.1/Makefile.in
===================================================================
--- gcc-4.1.1.orig/Makefile.in 2006-08-06 13:32:44.000000000 +0200
+++ gcc-4.1.1/Makefile.in 2006-08-06 13:32:46.000000000 +0200
@@ -194,6 +194,7 @@
AS="$(COMPILER_AS_FOR_TARGET)"; export AS; \
CC="$(CC_FOR_TARGET)"; export CC; \
CFLAGS="$(CFLAGS_FOR_TARGET)"; export CFLAGS; \
+ CPP="$(CC_FOR_TARGET) -E"; export CCP; \
CONFIG_SHELL="$(SHELL)"; export CONFIG_SHELL; \
CPPFLAGS="$(CPPFLAGS_FOR_TARGET)"; export CPPFLAGS; \
CXXFLAGS="$(CXXFLAGS_FOR_TARGET)"; export CXXFLAGS; \

23
meta/packages/gcc/gcc-cross-canadian_4.2.3.bb
View File

@ -1,23 +0,0 @@
inherit cross-canadian
require gcc-${PV}.inc
require gcc-cross-canadian.inc
require gcc-configure-sdk.inc
require gcc-package-sdk.inc
PR = "r8"
DEPENDS += "gmp-nativesdk mpfr-nativesdk"
RDEPENDS_${PN} += "mpfr-nativesdk"
SYSTEMHEADERS = "/usr/include"
SYSTEMLIBS1 = "/usr/lib/"
EXTRA_OECONF += "--disable-libunwind-exceptions --disable-libssp \
--disable-libgomp --disable-libmudflap \
--with-mpfr=${STAGING_DIR_HOST}${layout_exec_prefix}"
# to find libmpfr
# export LD_LIBRARY_PATH = "{STAGING_DIR_HOST}${layout_exec_prefix}"
PARALLEL_MAKE = ""

2
meta/packages/gcc/gcc-cross-initial_4.2.3.bb
View File

@ -1,2 +0,0 @@
require gcc-cross_${PV}.bb
require gcc-cross-initial.inc

2
meta/packages/gcc/gcc-cross-intermediate_4.2.3.bb
View File

@ -1,2 +0,0 @@
require gcc-cross_${PV}.bb
require gcc-cross-intermediate.inc

10
meta/packages/gcc/gcc-cross_4.2.3.bb
View File

@ -1,10 +0,0 @@
PR = "r7"
require gcc-${PV}.inc
require gcc-cross4.inc
SRC_URI_append_fail-fast = " file://zecke-no-host-includes.patch;patch=1 "
EXTRA_OECONF += "--disable-libunwind-exceptions --with-mpfr=${STAGING_DIR_NATIVE}${prefix_native}"
ARCH_FLAGS_FOR_TARGET += "-isystem${STAGING_DIR_TARGET}${target_includedir}"

2
meta/packages/gcc/gcc-crosssdk-initial_4.2.3.bb
View File

@ -1,2 +0,0 @@
require gcc-cross-initial_${PV}.bb
require gcc-crosssdk-initial.inc

3
meta/packages/gcc/gcc-crosssdk-intermediate_4.2.3.bb
View File

@ -1,3 +0,0 @@
require gcc-cross-intermediate_${PV}.bb
require gcc-crosssdk-intermediate.inc
PR = "r1"

2
meta/packages/gcc/gcc-crosssdk_4.2.3.bb
View File

@ -1,2 +0,0 @@
require gcc-cross_${PV}.bb
require gcc-crosssdk.inc

10
meta/packages/gcc/gcc-runtime_4.2.3.bb
View File

@ -1,10 +0,0 @@
PR = "r10"
require gcc-${PV}.inc
require gcc-configure-runtime.inc
require gcc-package-runtime.inc
SRC_URI_append = "file://fortran-cross-compile-hack.patch;patch=1"
ARCH_FLAGS_FOR_TARGET += "-isystem${STAGING_INCDIR}"

10
meta/packages/gcc/gcc_4.2.3.bb
View File

@ -1,10 +0,0 @@
PR = "r7"
require gcc-${PV}.inc
require gcc-configure-target.inc
require gcc-package-target.inc
SRC_URI_append = "file://fortran-cross-compile-hack.patch;patch=1"
ARCH_FLAGS_FOR_TARGET += "-isystem${STAGING_INCDIR}"