65 lines
1.7 KiB
C
65 lines
1.7 KiB
C
/*
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* (c) 2012 Juergen Beisert <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Collection of some SoC specific functions
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*/
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#include <common.h>
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#include <init.h>
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#include <mach/imx-regs.h>
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#include <io.h>
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#define HW_CLKCTRL_RESET 0x1e0
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# define HW_CLKCTRL_RESET_CHIP (1 << 1)
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#define HW_CLKCTRL_WDOG_POR_DISABLE (1 << 5)
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/* Reset the full i.MX28 SoC via a chipset feature */
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void __noreturn reset_cpu(unsigned long addr)
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{
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u32 reg;
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reg = readl(IMX_CCM_BASE + HW_CLKCTRL_RESET);
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writel(reg | HW_CLKCTRL_RESET_CHIP, IMX_CCM_BASE + HW_CLKCTRL_RESET);
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while (1)
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;
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/*NOTREACHED*/
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}
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EXPORT_SYMBOL(reset_cpu);
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static int imx28_init(void)
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{
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u32 reg;
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/*
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* The default setting for the WDT is to do a POR. If the SoC is only
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* powered via battery, then a WDT reset powers the chip down instead
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* of resetting it. Use a software reset only.
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*/
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reg = readl(IMX_CCM_BASE + HW_CLKCTRL_RESET) |
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HW_CLKCTRL_WDOG_POR_DISABLE;
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writel(reg, IMX_CCM_BASE + HW_CLKCTRL_RESET);
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return 0;
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}
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postcore_initcall(imx28_init);
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static int imx28_devices_init(void)
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{
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add_generic_device("imx28-dma-apbh", 0, NULL, MXS_APBH_BASE, 0x2000, IORESOURCE_MEM, NULL);
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add_generic_device("imx28-clkctrl", 0, NULL, IMX_CCM_BASE, 0x100, IORESOURCE_MEM, NULL);
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return 0;
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}
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postcore_initcall(imx28_devices_init);
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