233 lines
5.2 KiB
C
233 lines
5.2 KiB
C
/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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/*
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* CPU specific code for the MPC5xxx CPUs
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*/
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#include <common.h>
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#include <command.h>
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#include <mach/mpc5xxx.h>
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#include <asm/processor.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <init.h>
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#include <types.h>
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#include <errno.h>
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#include <of.h>
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#include <mach/clocks.h>
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int checkcpu (void)
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{
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ulong clock = get_cpu_clock();
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uint svr, pvr;
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puts ("CPU: ");
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svr = get_svr();
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pvr = get_pvr();
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switch (SVR_VER (svr)) {
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case SVR_MPC5200:
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printf ("MPC5200");
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break;
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default:
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printf ("MPC52?? (SVR %08x)", svr);
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break;
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}
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printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr),
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PVR_MAJ(pvr), PVR_MIN(pvr));
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printf (" at %ld Hz\n", clock);
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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void __noreturn reset_cpu (unsigned long addr)
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{
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ulong msr;
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/* Interrupts and MMU off */
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__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
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msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
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__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
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/* Charge the watchdog timer */
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*(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0x0001000f;
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*(vu_long *)(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden|ce|timer_ms */
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while(1);
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}
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/* ------------------------------------------------------------------------- */
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#ifdef CONFIG_OFTREE
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static int of_mpc5200_fixup(struct device_node *root, void *unused)
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{
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struct device_node *node;
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int div = in_8((void*)CFG_MBAR + 0x204) & 0x0020 ? 8 : 4;
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node = of_find_node_by_path("/cpus/PowerPC,5200@0");
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if (!node)
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return -EINVAL;
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of_property_write_u32(node, "timebase-frequency", get_timebase_clock());
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of_property_write_u32(node, "bus-frequency", get_bus_clock());
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of_property_write_u32(node, "clock-frequency", get_cpu_clock());
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node = of_find_node_by_path("/soc5200@f0000000");
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if (!node)
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return -EINVAL;
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of_property_write_u32(node, "bus-frequency", get_ipb_clock());
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of_property_write_u32(node, "system-frequency", get_bus_clock() * div);
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return 0;
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}
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static int of_register_mpc5200_fixup(void)
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{
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return of_register_fixup(of_mpc5200_fixup, NULL);
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}
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late_initcall(of_register_mpc5200_fixup);
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#endif
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unsigned long mpc5200_get_sdram_size(unsigned int cs)
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{
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unsigned long size;
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if (cs > 1)
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return 0;
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/* retrieve size of memory connected to SDRAM CS0 */
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size = *(vu_long *)(MPC5XXX_SDRAM_CS0CFG + (cs * 4)) & 0xFF;
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if (size >= 0x13)
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size = (1 << (size - 0x13)) << 20;
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else
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size = 0;
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return size;
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}
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int mpc5200_setup_bus_clocks(unsigned int ipbdiv, unsigned long pcidiv)
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{
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u32 cdmcfg = *(vu_long *)MPC5XXX_CDM_CFG;
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cdmcfg &= ~0x103;
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switch (ipbdiv) {
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case 1:
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break;
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case 2:
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cdmcfg |= 0x100;
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break;
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default:
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return -EINVAL;
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}
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switch (pcidiv) {
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case 1:
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if (ipbdiv == 2)
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return -EINVAL;
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break;
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case 2:
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if (ipbdiv == 1)
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cdmcfg |= 0x1; /* ipb / 2 */
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break;
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case 4:
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cdmcfg |= 0x2; /* xlb / 4 */
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break;
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default:
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return -EINVAL;
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}
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*(vu_long *)MPC5XXX_CDM_CFG = cdmcfg;
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return 0;
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}
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struct mpc5200_cs {
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void *start;
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void *stop;
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void *cfg;
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unsigned int addecr;
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};
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static struct mpc5200_cs chipselects[] = {
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{
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.start = (void *)MPC5XXX_CS0_START,
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.stop = (void *)MPC5XXX_CS0_STOP,
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.cfg = (void *)MPC5XXX_CS0_CFG,
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.addecr = 1 << 16,
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}, {
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.start = (void *)MPC5XXX_CS1_START,
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.stop = (void *)MPC5XXX_CS1_STOP,
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.cfg = (void *)MPC5XXX_CS1_CFG,
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.addecr = 1 << 17,
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}, {
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.start = (void *)MPC5XXX_CS2_START,
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.stop = (void *)MPC5XXX_CS2_STOP,
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.cfg = (void *)MPC5XXX_CS2_CFG,
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.addecr = 1 << 18,
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}, {
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.start = (void *)MPC5XXX_CS3_START,
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.stop = (void *)MPC5XXX_CS3_STOP,
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.cfg = (void *)MPC5XXX_CS3_CFG,
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.addecr = 1 << 19,
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}, {
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.start = (void *)MPC5XXX_CS4_START,
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.stop = (void *)MPC5XXX_CS4_STOP,
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.cfg = (void *)MPC5XXX_CS4_CFG,
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.addecr = 1 << 20,
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}, {
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.start = (void *)MPC5XXX_CS5_START,
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.stop = (void *)MPC5XXX_CS5_STOP,
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.cfg = (void *)MPC5XXX_CS5_CFG,
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.addecr = 1 << 21,
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}, {
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.start = (void *)MPC5XXX_CS6_START,
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.stop = (void *)MPC5XXX_CS6_STOP,
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.cfg = (void *)MPC5XXX_CS6_CFG,
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.addecr = 1 << 26,
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}, {
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.start = (void *)MPC5XXX_CS7_START,
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.stop = (void *)MPC5XXX_CS7_STOP,
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.cfg = (void *)MPC5XXX_CS7_CFG,
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.addecr = 1 << 27,
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}, {
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.start = (void *)MPC5XXX_BOOTCS_START,
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.stop = (void *)MPC5XXX_BOOTCS_STOP,
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.cfg = (void *)MPC5XXX_CS0_CFG,
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.addecr = 1 << 25,
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},
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};
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void mpc5200_setup_cs(int cs, unsigned long start, unsigned long size, u32 cfg)
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{
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u32 addecr;
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out_be32(chipselects[cs].start, START_REG(start));
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out_be32(chipselects[cs].stop, STOP_REG(start, size));
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out_be32(chipselects[cs].cfg, cfg);
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addecr = in_be32((void *)MPC5XXX_ADDECR);
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addecr |= chipselects[cs].addecr | 1;
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out_be32((void *)MPC5XXX_ADDECR, addecr);
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}
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