148 lines
2.9 KiB
C
148 lines
2.9 KiB
C
/*
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* cpu.c - A few helper functions for ARM
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*
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* Copyright (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/**
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* @file
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* @brief A few helper functions for ARM
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*/
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#include <common.h>
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#include <init.h>
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#include <command.h>
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#include <cache.h>
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#include <asm/mmu.h>
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#include <asm/system.h>
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#include <asm/memory.h>
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#include <asm-generic/memory_layout.h>
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#include <asm/cputype.h>
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#include <asm/cache.h>
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#include <asm/ptrace.h>
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#include "mmu.h"
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/**
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* Enable processor's instruction cache
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*/
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void icache_enable(void)
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{
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u32 r;
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r = get_cr();
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r |= CR_I;
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set_cr(r);
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}
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/**
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* Disable processor's instruction cache
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*/
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void icache_disable(void)
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{
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u32 r;
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r = get_cr();
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r &= ~CR_I;
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set_cr(r);
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}
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/**
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* Detect processor's current instruction cache status
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* @return 0=disabled, 1=enabled
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*/
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int icache_status(void)
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{
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return (get_cr () & CR_I) != 0;
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}
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/*
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* SoC like the ux500 have the l2x0 always enable
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* with or without MMU enable
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*/
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struct outer_cache_fns outer_cache;
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/*
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* Clean and invalide caches, disable MMU
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*/
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void mmu_disable(void)
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{
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if (outer_cache.disable)
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outer_cache.disable();
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__mmu_cache_flush();
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__mmu_cache_off();
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}
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/**
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* Disable MMU and D-cache, flush caches
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* @return 0 (always)
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*
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* This function is called by shutdown_barebox to get a clean
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* memory/cache state.
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*/
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void arch_shutdown(void)
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{
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uint32_t r;
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mmu_disable();
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flush_icache();
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/*
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* barebox normally does not use interrupts, but some functionalities
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* (eg. OMAP4_USBBOOT) require them enabled. So be sure interrupts are
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* disabled before exiting.
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*/
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__asm__ __volatile__("mrs %0, cpsr" : "=r"(r));
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r |= PSR_I_BIT;
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__asm__ __volatile__("msr cpsr, %0" : : "r"(r));
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}
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extern unsigned long arm_stack_top;
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static int arm_request_stack(void)
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{
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if (!request_sdram_region("stack", arm_stack_top - STACK_SIZE, STACK_SIZE))
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pr_err("Error: Cannot request SDRAM region for stack\n");
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return 0;
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}
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coredevice_initcall(arm_request_stack);
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#ifdef CONFIG_THUMB2_BAREBOX
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static void thumb2_execute(void *func, int argc, char *argv[])
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{
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/*
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* Switch back to ARM mode before executing external
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* programs.
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*/
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__asm__ __volatile__ (
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"mov r0, #0\n"
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"mov r1, %0\n"
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"mov r2, %1\n"
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"bx %2\n"
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:
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: "r" (argc - 1), "r" (&argv[1]), "r" (func)
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: "r0", "r1", "r2"
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);
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}
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static int execute_init(void)
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{
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do_execute = thumb2_execute;
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return 0;
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}
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postcore_initcall(execute_init);
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#endif
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