172 lines
6.2 KiB
C
172 lines
6.2 KiB
C
/*
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* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <asm/byteorder.h>
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#include <asm/barebox-arm-head.h>
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#include <mach/imx-flash-header.h>
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#include <mach/imx6-regs.h>
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void __naked __flash_header_start go(void)
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{
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barebox_arm_head();
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}
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#define DCD(a, v) { .addr = cpu_to_be32(a), .val = cpu_to_be32(v), }
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struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5a8, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5b0, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x524, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x51c, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x518, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x50c, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5b8, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5c0, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5ac, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5b4, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x528, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x520, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x514, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x510, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5bc, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5c4, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x56c, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x578, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x588, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x594, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x57c, 0x00020030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x590, 0x00003000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x598, 0x00003000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x58c, 0x00000000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x59c, 0x00003030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x5a0, 0x00003030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x784, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x788, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x794, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x79c, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x7a0, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x7a4, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x7a8, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x748, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x74c, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x750, 0x00020000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x758, 0x00000000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x774, 0x00020000),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x78c, 0x00000030),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x798, 0x000C0000),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x81c, 0x33333333),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x820, 0x33333333),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x824, 0x33333333),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x828, 0x33333333),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x81c, 0x33333333),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x820, 0x33333333),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x824, 0x33333333),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x828, 0x33333333),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x018, 0x00081740),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00008000),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x00c, 0x555A7975),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x030, 0x005B0E21),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x008, 0x09444040),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x004, 0x00025576),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x040, 0x00000027),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x000, 0xC31A0000),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04088032),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x0408803A),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00008033),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00428031),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00428039),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x09408030),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x09408038),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04008040),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04008048),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x800, 0xA1380003),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x800, 0xA1380003),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x020, 0x00005800),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x818, 0x00022227),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x818, 0x00022227),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x83c, 0x434B0350),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x840, 0x034C0359),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x83c, 0x434B0350),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x840, 0x03650348),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x848, 0x4436383B),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x848, 0x39393341),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x850, 0x35373933),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x850, 0x48254A36),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x810, 0x001F001F),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x80c, 0x00440044),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x810, 0x00440044),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800),
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DCD(MX6_MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00000000),
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DCD(MX6_MMDC_P0_BASE_ADDR + 0x404, 0x00011006),
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/* enable AXI cache for VDOA/VPU/IPU */
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DCD(MX6_IOMUXC_BASE_ADDR + 0x010, 0xf00000ff),
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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DCD(MX6_IOMUXC_BASE_ADDR + 0x018, 0x007f007f),
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DCD(MX6_IOMUXC_BASE_ADDR + 0x01c, 0x007f007f),
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};
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#define APP_DEST 0x10000000
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struct imx_flash_header_v2 __flash_header_section flash_header = {
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.header.tag = IVT_HEADER_TAG,
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.header.length = cpu_to_be16(32),
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.header.version = IVT_VERSION,
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.entry = APP_DEST + 0x1000,
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.dcd_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, dcd),
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.boot_data_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, boot_data),
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.self = APP_DEST + 0x400,
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.boot_data.start = APP_DEST,
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.boot_data.size = 0x40000,
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.dcd.header.tag = DCD_HEADER_TAG,
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.dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) + sizeof(dcd_entry)),
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.dcd.header.version = DCD_VERSION,
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.dcd.command.tag = DCD_COMMAND_WRITE_TAG,
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.dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)),
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.dcd.command.param = DCD_COMMAND_WRITE_PARAM,
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};
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