To avoid unnecessary preset initial state chipselect lines for SPI, set it to
inactive state when adding devices to the system.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The mc13xxx driver correctly bails out on failure, but leaves
mc_dev initialized, so a later mc13xxx_get won't fail but returns
an invalid pointer. Fix this. While at it, remove some superfluous
code from mc13xxx_get.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This causes allocation of a free id and avoids conflicts if multiple
identical SPI devices are attached.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Ok, I assume this should go into separate series. It fits both S5PV210 and S3C6410.
This adds support for S3C and S5P architectures (all of my knowledge) to the
serial driver. Since the only difference between them is in clock handling,
this is moved to an arch-dependent separate function.
Most modern architectures should define S3C_UART_HAS_UBRDIVSLOT and S3C_UART_HAS_UINTM.
This adds support for most
Signed-off-by: Alexey Galakhov <agalakhov@gmail.com>
Signed-off-by: Juergen Beisewrt <kernel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
If DEBUG is defined it fails due to wrong variable names
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The netX internal UART latches register settings and internally uses
them only if written in the correct order. Other orders may work, but
sometimes the UART gets stuck, as the baudrate has not correctly been
set.
Signed-off-by: Michael Trensch <MTrensch@gmail.com>
Acked-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Instead of directly accessing the struct member of struct param_d
use the provided getter function.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some phys need board specific fixups. To be able to do this
from board code add mii_open/mii_close functions so that the
board can use the regular mii_read/mii_write functions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Currently only 100Mb/s is tested. Freescale's U-Boot suggests that
there are some additional adjustments necessary for Gigabit support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Backport 2 fixes back from Linux kernel (title verbatim from
Linux kernel log) :
- docg3 fix in-middle of blocks reads
- docg3 reduce read alignment burden
These 2 enable partial reads from the MTD (ie. read only the
111 first bytes), which enable linux kernel booting or UBIFS
from barebox.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As per MMC spec, once power has been applied to an SD card, the card
can take as much as 250ms to complete its power-up cycle, and become
responsive to CMD0.
When this delay was not in place, activating the SD card in the env
init failed sometimes. With it, no more failure are observed.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The pxamci driver was not waiting for the BUSY line to be
deasserted. This was specifically breaking the CMD12 at
the end of block multiple writes, when the SD card had not
time enough to commit the last write.
Fix it by waiting for PRG_DONE bit (which is actually the
busy signal end condition).
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The pxamci requires a bit to be set in the command control
register when a CMD12 is sent. Set it, as required in the
PXA Developer Manuel, chapter "Stop Data Transmission
Command (CMD12 or IO/Abort with CMD52)".
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When preparing a command, apply a mask so that only the command part
will be used for the switch case. This will be more robust
for future command response types.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fix clock handling accordingly to PXA manual :
- enable the MMC controller clock once and for all
- only disable the MMC bus clock when changing the MMCLK by
adjusting the clock ratio, else let the controller and SD
card shut down the clock as the see fit.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Instead of using hard encoded values in the code, use defines to setup
the timeouts of reads/writes/commands.
Fix the read timeout as defined in the PXA Developer Manual.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Currently all devices have an id meaning that all devicenames
end with a number. This patch adds a DEVICE_ID_SINGLE to make
it ppossible to register a device without an id assigned to
it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This is based on the following U-Boot commit:
commit 5f4b4f2fed3ab8590c8c06b78642f8c1467acacf
Author: Vincent Palatin <vpalatin@chromium.org>
Date: Mon Dec 5 14:52:22 2011 -0800
ehci: speed up initialization
According to EHCI specification v1.0, the controller should stabilize
the power on a port at most 20 ms after the port power bit transition.
So, we put this setting in the virtual descriptor corresponding field,
(bPwrOn2PwrGood = 10 => 10 x 2ms = 20ms), this saves about 500ms at each
controller initialization/enumeration.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
for chache handling the ehci driver iterates over the hardware lists
of QHs/TDs. As we have a fixed number of maximum entries in this lists
we can allocate them as arrays and and clean/invalidate the arrays
instead which is much simpler. While at it, move the allocation to
ehci_probe so that we do not lose memory each time ehci_init is called.
Also, use memalign to allocate the QHs/TDs.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Also renamed config option name to MFD_MC13XXX.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The intel cfi buffer write has a problem with writing when
the alignment of the buffer in memory is smaller than the
flash bus width.
This patch fixes a alignment problem which may show during this
scenario:
- 32 or 64 attached NOR flash
- flashing an image directly from network to the nor flash
The involved network driver is "smc9111.c".
The data that comes from the network stack and should be written into
the flash isn't 32 bit aligned (at least with this network driver).
This is probably due to the 48 bit wide ethernet addresses.
However the "cfi_flash.c" driver doesn't handle this situation, and
accesses the not-aligned address with a 32 bit pointer.
This patch fixes the problem by reducing the access width if an
aligment problem between source and destination is found.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Alexey Galakhov
Sascha Hauer
Alexander Shiyan
Jan Luebbe
Antony Pavlov
Krzysztof Halasa
Jean-Christophe PLAGNIOL-VILLARD
Juergen Beisert
Michael Trensch
Robert Jarzmik
Uwe Hermann