pinctrl: switch i.MX iomux-v3 support to pinctrl
This switches the iomux-v3 (found on i.MX25,35,51,53,6) to pinctrl support. The old SoC specific API is kept for compatibility. The pinctrl devicetree support is enabled automatically when OFDEVICE support is available. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
7f63c0a246
commit
e20ee612d8
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@ -174,6 +174,7 @@ config ARCH_IMX25
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bool "i.MX25"
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select CPU_ARM926T
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select ARCH_HAS_FEC_IMX
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select PINCTRL_IMX_IOMUX_V3
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config ARCH_IMX27
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bool "i.MX27"
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@ -188,21 +189,25 @@ config ARCH_IMX35
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bool "i.MX35"
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select CPU_V6
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select ARCH_HAS_FEC_IMX
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select PINCTRL_IMX_IOMUX_V3
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config ARCH_IMX51
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bool "i.MX51"
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select CPU_V7
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select ARCH_HAS_FEC_IMX
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select PINCTRL_IMX_IOMUX_V3
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config ARCH_IMX53
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bool "i.MX53"
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select CPU_V7
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select ARCH_HAS_FEC_IMX
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select PINCTRL_IMX_IOMUX_V3
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config ARCH_IMX6
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bool "i.MX6"
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select ARCH_HAS_FEC_IMX
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select CPU_V7
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select PINCTRL_IMX_IOMUX_V3
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endchoice
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@ -1,14 +1,14 @@
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obj-y += clocksource.o gpio.o
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obj-$(CONFIG_ARCH_IMX1) += imx1.o iomux-v1.o clk-imx1.o
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obj-$(CONFIG_ARCH_IMX25) += imx25.o iomux-v3.o clk-imx25.o
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obj-$(CONFIG_ARCH_IMX25) += imx25.o clk-imx25.o
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obj-$(CONFIG_ARCH_IMX21) += imx21.o iomux-v1.o clk-imx21.o
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obj-$(CONFIG_ARCH_IMX27) += imx27.o iomux-v1.o clk-imx27.o
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obj-$(CONFIG_ARCH_IMX31) += imx31.o iomux-v2.o clk-imx31.o
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obj-$(CONFIG_ARCH_IMX35) += imx35.o iomux-v3.o clk-imx35.o
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obj-$(CONFIG_ARCH_IMX51) += imx51.o iomux-v3.o imx5.o clk-imx5.o
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obj-$(CONFIG_ARCH_IMX53) += imx53.o iomux-v3.o imx5.o clk-imx5.o esdctl-v4.o
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obj-$(CONFIG_ARCH_IMX35) += imx35.o clk-imx35.o
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obj-$(CONFIG_ARCH_IMX51) += imx51.o imx5.o clk-imx5.o
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obj-$(CONFIG_ARCH_IMX53) += imx53.o imx5.o clk-imx5.o esdctl-v4.o
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pbl-$(CONFIG_ARCH_IMX53) += imx53.o imx5.o esdctl-v4.o
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obj-$(CONFIG_ARCH_IMX6) += imx6.o iomux-v3.o usb-imx6.o clk-imx6.o
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obj-$(CONFIG_ARCH_IMX6) += imx6.o usb-imx6.o clk-imx6.o
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lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o
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obj-$(CONFIG_IMX_IIM) += iim.o
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obj-$(CONFIG_NAND_IMX) += nand.o
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@ -1,107 +0,0 @@
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/*
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* Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
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* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
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* <armlinux@phytec.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <mach/iomux-v3.h>
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static void __iomem *base;
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/*
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* configures a single pad in the iomuxer
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*/
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int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
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{
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u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
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u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
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u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
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u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
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u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
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u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
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if (!base)
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return -EINVAL;
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debug("%s: mux 0x%08x -> 0x%04x pad: 0x%08x -> 0x%04x sel_inp: 0x%08x -> 0x%04x\n",
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__func__, mux_mode, mux_ctrl_ofs, pad_ctrl, pad_ctrl_ofs, sel_input,
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sel_input_ofs);
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if (mux_ctrl_ofs)
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__raw_writel(mux_mode, base + mux_ctrl_ofs);
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if (sel_input_ofs)
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__raw_writel(sel_input, base + sel_input_ofs);
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if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
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__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
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return 0;
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}
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EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
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int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
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{
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iomux_v3_cfg_t *p = pad_list;
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int i;
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int ret;
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for (i = 0; i < count; i++) {
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ret = mxc_iomux_v3_setup_pad(*p);
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if (ret)
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return ret;
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p++;
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}
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return 0;
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}
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EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
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static int imx_iomux_probe(struct device_d *dev)
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{
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base = dev_request_mem_region(dev, 0);
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return 0;
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}
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static __maybe_unused struct of_device_id imx_iomux_dt_ids[] = {
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{
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.compatible = "fsl,imx35-iomux",
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}, {
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/* sentinel */
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}
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};
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static struct platform_device_id imx_iomux_ids[] = {
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{
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.name = "imx35-iomux",
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}, {
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/* sentinel */
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},
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};
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static struct driver_d imx_iomux_driver = {
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.name = "imx-iomuxv3",
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.probe = imx_iomux_probe,
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.of_compatible = DRV_OF_COMPAT(imx_iomux_dt_ids),
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.id_table = imx_iomux_ids,
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};
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static int imx_iomux_init(void)
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{
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return platform_driver_register(&imx_iomux_driver);
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}
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postcore_initcall(imx_iomux_init);
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@ -9,4 +9,10 @@ config PINCTRL
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from the devicetree. Legacy drivers here may not need this core
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support but instead provide their own SoC specific APIs
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config PINCTRL_IMX_IOMUX_V3
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select PINCTRL if OFDEVICE
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bool "i.MX iomux v3"
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help
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This iomux controller is found on i.MX25,35,51,53,6.
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endmenu
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@ -1 +1,2 @@
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obj-$(CONFIG_PINCTRL) += pinctrl.o
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obj-$(CONFIG_PINCTRL_IMX_IOMUX_V3) += imx-iomux-v3.o
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@ -0,0 +1,212 @@
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/*
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* imx-iomux-v3.c - i.MX iomux-v3 pinctrl support
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*
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* Copyright (c) 2013 Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <pinctrl.h>
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#include <malloc.h>
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#include <mach/iomux-v3.h>
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struct imx_iomux_v3 {
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void __iomem *base;
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struct pinctrl_device pinctrl;
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};
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static void __iomem *iomuxv3_base;
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static struct device_d *iomuxv3_dev;
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static void imx_iomuxv3_setup_single(void __iomem *base, struct device_d *dev,
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u32 mux_reg, u32 conf_reg, u32 input_reg,
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u32 mux_val, u32 conf_val, u32 input_val)
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{
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dev_dbg(dev,
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"mux: 0x%08x -> 0x%04x, conf: 0x%08x -> 0x%04x input: 0x%08x -> 0x%04x\n",
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mux_val, mux_reg, conf_val, conf_reg, input_val, input_reg);
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if (mux_reg)
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writel(mux_val, base + mux_reg);
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if (conf_reg)
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writel(conf_val, base + conf_reg);
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if (input_reg)
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writel(input_val, base + input_reg);
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}
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/*
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* configures a single pad in the iomuxer
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*/
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int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
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{
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u32 mux_reg = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
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u32 mux_val = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
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u32 input_reg = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
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u32 input_val = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
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u32 conf_reg = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
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u32 conf_val = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
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if (!iomuxv3_base)
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return -EINVAL;
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if (conf_val & NO_PAD_CTRL)
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conf_reg = 0;
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imx_iomuxv3_setup_single(iomuxv3_base, iomuxv3_dev,
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mux_reg, conf_reg, input_reg,
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mux_val, conf_val, input_val);
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return 0;
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}
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EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
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int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
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{
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iomux_v3_cfg_t *p = pad_list;
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int i;
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int ret;
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for (i = 0; i < count; i++) {
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ret = mxc_iomux_v3_setup_pad(*p);
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if (ret)
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return ret;
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p++;
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}
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return 0;
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}
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EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
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/*
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* Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
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* 1 u32 CONFIG, so 24 types in total for each pin.
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*/
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#define FSL_PIN_SIZE 24
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#define IMX_DT_NO_PAD_CTL (1 << 31)
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#define IMX_PAD_SION (1 << 30)
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#define IOMUXC_CONFIG_SION (0x1 << 4)
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static int imx_iomux_v3_set_state(struct pinctrl_device *pdev, struct device_node *np)
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{
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struct imx_iomux_v3 *iomux = container_of(pdev, struct imx_iomux_v3, pinctrl);
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const __be32 *list;
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int npins, size, i;
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dev_dbg(iomux->pinctrl.dev, "set state: %s\n", np->full_name);
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list = of_get_property(np, "fsl,pins", &size);
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if (!list)
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return -EINVAL;
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if (!size || size % FSL_PIN_SIZE) {
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dev_err(iomux->pinctrl.dev, "Invalid fsl,pins property\n");
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return -EINVAL;
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}
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npins = size / FSL_PIN_SIZE;
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for (i = 0; i < npins; i++) {
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u32 mux_reg = be32_to_cpu(*list++);
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u32 conf_reg = be32_to_cpu(*list++);
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u32 input_reg = be32_to_cpu(*list++);
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u32 mux_val = be32_to_cpu(*list++);
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u32 input_val = be32_to_cpu(*list++);
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u32 conf_val = be32_to_cpu(*list++);
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if (conf_val & IMX_PAD_SION)
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mux_val |= IOMUXC_CONFIG_SION;
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if (conf_val & IMX_DT_NO_PAD_CTL)
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conf_reg = 0;
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imx_iomuxv3_setup_single(iomux->base, iomux->pinctrl.dev,
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mux_reg, conf_reg, input_reg,
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mux_val, conf_val, input_val);
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}
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return 0;
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}
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static struct pinctrl_ops imx_iomux_v3_ops = {
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.set_state = imx_iomux_v3_set_state,
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};
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static int imx_pinctrl_dt(struct device_d *dev, void __iomem *base)
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{
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struct imx_iomux_v3 *iomux;
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int ret;
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iomux = xzalloc(sizeof(*iomux));
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iomux->base = base;
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iomux->pinctrl.dev = dev;
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iomux->pinctrl.ops = &imx_iomux_v3_ops;
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ret = pinctrl_register(&iomux->pinctrl);
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if (ret)
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free(iomux);
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return ret;
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}
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static int imx_iomux_v3_probe(struct device_d *dev)
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{
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int ret = 0;
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if (iomuxv3_base)
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return -EBUSY;
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iomuxv3_base = dev_request_mem_region(dev, 0);
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iomuxv3_dev = dev;
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if (IS_ENABLED(CONFIG_PINCTRL))
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ret = imx_pinctrl_dt(dev, iomuxv3_base);
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return ret;
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}
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static __maybe_unused struct of_device_id imx_iomux_v3_dt_ids[] = {
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{
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.compatible = "fsl,imx25-iomuxc",
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}, {
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.compatible = "fsl,imx35-iomuxc",
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}, {
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.compatible = "fsl,imx51-iomuxc",
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}, {
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.compatible = "fsl,imx53-iomuxc",
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}, {
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.compatible = "fsl,imx6q-iomuxc",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d imx_iomux_v3_driver = {
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.name = "imx-iomuxv3",
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.probe = imx_iomux_v3_probe,
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.of_compatible = DRV_OF_COMPAT(imx_iomux_v3_dt_ids),
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};
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static int imx_iomux_v3_init(void)
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{
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return platform_driver_register(&imx_iomux_v3_driver);
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}
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postcore_initcall(imx_iomux_v3_init);
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