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S5P lowlevel clock init 

Signed-off-by: Alexey Galakhov <agalakhov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Alexey Galakhov 2012-05-18 15:43:29 +06:00 committed by Sascha Hauer
parent d1e782ed95
commit df033b9f59
3 changed files with 66 additions and 0 deletions
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1
arch/arm/mach-samsung/Makefile
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@ -1,5 +1,6 @@
obj-y += s3c-timer.o generic.o
obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o mem-s3c24x0.o
obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o
obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)

4
arch/arm/mach-samsung/include/mach/s3c-generic.h
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@ -37,3 +37,7 @@ unsigned s3c_get_uart_clk(unsigned src);
uint32_t s3c24xx_get_memory_size(void);
void s3c24xx_disable_second_sdram_bank(void);
#endif
#ifdef CONFIG_ARCH_S5PCxx
void s5p_init_pll(void);
#endif

61
arch/arm/mach-samsung/lowlevel-s5pcxx.c Normal file
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@ -0,0 +1,61 @@
/*
* Copyright (C) 2012 Alexey Galakhov
*
* Based on code from u-boot found somewhere on the web
* that seems to originate from Samsung
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <config.h>
#include <common.h>
#include <io.h>
#include <init.h>
#include <mach/s3c-iomap.h>
#include <mach/s3c-clocks.h>
#include <mach/s3c-generic.h>
#ifdef CONFIG_S3C_PLL_INIT
void __bare_init s5p_init_pll(void)
{
uint32_t reg;
int i;
/* Set Mux to FIN */
writel(0, S5P_CLK_SRC0);
writel(BOARD_APLL_LOCKTIME, S5P_xPLL_LOCK + S5P_APLL);
/* Disable PLL */
writel(0, S5P_xPLL_CON + S5P_APLL);
writel(0, S5P_xPLL_CON + S5P_MPLL);
/* Set up dividers */
reg = readl(S5P_CLK_DIV0);
reg &= ~(BOARD_CLK_DIV0_MASK);
reg |= (BOARD_CLK_DIV0_VAL);
writel(reg, S5P_CLK_DIV0);
/* Set up PLLs */
writel(BOARD_APLL_VAL, S5P_xPLL_CON + S5P_APLL);
writel(BOARD_MPLL_VAL, S5P_xPLL_CON + S5P_MPLL);
writel(BOARD_EPLL_VAL, S5P_xPLL_CON + S5P_EPLL);
writel(BOARD_VPLL_VAL, S5P_xPLL_CON + S5P_VPLL);
/* Wait for sync */
for (i = 0; i < 0x10000; ++i)
barrier();
reg = readl(S5P_CLK_SRC0);
reg |= 0x1111; /* switch MUX to PLL outputs */
writel(reg, S5P_CLK_SRC0);
}
#endif /* CONFIG_S3C_PLL_INIT */