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@ -0,0 +1,278 @@
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soc vf610
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loadaddr 0x80000000
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dcdofs 0x400
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#define VF610_DDR_PAD_CTRL 0x00000180 /* 25 Ohm drive strength */
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#define VF610_DDR_PAD_CTRL_1 0x00010180 /* 25 Ohm drive strength + differential input */
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#define DDRMC_PHY_DQ_TIMING 0x00002613
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#define DDRMC_PHY_DQS_TIMING 0x00002615
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#define DDRMC_PHY_CTRL 0x00210000
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#define DDRMC_PHY_MASTER_CTRL 0x0001012a
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#define DDRMC_PHY_SLAVE_CTRL 0x00002000
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#define DDRMC_PHY_OFF 0x00000000
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#define DDRMC_PHY_PROC_PAD_ODT 0x00010101
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#ifdef DEBUG
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#define CHECKPOINT(n) wm 32 0x3f040000 n
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#else
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#define CHECKPOINT(n)
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#endif
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CHECKPOINT(1)
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/* ======================= Clock initialization =======================*/
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/*
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* Ungate all IP block clocks
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*/
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wm 32 0x4006b040 0xffffffff
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wm 32 0x4006b044 0xffffffff
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wm 32 0x4006b048 0xffffffff
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wm 32 0x4006b04c 0xffffffff
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wm 32 0x4006b050 0xffffffff
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wm 32 0x4006b058 0xffffffff
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wm 32 0x4006b05c 0xffffffff
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wm 32 0x4006b060 0xffffffff
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wm 32 0x4006b064 0xffffffff
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wm 32 0x4006b068 0xffffffff
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wm 32 0x4006b06c 0xffffffff
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/*
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* We have to options to clock DDR controller:
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*
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* - Use Core-A5 clock
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* - Use PLL2 PFD2 clock
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*
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* Using first option without changing PLL settings doesn't seem to be
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* possible given that DDRMC requires minimum of 300Mhz and MaskROM
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* configures it to be clocked at 264Mhz. Changing PLL1 settings
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* proved to be challenging becuase MaskROM code executing this DCD
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* will also be fetching the rest of the bootloader via some
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* peripheral interface whose clock is derived from Cortex-A5 clock.
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*
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* As a result this DCD configuration code uses the second option of
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* clocking DDR wiht PLL2 PFD2 clock output
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*
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* Turn PLL2 on
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*/
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wm 32 0x40050030 0x00002001 /* Fout = Fin * 22 */
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CHECKPOINT(2)
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/*
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* Wait for PLLs to lock
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*/
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check 32 while_any_bit_clear 0x40050030 0x80000000
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CHECKPOINT(3)
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/*
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* Switch DDRMC to be clocked with PLL2 PFD2 and enable PFD2 output
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*/
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clear_bits 32 0x4006b008 0x00000040
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set_bits 32 0x4006b008 0x00002000
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/* ======================= DDR IOMUX ======================= */
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CHECKPOINT(4)
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wm 32 0x40048220 VF610_DDR_PAD_CTRL
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wm 32 0x40048224 VF610_DDR_PAD_CTRL
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wm 32 0x40048228 VF610_DDR_PAD_CTRL
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wm 32 0x4004822c VF610_DDR_PAD_CTRL
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wm 32 0x40048230 VF610_DDR_PAD_CTRL
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wm 32 0x40048234 VF610_DDR_PAD_CTRL
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wm 32 0x40048238 VF610_DDR_PAD_CTRL
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wm 32 0x4004823c VF610_DDR_PAD_CTRL
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wm 32 0x40048240 VF610_DDR_PAD_CTRL
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wm 32 0x40048244 VF610_DDR_PAD_CTRL
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wm 32 0x40048248 VF610_DDR_PAD_CTRL
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wm 32 0x4004824c VF610_DDR_PAD_CTRL
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wm 32 0x40048250 VF610_DDR_PAD_CTRL
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wm 32 0x40048254 VF610_DDR_PAD_CTRL
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wm 32 0x40048258 VF610_DDR_PAD_CTRL
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wm 32 0x4004825c VF610_DDR_PAD_CTRL
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wm 32 0x40048260 VF610_DDR_PAD_CTRL
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wm 32 0x40048264 VF610_DDR_PAD_CTRL
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wm 32 0x40048268 VF610_DDR_PAD_CTRL
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wm 32 0x4004826c VF610_DDR_PAD_CTRL
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wm 32 0x40048270 VF610_DDR_PAD_CTRL
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wm 32 0x40048274 VF610_DDR_PAD_CTRL
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wm 32 0x40048278 VF610_DDR_PAD_CTRL
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wm 32 0x4004827c VF610_DDR_PAD_CTRL_1
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wm 32 0x40048280 VF610_DDR_PAD_CTRL_1
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wm 32 0x40048284 VF610_DDR_PAD_CTRL_1
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wm 32 0x40048288 VF610_DDR_PAD_CTRL_1
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wm 32 0x4004828c VF610_DDR_PAD_CTRL_1
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wm 32 0x40048290 VF610_DDR_PAD_CTRL_1
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wm 32 0x40048294 VF610_DDR_PAD_CTRL_1
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wm 32 0x40048298 VF610_DDR_PAD_CTRL_1
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wm 32 0x4004829c VF610_DDR_PAD_CTRL_1
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wm 32 0x400482a0 VF610_DDR_PAD_CTRL_1
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wm 32 0x400482a4 VF610_DDR_PAD_CTRL_1
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wm 32 0x400482a8 VF610_DDR_PAD_CTRL_1
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wm 32 0x400482ac VF610_DDR_PAD_CTRL_1
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wm 32 0x400482b0 VF610_DDR_PAD_CTRL_1
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wm 32 0x400482b4 VF610_DDR_PAD_CTRL_1
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wm 32 0x400482b8 VF610_DDR_PAD_CTRL_1
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wm 32 0x400482bc VF610_DDR_PAD_CTRL_1
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wm 32 0x400482c0 VF610_DDR_PAD_CTRL_1
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wm 32 0x400482c4 VF610_DDR_PAD_CTRL_1
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wm 32 0x400482c8 VF610_DDR_PAD_CTRL_1
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wm 32 0x400482cc VF610_DDR_PAD_CTRL
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wm 32 0x400482d0 VF610_DDR_PAD_CTRL
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wm 32 0x400482d4 VF610_DDR_PAD_CTRL
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wm 32 0x400482d8 VF610_DDR_PAD_CTRL
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wm 32 0x4004821c VF610_DDR_PAD_CTRL
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/* ======================= DDR Controller =======================*/
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CHECKPOINT(5)
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wm 32 0x400ae000 0x00000600
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wm 32 0x400ae008 0x00000020
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wm 32 0x400ae028 0x00013880
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wm 32 0x400ae02c 0x00030d40
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wm 32 0x400ae030 0x0000050c
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wm 32 0x400ae034 0x15040400
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wm 32 0x400ae038 0x1406040f
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wm 32 0x400ae040 0x04040000
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wm 32 0x400ae044 0x006db00c
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wm 32 0x400ae048 0x00000403
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wm 32 0x400ae050 0x01000000
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wm 32 0x400ae054 0x00060001
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wm 32 0x400ae058 0x000c0000
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wm 32 0x400ae05c 0x03000200
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wm 32 0x400ae060 0x00000006
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wm 32 0x400ae064 0x00010000
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wm 32 0x400ae068 0x0c30002c
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wm 32 0x400ae070 0x00000000
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wm 32 0x400ae074 0x00000003
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wm 32 0x400ae078 0x0000000a
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wm 32 0x400ae07c 0x003001d4
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wm 32 0x400ae084 0x00010000
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wm 32 0x400ae088 0x00050500
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wm 32 0x400ae098 0x00000000
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wm 32 0x400ae09c 0x04001002
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wm 32 0x400ae0a4 0x00000001
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wm 32 0x400ae0c0 0x00460420
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wm 32 0x400ae108 0x01000200
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wm 32 0x400ae10c 0x00000040
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wm 32 0x400ae114 0x00000200
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wm 32 0x400ae118 0x00000040
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wm 32 0x400ae120 0x00000000
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wm 32 0x400ae124 0x0a010300
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wm 32 0x400ae128 0x01014040
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wm 32 0x400ae12c 0x01010101
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wm 32 0x400ae130 0x03030100
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wm 32 0x400ae134 0x01000101
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wm 32 0x400ae138 0x0700000c
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wm 32 0x400ae13c 0x00000000
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wm 32 0x400ae148 0x10000000
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wm 32 0x400ae15c 0x01000000
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wm 32 0x400ae160 0x00040000
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wm 32 0x400ae164 0x00000002
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wm 32 0x400ae16c 0x00020000
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wm 32 0x400ae180 0x00002819
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wm 32 0x400ae184 0x01000000
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wm 32 0x400ae188 0x00000000
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wm 32 0x400ae18c 0x00000000
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wm 32 0x400ae198 0x00010100
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wm 32 0x400ae1a4 0x00000000
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wm 32 0x400ae1a8 0x00000004
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wm 32 0x400ae1b8 0x00040000
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wm 32 0x400ae1c8 0x00000000
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wm 32 0x400ae1cc 0x00000000
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wm 32 0x400ae1d4 0x00000000
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wm 32 0x400ae1d8 0x01010000
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wm 32 0x400ae1e0 0x02020000
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wm 32 0x400ae1e4 0x00000202
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wm 32 0x400ae1e8 0x01010064
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wm 32 0x400ae1ec 0x00010101
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wm 32 0x400ae1f0 0x00000064
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wm 32 0x400ae1f8 0x00000800
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wm 32 0x400ae210 0x00000506
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wm 32 0x400ae224 0x00020000
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wm 32 0x400ae228 0x01000000
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wm 32 0x400ae22c 0x04070303
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wm 32 0x400ae230 0x00000040
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wm 32 0x400ae23c 0x06000080
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wm 32 0x400ae240 0x04070303
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wm 32 0x400ae244 0x00000040
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wm 32 0x400ae248 0x00000040
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wm 32 0x400ae24c 0x000f0000
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wm 32 0x400ae250 0x000f0000
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wm 32 0x400ae25c 0x00000101
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wm 32 0x400ae268 0x682c4000
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wm 32 0x400ae26c 0x00000012
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wm 32 0x400ae278 0x00000006
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wm 32 0x400ae284 0x00010202
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/* ======================= DDR PHY =======================*/
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CHECKPOINT(6)
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wm 32 0x400ae400 DDRMC_PHY_DQ_TIMING
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wm 32 0x400ae440 DDRMC_PHY_DQ_TIMING
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wm 32 0x400ae480 DDRMC_PHY_DQ_TIMING
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wm 32 0x400ae404 DDRMC_PHY_DQS_TIMING
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wm 32 0x400ae444 DDRMC_PHY_DQS_TIMING
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wm 32 0x400ae408 DDRMC_PHY_CTRL
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wm 32 0x400ae448 DDRMC_PHY_CTRL
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wm 32 0x400ae488 DDRMC_PHY_CTRL
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wm 32 0x400ae40c DDRMC_PHY_MASTER_CTRL
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wm 32 0x400ae44c DDRMC_PHY_MASTER_CTRL
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wm 32 0x400ae48c DDRMC_PHY_MASTER_CTRL
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wm 32 0x400ae410 DDRMC_PHY_SLAVE_CTRL
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wm 32 0x400ae450 DDRMC_PHY_SLAVE_CTRL
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wm 32 0x400ae490 DDRMC_PHY_SLAVE_CTRL
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wm 32 0x400ae4c4 DDRMC_PHY_OFF
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wm 32 0x400ae4c8 0x00001100
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wm 32 0x400ae4d0 DDRMC_PHY_PROC_PAD_ODT
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wm 32 0x400ae000 0x00000601
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CHECKPOINT(7)
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check 32 while_any_bit_clear 0x400ae140 0x100
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CHECKPOINT(8)
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/*
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* Cargo cult DDR controller initialization here we come!
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*
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* Experemintation with VF610 Tower Board shows that without the
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* following code the board would not boot off of SD card when
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* power-cycled. It will however happily boot when reset via SW3/Reset
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* button. For whatever reason the following actions appear to be
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* necessary:
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*
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* - Initialize DDRMC as usual
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* - Issue a read to location in DDR address space
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* - Disable DDRMC
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* - Enable DDRMC and wait for it to finish initializing
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*
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* I am sure this is all going to be extrememly embarrassing to read
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* if/when the real problem and real solution is found.
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*/
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/*
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* Because there's no standalone read command what we do here instead
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* is write a pattern to memory and then checking that memory address
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* against that pattern
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*/
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wm 32 0x80000000 0xa5a5a5a5
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check 32 while_any_bit_clear 0x80000000 0xa5a5a5a5
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wm 32 0x400ae000 0x00000600
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wm 32 0x400ae000 0x00000601
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check 32 while_any_bit_clear 0x400ae140 0x100
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CHECKPOINT(9)
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