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cpu-85xx: start.S: clean up imported code 

Correct double spaces, indentation and vocabulary in the imported
start-up code.

Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Renaud Barbier 2014-01-15 11:47:44 +00:00 committed by Sascha Hauer
parent b79f78997d
commit d711f9cfd8
1 changed files with 11 additions and 11 deletions
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22
arch/ppc/cpu-85xx/start.S
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@ -180,9 +180,9 @@ _start_e500:
/*
* Search for the TLB that covers the code we're executing, and shrink it
* so that it covers only this 4K page. That will ensure that any other
* TLB we create won't interfere with it. We assume that the TLB exists,
* which is why we don't check the Valid bit of MAS1. We also assume
* so that it covers only this 4K page. That will ensure that any other
* TLB we create won't interfere with it. We assume that the TLB exists,
* which is why we don't check the Valid bit of MAS1. We also assume
* it is in TLB1.
*
* This is necessary, for example, when booting from the on-chip ROM,
@ -209,7 +209,7 @@ nexti: mflr r1 /* R1 = our PC */
/*
* Set the base address of the TLB to our PC. We assume that
* virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
* virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
*/
lis r3, MAS2_EPN@h
ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
@ -230,10 +230,10 @@ nexti: mflr r1 /* R1 = our PC */
msync
tlbwe
/*
* Clear out any other TLB entries that may exist, to avoid conflicts.
* Our TLB entry is in r14.
*/
/*
* Clear out any other TLB entries that may exist, to avoid conflicts.
* Our TLB entry is in r14.
*/
li r0, TLBIVAX_ALL | TLBIVAX_TLB0
tlbivax 0, r0
tlbsync
@ -268,7 +268,7 @@ nexti: mflr r1 /* R1 = our PC */
* in AS1.
*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
* bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
* because flash's virtual address maps to 0xff800000 - 0xffffffff.
* and this window is outside of 4K boot window.
*/
create_tlb1_entry PPC_E500_DEBUG_TLB, \
@ -316,8 +316,8 @@ nexti: mflr r1 /* R1 = our PC */
beq 2b
create_init_ram_area:
lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
/* create a temp mapping in AS=1 to the 4M boot window */
create_tlb1_entry 15, \