ARM: initial Tegra support
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Antony Pavlov
Sascha Hauer
parent
b2533ec18e
commit
cdf00414e5
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@ -83,6 +83,11 @@ config ARCH_VERSATILE
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bool "ARM Versatile boards (ARM926EJ-S)"
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select CPU_ARM926T
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config ARCH_TEGRA
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bool "Nvidia Tegra-based boards"
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select CPU_ARM926T
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select HAS_DEBUG_LL
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endchoice
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source arch/arm/cpu/Kconfig
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@ -96,6 +101,7 @@ source arch/arm/mach-omap/Kconfig
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source arch/arm/mach-pxa/Kconfig
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source arch/arm/mach-samsung/Kconfig
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source arch/arm/mach-versatile/Kconfig
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source arch/arm/mach-tegra/Kconfig
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config ARM_ASM_UNIFIED
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bool
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@ -61,6 +61,7 @@ machine-$(CONFIG_ARCH_OMAP) := omap
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machine-$(CONFIG_ARCH_PXA) := pxa
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machine-$(CONFIG_ARCH_SAMSUNG) := samsung
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machine-$(CONFIG_ARCH_VERSATILE) := versatile
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machine-$(CONFIG_ARCH_TEGRA) := tegra
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# Board directory name. This list is sorted alphanumerically
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# by CONFIG_* macro name.
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@ -0,0 +1,7 @@
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if ARCH_TEGRA
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config ARCH_TEXT_BASE
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hex
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default 0x31fc0000
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endif
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@ -0,0 +1,2 @@
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obj-y += clock.o
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obj-y += reset.o
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@ -0,0 +1,59 @@
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/*
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* Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* This file is part of barebox.
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* See file CREDITS for list of people who contributed to this project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/**
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* @file
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* @brief Clocksource based on Tegra internal timer
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*/
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#include <common.h>
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#include <clock.h>
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#include <linux/list.h>
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#include <linux/clk.h>
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#include <init.h>
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#include <asm/io.h>
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#include <mach/iomap.h>
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static void __iomem *timer_reg_base = (void __iomem *) (TEGRA_TMR1_BASE);
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#define timer_writel(value, reg) \
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__raw_writel(value, (u32)timer_reg_base + (reg))
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#define timer_readl(reg) \
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__raw_readl((u32)timer_reg_base + (reg))
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static uint64_t tegra_clocksource_read(void)
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{
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return timer_readl(0x10);
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}
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static struct clocksource cs = {
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.read = tegra_clocksource_read,
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.mask = 0xffffffff,
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};
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/* FIXME: here we have no initialization. All initialization made by U-Boot */
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static int clocksource_init(void)
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{
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cs.mult = clocksource_hz2mult(1000000, cs.shift);
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init_clock(&cs);
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return 0;
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}
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core_initcall(clocksource_init);
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@ -0,0 +1,45 @@
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/*
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* Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* This file is part of barebox.
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* See file CREDITS for list of people who contributed to this project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/** @file
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* This File contains declaration for early output support
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*/
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#ifndef __INCLUDE_ARCH_DEBUG_LL_H__
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#define __INCLUDE_ARCH_DEBUG_LL_H__
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#include <asm/io.h>
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#include <mach/iomap.h>
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#define DEBUG_LL_UART_ADDR TEGRA_UARTA_BASE
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#define DEBUG_LL_UART_RSHFT 2
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#define rbr (0 << DEBUG_LL_UART_RSHFT)
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#define lsr (5 << DEBUG_LL_UART_RSHFT)
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#define LSR_THRE 0x20 /* Xmit holding register empty */
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static inline void putc(char ch)
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{
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while (!(__raw_readb(DEBUG_LL_UART_ADDR + lsr) & LSR_THRE))
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;
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__raw_writeb(ch, DEBUG_LL_UART_ADDR + rbr);
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}
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#endif /* __INCLUDE_ARCH_DEBUG_LL_H__ */
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@ -0,0 +1,292 @@
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/*
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* arch/arm/mach-tegra/include/mach/iomap.h
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*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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* Erik Gilling <konkers@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MACH_TEGRA_IOMAP_H
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#define __MACH_TEGRA_IOMAP_H
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#include <sizes.h>
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#define TEGRA_IRAM_BASE 0x40000000
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#define TEGRA_IRAM_SIZE SZ_256K
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#define TEGRA_HOST1X_BASE 0x50000000
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#define TEGRA_HOST1X_SIZE 0x24000
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#define TEGRA_ARM_PERIF_BASE 0x50040000
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#define TEGRA_ARM_PERIF_SIZE SZ_8K
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#define TEGRA_ARM_PL310_BASE 0x50043000
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#define TEGRA_ARM_PL310_SIZE SZ_4K
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#define TEGRA_ARM_INT_DIST_BASE 0x50041000
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#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
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#define TEGRA_MPE_BASE 0x54040000
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#define TEGRA_MPE_SIZE SZ_256K
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#define TEGRA_VI_BASE 0x54080000
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#define TEGRA_VI_SIZE SZ_256K
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#define TEGRA_ISP_BASE 0x54100000
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#define TEGRA_ISP_SIZE SZ_256K
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#define TEGRA_DISPLAY_BASE 0x54200000
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#define TEGRA_DISPLAY_SIZE SZ_256K
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#define TEGRA_DISPLAY2_BASE 0x54240000
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#define TEGRA_DISPLAY2_SIZE SZ_256K
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#define TEGRA_HDMI_BASE 0x54280000
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#define TEGRA_HDMI_SIZE SZ_256K
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#define TEGRA_GART_BASE 0x58000000
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#define TEGRA_GART_SIZE SZ_32M
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#define TEGRA_RES_SEMA_BASE 0x60001000
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#define TEGRA_RES_SEMA_SIZE SZ_4K
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#define TEGRA_HDMI_BASE 0x54280000
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#define TEGRA_HDMI_SIZE SZ_256K
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#define TEGRA_GART_BASE 0x58000000
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#define TEGRA_GART_SIZE SZ_32M
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#define TEGRA_RES_SEMA_BASE 0x60001000
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#define TEGRA_RES_SEMA_SIZE SZ_4K
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#define TEGRA_ARB_SEMA_BASE 0x60002000
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#define TEGRA_ARB_SEMA_SIZE SZ_4K
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#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
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#define TEGRA_PRIMARY_ICTLR_SIZE 64
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#define TEGRA_ARBGNT_ICTLR_BASE 0x60004040
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#define TEGRA_ARBGNT_ICTLR_SIZE 192
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#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
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#define TEGRA_SECONDARY_ICTLR_SIZE 64
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#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
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#define TEGRA_TERTIARY_ICTLR_SIZE 64
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#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300
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#define TEGRA_QUATERNARY_ICTLR_SIZE 64
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#define TEGRA_TMR1_BASE 0x60005000
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#define TEGRA_TMR1_SIZE 8
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#define TEGRA_TMR2_BASE 0x60005008
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#define TEGRA_TMR2_SIZE 8
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#define TEGRA_TMRUS_BASE 0x60005010
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#define TEGRA_TMRUS_SIZE 64
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#define TEGRA_TMR3_BASE 0x60005050
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#define TEGRA_TMR3_SIZE 8
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#define TEGRA_TMR4_BASE 0x60005058
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#define TEGRA_TMR4_SIZE 8
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#define TEGRA_CLK_RESET_BASE 0x60006000
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#define TEGRA_CLK_RESET_SIZE SZ_4K
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#define TEGRA_FLOW_CTRL_BASE 0x60007000
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#define TEGRA_FLOW_CTRL_SIZE 20
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#define TEGRA_AHB_DMA_BASE 0x60008000
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#define TEGRA_AHB_DMA_SIZE SZ_4K
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#define TEGRA_AHB_DMA_CH0_BASE 0x60009000
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#define TEGRA_AHB_DMA_CH0_SIZE 32
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#define TEGRA_APB_DMA_BASE 0x6000A000
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#define TEGRA_APB_DMA_SIZE SZ_4K
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#define TEGRA_APB_DMA_CH0_BASE 0x6000B000
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#define TEGRA_APB_DMA_CH0_SIZE 32
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#define TEGRA_AHB_GIZMO_BASE 0x6000C004
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#define TEGRA_AHB_GIZMO_SIZE 0x10C
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#define TEGRA_STATMON_BASE 0x6000C400
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#define TEGRA_STATMON_SIZE SZ_1K
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#define TEGRA_GPIO_BASE 0x6000D000
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#define TEGRA_GPIO_SIZE SZ_4K
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#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
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#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
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#define TEGRA_VDE_BASE 0x6001A000
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#define TEGRA_VDE_SIZE (SZ_8K + SZ_4K - SZ_256)
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#define TEGRA_APB_MISC_BASE 0x70000000
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#define TEGRA_APB_MISC_SIZE SZ_4K
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#define TEGRA_APB_MISC_DAS_BASE 0x70000c00
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#define TEGRA_APB_MISC_DAS_SIZE SZ_128
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#define TEGRA_AC97_BASE 0x70002000
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#define TEGRA_AC97_SIZE SZ_512
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#define TEGRA_SPDIF_BASE 0x70002400
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#define TEGRA_SPDIF_SIZE SZ_512
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#define TEGRA_I2S1_BASE 0x70002800
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#define TEGRA_I2S1_SIZE SZ_256
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#define TEGRA_I2S2_BASE 0x70002A00
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#define TEGRA_I2S2_SIZE SZ_256
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#define TEGRA_UARTA_BASE 0x70006000
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#define TEGRA_UARTA_SIZE 64
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#define TEGRA_UARTB_BASE 0x70006040
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#define TEGRA_UARTB_SIZE 64
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#define TEGRA_UARTC_BASE 0x70006200
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#define TEGRA_UARTC_SIZE SZ_256
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#define TEGRA_UARTD_BASE 0x70006300
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#define TEGRA_UARTD_SIZE SZ_256
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#define TEGRA_UARTE_BASE 0x70006400
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#define TEGRA_UARTE_SIZE SZ_256
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#define TEGRA_NAND_BASE 0x70008000
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#define TEGRA_NAND_SIZE SZ_256
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#define TEGRA_HSMMC_BASE 0x70008500
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#define TEGRA_HSMMC_SIZE SZ_256
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#define TEGRA_SNOR_BASE 0x70009000
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#define TEGRA_SNOR_SIZE SZ_4K
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#define TEGRA_PWFM_BASE 0x7000A000
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#define TEGRA_PWFM_SIZE SZ_256
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#define TEGRA_PWFM0_BASE 0x7000A000
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#define TEGRA_PWFM0_SIZE 4
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#define TEGRA_PWFM1_BASE 0x7000A010
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#define TEGRA_PWFM1_SIZE 4
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#define TEGRA_PWFM2_BASE 0x7000A020
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#define TEGRA_PWFM2_SIZE 4
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#define TEGRA_PWFM3_BASE 0x7000A030
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#define TEGRA_PWFM3_SIZE 4
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#define TEGRA_MIPI_BASE 0x7000B000
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#define TEGRA_MIPI_SIZE SZ_256
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#define TEGRA_I2C_BASE 0x7000C000
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#define TEGRA_I2C_SIZE SZ_256
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#define TEGRA_TWC_BASE 0x7000C100
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#define TEGRA_TWC_SIZE SZ_256
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#define TEGRA_SPI_BASE 0x7000C380
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#define TEGRA_SPI_SIZE 48
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#define TEGRA_I2C2_BASE 0x7000C400
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#define TEGRA_I2C2_SIZE SZ_256
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#define TEGRA_I2C3_BASE 0x7000C500
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#define TEGRA_I2C3_SIZE SZ_256
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#define TEGRA_OWR_BASE 0x7000C600
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#define TEGRA_OWR_SIZE 80
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#define TEGRA_DVC_BASE 0x7000D000
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#define TEGRA_DVC_SIZE SZ_512
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#define TEGRA_SPI1_BASE 0x7000D400
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#define TEGRA_SPI1_SIZE SZ_512
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#define TEGRA_SPI2_BASE 0x7000D600
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#define TEGRA_SPI2_SIZE SZ_512
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#define TEGRA_SPI3_BASE 0x7000D800
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#define TEGRA_SPI3_SIZE SZ_512
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#define TEGRA_SPI4_BASE 0x7000DA00
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#define TEGRA_SPI4_SIZE SZ_512
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#define TEGRA_RTC_BASE 0x7000E000
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#define TEGRA_RTC_SIZE SZ_256
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#define TEGRA_KBC_BASE 0x7000E200
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#define TEGRA_KBC_SIZE SZ_256
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#define TEGRA_PMC_BASE 0x7000E400
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#define TEGRA_PMC_SIZE SZ_256
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#define TEGRA_MC_BASE 0x7000F000
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#define TEGRA_MC_SIZE SZ_1K
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#define TEGRA_EMC_BASE 0x7000F400
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#define TEGRA_EMC_SIZE SZ_1K
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#define TEGRA_FUSE_BASE 0x7000F800
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#define TEGRA_FUSE_SIZE SZ_1K
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#define TEGRA_KFUSE_BASE 0x7000FC00
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#define TEGRA_KFUSE_SIZE SZ_1K
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#define TEGRA_CSITE_BASE 0x70040000
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#define TEGRA_CSITE_SIZE SZ_256K
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#define TEGRA_USB_BASE 0xC5000000
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#define TEGRA_USB_SIZE SZ_16K
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#define TEGRA_USB2_BASE 0xC5004000
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#define TEGRA_USB2_SIZE SZ_16K
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#define TEGRA_USB3_BASE 0xC5008000
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#define TEGRA_USB3_SIZE SZ_16K
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#define TEGRA_SDMMC1_BASE 0xC8000000
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#define TEGRA_SDMMC1_SIZE SZ_512
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#define TEGRA_SDMMC2_BASE 0xC8000200
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#define TEGRA_SDMMC2_SIZE SZ_512
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#define TEGRA_SDMMC3_BASE 0xC8000400
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#define TEGRA_SDMMC3_SIZE SZ_512
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#define TEGRA_SDMMC4_BASE 0xC8000600
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#define TEGRA_SDMMC4_SIZE SZ_512
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#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
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# define TEGRA_DEBUG_UART_BASE 0
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#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
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# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
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#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
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# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
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#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
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# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
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#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
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# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
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#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
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# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
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#endif
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#endif
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@ -0,0 +1,42 @@
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/*
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||||
* Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
|
||||
*
|
||||
* This file is part of barebox.
|
||||
* See file CREDITS for list of people who contributed to this project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Resetting an malta board
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <mach/iomap.h>
|
||||
|
||||
#define PRM_RSTCTRL TEGRA_PMC_BASE
|
||||
|
||||
void __noreturn reset_cpu(ulong addr)
|
||||
{
|
||||
int rstctrl;
|
||||
|
||||
rstctrl = __raw_readl((char *)PRM_RSTCTRL);
|
||||
rstctrl |= 0x10;
|
||||
__raw_writel(rstctrl, (char *)PRM_RSTCTRL);
|
||||
|
||||
unreachable();
|
||||
}
|
||||
EXPORT_SYMBOL(reset_cpu);
|
||||
Loading…
Reference in New Issue