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@ -1,564 +0,0 @@
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/*
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* dm9000.c
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*
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* A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
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* Copyright (C) 1997 Sten Wang
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
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*
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* V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
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* 06/22/2001 Support DM9801 progrmming
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* E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
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* E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
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* R17 = (R17 & 0xfff0) | NF + 3
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* E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
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* R17 = (R17 & 0xfff0) | NF
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*
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* v1.00 modify by simon 2001.9.5
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* change for kernel 2.4.x
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*
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* v1.1 11/09/2001 fix force mode bug
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*
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* v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
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* Fixed phy reset.
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* Added tx/rx 32 bit mode.
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* Cleaned up for kernel merge.
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*
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*
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*
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* 12/15/2003 Initial port to barebox by Sascha Hauer
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* <saschahauer@web.de>
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*
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* ... see commit logs
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*/
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#include <common.h>
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#include <command.h>
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#include <driver.h>
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#include <clock.h>
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#include <miidev.h>
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#include <malloc.h>
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#include <net.h>
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#include <init.h>
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#include <io.h>
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#include <xfuncs.h>
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#include <dm9000.h>
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#include <errno.h>
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#define DM9000_ID 0x90000A46
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#define DM9000_PKT_MAX 1536 /* Received packet max size */
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#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
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#define DM9000_NCR 0x00
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#define DM9000_NSR 0x01
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#define DM9000_TCR 0x02
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#define DM9000_TSR1 0x03
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#define DM9000_TSR2 0x04
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#define DM9000_RCR 0x05
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#define DM9000_RSR 0x06
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#define DM9000_ROCR 0x07
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#define DM9000_BPTR 0x08
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#define DM9000_FCTR 0x09
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#define DM9000_FCR 0x0A
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#define DM9000_EPCR 0x0B
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#define DM9000_EPAR 0x0C
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#define DM9000_EPDRL 0x0D
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#define DM9000_EPDRH 0x0E
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#define DM9000_WCR 0x0F
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#define DM9000_PAR 0x10
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#define DM9000_MAR 0x16
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#define DM9000_GPCR 0x1e
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#define DM9000_GPR 0x1f
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#define DM9000_TRPAL 0x22
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#define DM9000_TRPAH 0x23
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#define DM9000_RWPAL 0x24
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#define DM9000_RWPAH 0x25
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#define DM9000_VIDL 0x28
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#define DM9000_VIDH 0x29
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#define DM9000_PIDL 0x2A
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#define DM9000_PIDH 0x2B
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#define DM9000_CHIPR 0x2C
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#define DM9000_SMCR 0x2F
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#define DM9000_PHY 0x40 /* PHY address 0x01 */
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#define DM9000_MRCMDX 0xF0
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#define DM9000_MRCMD 0xF2
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#define DM9000_MRRL 0xF4
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#define DM9000_MRRH 0xF5
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#define DM9000_MWCMDX 0xF6
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#define DM9000_MWCMD 0xF8
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#define DM9000_MWRL 0xFA
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#define DM9000_MWRH 0xFB
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#define DM9000_TXPLL 0xFC
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#define DM9000_TXPLH 0xFD
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#define DM9000_ISR 0xFE
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#define DM9000_IMR 0xFF
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#define NCR_EXT_PHY (1<<7)
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#define NCR_WAKEEN (1<<6)
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#define NCR_FCOL (1<<4)
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#define NCR_FDX (1<<3)
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#define NCR_LBK (3<<1)
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#define NCR_RST (1<<0)
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#define NSR_SPEED (1<<7)
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#define NSR_LINKST (1<<6)
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#define NSR_WAKEST (1<<5)
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#define NSR_TX2END (1<<3)
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#define NSR_TX1END (1<<2)
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#define NSR_RXOV (1<<1)
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#define TCR_TJDIS (1<<6)
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#define TCR_EXCECM (1<<5)
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#define TCR_PAD_DIS2 (1<<4)
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#define TCR_CRC_DIS2 (1<<3)
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#define TCR_PAD_DIS1 (1<<2)
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#define TCR_CRC_DIS1 (1<<1)
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#define TCR_TXREQ (1<<0)
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#define TSR_TJTO (1<<7)
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#define TSR_LC (1<<6)
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#define TSR_NC (1<<5)
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#define TSR_LCOL (1<<4)
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#define TSR_COL (1<<3)
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#define TSR_EC (1<<2)
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#define RCR_WTDIS (1<<6)
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#define RCR_DIS_LONG (1<<5)
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#define RCR_DIS_CRC (1<<4)
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#define RCR_ALL (1<<3)
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#define RCR_RUNT (1<<2)
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#define RCR_PRMSC (1<<1)
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#define RCR_RXEN (1<<0)
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#define RSR_RF (1<<7)
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#define RSR_MF (1<<6)
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#define RSR_LCS (1<<5)
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#define RSR_RWTO (1<<4)
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#define RSR_PLE (1<<3)
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#define RSR_AE (1<<2)
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#define RSR_CE (1<<1)
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#define RSR_FOE (1<<0)
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#define FCTR_HWOT(ot) (( ot & 0xf ) << 4 )
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#define FCTR_LWOT(ot) ( ot & 0xf )
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#define IMR_PAR (1<<7)
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#define IMR_ROOM (1<<3)
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#define IMR_ROM (1<<2)
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#define IMR_PTM (1<<1)
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#define IMR_PRM (1<<0)
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struct dm9000_priv {
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void __iomem *iobase;
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void __iomem *iodata;
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struct mii_device miidev;
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int buswidth;
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int srom;
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};
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#ifdef CONFIG_DM9000_DEBUG
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static void
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dump_regs(void)
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{
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debug("\n");
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debug("NCR (0x00): %02x\n", DM9000_ior(0));
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debug("NSR (0x01): %02x\n", DM9000_ior(1));
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debug("TCR (0x02): %02x\n", DM9000_ior(2));
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debug("TSRI (0x03): %02x\n", DM9000_ior(3));
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debug("TSRII (0x04): %02x\n", DM9000_ior(4));
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debug("RCR (0x05): %02x\n", DM9000_ior(5));
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debug("RSR (0x06): %02x\n", DM9000_ior(6));
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debug("ISR (0xFE): %02x\n", DM9000_ior(ISR));
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debug("\n");
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}
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#endif
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static u8 DM9000_ior(struct dm9000_priv *priv, int reg)
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{
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writeb(reg, priv->iobase);
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return readb(priv->iodata);
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}
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static void DM9000_iow(struct dm9000_priv *priv, int reg, u8 value)
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{
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writeb(reg, priv->iobase);
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writeb(value, priv->iodata);
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}
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static int dm9000_phy_read(struct mii_device *mdev, int addr, int reg)
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{
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int val;
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struct eth_device *edev = mdev->edev;
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struct dm9000_priv *priv = edev->priv;
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/* Fill the phyxcer register into REG_0C */
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DM9000_iow(priv, DM9000_EPAR, DM9000_PHY | reg);
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DM9000_iow(priv, DM9000_EPCR, 0xc); /* Issue phyxcer read command */
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udelay(100); /* Wait read complete */
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DM9000_iow(priv, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
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val = (DM9000_ior(priv, DM9000_EPDRH) << 8) | DM9000_ior(priv, DM9000_EPDRL);
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/* The read data keeps on REG_0D & REG_0E */
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debug("phy_read(%d): %d\n", reg, val);
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return val;
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}
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static int dm9000_phy_write(struct mii_device *mdev, int addr, int reg, int val)
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{
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struct eth_device *edev = mdev->edev;
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struct dm9000_priv *priv = edev->priv;
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/* Fill the phyxcer register into REG_0C */
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DM9000_iow(priv, DM9000_EPAR, DM9000_PHY | reg);
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/* Fill the written data into REG_0D & REG_0E */
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DM9000_iow(priv, DM9000_EPDRL, (val & 0xff));
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DM9000_iow(priv, DM9000_EPDRH, ((val >> 8) & 0xff));
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DM9000_iow(priv, DM9000_EPCR, 0xa); /* Issue phyxcer write command */
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udelay(500); /* Wait write complete */
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DM9000_iow(priv, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
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debug("phy_write(reg:%d, value:%d)\n", reg, value);
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return 0;
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}
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static int dm9000_check_id(struct dm9000_priv *priv)
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{
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u32 id_val;
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id_val = DM9000_ior(priv, DM9000_VIDL);
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id_val |= DM9000_ior(priv, DM9000_VIDH) << 8;
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id_val |= DM9000_ior(priv, DM9000_PIDL) << 16;
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id_val |= DM9000_ior(priv, DM9000_PIDH) << 24;
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if (id_val == DM9000_ID) {
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printf("dm9000 i/o: 0x%p, id: 0x%x \n", priv->iobase,
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id_val);
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return 0;
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} else {
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printf("dm9000 not found at 0x%p id: 0x%08x\n",
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priv->iobase, id_val);
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return -1;
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}
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}
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static void dm9000_reset(struct dm9000_priv *priv)
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{
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debug("resetting\n");
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DM9000_iow(priv, DM9000_NCR, NCR_RST);
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udelay(1000); /* delay 1ms */
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}
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static int dm9000_eth_open(struct eth_device *edev)
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{
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struct dm9000_priv *priv = (struct dm9000_priv *)edev->priv;
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miidev_wait_aneg(&priv->miidev);
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miidev_print_status(&priv->miidev);
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return 0;
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}
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static int dm9000_eth_send (struct eth_device *edev,
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void *packet, int length)
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{
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struct dm9000_priv *priv = (struct dm9000_priv *)edev->priv;
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char *data_ptr;
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u32 tmplen, i;
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uint64_t tmo;
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debug("eth_send: length: %d\n", length);
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for (i = 0; i < length; i++) {
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if (i % 8 == 0)
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debug("\nSend: 02x: ", i);
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debug("%02x ", ((unsigned char *) packet)[i]);
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} debug("\n");
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/* Move data to DM9000 TX RAM */
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data_ptr = (char *) packet;
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writeb(DM9000_MWCMD, priv->iobase);
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switch (priv->buswidth) {
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case IORESOURCE_MEM_8BIT:
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for (i = 0; i < length; i++)
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writeb(data_ptr[i] & 0xff, priv->iodata);
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break;
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case IORESOURCE_MEM_16BIT:
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tmplen = (length + 1) / 2;
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for (i = 0; i < tmplen; i++)
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|
writew(((u16 *)data_ptr)[i], priv->iodata);
|
|
|
|
|
break;
|
|
|
|
|
case IORESOURCE_MEM_32BIT:
|
|
|
|
|
tmplen = (length + 3) / 4;
|
|
|
|
|
for (i = 0; i < tmplen; i++)
|
|
|
|
|
writel(((u32 *) data_ptr)[i], priv->iodata);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
/* dm9000_probe makes sure this cannot happen */
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Set TX length to DM9000 */
|
|
|
|
|
DM9000_iow(priv, DM9000_TXPLL, length & 0xff);
|
|
|
|
|
DM9000_iow(priv, DM9000_TXPLH, (length >> 8) & 0xff);
|
|
|
|
|
|
|
|
|
|
/* Issue TX polling command */
|
|
|
|
|
DM9000_iow(priv, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
|
|
|
|
|
|
|
|
|
|
/* wait for end of transmission */
|
|
|
|
|
tmo = get_time_ns();
|
|
|
|
|
while (DM9000_ior(priv, DM9000_TCR) & TCR_TXREQ) {
|
|
|
|
|
if (is_timeout(tmo, 5 * SECOND)) {
|
|
|
|
|
printf("transmission timeout\n");
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
debug("transmit done\n\n");
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dm9000_eth_halt (struct eth_device *edev)
|
|
|
|
|
{
|
|
|
|
|
debug("eth_halt\n");
|
|
|
|
|
#if 0
|
|
|
|
|
phy_write(0, 0x8000); /* PHY RESET */
|
|
|
|
|
DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
|
|
|
|
|
DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
|
|
|
|
|
DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dm9000_eth_rx (struct eth_device *edev)
|
|
|
|
|
{
|
|
|
|
|
struct dm9000_priv *priv = (struct dm9000_priv *)edev->priv;
|
|
|
|
|
u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
|
|
|
|
|
u16 RxStatus, RxLen = 0;
|
|
|
|
|
u32 tmplen, i;
|
|
|
|
|
u32 tmpdata;
|
|
|
|
|
|
|
|
|
|
/* Check packet ready or not */
|
|
|
|
|
DM9000_ior(priv, DM9000_MRCMDX); /* Dummy read */
|
|
|
|
|
rxbyte = readb(priv->iodata); /* Got most updated data */
|
|
|
|
|
if (rxbyte == 0)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
/* Status check: this byte must be 0 or 1 */
|
|
|
|
|
if (rxbyte > 1) {
|
|
|
|
|
DM9000_iow(priv, DM9000_RCR, 0x00); /* Stop Device */
|
|
|
|
|
DM9000_iow(priv, DM9000_ISR, 0x80); /* Stop INT request */
|
|
|
|
|
debug("rx status check: %d\n", rxbyte);
|
|
|
|
|
}
|
|
|
|
|
debug("receiving packet\n");
|
|
|
|
|
|
|
|
|
|
/* A packet ready now & Get status/length */
|
|
|
|
|
writeb(DM9000_MRCMD, priv->iobase);
|
|
|
|
|
|
|
|
|
|
/* Move data from DM9000 */
|
|
|
|
|
/* Read received packet from RX SRAM */
|
|
|
|
|
switch (priv->buswidth) {
|
|
|
|
|
case IORESOURCE_MEM_8BIT:
|
|
|
|
|
RxStatus = readb(priv->iodata) + (readb(priv->iodata) << 8);
|
|
|
|
|
RxLen = readb(priv->iodata) + (readb(priv->iodata) << 8);
|
|
|
|
|
for (i = 0; i < RxLen; i++)
|
|
|
|
|
rdptr[i] = readb(priv->iodata);
|
|
|
|
|
break;
|
|
|
|
|
case IORESOURCE_MEM_16BIT:
|
|
|
|
|
RxStatus = readw(priv->iodata);
|
|
|
|
|
RxLen = readw(priv->iodata);
|
|
|
|
|
tmplen = (RxLen + 1) / 2;
|
|
|
|
|
for (i = 0; i < tmplen; i++)
|
|
|
|
|
((u16 *) rdptr)[i] = readw(priv->iodata);
|
|
|
|
|
break;
|
|
|
|
|
case IORESOURCE_MEM_32BIT:
|
|
|
|
|
tmpdata = readl(priv->iodata);
|
|
|
|
|
RxStatus = tmpdata;
|
|
|
|
|
RxLen = tmpdata >> 16;
|
|
|
|
|
tmplen = (RxLen + 3) / 4;
|
|
|
|
|
for (i = 0; i < tmplen; i++)
|
|
|
|
|
((u32 *) rdptr)[i] = readl(priv->iodata);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
/* dm9000_probe makes sure this cannot happen */
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((RxStatus & 0xbf00) || (RxLen < 0x40)
|
|
|
|
|
|| (RxLen > DM9000_PKT_MAX)) {
|
|
|
|
|
if (RxStatus & 0x100) {
|
|
|
|
|
printf("rx fifo error\n");
|
|
|
|
|
}
|
|
|
|
|
if (RxStatus & 0x200) {
|
|
|
|
|
printf("rx crc error\n");
|
|
|
|
|
}
|
|
|
|
|
if (RxStatus & 0x8000) {
|
|
|
|
|
printf("rx length error\n");
|
|
|
|
|
}
|
|
|
|
|
if (RxLen > DM9000_PKT_MAX) {
|
|
|
|
|
printf("rx length too big\n");
|
|
|
|
|
dm9000_reset(priv);
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
|
|
|
|
|
/* Pass to upper layer */
|
|
|
|
|
debug("passing packet to upper layer\n");
|
|
|
|
|
net_receive(NetRxPackets[0], RxLen);
|
|
|
|
|
return RxLen;
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static u16 read_srom_word(struct dm9000_priv *priv, int offset)
|
|
|
|
|
{
|
|
|
|
|
DM9000_iow(priv, DM9000_EPAR, offset);
|
|
|
|
|
DM9000_iow(priv, DM9000_EPCR, 0x4);
|
|
|
|
|
udelay(200);
|
|
|
|
|
DM9000_iow(priv, DM9000_EPCR, 0x0);
|
|
|
|
|
return (DM9000_ior(priv, DM9000_EPDRL) + (DM9000_ior(priv, DM9000_EPDRH) << 8));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dm9000_get_ethaddr(struct eth_device *edev, unsigned char *adr)
|
|
|
|
|
{
|
|
|
|
|
struct dm9000_priv *priv = (struct dm9000_priv *)edev->priv;
|
|
|
|
|
int i, oft;
|
|
|
|
|
|
|
|
|
|
if (priv->srom) {
|
|
|
|
|
for (i = 0; i < 3; i++)
|
|
|
|
|
((u16 *) adr)[i] = read_srom_word(priv, i);
|
|
|
|
|
} else {
|
|
|
|
|
for (i = 0, oft = 0x10; i < 6; i++, oft++)
|
|
|
|
|
adr[i] = DM9000_ior(priv, oft);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dm9000_set_ethaddr(struct eth_device *edev, unsigned char *adr)
|
|
|
|
|
{
|
|
|
|
|
struct dm9000_priv *priv = (struct dm9000_priv *)edev->priv;
|
|
|
|
|
int i, oft;
|
|
|
|
|
|
|
|
|
|
debug("%s\n", __FUNCTION__);
|
|
|
|
|
|
|
|
|
|
for (i = 0, oft = 0x10; i < 6; i++, oft++)
|
|
|
|
|
DM9000_iow(priv, oft, adr[i]);
|
|
|
|
|
for (i = 0, oft = 0x16; i < 8; i++, oft++)
|
|
|
|
|
DM9000_iow(priv, oft, 0xff);
|
|
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
|
for (i = 0; i < 5; i++)
|
|
|
|
|
printf ("%02x:", adr[i]);
|
|
|
|
|
printf ("%02x\n", adr[5]);
|
|
|
|
|
#endif
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dm9000_init_dev(struct eth_device *edev)
|
|
|
|
|
{
|
|
|
|
|
struct dm9000_priv *priv = (struct dm9000_priv *)edev->priv;
|
|
|
|
|
|
|
|
|
|
miidev_restart_aneg(&priv->miidev);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dm9000_probe(struct device_d *dev)
|
|
|
|
|
{
|
|
|
|
|
struct eth_device *edev;
|
|
|
|
|
struct dm9000_priv *priv;
|
|
|
|
|
struct dm9000_platform_data *pdata;
|
|
|
|
|
|
|
|
|
|
debug("dm9000_eth_init()\n");
|
|
|
|
|
|
|
|
|
|
edev = xzalloc(sizeof(struct eth_device) + sizeof(struct dm9000_priv));
|
|
|
|
|
dev->type_data = edev;
|
|
|
|
|
edev->priv = (struct dm9000_priv *)(edev + 1);
|
|
|
|
|
|
|
|
|
|
if (!dev->platform_data) {
|
|
|
|
|
printf("dm9000: no platform_data\n");
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (dev->num_resources < 2) {
|
|
|
|
|
printf("dm9000: need 2 resources base and data");
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
pdata = dev->platform_data;
|
|
|
|
|
|
|
|
|
|
priv = edev->priv;
|
|
|
|
|
|
|
|
|
|
priv->buswidth = dev->resource[0].flags & IORESOURCE_MEM_TYPE_MASK;
|
|
|
|
|
priv->iodata = dev_request_mem_region(dev, 1);
|
|
|
|
|
priv->iobase = dev_request_mem_region(dev, 0);
|
|
|
|
|
priv->srom = pdata->srom;
|
|
|
|
|
|
|
|
|
|
edev->init = dm9000_init_dev;
|
|
|
|
|
edev->open = dm9000_eth_open;
|
|
|
|
|
edev->send = dm9000_eth_send;
|
|
|
|
|
edev->recv = dm9000_eth_rx;
|
|
|
|
|
edev->halt = dm9000_eth_halt;
|
|
|
|
|
edev->set_ethaddr = dm9000_set_ethaddr;
|
|
|
|
|
edev->get_ethaddr = dm9000_get_ethaddr;
|
|
|
|
|
edev->parent = dev;
|
|
|
|
|
|
|
|
|
|
/* RESET device */
|
|
|
|
|
dm9000_reset(priv);
|
|
|
|
|
if(dm9000_check_id(priv))
|
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
|
|
/* Program operating register */
|
|
|
|
|
DM9000_iow(priv, DM9000_NCR, 0x0); /* only intern phy supported by now */
|
|
|
|
|
DM9000_iow(priv, DM9000_TCR, 0); /* TX Polling clear */
|
|
|
|
|
DM9000_iow(priv, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
|
|
|
|
|
DM9000_iow(priv, DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */
|
|
|
|
|
DM9000_iow(priv, DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */
|
|
|
|
|
DM9000_iow(priv, DM9000_SMCR, 0); /* Special Mode */
|
|
|
|
|
DM9000_iow(priv, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
|
|
|
|
|
DM9000_iow(priv, DM9000_ISR, 0x0f); /* Clear interrupt status */
|
|
|
|
|
|
|
|
|
|
/* Activate DM9000 */
|
|
|
|
|
DM9000_iow(priv, DM9000_GPCR, 0x01); /* Let GPIO0 output */
|
|
|
|
|
DM9000_iow(priv, DM9000_GPR, 0x00); /* Enable PHY */
|
|
|
|
|
DM9000_iow(priv, DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */
|
|
|
|
|
DM9000_iow(priv, DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */
|
|
|
|
|
|
|
|
|
|
priv->miidev.read = dm9000_phy_read;
|
|
|
|
|
priv->miidev.write = dm9000_phy_write;
|
|
|
|
|
priv->miidev.address = 0;
|
|
|
|
|
priv->miidev.flags = 0;
|
|
|
|
|
priv->miidev.edev = edev;
|
|
|
|
|
priv->miidev.parent = dev;
|
|
|
|
|
|
|
|
|
|
mii_register(&priv->miidev);
|
|
|
|
|
eth_register(edev);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct driver_d dm9000_driver = {
|
|
|
|
|
.name = "dm9000",
|
|
|
|
|
.probe = dm9000_probe,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int dm9000_init(void)
|
|
|
|
|
{
|
|
|
|
|
register_driver(&dm9000_driver);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
device_initcall(dm9000_init);
|
|
|
|
|
|