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* Some code cleanup 

* Patch by Josef Baumgartner, 10 Feb 2004:
  Fixes for Coldfire port

* Patch by Brad Kemp, 11 Feb 2004:
  Fix CFI flash driver problems
This commit is contained in:
wdenk 2004-02-12 00:47:09 +00:00
parent a2d18bb7d3
commit bf9e3b38f7
76 changed files with 7717 additions and 5120 deletions
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10
CHANGELOG
View File

@ -2,9 +2,17 @@
Changes since U-Boot 1.0.1:
======================================================================
* Some code cleanup
* Patch by Josef Baumgartner, 10 Feb 2004:
Fixes for Coldfire port
* Patch by Brad Kemp, 11 Feb 2004:
Fix CFI flash driver problems
* Make sure to use a bus clock divider of 2 only when running TQM8xxM
modules at CPU clock frequencies above 66 MHz.
* Optimize flash programming speed for LWMON (by another 100% :-)
* Patch by Jian Zhang, 3 Feb 2004:

4
Makefile
View File

@ -833,10 +833,10 @@ ZPC1900_config: unconfig
#########################################################################
M5272C3_config : unconfig
@./mkconfig $(@:_config=) m68k coldfire m5272c3
@./mkconfig $(@:_config=) m68k mcf52x2 m5272c3
M5282EVB_config : unconfig
@./mkconfig $(@:_config=) m68k coldfire m5282evb
@./mkconfig $(@:_config=) m68k mcf52x2 m5282evb
#########################################################################
## MPC85xx Systems

1098
board/bmw/flash.c
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File diff suppressed because it is too large Load Diff

62
board/bmw/ns16550.c
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@ -9,49 +9,49 @@
typedef struct NS16550 *NS16550_t;
const NS16550_t COM_PORTS[] = { (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500), (NS16550_t) ((CFG_EUMB_ADDR) + 0x4600)};
const NS16550_t COM_PORTS[] =
{ (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500),
(NS16550_t) ((CFG_EUMB_ADDR) + 0x4600) };
volatile struct NS16550 *
NS16550_init(int chan, int baud_divisor)
volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
{
volatile struct NS16550 *com_port;
com_port = (struct NS16550 *) COM_PORTS[chan];
com_port->ier = 0x00;
com_port->lcr = LCR_BKSE; /* Access baud rate */
com_port->dll = baud_divisor & 0xff; /* 9600 baud */
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
com_port->mcr = MCR_RTS; /* RTS/DTR */
com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */
return (com_port);
volatile struct NS16550 *com_port;
com_port = (struct NS16550 *) COM_PORTS[chan];
com_port->ier = 0x00;
com_port->lcr = LCR_BKSE; /* Access baud rate */
com_port->dll = baud_divisor & 0xff; /* 9600 baud */
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
com_port->mcr = MCR_RTS; /* RTS/DTR */
com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */
return (com_port);
}
void
NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor)
void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
{
com_port->ier = 0x00;
com_port->lcr = LCR_BKSE; /* Access baud rate */
com_port->dll = baud_divisor & 0xff; /* 9600 baud */
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
com_port->mcr = MCR_RTS; /* RTS/DTR */
com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */
com_port->ier = 0x00;
com_port->lcr = LCR_BKSE; /* Access baud rate */
com_port->dll = baud_divisor & 0xff; /* 9600 baud */
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
com_port->mcr = MCR_RTS; /* RTS/DTR */
com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */
}
void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c)
void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
{
while ((com_port->lsr & LSR_THRE) == 0) ;
com_port->thr = c;
while ((com_port->lsr & LSR_THRE) == 0);
com_port->thr = c;
}
unsigned char
NS16550_getc(volatile struct NS16550 *com_port)
unsigned char NS16550_getc (volatile struct NS16550 *com_port)
{
while ((com_port->lsr & LSR_DR) == 0) ;
return (com_port->rbr);
while ((com_port->lsr & LSR_DR) == 0);
return (com_port->rbr);
}
int NS16550_tstc(volatile struct NS16550 *com_port)
int NS16550_tstc (volatile struct NS16550 *com_port)
{
return ((com_port->lsr & LSR_DR) != 0);
return ((com_port->lsr & LSR_DR) != 0);
}

85
board/bmw/ns16550.h
View File

@ -12,20 +12,19 @@
*/
struct NS16550
{
unsigned char rbrthrdlb; /* 0 */
unsigned char ierdmb; /* 1 */
unsigned char iirfcrafr; /* 2 */
unsigned char lcr; /* 3 */
unsigned char mcr; /* 4 */
unsigned char lsr; /* 5 */
unsigned char msr; /* 6 */
unsigned char scr; /* 7 */
unsigned char reserved[2]; /* 8 & 9 */
unsigned char dsr; /* 10 */
unsigned char dcr; /* 11 */
};
struct NS16550 {
unsigned char rbrthrdlb; /* 0 */
unsigned char ierdmb; /* 1 */
unsigned char iirfcrafr; /* 2 */
unsigned char lcr; /* 3 */
unsigned char mcr; /* 4 */
unsigned char lsr; /* 5 */
unsigned char msr; /* 6 */
unsigned char scr; /* 7 */
unsigned char reserved[2]; /* 8 & 9 */
unsigned char dsr; /* 10 */
unsigned char dcr; /* 11 */
};
#define rbr rbrthrdlb
@ -37,44 +36,44 @@ struct NS16550
#define fcr iirfcrafr
#define afr iirfcrafr
#define FCR_FIFO_EN 0x01 /*fifo enable*/
#define FCR_RXSR 0x02 /*reciever soft reset*/
#define FCR_TXSR 0x04 /*transmitter soft reset*/
#define FCR_DMS 0x08 /* DMA Mode Select */
#define FCR_FIFO_EN 0x01 /*fifo enable */
#define FCR_RXSR 0x02 /*reciever soft reset */
#define FCR_TXSR 0x04 /*transmitter soft reset */
#define FCR_DMS 0x08 /* DMA Mode Select */
#define MCR_RTS 0x02 /* Readyu to Send */
#define MCR_RTS 0x02 /* Readyu to Send */
#define MCR_LOOP 0x10 /* Local loopback mode enable */
/* #define MCR_DTR 0x01 noton 8245 duart */
/* #define MCR_DMA_EN 0x04 noton 8245 duart */
/* #define MCR_TX_DFR 0x08 noton 8245 duart */
#define LCR_WLS_MSK 0x03 /* character length slect mask*/
#define LCR_WLS_5 0x00 /* 5 bit character length */
#define LCR_WLS_6 0x01 /* 6 bit character length */
#define LCR_WLS_7 0x02 /* 7 bit character length */
#define LCR_WLS_8 0x03 /* 8 bit character length */
#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
#define LCR_PEN 0x08 /* Parity eneble*/
#define LCR_EPS 0x10 /* Even Parity Select*/
#define LCR_STKP 0x20 /* Stick Parity*/
#define LCR_SBRK 0x40 /* Set Break*/
#define LCR_BKSE 0x80 /* Bank select enable - aka DLAB on 8245 */
#define LCR_WLS_MSK 0x03 /* character length slect mask */
#define LCR_WLS_5 0x00 /* 5 bit character length */
#define LCR_WLS_6 0x01 /* 6 bit character length */
#define LCR_WLS_7 0x02 /* 7 bit character length */
#define LCR_WLS_8 0x03 /* 8 bit character length */
#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
#define LCR_PEN 0x08 /* Parity eneble */
#define LCR_EPS 0x10 /* Even Parity Select */
#define LCR_STKP 0x20 /* Stick Parity */
#define LCR_SBRK 0x40 /* Set Break */
#define LCR_BKSE 0x80 /* Bank select enable - aka DLAB on 8245 */
#define LSR_DR 0x01 /* Data ready */
#define LSR_OE 0x02 /* Overrun */
#define LSR_PE 0x04 /* Parity error */
#define LSR_FE 0x08 /* Framing error */
#define LSR_BI 0x10 /* Break */
#define LSR_THRE 0x20 /* Xmit holding register empty */
#define LSR_TEMT 0x40 /* Xmitter empty */
#define LSR_ERR 0x80 /* Error */
#define LSR_DR 0x01 /* Data ready */
#define LSR_OE 0x02 /* Overrun */
#define LSR_PE 0x04 /* Parity error */
#define LSR_FE 0x08 /* Framing error */
#define LSR_BI 0x10 /* Break */
#define LSR_THRE 0x20 /* Xmit holding register empty */
#define LSR_TEMT 0x40 /* Xmitter empty */
#define LSR_ERR 0x80 /* Error */
/* useful defaults for LCR*/
#define LCR_8N1 0x03
volatile struct NS16550 * NS16550_init(int chan, int baud_divisor);
void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c);
unsigned char NS16550_getc(volatile struct NS16550 *com_port);
int NS16550_tstc(volatile struct NS16550 *com_port);
void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
volatile struct NS16550 *NS16550_init (int chan, int baud_divisor);
void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c);
unsigned char NS16550_getc (volatile struct NS16550 *com_port);
int NS16550_tstc (volatile struct NS16550 *com_port);
void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor);

371
board/cogent/mb.c
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@ -43,152 +43,166 @@
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 0, 0, 0, 0, 0, 0 },
/* PA30 */ { 0, 0, 0, 0, 0, 0 },
/* PA29 */ { 0, 0, 0, 0, 0, 0 },
/* PA28 */ { 0, 0, 0, 0, 0, 0 },
/* PA27 */ { 0, 0, 0, 0, 0, 0 },
/* PA26 */ { 0, 0, 0, 0, 0, 0 },
/* PA25 */ { 0, 0, 0, 0, 0, 0 },
/* PA24 */ { 0, 0, 0, 0, 0, 0 },
/* PA23 */ { 0, 0, 0, 0, 0, 0 },
/* PA22 */ { 0, 0, 0, 0, 0, 0 },
/* PA21 */ { 0, 0, 0, 0, 0, 0 },
/* PA20 */ { 0, 0, 0, 0, 0, 0 },
/* PA19 */ { 0, 0, 0, 0, 0, 0 },
/* PA18 */ { 0, 0, 0, 0, 0, 0 },
/* PA17 */ { 0, 0, 0, 0, 0, 0 },
/* PA16 */ { 0, 0, 0, 0, 0, 0 },
/* PA15 */ { 0, 0, 0, 0, 0, 0 },
/* PA14 */ { 0, 0, 0, 0, 0, 0 },
/* PA13 */ { 0, 0, 0, 0, 0, 0 },
/* PA12 */ { 0, 0, 0, 0, 0, 0 },
/* PA11 */ { 0, 0, 0, 0, 0, 0 },
/* PA10 */ { 0, 0, 0, 0, 0, 0 },
/* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
/* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
/* PA7 */ { 0, 0, 0, 0, 0, 0 },
/* PA6 */ { 0, 0, 0, 0, 0, 0 },
/* PA5 */ { 0, 0, 0, 0, 0, 0 },
/* PA4 */ { 0, 0, 0, 0, 0, 0 },
/* PA3 */ { 0, 0, 0, 0, 0, 0 },
/* PA2 */ { 0, 0, 0, 0, 0, 0 },
/* PA1 */ { 0, 0, 0, 0, 0, 0 },
/* PA0 */ { 0, 0, 0, 0, 0, 0 }
},
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ {0, 0, 0, 0, 0, 0},
/* PA30 */ {0, 0, 0, 0, 0, 0},
/* PA29 */ {0, 0, 0, 0, 0, 0},
/* PA28 */ {0, 0, 0, 0, 0, 0},
/* PA27 */ {0, 0, 0, 0, 0, 0},
/* PA26 */ {0, 0, 0, 0, 0, 0},
/* PA25 */ {0, 0, 0, 0, 0, 0},
/* PA24 */ {0, 0, 0, 0, 0, 0},
/* PA23 */ {0, 0, 0, 0, 0, 0},
/* PA22 */ {0, 0, 0, 0, 0, 0},
/* PA21 */ {0, 0, 0, 0, 0, 0},
/* PA20 */ {0, 0, 0, 0, 0, 0},
/* PA19 */ {0, 0, 0, 0, 0, 0},
/* PA18 */ {0, 0, 0, 0, 0, 0},
/* PA17 */ {0, 0, 0, 0, 0, 0},
/* PA16 */ {0, 0, 0, 0, 0, 0},
/* PA15 */ {0, 0, 0, 0, 0, 0},
/* PA14 */ {0, 0, 0, 0, 0, 0},
/* PA13 */ {0, 0, 0, 0, 0, 0},
/* PA12 */ {0, 0, 0, 0, 0, 0},
/* PA11 */ {0, 0, 0, 0, 0, 0},
/* PA10 */ {0, 0, 0, 0, 0, 0},
/* PA9 */ {1, 1, 0, 1, 0, 0},
/* SMC2 TXD */
/* PA8 */ {1, 1, 0, 0, 0, 0},
/* SMC2 RXD */
/* PA7 */ {0, 0, 0, 0, 0, 0},
/* PA6 */ {0, 0, 0, 0, 0, 0},
/* PA5 */ {0, 0, 0, 0, 0, 0},
/* PA4 */ {0, 0, 0, 0, 0, 0},
/* PA3 */ {0, 0, 0, 0, 0, 0},
/* PA2 */ {0, 0, 0, 0, 0, 0},
/* PA1 */ {0, 0, 0, 0, 0, 0},
/* PA0 */ {0, 0, 0, 0, 0, 0}
},
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 0, 0, 0, 0, 0, 0 },
/* PB30 */ { 0, 0, 0, 0, 0, 0 },
/* PB29 */ { 0, 0, 0, 0, 0, 0 },
/* PB28 */ { 0, 0, 0, 0, 0, 0 },
/* PB27 */ { 0, 0, 0, 0, 0, 0 },
/* PB26 */ { 0, 0, 0, 0, 0, 0 },
/* PB25 */ { 0, 0, 0, 0, 0, 0 },
/* PB24 */ { 0, 0, 0, 0, 0, 0 },
/* PB23 */ { 0, 0, 0, 0, 0, 0 },
/* PB22 */ { 0, 0, 0, 0, 0, 0 },
/* PB21 */ { 0, 0, 0, 0, 0, 0 },
/* PB20 */ { 0, 0, 0, 0, 0, 0 },
/* PB19 */ { 0, 0, 0, 0, 0, 0 },
/* PB18 */ { 0, 0, 0, 0, 0, 0 },
/* PB17 */ { 0, 0, 0, 0, 0, 0 },
/* PB16 */ { 0, 0, 0, 0, 0, 0 },
/* PB15 */ { 0, 0, 0, 0, 0, 0 },
/* PB14 */ { 0, 0, 0, 0, 0, 0 },
/* PB13 */ { 0, 0, 0, 0, 0, 0 },
/* PB12 */ { 0, 0, 0, 0, 0, 0 },
/* PB11 */ { 0, 0, 0, 0, 0, 0 },
/* PB10 */ { 0, 0, 0, 0, 0, 0 },
/* PB9 */ { 0, 0, 0, 0, 0, 0 },
/* PB8 */ { 0, 0, 0, 0, 0, 0 },
/* PB7 */ { 0, 0, 0, 0, 0, 0 },
/* PB6 */ { 0, 0, 0, 0, 0, 0 },
/* PB5 */ { 0, 0, 0, 0, 0, 0 },
/* PB4 */ { 0, 0, 0, 0, 0, 0 },
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ {0, 0, 0, 0, 0, 0},
/* PB30 */ {0, 0, 0, 0, 0, 0},
/* PB29 */ {0, 0, 0, 0, 0, 0},
/* PB28 */ {0, 0, 0, 0, 0, 0},
/* PB27 */ {0, 0, 0, 0, 0, 0},
/* PB26 */ {0, 0, 0, 0, 0, 0},
/* PB25 */ {0, 0, 0, 0, 0, 0},
/* PB24 */ {0, 0, 0, 0, 0, 0},
/* PB23 */ {0, 0, 0, 0, 0, 0},
/* PB22 */ {0, 0, 0, 0, 0, 0},
/* PB21 */ {0, 0, 0, 0, 0, 0},
/* PB20 */ {0, 0, 0, 0, 0, 0},
/* PB19 */ {0, 0, 0, 0, 0, 0},
/* PB18 */ {0, 0, 0, 0, 0, 0},
/* PB17 */ {0, 0, 0, 0, 0, 0},
/* PB16 */ {0, 0, 0, 0, 0, 0},
/* PB15 */ {0, 0, 0, 0, 0, 0},
/* PB14 */ {0, 0, 0, 0, 0, 0},
/* PB13 */ {0, 0, 0, 0, 0, 0},
/* PB12 */ {0, 0, 0, 0, 0, 0},
/* PB11 */ {0, 0, 0, 0, 0, 0},
/* PB10 */ {0, 0, 0, 0, 0, 0},
/* PB9 */ {0, 0, 0, 0, 0, 0},
/* PB8 */ {0, 0, 0, 0, 0, 0},
/* PB7 */ {0, 0, 0, 0, 0, 0},
/* PB6 */ {0, 0, 0, 0, 0, 0},
/* PB5 */ {0, 0, 0, 0, 0, 0},
/* PB4 */ {0, 0, 0, 0, 0, 0},
/* PB3 */ {0, 0, 0, 0, 0, 0},
/* pin doesn't exist */
/* PB2 */ {0, 0, 0, 0, 0, 0},
/* pin doesn't exist */
/* PB1 */ {0, 0, 0, 0, 0, 0},
/* pin doesn't exist */
/* PB0 */ {0, 0, 0, 0, 0, 0}
/* pin doesn't exist */
},
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 0, 0, 0 },
/* PC30 */ { 0, 0, 0, 0, 0, 0 },
/* PC29 */ { 0, 0, 0, 0, 0, 0 },
/* PC28 */ { 0, 0, 0, 0, 0, 0 },
/* PC27 */ { 0, 0, 0, 0, 0, 0 },
/* PC26 */ { 0, 0, 0, 0, 0, 0 },
/* PC25 */ { 0, 0, 0, 0, 0, 0 },
/* PC24 */ { 0, 0, 0, 0, 0, 0 },
/* PC23 */ { 0, 0, 0, 0, 0, 0 },
/* PC22 */ { 0, 0, 0, 0, 0, 0 },
/* PC21 */ { 0, 0, 0, 0, 0, 0 },
/* PC20 */ { 0, 0, 0, 0, 0, 0 },
/* PC19 */ { 0, 0, 0, 0, 0, 0 },
/* PC18 */ { 0, 0, 0, 0, 0, 0 },
/* PC17 */ { 0, 0, 0, 0, 0, 0 },
/* PC16 */ { 0, 0, 0, 0, 0, 0 },
/* PC15 */ { 0, 0, 0, 0, 0, 0 },
/* PC14 */ { 0, 0, 0, 0, 0, 0 },
/* PC13 */ { 0, 0, 0, 0, 0, 0 },
/* PC12 */ { 0, 0, 0, 0, 0, 0 },
/* PC11 */ { 0, 0, 0, 0, 0, 0 },
/* PC10 */ { 0, 0, 0, 0, 0, 0 },
/* PC9 */ { 0, 0, 0, 0, 0, 0 },
/* PC8 */ { 0, 0, 0, 0, 0, 0 },
/* PC7 */ { 0, 0, 0, 0, 0, 0 },
/* PC6 */ { 0, 0, 0, 0, 0, 0 },
/* PC5 */ { 0, 0, 0, 0, 0, 0 },
/* PC4 */ { 0, 0, 0, 0, 0, 0 },
/* PC3 */ { 0, 0, 0, 0, 0, 0 },
/* PC2 */ { 0, 0, 0, 0, 0, 0 },
/* PC1 */ { 0, 0, 0, 0, 0, 0 },
/* PC0 */ { 0, 0, 0, 0, 0, 0 }
},
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ {0, 0, 0, 0, 0, 0},
/* PC30 */ {0, 0, 0, 0, 0, 0},
/* PC29 */ {0, 0, 0, 0, 0, 0},
/* PC28 */ {0, 0, 0, 0, 0, 0},
/* PC27 */ {0, 0, 0, 0, 0, 0},
/* PC26 */ {0, 0, 0, 0, 0, 0},
/* PC25 */ {0, 0, 0, 0, 0, 0},
/* PC24 */ {0, 0, 0, 0, 0, 0},
/* PC23 */ {0, 0, 0, 0, 0, 0},
/* PC22 */ {0, 0, 0, 0, 0, 0},
/* PC21 */ {0, 0, 0, 0, 0, 0},
/* PC20 */ {0, 0, 0, 0, 0, 0},
/* PC19 */ {0, 0, 0, 0, 0, 0},
/* PC18 */ {0, 0, 0, 0, 0, 0},
/* PC17 */ {0, 0, 0, 0, 0, 0},
/* PC16 */ {0, 0, 0, 0, 0, 0},
/* PC15 */ {0, 0, 0, 0, 0, 0},
/* PC14 */ {0, 0, 0, 0, 0, 0},
/* PC13 */ {0, 0, 0, 0, 0, 0},
/* PC12 */ {0, 0, 0, 0, 0, 0},
/* PC11 */ {0, 0, 0, 0, 0, 0},
/* PC10 */ {0, 0, 0, 0, 0, 0},
/* PC9 */ {0, 0, 0, 0, 0, 0},
/* PC8 */ {0, 0, 0, 0, 0, 0},
/* PC7 */ {0, 0, 0, 0, 0, 0},
/* PC6 */ {0, 0, 0, 0, 0, 0},
/* PC5 */ {0, 0, 0, 0, 0, 0},
/* PC4 */ {0, 0, 0, 0, 0, 0},
/* PC3 */ {0, 0, 0, 0, 0, 0},
/* PC2 */ {0, 0, 0, 0, 0, 0},
/* PC1 */ {0, 0, 0, 0, 0, 0},
/* PC0 */ {0, 0, 0, 0, 0, 0}
},
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 0, 0, 0, 0, 0, 0 },
/* PD30 */ { 0, 0, 0, 0, 0, 0 },
/* PD29 */ { 0, 0, 0, 0, 0, 0 },
/* PD28 */ { 0, 0, 0, 0, 0, 0 },
/* PD27 */ { 0, 0, 0, 0, 0, 0 },
/* PD26 */ { 0, 0, 0, 0, 0, 0 },
/* PD25 */ { 0, 0, 0, 0, 0, 0 },
/* PD24 */ { 0, 0, 0, 0, 0, 0 },
/* PD23 */ { 0, 0, 0, 0, 0, 0 },
/* PD22 */ { 0, 0, 0, 0, 0, 0 },
/* PD21 */ { 0, 0, 0, 0, 0, 0 },
/* PD20 */ { 0, 0, 0, 0, 0, 0 },
/* PD19 */ { 0, 0, 0, 0, 0, 0 },
/* PD18 */ { 0, 0, 0, 0, 0, 0 },
/* PD17 */ { 0, 0, 0, 0, 0, 0 },
/* PD16 */ { 0, 0, 0, 0, 0, 0 },
/* PD15 */ { 1, 1, 1, 0, 0, 0 }, /* I2C SDA */
/* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C SCL */
/* PD13 */ { 0, 0, 0, 0, 0, 0 },
/* PD12 */ { 0, 0, 0, 0, 0, 0 },
/* PD11 */ { 0, 0, 0, 0, 0, 0 },
/* PD10 */ { 0, 0, 0, 0, 0, 0 },
/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
/* PD7 */ { 0, 0, 0, 0, 0, 0 },
/* PD6 */ { 0, 0, 0, 0, 0, 0 },
/* PD5 */ { 0, 0, 0, 0, 0, 0 },
/* PD4 */ { 0, 0, 0, 0, 0, 0 },
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ {0, 0, 0, 0, 0, 0},
/* PD30 */ {0, 0, 0, 0, 0, 0},
/* PD29 */ {0, 0, 0, 0, 0, 0},
/* PD28 */ {0, 0, 0, 0, 0, 0},
/* PD27 */ {0, 0, 0, 0, 0, 0},
/* PD26 */ {0, 0, 0, 0, 0, 0},
/* PD25 */ {0, 0, 0, 0, 0, 0},
/* PD24 */ {0, 0, 0, 0, 0, 0},
/* PD23 */ {0, 0, 0, 0, 0, 0},
/* PD22 */ {0, 0, 0, 0, 0, 0},
/* PD21 */ {0, 0, 0, 0, 0, 0},
/* PD20 */ {0, 0, 0, 0, 0, 0},
/* PD19 */ {0, 0, 0, 0, 0, 0},
/* PD18 */ {0, 0, 0, 0, 0, 0},
/* PD17 */ {0, 0, 0, 0, 0, 0},
/* PD16 */ {0, 0, 0, 0, 0, 0},
/* PD15 */ {1, 1, 1, 0, 0, 0},
/* I2C SDA */
/* PD14 */ {1, 1, 1, 0, 0, 0},
/* I2C SCL */
/* PD13 */ {0, 0, 0, 0, 0, 0},
/* PD12 */ {0, 0, 0, 0, 0, 0},
/* PD11 */ {0, 0, 0, 0, 0, 0},
/* PD10 */ {0, 0, 0, 0, 0, 0},
/* PD9 */ {1, 1, 0, 1, 0, 0},
/* SMC1 TXD */
/* PD8 */ {1, 1, 0, 0, 0, 0},
/* SMC1 RXD */
/* PD7 */ {0, 0, 0, 0, 0, 0},
/* PD6 */ {0, 0, 0, 0, 0, 0},
/* PD5 */ {0, 0, 0, 0, 0, 0},
/* PD4 */ {0, 0, 0, 0, 0, 0},
/* PD3 */ {0, 0, 0, 0, 0, 0},
/* pin doesn't exist */
/* PD2 */ {0, 0, 0, 0, 0, 0},
/* pin doesn't exist */
/* PD1 */ {0, 0, 0, 0, 0, 0},
/* pin doesn't exist */
/* PD0 */ {0, 0, 0, 0, 0, 0}
/* pin doesn't exist */
}
};
#endif /* CONFIG_8260 */
#endif /* CONFIG_8260 */
/* ------------------------------------------------------------------------- */
@ -196,12 +210,11 @@ const iop_conf_t iop_conf_tab[4][32] = {
* Check Board Identity:
*/
int
checkboard(void)
int checkboard (void)
{
puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a "
COGENT_CPU_MODULE " CPU Module\n");
return (0);
puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a "
COGENT_CPU_MODULE " CPU Module\n");
return (0);
}
/* ------------------------------------------------------------------------- */
@ -213,46 +226,44 @@ checkboard(void)
int misc_init_f (void)
{
printf ("DIPSW: ");
dipsw_init();
return (0);
printf ("DIPSW: ");
dipsw_init ();
return (0);
}
/* ------------------------------------------------------------------------- */
long int
initdram(int board_type)
long int initdram (int board_type)
{
#if CONFIG_CMA111
return (32L * 1024L * 1024L);
return (32L * 1024L * 1024L);
#else
unsigned char dipsw_val;
int dual, size0, size1;
long int memsize;
unsigned char dipsw_val;
int dual, size0, size1;
long int memsize;
dipsw_val = dipsw_cooked();
dipsw_val = dipsw_cooked ();
dual = dipsw_val & 0x01;
size0 = (dipsw_val & 0x08) >> 3;
size1 = (dipsw_val & 0x04) >> 2;
dual = dipsw_val & 0x01;
size0 = (dipsw_val & 0x08) >> 3;
size1 = (dipsw_val & 0x04) >> 2;
if (size0)
if (size1)
memsize = 16L * 1024L * 1024L;
else
memsize = 1L * 1024L * 1024L;
else
if (size1)
memsize = 4L * 1024L * 1024L;
if (size0)
if (size1)
memsize = 16L * 1024L * 1024L;
else
memsize = 1L * 1024L * 1024L;
else if (size1)
memsize = 4L * 1024L * 1024L;
else {
printf("[Illegal dip switch settings - assuming 16Mbyte SIMMs] ");
memsize = 16L * 1024L * 1024L; /* shouldn't happen - guess 16M */
printf ("[Illegal dip switch settings - assuming 16Mbyte SIMMs] ");
memsize = 16L * 1024L * 1024L; /* shouldn't happen - guess 16M */
}
if (dual)
memsize *= 2L;
if (dual)
memsize *= 2L;
return (memsize);
return (memsize);
#endif
}
@ -265,21 +276,21 @@ initdram(int board_type)
int misc_init_r (void)
{
printf ("LCD: ");
lcd_init();
printf ("LCD: ");
lcd_init ();
#if 0
printf ("RTC: ");
rtc_init();
printf ("RTC: ");
rtc_init ();
printf ("PAR: ");
par_init();
printf ("PAR: ");
par_init ();
printf ("KBM: ");
kbm_init();
printf ("KBM: ");
kbm_init ();
printf ("PCI: ");
pci_init();
printf ("PCI: ");
pci_init ();
#endif
return (0);
return (0);
}

191
board/eltec/bab7xx/bab7xx.c
View File

@ -37,17 +37,18 @@
*/
ulong bab7xx_get_bus_freq (void)
{
/*
* The GPIO Port 1 on BAB7xx reflects the bus speed.
*/
volatile struct GPIO *gpio = (struct GPIO *)(CFG_ISA_IO + CFG_NS87308_GPIO_BASE);
/*
* The GPIO Port 1 on BAB7xx reflects the bus speed.
*/
volatile struct GPIO *gpio =
(struct GPIO *) (CFG_ISA_IO + CFG_NS87308_GPIO_BASE);
unsigned char data = gpio->dta1;
unsigned char data = gpio->dta1;
if (data & 0x02)
return 66666666;
if (data & 0x02)
return 66666666;
return 83333333;
return 83333333;
}
/*---------------------------------------------------------------------------*/
@ -57,24 +58,26 @@ ulong bab7xx_get_bus_freq (void)
*/
ulong bab7xx_get_gclk_freq (void)
{
static const int pllratio_to_factor[] = {
00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35, 00,
};
static const int pllratio_to_factor[] = {
00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35,
00,
};
return pllratio_to_factor[get_hid1 () >> 28] * (bab7xx_get_bus_freq() / 10);
return pllratio_to_factor[get_hid1 () >> 28] *
(bab7xx_get_bus_freq () / 10);
}
/*----------------------------------------------------------------------------*/
int checkcpu (void)
{
uint pvr = get_pvr();
uint pvr = get_pvr ();
printf ("MPC7xx V%d.%d",(pvr >> 8) & 0xFF, pvr & 0xFF);
printf (" at %ld / %ld MHz\n", bab7xx_get_gclk_freq()/1000000,
bab7xx_get_bus_freq()/1000000);
printf ("MPC7xx V%d.%d", (pvr >> 8) & 0xFF, pvr & 0xFF);
printf (" at %ld / %ld MHz\n", bab7xx_get_gclk_freq () / 1000000,
bab7xx_get_bus_freq () / 1000000);
return (0);
return (0);
}
/* ------------------------------------------------------------------------- */
@ -82,20 +85,20 @@ int checkcpu (void)
int checkboard (void)
{
#ifdef CFG_ADDRESS_MAP_A
puts ("Board: ELTEC BAB7xx PReP\n");
puts ("Board: ELTEC BAB7xx PReP\n");
#else
puts ("Board: ELTEC BAB7xx CHRP\n");
puts ("Board: ELTEC BAB7xx CHRP\n");
#endif
return (0);
return (0);
}
/* ------------------------------------------------------------------------- */
int checkflash (void)
{
/* TODO: XXX XXX XXX */
printf ("2 MB ## Test not implemented yet ##\n");
return (0);
/* TODO: XXX XXX XXX */
printf ("2 MB ## Test not implemented yet ##\n");
return (0);
}
/* ------------------------------------------------------------------------- */
@ -103,77 +106,75 @@ int checkflash (void)
static unsigned int mpc106_read_cfg_dword (unsigned int reg)
{
unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
out32r(MPC106_REG_ADDR, reg_addr);
out32r (MPC106_REG_ADDR, reg_addr);
return (in32r(MPC106_REG_DATA | (reg & 0x3)));
return (in32r (MPC106_REG_DATA | (reg & 0x3)));
}
/* ------------------------------------------------------------------------- */
long int dram_size (int board_type)
{
/* No actual initialisation to do - done when setting up
* PICRs MCCRs ME/SARs etc in ram_init.S.
*/
/* No actual initialisation to do - done when setting up
* PICRs MCCRs ME/SARs etc in ram_init.S.
*/
register unsigned long i, msar1, mear1, memSize;
register unsigned long i, msar1, mear1, memSize;
#if defined(CFG_MEMTEST)
register unsigned long reg;
register unsigned long reg;
printf("Testing DRAM\n");
printf ("Testing DRAM\n");
/* write each mem addr with it's address */
for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg+=4)
*reg = reg;
/* write each mem addr with it's address */
for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4)
*reg = reg;
for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg+=4)
{
if (*reg != reg)
return -1;
}
for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) {
if (*reg != reg)
return -1;
}
#endif
/*
* Since MPC106 memory controller chip has already been set to
* control all memory, just read and interpret its memory boundery register.
*/
memSize = 0;
msar1 = mpc106_read_cfg_dword(MPC106_MSAR1);
mear1 = mpc106_read_cfg_dword(MPC106_MEAR1);
i = mpc106_read_cfg_dword(MPC106_MBER) & 0xf;
/*
* Since MPC106 memory controller chip has already been set to
* control all memory, just read and interpret its memory boundery register.
*/
memSize = 0;
msar1 = mpc106_read_cfg_dword (MPC106_MSAR1);
mear1 = mpc106_read_cfg_dword (MPC106_MEAR1);
i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf;
do
{
if (i & 0x01) /* is bank enabled ? */
memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
msar1 >>= 8;
mear1 >>= 8;
i >>= 1;
} while (i);
do {
if (i & 0x01) /* is bank enabled ? */
memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
msar1 >>= 8;
mear1 >>= 8;
i >>= 1;
} while (i);
return (memSize * 0x100000);
return (memSize * 0x100000);
}
/* ------------------------------------------------------------------------- */
long int initdram(int board_type)
long int initdram (int board_type)
{
return dram_size(board_type);
return dram_size (board_type);
}
/* ------------------------------------------------------------------------- */
void after_reloc (ulong dest_addr)
{
DECLARE_GLOBAL_DATA_PTR;
DECLARE_GLOBAL_DATA_PTR;
/*
* Jump to the main U-Boot board init code
*/
board_init_r((gd_t *)gd, dest_addr);
/*
* Jump to the main U-Boot board init code
*/
board_init_r ((gd_t *) gd, dest_addr);
}
/* ------------------------------------------------------------------------- */
@ -182,14 +183,13 @@ void after_reloc (ulong dest_addr)
* do_reset is done here because in this case it is board specific, since the
* 7xx CPUs can only be reset by external HW (the RTC in this case).
*/
void
do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
void do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
#if defined(CONFIG_RTC_MK48T59)
/* trigger watchdog immediately */
rtc_set_watchdog(1, RTC_WD_RB_16TH);
/* trigger watchdog immediately */
rtc_set_watchdog (1, RTC_WD_RB_16TH);
#else
#error "You must define the macro CONFIG_RTC_MK48T59."
#error "You must define the macro CONFIG_RTC_MK48T59."
#endif
}
@ -200,16 +200,16 @@ do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
* Since the 7xx CPUs don't have an internal watchdog, this function is
* board specific. We use the RTC here.
*/
void watchdog_reset(void)
void watchdog_reset (void)
{
#if defined(CONFIG_RTC_MK48T59)
/* we use a 32 sec watchdog timer */
rtc_set_watchdog(8, RTC_WD_RB_4);
/* we use a 32 sec watchdog timer */
rtc_set_watchdog (8, RTC_WD_RB_4);
#else
#error "You must define the macro CONFIG_RTC_MK48T59."
#error "You must define the macro CONFIG_RTC_MK48T59."
#endif
}
#endif /* CONFIG_WATCHDOG */
#endif /* CONFIG_WATCHDOG */
/* ------------------------------------------------------------------------- */
@ -218,29 +218,28 @@ extern GraphicDevice smi;
void video_get_info_str (int line_number, char *info)
{
/* init video info strings for graphic console */
switch (line_number)
{
case 1:
sprintf (info," MPC7xx V%d.%d at %ld / %ld MHz",
(get_pvr() >> 8) & 0xFF,
get_pvr() & 0xFF,
bab7xx_get_gclk_freq()/1000000,
bab7xx_get_bus_freq()/1000000);
return;
case 2:
sprintf (info, " ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH",
dram_size(0)/0x100000,
flash_init()/0x100000);
return;
case 3:
sprintf (info, " %s", smi.modeIdent);
return;
}
/* init video info strings for graphic console */
switch (line_number) {
case 1:
sprintf (info, " MPC7xx V%d.%d at %ld / %ld MHz",
(get_pvr () >> 8) & 0xFF,
get_pvr () & 0xFF,
bab7xx_get_gclk_freq () / 1000000,
bab7xx_get_bus_freq () / 1000000);
return;
case 2:
sprintf (info,
" ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH",
dram_size (0) / 0x100000, flash_init () / 0x100000);
return;
case 3:
sprintf (info, " %s", smi.modeIdent);
return;
}
/* no more info lines */
*info = 0;
return;
/* no more info lines */
*info = 0;
return;
}
#endif

369
board/eltec/elppc/misc.c
View File

@ -31,32 +31,32 @@
/* imports */
extern char console_buffer[CFG_CBSIZE];
extern int l2_cache_enable (int l2control);
extern int eepro100_write_eeprom (struct eth_device* dev, int location,
int addr_len, unsigned short data);
extern int read_eeprom (struct eth_device* dev, int location, int addr_len);
extern int eepro100_write_eeprom (struct eth_device *dev, int location,
int addr_len, unsigned short data);
extern int read_eeprom (struct eth_device *dev, int location, int addr_len);
/*----------------------------------------------------------------------------*/
/*
* read/write to nvram is only byte access
*/
void *nvram_read(void *dest, const long src, size_t count)
void *nvram_read (void *dest, const long src, size_t count)
{
uchar *d = (uchar *) dest;
uchar *s = (uchar *) (CFG_ENV_MAP_ADRS + src);
uchar *d = (uchar *) dest;
uchar *s = (uchar *) (CFG_ENV_MAP_ADRS + src);
while (count--)
*d++ = *s++;
while (count--)
*d++ = *s++;
return dest;
return dest;
}
void nvram_write(long dest, const void *src, size_t count)
void nvram_write (long dest, const void *src, size_t count)
{
uchar *d = (uchar *) (CFG_ENV_MAP_ADRS + dest);
uchar *s = (uchar *) src;
uchar *d = (uchar *) (CFG_ENV_MAP_ADRS + dest);
uchar *s = (uchar *) src;
while (count--)
*d++ = *s++;
while (count--)
*d++ = *s++;
}
/*----------------------------------------------------------------------------*/
@ -67,192 +67,199 @@ void nvram_write(long dest, const void *src, size_t count)
*/
int misc_init_r (void)
{
revinfo eerev;
u_char *ptr;
u_int i, l, initSrom, copyNv;
char buf[256];
char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
0, 0, 0, 0, 10, 11, 12, 13, 14, 15 };
revinfo eerev;
u_char *ptr;
u_int i, l, initSrom, copyNv;
char buf[256];
char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
0, 0, 0, 0, 10, 11, 12, 13, 14, 15
};
/* Clock setting for MPC107 i2c */
mpc107_i2c_init (MPC107_EUMB_ADDR, 0x2b);
/* Clock setting for MPC107 i2c */
mpc107_i2c_init (MPC107_EUMB_ADDR, 0x2b);
/* Reset the EPIC */
out32r (MPC107_EUMB_GCR, 0xa0000000);
while (in32r (MPC107_EUMB_GCR) & 0x80000000); /* Wait for reset to complete */
out32r (MPC107_EUMB_GCR, 0x20000000); /* Put into into mixed mode */
while (in32r (MPC107_EUMB_IACKR) != 0xff); /* Clear all pending interrupts */
/* Reset the EPIC */
out32r (MPC107_EUMB_GCR, 0xa0000000);
while (in32r (MPC107_EUMB_GCR) & 0x80000000); /* Wait for reset to complete */
out32r (MPC107_EUMB_GCR, 0x20000000); /* Put into into mixed mode */
while (in32r (MPC107_EUMB_IACKR) != 0xff); /* Clear all pending interrupts */
/*
* Check/Remake revision info
*/
initSrom = 0;
copyNv = 0;
/*
* Check/Remake revision info
*/
initSrom = 0;
copyNv = 0;
/* read out current revision srom contens */
mpc107_srom_load (0x0000, (u_char*)&eerev, sizeof(revinfo),
SECOND_DEVICE, FIRST_BLOCK);
/* read out current revision srom contens */
mpc107_srom_load (0x0000, (u_char *) & eerev, sizeof (revinfo),
SECOND_DEVICE, FIRST_BLOCK);
/* read out current nvram shadow image */
nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE);
/* read out current nvram shadow image */
nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE);
if (strcmp (eerev.magic, "ELTEC") != 0)
{
/* srom is not initialized -> create a default revision info */
for (i = 0, ptr = (u_char *)&eerev; i < sizeof(revinfo); i++)
*ptr++ = 0x00;
strcpy(eerev.magic, "ELTEC");
eerev.revrev[0] = 1;
eerev.revrev[1] = 0;
eerev.size = 0x00E0;
eerev.category[0] = 0x01;
if (strcmp (eerev.magic, "ELTEC") != 0) {
/* srom is not initialized -> create a default revision info */
for (i = 0, ptr = (u_char *) & eerev; i < sizeof (revinfo);
i++)
*ptr++ = 0x00;
strcpy (eerev.magic, "ELTEC");
eerev.revrev[0] = 1;
eerev.revrev[1] = 0;
eerev.size = 0x00E0;
eerev.category[0] = 0x01;
/* node id from dead e128 as default */
eerev.etheraddr[0] = 0x00;
eerev.etheraddr[1] = 0x00;
eerev.etheraddr[2] = 0x5B;
eerev.etheraddr[3] = 0x00;
eerev.etheraddr[4] = 0x2E;
eerev.etheraddr[5] = 0x4D;
/* node id from dead e128 as default */
eerev.etheraddr[0] = 0x00;
eerev.etheraddr[1] = 0x00;
eerev.etheraddr[2] = 0x5B;
eerev.etheraddr[3] = 0x00;
eerev.etheraddr[4] = 0x2E;
eerev.etheraddr[5] = 0x4D;
/* cache config word for ELPPC */
*(int*)&eerev.res[0] = 0;
/* cache config word for ELPPC */
*(int *) &eerev.res[0] = 0;
initSrom = 1; /* force dialog */
copyNv = 1; /* copy to nvram */
}
if ((copyNv == 0) && (el_srom_checksum((u_char*)&eerev, CFG_SROM_SIZE) !=
el_srom_checksum((u_char*)buf, CFG_SROM_SIZE)))
{
printf ("Invalid revision info copy in nvram !\n");
printf ("Press key:\n <c> to copy current revision info to nvram.\n");
printf (" <r> to reenter revision info.\n");
printf ("=> ");
if (0 != readline (NULL))
{
switch ((char)toupper(console_buffer[0]))
{
case 'C':
copyNv = 1;
break;
case 'R':
copyNv = 1;
initSrom = 1;
break;
}
}
}
if (initSrom)
{
memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */
printf ("Enter revision number (0-9): %c ", eerev.revision[0][0]);
if (0 != readline (NULL))
{
eerev.revision[0][0] = (char)toupper(console_buffer[0]);
memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */
initSrom = 1; /* force dialog */
copyNv = 1; /* copy to nvram */
}
printf ("Enter revision character (A-Z): %c ", eerev.revision[0][1]);
if (1 == readline (NULL))
{
eerev.revision[0][1] = (char)toupper(console_buffer[0]);
if ((copyNv == 0)
&& (el_srom_checksum ((u_char *) & eerev, CFG_SROM_SIZE) !=
el_srom_checksum ((u_char *) buf, CFG_SROM_SIZE))) {
printf ("Invalid revision info copy in nvram !\n");
printf ("Press key:\n <c> to copy current revision info to nvram.\n");
printf (" <r> to reenter revision info.\n");
printf ("=> ");
if (0 != readline (NULL)) {
switch ((char) toupper (console_buffer[0])) {
case 'C':
copyNv = 1;
break;
case 'R':
copyNv = 1;
initSrom = 1;
break;
}
}
}
printf ("Enter board name (V-XXXX-XXXX): %s ", (char *)&eerev.board);
if (11 == readline (NULL))
{
for (i=0; i<11; i++)
eerev.board[i] = (char)toupper(console_buffer[i]);
eerev.board[11] = '\0';
if (initSrom) {
memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */
printf ("Enter revision number (0-9): %c ",
eerev.revision[0][0]);
if (0 != readline (NULL)) {
eerev.revision[0][0] =
(char) toupper (console_buffer[0]);
memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */
}
printf ("Enter revision character (A-Z): %c ",
eerev.revision[0][1]);
if (1 == readline (NULL)) {
eerev.revision[0][1] =
(char) toupper (console_buffer[0]);
}
printf ("Enter board name (V-XXXX-XXXX): %s ",
(char *) &eerev.board);
if (11 == readline (NULL)) {
for (i = 0; i < 11; i++)
eerev.board[i] =
(char) toupper (console_buffer[i]);
eerev.board[11] = '\0';
}
printf ("Enter serial number: %s ", (char *) &eerev.serial);
if (6 == readline (NULL)) {
for (i = 0; i < 6; i++)
eerev.serial[i] = console_buffer[i];
eerev.serial[6] = '\0';
}
printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]);
if (12 == readline (NULL)) {
for (i = 0; i < 12; i += 2)
eerev.etheraddr[i >> 1] =
(char) (16 *
hex[toupper
(console_buffer[i]) -
'0'] +
hex[toupper
(console_buffer[i + 1]) -
'0']);
}
l = strlen ((char *) &eerev.text);
printf ("Add to text section (max 64 chr): %s ",
(char *) &eerev.text);
if (0 != readline (NULL)) {
for (i = l; i < 63; i++)
eerev.text[i] = console_buffer[i - l];
eerev.text[63] = '\0';
}
/* prepare network eeprom */
memset (buf, 0, 128);
buf[0] = eerev.etheraddr[1];
buf[1] = eerev.etheraddr[0];
buf[2] = eerev.etheraddr[3];
buf[3] = eerev.etheraddr[2];
buf[4] = eerev.etheraddr[5];
buf[5] = eerev.etheraddr[4];
*(unsigned short *) &buf[20] = 0x48B2;
*(unsigned short *) &buf[22] = 0x0004;
*(unsigned short *) &buf[24] = 0x1433;
printf ("\nSRom: Writing i82559 info ........ ");
if (eepro100_srom_store ((unsigned short *) buf) == -1)
printf ("FAILED\n");
else
printf ("OK\n");
/* update CRC */
eerev.crc =
el_srom_checksum ((u_char *) eerev.board, eerev.size);
/* write new values */
printf ("\nSRom: Writing revision info ...... ");
if (mpc107_srom_store
((BLOCK_SIZE - sizeof (revinfo)), (u_char *) & eerev,
sizeof (revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1)
printf ("FAILED\n\n");
else
printf ("OK\n\n");
/* write new values as shadow image to nvram */
nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev,
CFG_SROM_SIZE);
}
printf ("Enter serial number: %s ", (char *)&eerev.serial );
if (6 == readline (NULL))
{
for (i=0; i<6; i++)
eerev.serial[i] = console_buffer[i];
eerev.serial[6] = '\0';
}
/*if (initSrom) */
/* copy current values as shadow image to nvram */
if (initSrom == 0 && copyNv == 1)
nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev,
CFG_SROM_SIZE);
printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ",
eerev.etheraddr[0], eerev.etheraddr[1],
eerev.etheraddr[2], eerev.etheraddr[3],
eerev.etheraddr[4], eerev.etheraddr[5]);
if (12 == readline (NULL))
{
for (i=0; i<12; i+=2)
eerev.etheraddr[i>>1] = (char)(16*hex[toupper(console_buffer[i])-'0'] +
hex[toupper(console_buffer[i+1])-'0']);
}
/* update environment */
sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
eerev.etheraddr[0], eerev.etheraddr[1],
eerev.etheraddr[2], eerev.etheraddr[3],
eerev.etheraddr[4], eerev.etheraddr[5]);
setenv ("ethaddr", buf);
l = strlen ((char *)&eerev.text);
printf("Add to text section (max 64 chr): %s ", (char *)&eerev.text );
if (0 != readline (NULL))
{
for (i = l; i<63; i++)
eerev.text[i] = console_buffer[i-l];
eerev.text[63] = '\0';
}
/* set serial console as default */
if ((ptr = getenv ("console")) == NULL)
setenv ("console", "serial");
/* prepare network eeprom */
memset (buf, 0, 128);
/* print actual board identification */
printf ("Ident: %s Ser %s Rev %c%c\n",
eerev.board, (char *) &eerev.serial,
eerev.revision[0][0], eerev.revision[0][1]);
buf[0] = eerev.etheraddr[1];
buf[1] = eerev.etheraddr[0];
buf[2] = eerev.etheraddr[3];
buf[3] = eerev.etheraddr[2];
buf[4] = eerev.etheraddr[5];
buf[5] = eerev.etheraddr[4];
*(unsigned short *)&buf[20] = 0x48B2;
*(unsigned short *)&buf[22] = 0x0004;
*(unsigned short *)&buf[24] = 0x1433;
printf("\nSRom: Writing i82559 info ........ ");
if (eepro100_srom_store ((unsigned short *)buf) == -1)
printf("FAILED\n");
else
printf("OK\n");
/* update CRC */
eerev.crc = el_srom_checksum((u_char *)eerev.board, eerev.size);
/* write new values */
printf("\nSRom: Writing revision info ...... ");
if (mpc107_srom_store((BLOCK_SIZE-sizeof(revinfo)), (u_char *)&eerev,
sizeof(revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1)
printf("FAILED\n\n");
else
printf("OK\n\n");
/* write new values as shadow image to nvram */
nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE);
} /*if (initSrom) */
/* copy current values as shadow image to nvram */
if (initSrom == 0 && copyNv == 1)
nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE);
/* update environment */
sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
eerev.etheraddr[0], eerev.etheraddr[1],
eerev.etheraddr[2], eerev.etheraddr[3],
eerev.etheraddr[4], eerev.etheraddr[5]);
setenv ("ethaddr", buf);
/* set serial console as default */
if ((ptr = getenv ("console")) == NULL)
setenv ("console", "serial");
/* print actual board identification */
printf("Ident: %s Ser %s Rev %c%c\n",
eerev.board, (char *)&eerev.serial,
eerev.revision[0][0], eerev.revision[0][1]);
return (0);
return (0);
}
/*----------------------------------------------------------------------------*/

644
board/eltec/mhpc/mhpc.c
View File

@ -38,19 +38,19 @@
/* imports from common/main.c */
extern char console_buffer[CFG_CBSIZE];
extern void eeprom_init (void);
extern int eeprom_read (unsigned dev_addr, unsigned offset,
unsigned char *buffer, unsigned cnt);
extern int eeprom_write (unsigned dev_addr, unsigned offset,
unsigned char *buffer, unsigned cnt);
extern void eeprom_init (void);
extern int eeprom_read (unsigned dev_addr, unsigned offset,
unsigned char *buffer, unsigned cnt);
extern int eeprom_write (unsigned dev_addr, unsigned offset,
unsigned char *buffer, unsigned cnt);
/* globals */
void *video_hw_init(void);
void video_set_lut (unsigned int index, /* color number */
unsigned char r, /* red */
unsigned char g, /* green */
unsigned char b /* blue */
);
void *video_hw_init (void);
void video_set_lut (unsigned int index, /* color number */
unsigned char r, /* red */
unsigned char g, /* green */
unsigned char b /* blue */
);
GraphicDevice gdev;
@ -60,79 +60,78 @@ static void video_test_image (void);
static void video_default_lut (unsigned int clut_type);
/* revision info foer MHPC EEPROM offset 480 */
typedef struct {
char board[12]; /* 000 - Board Revision information */
char sensor; /* 012 - Sensor Type information */
char serial[8]; /* 013 - Board serial number */
char etheraddr[6]; /* 021 - Ethernet node addresse */
char revision[2]; /* 027 - Revision code */
char option[3]; /* 029 - resevered for options */
typedef struct {
char board[12]; /* 000 - Board Revision information */
char sensor; /* 012 - Sensor Type information */
char serial[8]; /* 013 - Board serial number */
char etheraddr[6]; /* 021 - Ethernet node addresse */
char revision[2]; /* 027 - Revision code */
char option[3]; /* 029 - resevered for options */
} revinfo;
/* ------------------------------------------------------------------------- */
static const unsigned int sdram_table[] =
{
/* read single beat cycle */
0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00,
0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35,
static const unsigned int sdram_table[] = {
/* read single beat cycle */
0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00,
0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35,
/* read burst cycle */
0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00,
0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* read burst cycle */
0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00,
0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* write single beat cycle */
0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* write single beat cycle */
0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* write burst cycle */
0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440,
0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* write burst cycle */
0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440,
0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* periodic timer expired */
0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84,
0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* periodic timer expired */
0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84,
0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* exception */
0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04
/* exception */
0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04
};
/* ------------------------------------------------------------------------- */
int board_early_init_f (void)
{
volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cp = &(im->im_cpm);
volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
volatile immap_t *im = (immap_t *) CFG_IMMR;
volatile cpm8xx_t *cp = &(im->im_cpm);
volatile iop8xx_t *ip = (iop8xx_t *) & (im->im_ioport);
/* reset the port A s.a. cpm-routines */
ip->iop_padat = 0x0000;
ip->iop_papar = 0x0000;
ip->iop_padir = 0x0800;
ip->iop_paodr = 0x0000;
/* reset the port A s.a. cpm-routines */
ip->iop_padat = 0x0000;
ip->iop_papar = 0x0000;
ip->iop_padir = 0x0800;
ip->iop_paodr = 0x0000;
/* reset the port B for digital and LCD output */
cp->cp_pbdat = 0x0300;
cp->cp_pbpar = 0x5001;
cp->cp_pbdir = 0x5301;
cp->cp_pbodr = 0x0000;
/* reset the port B for digital and LCD output */
cp->cp_pbdat = 0x0300;
cp->cp_pbpar = 0x5001;
cp->cp_pbdir = 0x5301;
cp->cp_pbodr = 0x0000;
/* reset the port C configured for SMC1 serial port and aqc. control */
ip->iop_pcdat = 0x0800;
ip->iop_pcpar = 0x0000;
ip->iop_pcdir = 0x0e30;
ip->iop_pcso = 0x0000;
/* reset the port C configured for SMC1 serial port and aqc. control */
ip->iop_pcdat = 0x0800;
ip->iop_pcpar = 0x0000;
ip->iop_pcdir = 0x0e30;
ip->iop_pcso = 0x0000;
/* Config port D for LCD output */
ip->iop_pdpar = 0x1fff;
ip->iop_pddir = 0x1fff;
/* Config port D for LCD output */
ip->iop_pdpar = 0x1fff;
ip->iop_pddir = 0x1fff;
return (0);
return (0);
}
/* ------------------------------------------------------------------------- */
@ -142,322 +141,327 @@ int board_early_init_f (void)
*/
int checkboard (void)
{
puts ("Board: ELTEC miniHiperCam\n");
return(0);
puts ("Board: ELTEC miniHiperCam\n");
return (0);
}
/* ------------------------------------------------------------------------- */
int misc_init_r(void)
int misc_init_r (void)
{
revinfo mhpcRevInfo;
char nid[32];
char *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color",
"OMNIVISON OV7110 b&w", NULL };
char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
0, 0, 0, 0, 10, 11, 12, 13, 14, 15 };
int i;
revinfo mhpcRevInfo;
char nid[32];
char *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color",
"OMNIVISON OV7110 b&w", NULL
};
char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
0, 0, 0, 0, 10, 11, 12, 13, 14, 15
};
int i;
/* check revision data */
eeprom_read (CFG_I2C_EEPROM_ADDR, 480, (char*)&mhpcRevInfo, 32);
/* check revision data */
eeprom_read (CFG_I2C_EEPROM_ADDR, 480, (char *) &mhpcRevInfo, 32);
if (strncmp((char *)&mhpcRevInfo.board[2], "MHPC", 4) != 0)
{
printf ("Enter revision number (0-9): %c ", mhpcRevInfo.revision[0]);
if (0 != readline (NULL))
{
mhpcRevInfo.revision[0] = (char)toupper(console_buffer[0]);
}
if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) {
printf ("Enter revision number (0-9): %c ",
mhpcRevInfo.revision[0]);
if (0 != readline (NULL)) {
mhpcRevInfo.revision[0] =
(char) toupper (console_buffer[0]);
}
printf ("Enter revision character (A-Z): %c ", mhpcRevInfo.revision[1]);
if (1 == readline (NULL))
{
mhpcRevInfo.revision[1] = (char)toupper(console_buffer[0]);
}
printf ("Enter revision character (A-Z): %c ",
mhpcRevInfo.revision[1]);
if (1 == readline (NULL)) {
mhpcRevInfo.revision[1] =
(char) toupper (console_buffer[0]);
}
printf("Enter board name (V-XXXX-XXXX): %s ", (char *)&mhpcRevInfo.board);
if (11 == readline (NULL))
{
for (i=0; i<11; i++)
{
mhpcRevInfo.board[i] = (char)toupper(console_buffer[i]);
mhpcRevInfo.board[11] = '\0';
printf ("Enter board name (V-XXXX-XXXX): %s ",
(char *) &mhpcRevInfo.board);
if (11 == readline (NULL)) {
for (i = 0; i < 11; i++) {
mhpcRevInfo.board[i] =
(char) toupper (console_buffer[i]);
mhpcRevInfo.board[11] = '\0';
}
}
printf ("Supported sensor types:\n");
i = 0;
do {
printf ("\n \'%d\' : %s\n", i, mhpcSensorTypes[i]);
} while (mhpcSensorTypes[++i] != NULL);
do {
printf ("\nEnter sensor number (0-255): %d ",
(int) mhpcRevInfo.sensor);
if (0 != readline (NULL)) {
mhpcRevInfo.sensor =
(unsigned char)
simple_strtoul (console_buffer, NULL,
10);
}
} while (mhpcRevInfo.sensor >= i);
printf ("Enter serial number: %s ",
(char *) &mhpcRevInfo.serial);
if (6 == readline (NULL)) {
for (i = 0; i < 6; i++) {
mhpcRevInfo.serial[i] = console_buffer[i];
}
mhpcRevInfo.serial[6] = '\0';
}
printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
if (12 == readline (NULL)) {
for (i = 0; i < 12; i += 2) {
mhpcRevInfo.etheraddr[i >> 1] =
(char) (16 *
hex[toupper
(console_buffer[i]) -
'0'] +
hex[toupper
(console_buffer[i + 1]) -
'0']);
}
}
/* setup new revision data */
eeprom_write (CFG_I2C_EEPROM_ADDR, 480, (char *) &mhpcRevInfo,
32);
}
}
printf("Supported sensor types:\n");
i=0;
do
{
printf("\n \'%d\' : %s\n", i, mhpcSensorTypes[i]);
} while ( mhpcSensorTypes[++i] != NULL );
/* set environment */
sprintf (nid, "%02x:%02x:%02x:%02x:%02x:%02x",
mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
setenv ("ethaddr", nid);
do
{
printf("\nEnter sensor number (0-255): %d ", (int)mhpcRevInfo.sensor );
if (0 != readline (NULL))
{
mhpcRevInfo.sensor = (unsigned char)simple_strtoul(console_buffer, NULL, 10);
}
} while ( mhpcRevInfo.sensor >= i );
/* print actual board identification */
printf ("Ident: %s %s Ser %s Rev %c%c\n",
mhpcRevInfo.board,
(mhpcRevInfo.sensor == 0 ? "color" : "b&w"),
(char *) &mhpcRevInfo.serial, mhpcRevInfo.revision[0],
mhpcRevInfo.revision[1]);
printf("Enter serial number: %s ", (char *)&mhpcRevInfo.serial );
if (6 == readline (NULL))
{
for (i=0; i<6; i++)
{
mhpcRevInfo.serial[i] = console_buffer[i];
}
mhpcRevInfo.serial[6] = '\0';
}
printf("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ",
mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5] );
if (12 == readline (NULL))
{
for (i=0; i<12; i+=2)
{
mhpcRevInfo.etheraddr[i>>1] = (char)(16*hex[toupper(console_buffer[i])-'0'] +
hex[toupper(console_buffer[i+1])-'0']);
}
}
/* setup new revision data */
eeprom_write (CFG_I2C_EEPROM_ADDR, 480, (char*)&mhpcRevInfo, 32);
}
/* set environment */
sprintf( nid, "%02x:%02x:%02x:%02x:%02x:%02x",
mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
setenv("ethaddr", nid);
/* print actual board identification */
printf("Ident: %s %s Ser %s Rev %c%c\n",
mhpcRevInfo.board, (mhpcRevInfo.sensor==0?"color":"b&w"),
(char *)&mhpcRevInfo.serial,
mhpcRevInfo.revision[0], mhpcRevInfo.revision[1]);
return (0);
return (0);
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
memctl->memc_mbmr = MBMR_GPL_B4DIS; /* should this be mamr? - NTL */
memctl->memc_mptpr = MPTPR_PTP_DIV64;
memctl->memc_mar = 0x00008800;
memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
memctl->memc_mbmr = MBMR_GPL_B4DIS; /* should this be mamr? - NTL */
memctl->memc_mptpr = MPTPR_PTP_DIV64;
memctl->memc_mar = 0x00008800;
/*
* Map controller SDRAM bank 0
*/
memctl->memc_or1 = CFG_OR1_PRELIM;
memctl->memc_br1 = CFG_BR1_PRELIM;
udelay(200);
/*
* Map controller SDRAM bank 0
*/
memctl->memc_or1 = CFG_OR1_PRELIM;
memctl->memc_br1 = CFG_BR1_PRELIM;
udelay (200);
/*
* Map controller SDRAM bank 1
*/
memctl->memc_or2 = CFG_OR2;
memctl->memc_br2 = CFG_BR2;
/*
* Map controller SDRAM bank 1
*/
memctl->memc_or2 = CFG_OR2;
memctl->memc_br2 = CFG_BR2;
/*
* Perform SDRAM initializsation sequence
*/
memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
udelay(1);
memctl->memc_mcr = 0x80002730; /* SDRAM bank 0 - execute twice */
udelay(1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
/*
* Perform SDRAM initializsation sequence
*/
memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
udelay (1);
memctl->memc_mcr = 0x80002730; /* SDRAM bank 0 - execute twice */
udelay (1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay(10000);
udelay (10000);
/* leave place for framebuffers */
return (SDRAM_MAX_SIZE-SDRAM_RES_SIZE);
/* leave place for framebuffers */
return (SDRAM_MAX_SIZE - SDRAM_RES_SIZE);
}
/* ------------------------------------------------------------------------- */
static void video_circle (char *center, int radius, int color, int pitch)
{
int x,y,d,dE,dSE;
int x, y, d, dE, dSE;
x = 0;
y = radius;
d = 1-radius;
dE = 3;
dSE = -2*radius+5;
x = 0;
y = radius;
d = 1 - radius;
dE = 3;
dSE = -2 * radius + 5;
*(center+x+y*pitch) = color;
*(center+y+x*pitch) = color;
*(center+y-x*pitch) = color;
*(center+x-y*pitch) = color;
*(center-x-y*pitch) = color;
*(center-y-x*pitch) = color;
*(center-y+x*pitch) = color;
*(center-x+y*pitch) = color;
while(y>x)
{
if (d<0)
{
d += dE;
dE += 2;
dSE += 2;
x++;
*(center + x + y * pitch) = color;
*(center + y + x * pitch) = color;
*(center + y - x * pitch) = color;
*(center + x - y * pitch) = color;
*(center - x - y * pitch) = color;
*(center - y - x * pitch) = color;
*(center - y + x * pitch) = color;
*(center - x + y * pitch) = color;
while (y > x) {
if (d < 0) {
d += dE;
dE += 2;
dSE += 2;
x++;
} else {
d += dSE;
dE += 2;
dSE += 4;
x++;
y--;
}
*(center + x + y * pitch) = color;
*(center + y + x * pitch) = color;
*(center + y - x * pitch) = color;
*(center + x - y * pitch) = color;
*(center - x - y * pitch) = color;
*(center - y - x * pitch) = color;
*(center - y + x * pitch) = color;
*(center - x + y * pitch) = color;
}
else
{
d += dSE;
dE += 2;
dSE += 4;
x++;
y--;
}
*(center+x+y*pitch) = color;
*(center+y+x*pitch) = color;
*(center+y-x*pitch) = color;
*(center+x-y*pitch) = color;
*(center-x-y*pitch) = color;
*(center-y-x*pitch) = color;
*(center-y+x*pitch) = color;
*(center-x+y*pitch) = color;
}
}
/* ------------------------------------------------------------------------- */
static void video_test_image(void)
static void video_test_image (void)
{
char *di;
int i, n;
char *di;
int i, n;
/* draw raster */
for (i=0; i<LCD_VIDEO_ROWS; i+=32)
{
memset((char*)(LCD_VIDEO_ADDR+i*LCD_VIDEO_COLS), LCD_VIDEO_FG, LCD_VIDEO_COLS);
for (n=i+1;n<i+32;n++)
memset((char*)(LCD_VIDEO_ADDR+n*LCD_VIDEO_COLS), LCD_VIDEO_BG, LCD_VIDEO_COLS);
}
for (i=0; i<LCD_VIDEO_COLS; i+=32)
{
for (n=0; n<LCD_VIDEO_ROWS; n++)
*(char*)(LCD_VIDEO_ADDR+n*LCD_VIDEO_COLS+i) = LCD_VIDEO_FG;
}
/* draw gray bar */
di = (char *)(LCD_VIDEO_ADDR + (LCD_VIDEO_COLS-256)/64*32 + 97*LCD_VIDEO_COLS);
for (n=0; n<63; n++)
{
for (i=0; i<256; i++)
{
*di++ = (char)i;
*(di+LCD_VIDEO_COLS*64) = (i&1)*255;
/* draw raster */
for (i = 0; i < LCD_VIDEO_ROWS; i += 32) {
memset ((char *) (LCD_VIDEO_ADDR + i * LCD_VIDEO_COLS),
LCD_VIDEO_FG, LCD_VIDEO_COLS);
for (n = i + 1; n < i + 32; n++)
memset ((char *) (LCD_VIDEO_ADDR +
n * LCD_VIDEO_COLS), LCD_VIDEO_BG,
LCD_VIDEO_COLS);
}
di += LCD_VIDEO_COLS-256;
}
video_circle ((char*)LCD_VIDEO_ADDR+LCD_VIDEO_COLS/2+LCD_VIDEO_ROWS/2*LCD_VIDEO_COLS,
LCD_VIDEO_ROWS/2,LCD_VIDEO_FG, LCD_VIDEO_COLS);
for (i = 0; i < LCD_VIDEO_COLS; i += 32) {
for (n = 0; n < LCD_VIDEO_ROWS; n++)
*(char *) (LCD_VIDEO_ADDR + n * LCD_VIDEO_COLS + i) =
LCD_VIDEO_FG;
}
/* draw gray bar */
di = (char *) (LCD_VIDEO_ADDR + (LCD_VIDEO_COLS - 256) / 64 * 32 +
97 * LCD_VIDEO_COLS);
for (n = 0; n < 63; n++) {
for (i = 0; i < 256; i++) {
*di++ = (char) i;
*(di + LCD_VIDEO_COLS * 64) = (i & 1) * 255;
}
di += LCD_VIDEO_COLS - 256;
}
video_circle ((char *) LCD_VIDEO_ADDR + LCD_VIDEO_COLS / 2 +
LCD_VIDEO_ROWS / 2 * LCD_VIDEO_COLS, LCD_VIDEO_ROWS / 2,
LCD_VIDEO_FG, LCD_VIDEO_COLS);
}
/* ------------------------------------------------------------------------- */
static void video_default_lut (unsigned int clut_type)
{
unsigned int i;
unsigned char RGB[] =
{
0x00, 0x00, 0x00, /* black */
0x80, 0x80, 0x80, /* gray */
0xff, 0x00, 0x00, /* red */
0x00, 0xff, 0x00, /* green */
0x00, 0x00, 0xff, /* blue */
0x00, 0xff, 0xff, /* cyan */
0xff, 0x00, 0xff, /* magenta */
0xff, 0xff, 0x00, /* yellow */
0x80, 0x00, 0x00, /* dark red */
0x00, 0x80, 0x00, /* dark green */
0x00, 0x00, 0x80, /* dark blue */
0x00, 0x80, 0x80, /* dark cyan */
0x80, 0x00, 0x80, /* dark magenta */
0x80, 0x80, 0x00, /* dark yellow */
0xc0, 0xc0, 0xc0, /* light gray */
0xff, 0xff, 0xff, /* white */
unsigned int i;
unsigned char RGB[] = {
0x00, 0x00, 0x00, /* black */
0x80, 0x80, 0x80, /* gray */
0xff, 0x00, 0x00, /* red */
0x00, 0xff, 0x00, /* green */
0x00, 0x00, 0xff, /* blue */
0x00, 0xff, 0xff, /* cyan */
0xff, 0x00, 0xff, /* magenta */
0xff, 0xff, 0x00, /* yellow */
0x80, 0x00, 0x00, /* dark red */
0x00, 0x80, 0x00, /* dark green */
0x00, 0x00, 0x80, /* dark blue */
0x00, 0x80, 0x80, /* dark cyan */
0x80, 0x00, 0x80, /* dark magenta */
0x80, 0x80, 0x00, /* dark yellow */
0xc0, 0xc0, 0xc0, /* light gray */
0xff, 0xff, 0xff, /* white */
};
switch (clut_type)
{
case 1:
for (i=0; i<240; i++)
video_set_lut (i, i, i, i);
for (i=0; i<16; i++)
video_set_lut (i+240, RGB[i*3], RGB[i*3+1], RGB[i*3+2]);
break;
default:
for (i=0; i<256; i++)
video_set_lut (i, i, i, i);
}
switch (clut_type) {
case 1:
for (i = 0; i < 240; i++)
video_set_lut (i, i, i, i);
for (i = 0; i < 16; i++)
video_set_lut (i + 240, RGB[i * 3], RGB[i * 3 + 1],
RGB[i * 3 + 2]);
break;
default:
for (i = 0; i < 256; i++)
video_set_lut (i, i, i, i);
}
}
/* ------------------------------------------------------------------------- */
void *video_hw_init (void)
{
unsigned int clut = 0;
unsigned char *penv;
immap_t *immr = (immap_t *) CFG_IMMR;
unsigned int clut = 0;
unsigned char *penv;
immap_t *immr = (immap_t *) CFG_IMMR;
/* enable video only on CLUT value */
if ((penv = getenv ("clut")) != NULL)
clut = (u_int)simple_strtoul (penv, NULL, 10);
else
return NULL;
/* enable video only on CLUT value */
if ((penv = getenv ("clut")) != NULL)
clut = (u_int) simple_strtoul (penv, NULL, 10);
else
return NULL;
/* disable graphic before write LCD regs. */
immr->im_lcd.lcd_lccr = 0x96000866;
/* disable graphic before write LCD regs. */
immr->im_lcd.lcd_lccr = 0x96000866;
/* config LCD regs. */
immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR;
immr->im_lcd.lcd_lchcr = 0x010a0093;
immr->im_lcd.lcd_lcvcr = 0x900f0024;
/* config LCD regs. */
immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR;
immr->im_lcd.lcd_lchcr = 0x010a0093;
immr->im_lcd.lcd_lcvcr = 0x900f0024;
printf ("Video: 640x480 8Bit Index Lut %s\n",
(clut==1?"240/16 (gray/vga)":"256(gray)"));
printf ("Video: 640x480 8Bit Index Lut %s\n",
(clut == 1 ? "240/16 (gray/vga)" : "256(gray)"));
video_default_lut (clut);
video_default_lut (clut);
/* clear framebuffer */
memset ( (char*)(LCD_VIDEO_ADDR), LCD_VIDEO_BG, LCD_VIDEO_ROWS*LCD_VIDEO_COLS );
/* clear framebuffer */
memset ((char *) (LCD_VIDEO_ADDR), LCD_VIDEO_BG,
LCD_VIDEO_ROWS * LCD_VIDEO_COLS);
/* enable graphic */
immr->im_lcd.lcd_lccr = 0x96000867;
/* enable graphic */
immr->im_lcd.lcd_lccr = 0x96000867;
/* fill in Graphic Device */
gdev.frameAdrs = LCD_VIDEO_ADDR;
gdev.winSizeX = LCD_VIDEO_COLS;
gdev.winSizeY = LCD_VIDEO_ROWS;
gdev.gdfBytesPP = 1;
gdev.gdfIndex = GDF__8BIT_INDEX;
/* fill in Graphic Device */
gdev.frameAdrs = LCD_VIDEO_ADDR;
gdev.winSizeX = LCD_VIDEO_COLS;
gdev.winSizeY = LCD_VIDEO_ROWS;
gdev.gdfBytesPP = 1;
gdev.gdfIndex = GDF__8BIT_INDEX;
if (clut > 1)
/* return Graphic Device for console */
return (void *)&gdev;
else
/* just graphic enabled - draw something beautiful */
video_test_image();
if (clut > 1)
/* return Graphic Device for console */
return (void *) &gdev;
else
/* just graphic enabled - draw something beautiful */
video_test_image ();
return NULL; /* this disabels cfb - console */
return NULL; /* this disabels cfb - console */
}
/* ------------------------------------------------------------------------- */
@ -465,13 +469,15 @@ void *video_hw_init (void)
void video_set_lut (unsigned int index,
unsigned char r, unsigned char g, unsigned char b)
{
unsigned int lum;
unsigned short *pLut = (unsigned short *)(CFG_IMMR + 0x0e00);
unsigned int lum;
unsigned short *pLut = (unsigned short *) (CFG_IMMR + 0x0e00);
/* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */
/* y = 0.299*R + 0.587*G + 0.114*B */
lum = (2990*r + 5870*g + 1140*b)/10000;
pLut[index] = ((b & 0xc0)<<4) | ((g & 0xc0)<<2) | (r & 0xc0) | (lum & 0x3f);
/* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */
/* y = 0.299*R + 0.587*G + 0.114*B */
lum = (2990 * r + 5870 * g + 1140 * b) / 10000;
pLut[index] =
((b & 0xc0) << 4) | ((g & 0xc0) << 2) | (r & 0xc0) | (lum &
0x3f);
}
/* ------------------------------------------------------------------------- */

55
board/ep8260/ep8260.c
View File

@ -190,21 +190,22 @@ const iop_conf_t iop_conf_tab[4][32] = {
*/
int board_early_init_f (void)
{
volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
memctl->memc_br4 = CFG_BR4_PRELIM;
memctl->memc_or4 = CFG_OR4_PRELIM;
regs->bcsr1 = 0x62; /* to enable terminal on SMC1 */
regs->bcsr2 = 0x30; /* enable NVRAM and writing FLASH */
return 0;
volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
memctl->memc_br4 = CFG_BR4_PRELIM;
memctl->memc_or4 = CFG_OR4_PRELIM;
regs->bcsr1 = 0x62; /* to enable terminal on SMC1 */
regs->bcsr2 = 0x30; /* enable NVRAM and writing FLASH */
return 0;
}
void
reset_phy(void)
void reset_phy (void)
{
volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
regs->bcsr4 = 0xC0;
volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
regs->bcsr4 = 0xC0;
}
/*
@ -213,15 +214,21 @@ reset_phy(void)
* Thats why its a static interpretation ...
*/
int
checkboard(void)
int checkboard (void)
{
volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
uint major=0, minor=0;
volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
uint major = 0, minor = 0;
switch (regs->bcsr0) {
case 0x02: major = 1; break;
case 0x03: major = 1; minor = 1; break;
default: break;
case 0x02:
major = 1;
break;
case 0x03:
major = 1;
minor = 1;
break;
default:
break;
}
printf ("Board: Embedded Planet EP8260, Revision %d.%d\n",
major, minor);
@ -232,13 +239,13 @@ checkboard(void)
/* ------------------------------------------------------------------------- */
long int
initdram(int board_type)
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar c = 0;
volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE) + 0x110;
volatile uchar *ramaddr = (uchar *) (CFG_SDRAM_BASE) + 0x110;
/*
ulong psdmr = CFG_PSDMR;
#ifdef CFG_LSDRAM
@ -288,7 +295,7 @@ initdram(int board_type)
#ifndef CFG_RAMBOOT
#ifdef CFG_LSDRAM
size += CFG_SDRAM1_SIZE;
ramaddr = (uchar *)(CFG_SDRAM1_BASE) + 0x8c;
ramaddr = (uchar *) (CFG_SDRAM1_BASE) + 0x8c;
memctl->memc_lsrt = CFG_LSRT;
memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_PREA;

176
board/evb64260/ecctest.c
View File

@ -1,91 +1,111 @@
indent: Standard input:27: Warning:old style assignment ambiguity in "=*". Assuming "= *"
#ifdef ECC_TEST
static inline void ecc_off(void)
static inline void ecc_off (void)
{
*(volatile int *)(INTERNAL_REG_BASE_ADDR+0x4b4) &= ~0x00200000;
*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000;
}
static inline void ecc_on(void)
static inline void ecc_on (void)
{
*(volatile int *)(INTERNAL_REG_BASE_ADDR+0x4b4) |= 0x00200000;
*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000;
}
static int putshex(const char *buf, int len)
static int putshex (const char *buf, int len)
{
int i;
for (i=0;i<len;i++) {
printf("%02x", buf[i]);
}
return 0;
}
int i;
static int char_memcpy(void *d, const void *s, int len)
{
int i;
char *cd=d;
const char *cs=s;
for(i=0;i<len;i++) {
*(cd++)=*(cs++);
}
return 0;
}
static int memory_test(char *buf)
{
const char src[][16]={
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01},
{0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02},
{0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04},
{0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08},
{0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10},
{0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20},
{0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
{0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80},
{0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55},
{0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa},
{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}
};
const int foo[] = {0};
int i,j,a;
printf("\ntest @ %d %p\n", foo[0], buf);
for(i=0;i<12;i++) {
for(a=0;a<8;a++) {
const char *s=src[i]+a;
int align=(unsigned)(s)&0x7;
/* ecc_off(); */
memcpy(buf,s,8);
/* ecc_on(); */
putshex(s,8);
if(memcmp(buf,s,8)) {
putc('\n');
putshex(buf,8);
printf(" [FAIL] (%p) align=%d\n", s, align);
for(j=0;j<8;j++) {
s[j]==buf[j]?puts(" "):printf("%02x", (s[j])^(buf[j]));
}
putc('\n');
} else {
printf(" [PASS] (%p) align=%d\n", s, align);
}
/* ecc_off(); */
char_memcpy(buf,s,8);
/* ecc_on(); */
putshex(s,8);
if(memcmp(buf,s,8)) {
putc('\n');
putshex(buf,8);
printf(" [FAIL] (%p) align=%d\n", s, align);
for(j=0;j<8;j++) {
s[j]==buf[j]?puts(" "):printf("%02x", (s[j])^(buf[j]));
}
putc('\n');
} else {
printf(" [PASS] (%p) align=%d\n", s, align);
}
for (i = 0; i < len; i++) {
printf ("%02x", buf[i]);
}
}
return 0;
}
return 0;
static int char_memcpy (void *d, const void *s, int len)
{
int i;
char *cd = d;
const char *cs = s;
for (i = 0; i < len; i++) {
*(cd++) = *(cs++);
}
return 0;
}
static int memory_test (char *buf)
{
const char src[][16] = {
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01},
{0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
0x02, 0x02, 0x02, 0x02, 0x02, 0x02},
{0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
0x04, 0x04, 0x04, 0x04, 0x04, 0x04},
{0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
0x08, 0x08, 0x08, 0x08, 0x08, 0x08},
{0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
0x10, 0x10, 0x10, 0x10, 0x10, 0x10},
{0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20},
{0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
0x40, 0x40, 0x40, 0x40, 0x40, 0x40},
{0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
0x80, 0x80, 0x80, 0x80, 0x80, 0x80},
{0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
0x55, 0x55, 0x55, 0x55, 0x55, 0x55},
{0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa},
{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
};
const int foo[] = { 0 };
int i, j, a;
printf ("\ntest @ %d %p\n", foo[0], buf);
for (i = 0; i < 12; i++) {
for (a = 0; a < 8; a++) {
const char *s = src[i] + a;
int align = (unsigned) (s) & 0x7;
/* ecc_off(); */
memcpy (buf, s, 8);
/* ecc_on(); */
putshex (s, 8);
if (memcmp (buf, s, 8)) {
putc ('\n');
putshex (buf, 8);
printf (" [FAIL] (%p) align=%d\n", s, align);
for (j = 0; j < 8; j++) {
s[j] == buf[j] ? puts (" ") :
printf ("%02x",
(s[j]) ^ (buf[j]));
}
putc ('\n');
} else {
printf (" [PASS] (%p) align=%d\n", s, align);
}
/* ecc_off(); */
char_memcpy (buf, s, 8);
/* ecc_on(); */
putshex (s, 8);
if (memcmp (buf, s, 8)) {
putc ('\n');
putshex (buf, 8);
printf (" [FAIL] (%p) align=%d\n", s, align);
for (j = 0; j < 8; j++) {
s[j] == buf[j] ? puts (" ") :
printf ("%02x",
(s[j]) ^ (buf[j]));
}
putc ('\n');
} else {
printf (" [PASS] (%p) align=%d\n", s, align);
}
}
}
return 0;
}
#endif

249
board/evb64260/eth_addrtbl.c
View File

@ -13,66 +13,68 @@
#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
static u32 addressTableHashMode[ GAL_ETH_DEVS ] = { 0, };
static u32 addressTableHashSize[ GAL_ETH_DEVS ] = { 0, };
static addrTblEntry *addressTableBase[ GAL_ETH_DEVS ] = { 0, };
static void *realAddrTableBase[ GAL_ETH_DEVS ] = { 0, };
static u32 addressTableHashMode[GAL_ETH_DEVS] = { 0, };
static u32 addressTableHashSize[GAL_ETH_DEVS] = { 0, };
static addrTblEntry *addressTableBase[GAL_ETH_DEVS] = { 0, };
static void *realAddrTableBase[GAL_ETH_DEVS] = { 0, };
static const u32 hashLength[ 2 ] = {
(0x8000), /* 8K * 4 entries */
(0x8000/16), /* 512 * 4 entries */
static const u32 hashLength[2] = {
(0x8000), /* 8K * 4 entries */
(0x8000 / 16), /* 512 * 4 entries */
};
/* Initialize the address table for a port, if needed */
unsigned int initAddressTable( u32 port, u32 hashMode, u32 hashSizeSelector)
unsigned int initAddressTable (u32 port, u32 hashMode, u32 hashSizeSelector)
{
unsigned int tableBase;
unsigned int tableBase;
if( port < 0 || port >= GAL_ETH_DEVS ) {
printf("%s: Invalid port number %d\n", __FUNCTION__, port );
if (port < 0 || port >= GAL_ETH_DEVS) {
printf ("%s: Invalid port number %d\n", __FUNCTION__, port);
return 0;
}
if (hashMode > 1) {
printf("%s: Invalid Hash Mode %d\n", __FUNCTION__, port );
printf ("%s: Invalid Hash Mode %d\n", __FUNCTION__, port);
return 0;
}
if ( realAddrTableBase[port] &&
( addressTableHashSize[port] != hashSizeSelector )) {
if (realAddrTableBase[port] &&
(addressTableHashSize[port] != hashSizeSelector)) {
/* we have been here before,
* but now we want a different sized table
*/
free( realAddrTableBase[port] );
free (realAddrTableBase[port]);
realAddrTableBase[port] = 0;
addressTableBase[port] = 0;
}
tableBase = (unsigned int)addressTableBase[port];
tableBase = (unsigned int) addressTableBase[port];
/* we get called for every probe, so only do this once */
if ( !tableBase ) {
int bytes = hashLength[hashSizeSelector] * sizeof(addrTblEntry);
if (!tableBase) {
int bytes =
hashLength[hashSizeSelector] * sizeof (addrTblEntry);
tableBase = (unsigned int)realAddrTableBase[port] = malloc(bytes+64);
tableBase = (unsigned int) realAddrTableBase[port] =
malloc (bytes + 64);
if(!tableBase)
{
printf("%s: alloc memory failed \n", __FUNCTION__);
if (!tableBase) {
printf ("%s: alloc memory failed \n", __FUNCTION__);
return 0;
}
/* align to octal byte */
if(tableBase&63) tableBase=(tableBase+63) & ~63;
/* align to octal byte */
if (tableBase & 63)
tableBase = (tableBase + 63) & ~63;
addressTableHashMode[port] = hashMode;
addressTableHashSize[port] = hashSizeSelector;
addressTableBase[port] = (addrTblEntry *)tableBase;
addressTableHashMode[port] = hashMode;
addressTableHashSize[port] = hashSizeSelector;
addressTableBase[port] = (addrTblEntry *) tableBase;
memset((void *)tableBase,0,bytes);
memset ((void *) tableBase, 0, bytes);
}
return tableBase;
return tableBase;
}
/*
@ -87,61 +89,61 @@ unsigned int initAddressTable( u32 port, u32 hashMode, u32 hashSizeSelector)
* Outputs
* return the calculated entry.
*/
u32
hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
u32 hashTableFunction (u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
{
u32 hashResult;
u32 addrH;
u32 addrL;
u32 addr0;
u32 addr1;
u32 addr2;
u32 addr3;
u32 addrHSwapped;
u32 addrLSwapped;
u32 hashResult;
u32 addrH;
u32 addrL;
u32 addr0;
u32 addr1;
u32 addr2;
u32 addr3;
u32 addrHSwapped;
u32 addrLSwapped;
addrH = NIBBLE_SWAPPING_16_BIT( macH );
addrL = NIBBLE_SWAPPING_32_BIT( macL );
addrH = NIBBLE_SWAPPING_16_BIT (macH);
addrL = NIBBLE_SWAPPING_32_BIT (macL);
addrHSwapped = FLIP_4_BITS( addrH & 0xf )
+ ((FLIP_4_BITS( (addrH >> 4) & 0xf)) << 4)
+ ((FLIP_4_BITS( (addrH >> 8) & 0xf)) << 8)
+ ((FLIP_4_BITS( (addrH >> 12) & 0xf)) << 12);
addrHSwapped = FLIP_4_BITS (addrH & 0xf)
+ ((FLIP_4_BITS ((addrH >> 4) & 0xf)) << 4)
+ ((FLIP_4_BITS ((addrH >> 8) & 0xf)) << 8)
+ ((FLIP_4_BITS ((addrH >> 12) & 0xf)) << 12);
addrLSwapped = FLIP_4_BITS( addrL & 0xf )
+ ((FLIP_4_BITS( (addrL >> 4) & 0xf)) << 4)
+ ((FLIP_4_BITS( (addrL >> 8) & 0xf)) << 8)
+ ((FLIP_4_BITS( (addrL >> 12) & 0xf)) << 12)
+ ((FLIP_4_BITS( (addrL >> 16) & 0xf)) << 16)
+ ((FLIP_4_BITS( (addrL >> 20) & 0xf)) << 20)
+ ((FLIP_4_BITS( (addrL >> 24) & 0xf)) << 24)
+ ((FLIP_4_BITS( (addrL >> 28) & 0xf)) << 28);
addrLSwapped = FLIP_4_BITS (addrL & 0xf)
+ ((FLIP_4_BITS ((addrL >> 4) & 0xf)) << 4)
+ ((FLIP_4_BITS ((addrL >> 8) & 0xf)) << 8)
+ ((FLIP_4_BITS ((addrL >> 12) & 0xf)) << 12)
+ ((FLIP_4_BITS ((addrL >> 16) & 0xf)) << 16)
+ ((FLIP_4_BITS ((addrL >> 20) & 0xf)) << 20)
+ ((FLIP_4_BITS ((addrL >> 24) & 0xf)) << 24)
+ ((FLIP_4_BITS ((addrL >> 28) & 0xf)) << 28);
addrH = addrHSwapped;
addrL = addrLSwapped;
addrH = addrHSwapped;
addrL = addrLSwapped;
if( hash_mode == 0 ) {
addr0 = (addrL >> 2) & 0x03f;
addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2;
addr2 = (addrL >> 15) & 0x1ff;
addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8);
} else {
addr0 = FLIP_6_BITS( addrL & 0x03f );
addr1 = FLIP_9_BITS( ((addrL >> 6) & 0x1ff));
addr2 = FLIP_9_BITS( (addrL >> 15) & 0x1ff);
addr3 = FLIP_9_BITS( (((addrL >> 24) & 0x0ff) | ((addrH & 0x1) << 8)));
}
if (hash_mode == 0) {
addr0 = (addrL >> 2) & 0x03f;
addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2;
addr2 = (addrL >> 15) & 0x1ff;
addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8);
} else {
addr0 = FLIP_6_BITS (addrL & 0x03f);
addr1 = FLIP_9_BITS (((addrL >> 6) & 0x1ff));
addr2 = FLIP_9_BITS ((addrL >> 15) & 0x1ff);
addr3 = FLIP_9_BITS ((((addrL >> 24) & 0x0ff) |
((addrH & 0x1) << 8)));
}
hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
if( HashSize == _8K_TABLE ) {
hashResult = hashResult & 0xffff;
} else {
hashResult = hashResult & 0x07ff;
}
if (HashSize == _8K_TABLE) {
hashResult = hashResult & 0xffff;
} else {
hashResult = hashResult & 0x07ff;
}
return( hashResult );
return (hashResult);
}
@ -160,66 +162,59 @@ hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
* TRUE if success.
* FALSE if table full
*/
int
addAddressTableEntry(
u32 port,
u32 macH,
u32 macL,
u32 rd,
u32 skip )
int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip)
{
addrTblEntry *entry;
u32 newHi;
u32 newLo;
u32 i;
addrTblEntry *entry;
u32 newHi;
u32 newLo;
u32 i;
newLo = (((macH >> 4) & 0xf) << 15)
| (((macH >> 0) & 0xf) << 11)
| (((macH >> 12) & 0xf) << 7)
| (((macH >> 8) & 0xf) << 3)
| (((macL >> 20) & 0x1) << 31)
| (((macL >> 16) & 0xf) << 27)
| (((macL >> 28) & 0xf) << 23)
| (((macL >> 24) & 0xf) << 19)
| (skip << SKIP_BIT) | (rd << 2) | VALID;
newLo = (((macH >> 4) & 0xf) << 15)
| (((macH >> 0) & 0xf) << 11)
| (((macH >> 12) & 0xf) << 7)
| (((macH >> 8) & 0xf) << 3)
| (((macL >> 20) & 0x1) << 31)
| (((macL >> 16) & 0xf) << 27)
| (((macL >> 28) & 0xf) << 23)
| (((macL >> 24) & 0xf) << 19)
| (skip << SKIP_BIT) | (rd << 2) | VALID;
newHi = (((macL >> 4) & 0xf) << 15)
| (((macL >> 0) & 0xf) << 11)
| (((macL >> 12) & 0xf) << 7)
| (((macL >> 8) & 0xf) << 3)
| (((macL >> 21) & 0x7) << 0);
newHi = (((macL >> 4) & 0xf) << 15)
| (((macL >> 0) & 0xf) << 11)
| (((macL >> 12) & 0xf) << 7)
| (((macL >> 8) & 0xf) << 3)
| (((macL >> 21) & 0x7) << 0);
/*
* Pick the appropriate table, start scanning for free/reusable
* entries at the index obtained by hashing the specified MAC address
*/
entry = addressTableBase[port];
entry += hashTableFunction( macH, macL, addressTableHashSize[port],
addressTableHashMode[port] );
for( i = 0; i < HOP_NUMBER; i++, entry++ ) {
if( !(entry->lo & VALID) /*|| (entry->lo & SKIP)*/ ) {
break;
} else { /* if same address put in same position */
if( ((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8))
&& (entry->hi == newHi) )
{
break;
}
/*
* Pick the appropriate table, start scanning for free/reusable
* entries at the index obtained by hashing the specified MAC address
*/
entry = addressTableBase[port];
entry += hashTableFunction (macH, macL, addressTableHashSize[port],
addressTableHashMode[port]);
for (i = 0; i < HOP_NUMBER; i++, entry++) {
if (!(entry->lo & VALID) /*|| (entry->lo & SKIP) */ ) {
break;
} else { /* if same address put in same position */
if (((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8))
&& (entry->hi == newHi)) {
break;
}
}
}
}
if( i == HOP_NUMBER ) {
PRINTF( "addGT64260addressTableEntry: table section is full\n" );
return( FALSE );
}
if (i == HOP_NUMBER) {
PRINTF ("addGT64260addressTableEntry: table section is full\n");
return (FALSE);
}
/*
* Update the selected entry
*/
entry->hi = newHi;
entry->lo = newLo;
DCACHE_FLUSH_N_SYNC( (u32)entry, MAC_ENTRY_SIZE );
return( TRUE );
/*
* Update the selected entry
*/
entry->hi = newHi;
entry->lo = newLo;
DCACHE_FLUSH_N_SYNC ((u32) entry, MAC_ENTRY_SIZE);
return (TRUE);
}
#endif /* CONFIG_GT_USE_MAC_HASH_TABLE */

822
board/evb64260/pci.c
View File

File diff suppressed because it is too large Load Diff

410
board/evb64260/sdram_init.c
View File

@ -54,65 +54,64 @@ typedef struct sdram_info {
uchar tras_clocks;
uchar burst_len;
uchar banks, slot;
int size; /* detected size, not from I2C but from dram_size() */
int size; /* detected size, not from I2C but from dram_size() */
} sdram_info_t;
#ifdef DEBUG
void dump_dimm_info(struct sdram_info *d)
void dump_dimm_info (struct sdram_info *d)
{
static const char *ecc_legend[]={""," Parity"," ECC"};
printf("dimm%s %sDRAM: %dMibytes:\n",
ecc_legend[d->ecc],
d->registered?"R":"",
(d->size>>20));
printf(" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
d->banks, d->slot);
static const char *ecc_legend[] = { "", " Parity", " ECC" };
printf ("dimm%s %sDRAM: %dMibytes:\n",
ecc_legend[d->ecc],
d->registered ? "R" : "", (d->size >> 20));
printf (" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
d->banks, d->slot);
}
#endif
static int
memory_map_bank(unsigned int bankNo,
unsigned int bankBase,
unsigned int bankLength)
memory_map_bank (unsigned int bankNo,
unsigned int bankBase, unsigned int bankLength)
{
#ifdef DEBUG
if (bankLength > 0) {
printf("mapping bank %d at %08x - %08x\n",
bankNo, bankBase, bankBase + bankLength - 1);
printf ("mapping bank %d at %08x - %08x\n",
bankNo, bankBase, bankBase + bankLength - 1);
} else {
printf("unmapping bank %d\n", bankNo);
printf ("unmapping bank %d\n", bankNo);
}
#endif
memoryMapBank(bankNo, bankBase, bankLength);
memoryMapBank (bankNo, bankBase, bankLength);
return 0;
}
#ifdef MAP_PCI
static int
memory_map_bank_pci(unsigned int bankNo,
unsigned int bankBase,
unsigned int bankLength)
memory_map_bank_pci (unsigned int bankNo,
unsigned int bankBase, unsigned int bankLength)
{
PCI_HOST host;
for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
const int features=
for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
const int features =
PREFETCH_ENABLE |
DELAYED_READ_ENABLE |
AGGRESSIVE_PREFETCH |
READ_LINE_AGGRESSIVE_PREFETCH |
READ_MULTI_AGGRESSIVE_PREFETCH |
MAX_BURST_4 |
PCI_NO_SWAP;
MAX_BURST_4 | PCI_NO_SWAP;
pciMapMemoryBank(host, bankNo, bankBase, bankLength);
pciMapMemoryBank (host, bankNo, bankBase, bankLength);
pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
bankLength);
pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
bankLength);
pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
pciSetRegionFeatures (host, bankNo, features, bankBase,
bankLength);
}
return 0;
}
@ -128,8 +127,7 @@ memory_map_bank_pci(unsigned int bankNo,
* translate ns.ns/10 coding of SPD timing values
* into 10 ps unit values
*/
static inline unsigned short
NS10to10PS(unsigned char spd_byte)
static inline unsigned short NS10to10PS (unsigned char spd_byte)
{
unsigned short ns, ns10;
@ -138,37 +136,35 @@ NS10to10PS(unsigned char spd_byte)
/* isolate lower nibble */
ns10 = (spd_byte & 0x0F);
return(ns*100 + ns10*10);
return (ns * 100 + ns10 * 10);
}
/*
* translate ns coding of SPD timing values
* into 10 ps unit values
*/
static inline unsigned short
NSto10PS(unsigned char spd_byte)
static inline unsigned short NSto10PS (unsigned char spd_byte)
{
return(spd_byte*100);
return (spd_byte * 100);
}
#ifdef CONFIG_ZUMA_V2
static int
check_dimm(uchar slot, sdram_info_t *info)
static int check_dimm (uchar slot, sdram_info_t * info)
{
/* assume 2 dimms, 2 banks each 256M - we dont have an
* dimm i2c so rely on the detection routines later */
memset(info, 0, sizeof(*info));
memset (info, 0, sizeof (*info));
info->slot = slot;
info->banks = 2; /* Detect later */
info->registered = 0;
info->registered = 0;
info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit
but doesn't matter, both do same
thing in setup_sdram() */
info->tpar = 3;
info->tras_clocks = 5;
info->burst_len = 4;
info->tpar = 3;
info->tras_clocks = 5;
info->burst_len = 4;
#ifdef CONFIG_ECC
info->ecc = 0; /* Detect later */
#endif /* CONFIG_ECC */
@ -177,10 +173,9 @@ check_dimm(uchar slot, sdram_info_t *info)
#elif defined(CONFIG_P3G4)
static int
check_dimm(uchar slot, sdram_info_t *info)
static int check_dimm (uchar slot, sdram_info_t * info)
{
memset(info, 0, sizeof(*info));
memset (info, 0, sizeof (*info));
if (slot)
return 0;
@ -198,12 +193,11 @@ check_dimm(uchar slot, sdram_info_t *info)
return 0;
}
#else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4*/
#else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */
/* This code reads the SPD chip on the sdram and populates
* the array which is passed in with the relevant information */
static int
check_dimm(uchar slot, sdram_info_t *info)
static int check_dimm (uchar slot, sdram_info_t * info)
{
DECLARE_GLOBAL_DATA_PTR;
uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
@ -215,32 +209,32 @@ check_dimm(uchar slot, sdram_info_t *info)
get_clocks ();
tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */
tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */
#ifdef CONFIG_EVB64260_750CX
if (0 != slot) {
printf("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
printf(" called with slot=%d insetad!\n", slot);
printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
printf (" called with slot=%d insetad!\n", slot);
return 0;
}
#endif
DP(puts("before i2c read\n"));
DP (puts ("before i2c read\n"));
ret = i2c_read(addr, 0, 128, data, 0);
ret = i2c_read (addr, 0, 128, data, 0);
DP(puts("after i2c read\n"));
DP (puts ("after i2c read\n"));
/* zero all the values */
memset(info, 0, sizeof(*info));
memset (info, 0, sizeof (*info));
if (ret) {
DP(printf("No DIMM in slot %d [err = %x]\n", slot, ret));
DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
return 0;
}
/* first, do some sanity checks */
if (data[2] != 0x4) {
printf("Not SDRAM in slot %d\n", slot);
printf ("Not SDRAM in slot %d\n", slot);
return 0;
}
@ -251,7 +245,8 @@ check_dimm(uchar slot, sdram_info_t *info)
sdram_banks = data[17];
width = data[13] & 0x7f;
DP(printf("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
DP (printf
("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
/* check if the memory is registered */
if (data[21] & (BIT1 | BIT4))
@ -266,31 +261,31 @@ check_dimm(uchar slot, sdram_info_t *info)
supp_cal = (data[18] & 0x6) >> 1;
/* compute the relevant clock values */
trp_clocks = (NSto10PS(data[27])+(tmemclk-1)) / tmemclk;
trcd_clocks = (NSto10PS(data[29])+(tmemclk-1)) / tmemclk;
info->tras_clocks = (NSto10PS(data[30])+(tmemclk-1)) / tmemclk;
trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk;
trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk;
info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk;
DP(printf("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
trp_clocks, trcd_clocks, info->tras_clocks));
DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
trp_clocks, trcd_clocks, info->tras_clocks));
/* try a CAS latency of 3 first... */
cal_val = 0;
if (supp_cal & 3) {
if (NS10to10PS(data[9]) <= tmemclk)
if (NS10to10PS (data[9]) <= tmemclk)
cal_val = 3;
}
/* then 2... */
if (supp_cal & 2) {
if (NS10to10PS(data[23]) <= tmemclk)
if (NS10to10PS (data[23]) <= tmemclk)
cal_val = 2;
}
DP(printf("cal_val = %d\n", cal_val));
DP (printf ("cal_val = %d\n", cal_val));
/* bummer, did't work... */
if (cal_val == 0) {
DP(printf("Couldn't find a good CAS latency\n"));
DP (printf ("Couldn't find a good CAS latency\n"));
return 0;
}
@ -302,18 +297,19 @@ check_dimm(uchar slot, sdram_info_t *info)
if (trcd_clocks > info->tpar)
info->tpar = trcd_clocks;
DP(printf("tpar set to: %d\n", info->tpar));
DP (printf ("tpar set to: %d\n", info->tpar));
#ifdef CFG_BROKEN_CL2
if (info->tpar == 2){
if (info->tpar == 2) {
info->tpar = 3;
DP(printf("tpar fixed-up to: %d\n", info->tpar));
DP (printf ("tpar fixed-up to: %d\n", info->tpar));
}
#endif
/* compute the module DRB size */
info->drb_size = (((1 << (rows + cols)) * sdram_banks) * width) / _16M;
info->drb_size =
(((1 << (rows + cols)) * sdram_banks) * width) / _16M;
DP(printf("drb_size set to: %d\n", info->drb_size));
DP (printf ("drb_size set to: %d\n", info->drb_size));
/* find the burst len */
info->burst_len = data[16] & 0xf;
@ -330,40 +326,52 @@ check_dimm(uchar slot, sdram_info_t *info)
}
#endif /* ! CONFIG_ZUMA_V2 */
static int
setup_sdram_common(sdram_info_t info[2])
static int setup_sdram_common (sdram_info_t info[2])
{
ulong tmp;
int tpar=2, tras_clocks=5, registered=1, ecc=2;
int tpar = 2, tras_clocks = 5, registered = 1, ecc = 2;
if(!info[0].banks && !info[1].banks) return 0;
if (!info[0].banks && !info[1].banks)
return 0;
if(info[0].banks) {
if(info[0].tpar>tpar) tpar=info[0].tpar;
if(info[0].tras_clocks>tras_clocks) tras_clocks=info[0].tras_clocks;
if(!info[0].registered) registered=0;
if(info[0].ecc!=2) ecc=0;
if (info[0].banks) {
if (info[0].tpar > tpar)
tpar = info[0].tpar;
if (info[0].tras_clocks > tras_clocks)
tras_clocks = info[0].tras_clocks;
if (!info[0].registered)
registered = 0;
if (info[0].ecc != 2indent: Standard input:491: Warning:old style assignment ambiguity in "=*". Assuming "= *"
indent: Standard input:492: Warning:old style assignment ambiguity in "=*". Assuming "= *"
)
ecc = 0;
}
if(info[1].banks) {
if(info[1].tpar>tpar) tpar=info[1].tpar;
if(info[1].tras_clocks>tras_clocks) tras_clocks=info[1].tras_clocks;
if(!info[1].registered) registered=0;
if(info[1].ecc!=2) ecc=0;
if (info[1].banks) {
if (info[1].tpar > tpar)
tpar = info[1].tpar;
if (info[1].tras_clocks > tras_clocks)
tras_clocks = info[1].tras_clocks;
if (!info[1].registered)
registered = 0;
if (info[1].ecc != 2)
ecc = 0;
}
/* SDRAM configuration */
tmp = GTREGREAD(SDRAM_CONFIGURATION);
tmp = GTREGREAD (SDRAM_CONFIGURATION);
/* Turn on physical interleave if both DIMMs
* have even numbers of banks. */
if( (info[0].banks == 0 || info[0].banks == 2) &&
(info[1].banks == 0 || info[1].banks == 2) ) {
/* physical interleave on */
tmp &= ~(1 << 15);
if ((info[0].banks == 0 || info[0].banks == 2) &&
(info[1].banks == 0 || info[1].banks == 2)) {
/* physical interleave on */
tmp &= ~(1 << 15);
} else {
/* physical interleave off */
tmp |= (1 << 15);
/* physical interleave off */
tmp |= (1 << 15);
}
tmp |= (registered << 17);
@ -372,52 +380,51 @@ setup_sdram_common(sdram_info_t info[2])
* See Res #12 */
tmp |= (1 << 26);
GT_REG_WRITE(SDRAM_CONFIGURATION, tmp);
DP(printf("SDRAM config: %08x\n",
GTREGREAD(SDRAM_CONFIGURATION)));
GT_REG_WRITE (SDRAM_CONFIGURATION, tmp);
DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION)));
/* SDRAM timing */
tmp = (((tpar == 3) ? 2 : 1) |
(((tpar == 3) ? 2 : 1) << 2) |
(((tpar == 3) ? 2 : 1) << 4) |
(tras_clocks << 8));
(((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8));
#ifdef CONFIG_ECC
/* Setup ECC */
if (ecc == 2) tmp |= 1<<13;
if (ecc == 2)
tmp |= 1 << 13;
#endif /* CONFIG_ECC */
GT_REG_WRITE(SDRAM_TIMING, tmp);
DP(printf("SDRAM timing: %08x (%d,%d,%d,%d)\n",
GTREGREAD(SDRAM_TIMING), tpar,tpar,tpar,tras_clocks));
GT_REG_WRITE (SDRAM_TIMING, tmp);
DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n",
GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks));
/* SDRAM address decode register */
/* program this with the default value */
GT_REG_WRITE(SDRAM_ADDRESS_DECODE, 0x2);
DP(printf("SDRAM decode: %08x\n",
GTREGREAD(SDRAM_ADDRESS_DECODE)));
GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2);
DP (printf ("SDRAM decode: %08x\n",
GTREGREAD (SDRAM_ADDRESS_DECODE)));
return 0;
}
/* sets up the GT properly with information passed in */
static int
setup_sdram(sdram_info_t *info)
static int setup_sdram (sdram_info_t * info)
{
ulong tmp, check;
ulong *addr = 0;
int i;
/* sanity checking */
if (! info->banks) return 0;
if (!info->banks)
return 0;
/* ---------------------------- */
/* Program the GT with the discovered data */
/* bank parameters */
tmp = (0xf<<16); /* leave all virt bank pages open */
tmp = (0xf << 16); /* leave all virt bank pages open */
DP(printf("drb_size: %d\n", info->drb_size));
DP (printf ("drb_size: %d\n", info->drb_size));
switch (info->drb_size) {
case 1:
tmp |= (1 << 14);
@ -431,41 +438,42 @@ setup_sdram(sdram_info_t *info)
tmp |= (3 << 14);
break;
default:
printf("Error in dram size calculation\n");
printf ("Error in dram size calculation\n");
return 1;
}
/* SDRAM bank parameters */
/* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
GT_REG_WRITE(SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
GT_REG_WRITE(SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
DP(printf("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot, info->slot*2, (info->slot*2)+1, tmp));
GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
DP (printf
("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot,
info->slot * 2, (info->slot * 2) + 1, tmp));
/* set the SDRAM configuration for each bank */
for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) {
DP(printf("*** Running a MRS cycle for bank %d ***\n", i));
DP (printf ("*** Running a MRS cycle for bank %d ***\n", i));
/* map the bank */
memory_map_bank(i, 0, GB/4);
memory_map_bank (i, 0, GB / 4);
/* set SDRAM mode */
GT_REG_WRITE(SDRAM_OPERATION_MODE, 0x3);
check = GTREGREAD(SDRAM_OPERATION_MODE);
GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3);
check = GTREGREAD (SDRAM_OPERATION_MODE);
/* dummy write */
*addr = 0;
/* wait for the command to complete */
while ((GTREGREAD(SDRAM_OPERATION_MODE) & (1 << 31)) == 0)
;
while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0);
/* switch back to normal operation mode */
GT_REG_WRITE(SDRAM_OPERATION_MODE, 0);
check = GTREGREAD(SDRAM_OPERATION_MODE);
GT_REG_WRITE (SDRAM_OPERATION_MODE, 0);
check = GTREGREAD (SDRAM_OPERATION_MODE);
/* unmap the bank */
memory_map_bank(i, 0, 0);
DP(printf("*** MRS cycle for bank %d done ***\n", i));
memory_map_bank (i, 0, 0);
DP (printf ("*** MRS cycle for bank %d done ***\n", i));
}
return 0;
@ -478,50 +486,50 @@ setup_sdram(sdram_info_t *info)
* - short between address lines
* - short between data lines
*/
static long int
dram_size(long int *base, long int maxsize)
static long int dram_size (long int *base, long int maxsize)
{
volatile long int *addr, *b=base;
long int cnt, val, save1, save2;
volatile long int *addr, *b = base;
long int cnt, val, save1, save2;
#define STARTVAL (1<<20) /* start test at 1M */
for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
save1=*addr; /* save contents of addr */
save2=*b; /* save contents of base */
save1 = *addr; /* save contents of addr */
save2 = *b; /* save contents of base */
*addr=cnt; /* write cnt to addr */
*b=0; /* put null at base */
*addr = cnt; /* write cnt to addr */
*b = 0; /* put null at base */
/* check at base address */
if ((*b) != 0) {
*addr=save1; /* restore *addr */
*b=save2; /* restore *b */
return (0);
}
val = *addr; /* read *addr */
/* check at base address */
if ((*b) != 0) {
*addr = save1; /* restore *addr */
*b = save2; /* restore *b */
return (0);
}
val = *addr; /* read *addr */
*addr=save1;
*b=save2;
*addr = save1;
*b = save2;
if (val != cnt) {
/* fix boundary condition.. STARTVAL means zero */
if(cnt==STARTVAL/sizeof(long)) cnt=0;
return (cnt * sizeof(long));
}
}
return maxsize;
if (val != cnt) {
/* fix boundary condition.. STARTVAL means zero */
if (cnt == STARTVAL / sizeof (long))
cnt = 0;
return (cnt * sizeof (long));
}
}
return maxsize;
}
/* ------------------------------------------------------------------------- */
/* U-Boot interface function to SDRAM init - this is where all the
* controlling logic happens */
long int
initdram(int board_type)
long int initdram (int board_type)
{
ulong checkbank[4] = { [0 ... 3] = 0 };
ulong checkbank[4] = {[0 ... 3] = 0 };
int bank_no;
ulong total;
int nhr;
@ -531,92 +539,97 @@ initdram(int board_type)
/* first, use the SPD to get info about the SDRAM */
/* check the NHR bit and skip mem init if it's already done */
nhr = get_hid0() & (1 << 16);
nhr = get_hid0 () & (1 << 16);
if (nhr) {
printf("Skipping SDRAM setup due to NHR bit being set\n");
printf ("Skipping SDRAM setup due to NHR bit being set\n");
} else {
/* DIMM0 */
check_dimm(0, &dimm_info[0]);
check_dimm (0, &dimm_info[0]);
/* DIMM1 */
#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */
check_dimm(1, &dimm_info[1]);
#else /* CONFIG_EVB64260_750CX */
memset(&dimm_info[1], 0, sizeof(sdram_info_t));
#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */
check_dimm (1, &dimm_info[1]);
#else /* CONFIG_EVB64260_750CX */
memset (&dimm_info[1], 0, sizeof (sdram_info_t));
#endif
/* unmap all banks */
memory_map_bank(0, 0, 0);
memory_map_bank(1, 0, 0);
memory_map_bank(2, 0, 0);
memory_map_bank(3, 0, 0);
memory_map_bank (0, 0, 0);
memory_map_bank (1, 0, 0);
memory_map_bank (2, 0, 0);
memory_map_bank (3, 0, 0);
/* Now, program the GT with the correct values */
if (setup_sdram_common(dimm_info)) {
printf("Setup common failed.\n");
if (setup_sdram_common (dimm_info)) {
printf ("Setup common failed.\n");
}
if (setup_sdram(&dimm_info[0])) {
printf("Setup for DIMM1 failed.\n");
if (setup_sdram (&dimm_info[0])) {
printf ("Setup for DIMM1 failed.\n");
}
if (setup_sdram(&dimm_info[1])) {
printf("Setup for DIMM2 failed.\n");
if (setup_sdram (&dimm_info[1])) {
printf ("Setup for DIMM2 failed.\n");
}
/* set the NHR bit */
set_hid0(get_hid0() | (1 << 16));
set_hid0 (get_hid0 () | (1 << 16));
}
/* next, size the SDRAM banks */
total = 0;
if (dimm_info[0].banks > 0) checkbank[0] = 1;
if (dimm_info[0].banks > 1) checkbank[1] = 1;
if (dimm_info[0].banks > 0)
checkbank[0] = 1;
if (dimm_info[0].banks > 1)
checkbank[1] = 1;
if (dimm_info[0].banks > 2)
printf("Error, SPD claims DIMM1 has >2 banks\n");
printf ("Error, SPD claims DIMM1 has >2 banks\n");
if (dimm_info[1].banks > 0) checkbank[2] = 1;
if (dimm_info[1].banks > 1) checkbank[3] = 1;
if (dimm_info[1].banks > 0)
checkbank[2] = 1;
if (dimm_info[1].banks > 1)
checkbank[3] = 1;
if (dimm_info[1].banks > 2)
printf("Error, SPD claims DIMM2 has >2 banks\n");
printf ("Error, SPD claims DIMM2 has >2 banks\n");
/* Generic dram sizer: works even if we don't have i2c DIMMs,
* as long as the timing settings are more or less correct */
/*
* pass 1: size all the banks, using first bat (0-256M)
* limitation: we only support 256M per bank due to
* us only having 1 BAT for all DRAM
* limitation: we only support 256M per bank due to
* us only having 1 BAT for all DRAM
*/
for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
/* skip over banks that are not populated */
if (! checkbank[bank_no])
if (!checkbank[bank_no])
continue;
DP(printf("checking bank %d\n", bank_no));
DP (printf ("checking bank %d\n", bank_no));
memory_map_bank(bank_no, 0, GB/4);
checkbank[bank_no] = dram_size(NULL, GB/4);
memory_map_bank(bank_no, 0, 0);
memory_map_bank (bank_no, 0, GB / 4);
checkbank[bank_no] = dram_size (NULL, GB / 4);
memory_map_bank (bank_no, 0, 0);
DP(printf("bank %d %08lx\n", bank_no, checkbank[bank_no]));
DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no]));
}
/*
* pass 2: contiguously map each bank into physical address
* space.
* space.
*/
dimm_info[0].banks=dimm_info[1].banks=0;
dimm_info[0].banks = dimm_info[1].banks = 0;
for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
if(!checkbank[bank_no]) continue;
if (!checkbank[bank_no])
continue;
dimm_info[bank_no/2].banks++;
dimm_info[bank_no/2].size+=checkbank[bank_no];
dimm_info[bank_no / 2].banks++;
dimm_info[bank_no / 2].size += checkbank[bank_no];
memory_map_bank(bank_no, total, checkbank[bank_no]);
memory_map_bank (bank_no, total, checkbank[bank_no]);
#ifdef MAP_PCI
memory_map_bank_pci(bank_no, total, checkbank[bank_no]);
memory_map_bank_pci (bank_no, total, checkbank[bank_no]);
#endif
total += checkbank[bank_no];
}
@ -630,21 +643,22 @@ initdram(int board_type)
* in that configuration, ECC chips are mounted, even for stacked
* chips)
*/
if (checkbank[2]==0 && checkbank[3]==0) {
dimm_info[0].ecc=2;
GT_REG_WRITE(SDRAM_TIMING, GTREGREAD(SDRAM_TIMING) | (1 << 13));
if (checkbank[2] == 0 && checkbank[3] == 0) {
dimm_info[0].ecc = 2;
GT_REG_WRITE (SDRAM_TIMING,
GTREGREAD (SDRAM_TIMING) | (1 << 13));
/* TODO: do we have to run MRS cycles again? */
}
#endif /* CONFIG_ZUMA_V2 */
if (GTREGREAD(SDRAM_TIMING) & (1 << 13)) {
puts("[ECC] ");
if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) {
puts ("[ECC] ");
}
#endif /* CONFIG_ECC */
#ifdef DEBUG
dump_dimm_info(&dimm_info[0]);
dump_dimm_info(&dimm_info[1]);
dump_dimm_info (&dimm_info[0]);
dump_dimm_info (&dimm_info[1]);
#endif
/* TODO: return at MOST 256M? */
/* return total > GB/4 ? GB/4 : total; */

42
board/evb64260/zuma_pbb_mbox.h
View File

@ -2,33 +2,33 @@
#define OUT_PENDING 2
enum {
ZUMA_MBOXMSG_DONE,
ZUMA_MBOXMSG_MACL,
ZUMA_MBOXMSG_MACH,
ZUMA_MBOXMSG_IP,
ZUMA_MBOXMSG_SLOT,
ZUMA_MBOXMSG_RESET,
ZUMA_MBOXMSG_BAUD,
ZUMA_MBOXMSG_START,
ZUMA_MBOXMSG_ENG_PRV_MACL,
ZUMA_MBOXMSG_ENG_PRV_MACH,
ZUMA_MBOXMSG_DONE,
ZUMA_MBOXMSG_MACL,
ZUMA_MBOXMSG_MACH,
ZUMA_MBOXMSG_IP,
ZUMA_MBOXMSG_SLOT,
ZUMA_MBOXMSG_RESET,
ZUMA_MBOXMSG_BAUD,
ZUMA_MBOXMSG_START,
ZUMA_MBOXMSG_ENG_PRV_MACL,
ZUMA_MBOXMSG_ENG_PRV_MACH,
MBOXMSG_LAST
MBOXMSG_LAST
};
struct zuma_mailbox_info {
unsigned char acc_mac[6];
unsigned char prv_mac[6];
unsigned int ip;
unsigned int slot_bac;
unsigned int console_baud;
unsigned int debug_baud;
unsigned char acc_mac[6];
unsigned char prv_mac[6];
unsigned int ip;
unsigned int slot_bac;
unsigned int console_baud;
unsigned int debug_baud;
};
struct _zuma_mbox_dev {
pci_dev_t dev;
PBB_DMA_REG_MAP *sip;
struct zuma_mailbox_info mailbox;
pci_dev_t dev;
PBB_DMA_REG_MAP *sip;
struct zuma_mailbox_info mailbox;
};
#define zuma_prv_mac zuma_mbox_dev.mailbox.prv_mac
@ -40,4 +40,4 @@ struct _zuma_mbox_dev {
extern struct _zuma_mbox_dev zuma_mbox_dev;
extern int zuma_mbox_init(void);
extern int zuma_mbox_init (void);

407
board/fads/flash.c
View File

@ -24,7 +24,7 @@
#include <common.h>
#include <mpc8xx.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#if defined(CFG_ENV_IS_IN_FLASH)
# ifndef CFG_ENV_ADDR
@ -41,43 +41,42 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t *info);
static ulong flash_get_size (vu_long * addr, flash_info_t * info);
static int write_word (flash_info_t * info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t * info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long total_size;
unsigned long size_b0, size_b1;
int i;
/* Init: no FLASHes known */
for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
{
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
total_size = 0;
size_b0 = 0xffffffff;
for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
{
size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + total_size), &flash_info[i]);
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
size_b1 =
flash_get_size ((vu_long *) (CFG_FLASH_BASE +
total_size),
&flash_info[i]);
if (flash_info[i].flash_id == FLASH_UNKNOWN)
{
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", i, size_b1, size_b1>>20);
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", i, size_b1, size_b1 >> 20);
}
/* Is this really needed ? - LP */
if (size_b1 > size_b0) {
printf ("## ERROR: Bank %d (0x%08lx = %ld MB) > Bank %d (0x%08lx = %ld MB)\n",
i, size_b1, size_b1>>20, i-1, size_b0, size_b0>>20);
printf ("## ERROR: Bank %d (0x%08lx = %ld MB) > Bank %d (0x%08lx = %ld MB)\n", i, size_b1, size_b1 >> 20, i - 1, size_b0, size_b0 >> 20);
goto out_error;
}
size_b0 = size_b1;
@ -85,43 +84,47 @@ unsigned long flash_init (void)
}
/* Compute the Address Mask */
for (i=0; (total_size >> i) != 0; ++i) {};
for (i = 0; (total_size >> i) != 0; ++i) {
}
i--;
if (total_size != (1 << i)) {
printf ("## WARNING: Total FLASH size (0x%08lx = %ld MB) is not a power of 2\n",
total_size, total_size>>20);
printf ("## WARNING: Total FLASH size (0x%08lx = %ld MB) is not a power of 2\n", total_size, total_size >> 20);
}
/* Remap FLASH according to real size */
memctl->memc_or0 = ((((unsigned long)~1) << i) & OR_AM_MSK) | CFG_OR_TIMING_FLASH;
memctl->memc_or0 =
((((unsigned long) ~1) << i) & OR_AM_MSK) |
CFG_OR_TIMING_FLASH;
memctl->memc_br0 = CFG_BR0_PRELIM;
total_size = 0;
for (i=0; i < CFG_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i)
{
for (i = 0; i < CFG_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i) {
/* Re-do sizing to get full correct info */
/* Why ? - LP */
size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + total_size), &flash_info[i]);
size_b1 =
flash_get_size ((vu_long *) (CFG_FLASH_BASE +
total_size),
&flash_info[i]);
/* This is done by flash_get_size - LP */
/* flash_get_offsets (CFG_FLASH_BASE + total_size, &flash_info[i]); */
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
&flash_info[i]);
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[i]);
#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR+CFG_ENV_SIZE-1,
&flash_info[i]);
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
&flash_info[i]);
#endif
total_size += size_b1;
@ -129,12 +132,11 @@ unsigned long flash_init (void)
return (total_size);
out_error:
for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
{
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
out_error:
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
}
return (0);
@ -142,13 +144,14 @@ out_error:
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t *info)
static void flash_get_offsets (ulong base, flash_info_t * info)
{
int i;
/* set up sector start address table */
if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040 || (info->flash_id & FLASH_TYPEMASK) == FLASH_AM080 ) {
/* set sector offsets for uniform sector type */
if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040
|| (info->flash_id & FLASH_TYPEMASK) == FLASH_AM080) {
/* set sector offsets for uniform sector type */
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00040000);
}
@ -157,64 +160,78 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
void flash_print_info (flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN)
{
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK)
{
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
default: printf ("Unknown Vendor "); break;
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
printf ("AMD ");
break;
case FLASH_MAN_FUJ:
printf ("FUJITSU ");
break;
case FLASH_MAN_BM:
printf ("BRIGHT MICRO ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK)
{
case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
break;
case FLASH_AM080: printf ("29F080 or 29LV080 (8 Mbit, uniform sectors)\n");
break;
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM040:
printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
break;
case FLASH_AM080:
printf ("29F080 or 29LV080 (8 Mbit, uniform sectors)\n");
break;
case FLASH_AM400B:
printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T:
printf ("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B:
printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T:
printf ("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B:
printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T:
printf ("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B:
printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T:
printf ("AM29LV320T (32 Mbit, top boot sector)\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count);
printf (" Size: %ld MB in %d Sectors\n", info->size >> 20,
info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i)
{
if ((i % 5) == 0)
{
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0) {
printf ("\n ");
}
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " ");
info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
@ -232,11 +249,12 @@ void flash_print_info (flash_info_t *info)
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
static ulong flash_get_size (vu_long * addr, flash_info_t * info)
{
short i;
#if 0
ulong base = (ulong)addr;
ulong base = (ulong) addr;
#endif
uchar value;
@ -253,97 +271,95 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
value = addr[0];
switch (value + (value << 16))
{
case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
switch (value + (value << 16)) {
case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
break;
}
value = addr[1]; /* device ID */
value = addr[1]; /* device ID */
switch (value)
{
case AMD_ID_F040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x00200000;
break; /* => 2 MB */
switch (value) {
case AMD_ID_F040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x00200000;
break; /* => 2 MB */
case AMD_ID_F080B:
info->flash_id += FLASH_AM080;
info->sector_count =16;
info->size = 0x00400000;
break; /* => 4 MB */
case AMD_ID_F080B:
info->flash_id += FLASH_AM080;
info->sector_count = 16;
info->size = 0x00400000;
break; /* => 4 MB */
case AMD_ID_LV400T:
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00100000;
break; /* => 1 MB */
case AMD_ID_LV400T:
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00100000;
break; /* => 1 MB */
case AMD_ID_LV400B:
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00100000;
break; /* => 1 MB */
case AMD_ID_LV400B:
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00100000;
break; /* => 1 MB */
case AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00200000;
break; /* => 2 MB */
case AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00200000;
break; /* => 2 MB */
case AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00200000;
break; /* => 2 MB */
case AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00200000;
break; /* => 2 MB */
case AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00400000;
break; /* => 4 MB */
case AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00400000;
break; /* => 4 MB */
case AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00400000;
break; /* => 4 MB */
#if 0 /* enable when device IDs are available */
case AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 67;
info->size = 0x00800000;
break; /* => 8 MB */
case AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00400000;
break; /* => 4 MB */
#if 0 /* enable when device IDs are available */
case AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 67;
info->size = 0x00800000;
break; /* => 8 MB */
case AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
info->sector_count = 67;
info->size = 0x00800000;
break; /* => 8 MB */
case AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
info->sector_count = 67;
info->size = 0x00800000;
break; /* => 8 MB */
#endif
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
#if 0
/* set up sector start address table */
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x0000C000;
@ -352,7 +368,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
info->start[i] = base + (i * 0x00020000) - 0x00060000;
}
} else {
/* set sector offsets for top boot block type */
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00008000;
info->start[i--] = base + info->size - 0x0000C000;
@ -362,24 +378,22 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
}
}
#else
flash_get_offsets ((ulong)addr, info);
flash_get_offsets ((ulong) addr, info);
#endif
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++)
{
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr = (volatile unsigned long *)(info->start[i]);
addr = (volatile unsigned long *) (info->start[i]);
info->protect[i] = addr[2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN)
{
addr = (volatile unsigned long *)info->start[0];
if (info->flash_id != FLASH_UNKNOWN) {
addr = (volatile unsigned long *) info->start[0];
#if 0
*addr = 0x00F000F0; /* reset bank */
#else
@ -394,9 +408,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
vu_long *addr = (vu_long*)(info->start[0]);
vu_long *addr = (vu_long *) (info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
@ -416,15 +430,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf ("\n");
}
@ -432,7 +445,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
flag = disable_interrupts ();
#if 0
addr[0x0555] = 0x00AA00AA;
@ -449,9 +462,9 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
#endif
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (vu_long*)(info->start[sect]);
addr = (vu_long *) (info->start[sect]);
#if 0
addr[0] = 0x00300030;
#else
@ -463,7 +476,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
enable_interrupts ();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
@ -475,15 +488,15 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
goto DONE;
start = get_timer (0);
last = start;
addr = (vu_long*)(info->start[l_sect]);
last = start;
addr = (vu_long *) (info->start[l_sect]);
#if 0
while ((addr[0] & 0x00800080) != 0x00800080)
#else
while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
#endif
{
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
@ -494,9 +507,9 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
}
}
DONE:
DONE:
/* reset to read mode */
addr = (volatile unsigned long *)info->start[0];
addr = (volatile unsigned long *) info->start[0];
#if 0
addr[0] = 0x00F000F0; /* reset bank */
#else
@ -514,7 +527,7 @@ DONE:
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
@ -526,19 +539,19 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i<4 && cnt>0; ++i) {
for (; i < 4 && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
for (; cnt == 0 && i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
wp += 4;
@ -549,13 +562,13 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
for (i = 0; i < 4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
}
wp += 4;
wp += 4;
cnt -= 4;
}
@ -567,15 +580,15 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
for (; i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return (write_word(info, wp, data));
return (write_word (info, wp, data));
}
/*-----------------------------------------------------------------------
@ -584,18 +597,18 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
static int write_word (flash_info_t * info, ulong dest, ulong data)
{
vu_long *addr = (vu_long*)(info->start[0]);
vu_long *addr = (vu_long *) (info->start[0]);
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_long *)dest) & data) != data) {
if ((*((vu_long *) dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
flag = disable_interrupts ();
#if 0
addr[0x0555] = 0x00AA00AA;
@ -607,21 +620,21 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
addr[0x0555] = 0xA0A0A0A0;
#endif
*((vu_long *)dest) = data;
*((vu_long *) dest) = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
enable_interrupts ();
/* data polling for D7 */
start = get_timer (0);
#if 0
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080))
while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080))
#else
while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080))
while ((*((vu_long *) dest) & 0x80808080) != (data & 0x80808080))
#endif
{
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}

227
board/gen860t/fpga.c
View File

@ -72,30 +72,27 @@ Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
};
Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
{ Xilinx_Virtex2,
slave_selectmap,
XILINX_XC2V3000_SIZE,
(void *)&fpga_fns,
0
}
{Xilinx_Virtex2,
slave_selectmap,
XILINX_XC2V3000_SIZE,
(void *) &fpga_fns,
0}
};
/*
* Display FPGA revision information
*/
void
print_fpga_revision(void)
void print_fpga_revision (void)
{
vu_long *rev_p = (vu_long *)0x60000008;
vu_long *rev_p = (vu_long *) 0x60000008;
printf("FPGA Revision 0x%.8lx"
" (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n",
*rev_p,
((*rev_p >> 28) & 0xf),
((*rev_p >> 20) & 0xff),
((*rev_p >> 12) & 0xff),
((*rev_p >> 8) & 0xf),
(*rev_p & 0xff));
printf ("FPGA Revision 0x%.8lx"
" (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n",
*rev_p,
((*rev_p >> 28) & 0xf),
((*rev_p >> 20) & 0xff),
((*rev_p >> 12) & 0xff),
((*rev_p >> 8) & 0xf), (*rev_p & 0xff));
}
@ -106,10 +103,9 @@ print_fpga_revision(void)
* problems with bus charging.
* Return 0 on failure, 1 on success.
*/
int
test_fpga_ibtr(void)
int test_fpga_ibtr (void)
{
vu_long *ibtr_p = (vu_long *)0x60000010;
vu_long *ibtr_p = (vu_long *) 0x60000010;
vu_long readback;
vu_long compare;
int i;
@ -118,40 +114,41 @@ test_fpga_ibtr(void)
int pass = 1;
static const ulong bitpattern[] = {
0xdeadbeef, /* magic ID pattern for debug */
0x00000001, /* single bit */
0x00000003, /* two adjacent bits */
0x00000007, /* three adjacent bits */
0x0000000F, /* four adjacent bits */
0x00000005, /* two non-adjacent bits */
0x00000015, /* three non-adjacent bits */
0x00000055, /* four non-adjacent bits */
0xaaaaaaaa, /* alternating 1/0 */
0xdeadbeef, /* magic ID pattern for debug */
0x00000001, /* single bit */
0x00000003, /* two adjacent bits */
0x00000007, /* three adjacent bits */
0x0000000F, /* four adjacent bits */
0x00000005, /* two non-adjacent bits */
0x00000015, /* three non-adjacent bits */
0x00000055, /* four non-adjacent bits */
0xaaaaaaaa, /* alternating 1/0 */
};
for (i = 0; i < 1024; i++) {
for (j = 0; j < 31; j++) {
for (k = 0; k < sizeof(bitpattern)/sizeof(bitpattern[0]); k++) {
for (k = 0;
k < sizeof (bitpattern) / sizeof (bitpattern[0]);
k++) {
*ibtr_p = compare = (bitpattern[k] << j);
readback = *ibtr_p;
if (readback != ~compare) {
printf("%s:%d: FPGA test fail: expected 0x%.8lx"
" actual 0x%.8lx\n",
__FUNCTION__, __LINE__, ~compare, readback);
printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback);
pass = 0;
break;
}
}
if (!pass) break;
if (!pass)
break;
}
if (!pass) break;
if (!pass)
break;
}
if (pass) {
printf("FPGA inverting bus test passed\n");
print_fpga_revision();
}
else {
printf("** FPGA inverting bus test failed\n");
printf ("FPGA inverting bus test passed\n");
print_fpga_revision ();
} else {
printf ("** FPGA inverting bus test failed\n");
}
return pass;
}
@ -160,19 +157,17 @@ test_fpga_ibtr(void)
/*
* Set the active-low FPGA reset signal.
*/
void
fpga_reset(int assert)
void fpga_reset (int assert)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
PRINTF("%s:%d: RESET ", __FUNCTION__, __LINE__);
PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__);
if (assert) {
immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM);
PRINTF("asserted\n");
}
else {
PRINTF ("asserted\n");
} else {
immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM);
PRINTF("deasserted\n");
PRINTF ("deasserted\n");
}
}
@ -181,54 +176,52 @@ fpga_reset(int assert)
* Initialize the SelectMap interface. We assume that the mode and the
* initial state of all of the port pins have already been set!
*/
void
fpga_selectmap_init(void)
void fpga_selectmap_init (void)
{
PRINTF("%s:%d: Initialize SelectMap interface\n", __FUNCTION__, __LINE__);
fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */
PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__,
__LINE__);
fpga_pgm_fn (FALSE, FALSE, 0); /* make sure program pin is inactive */
}
/*
* Initialize the fpga. Return 1 on success, 0 on failure.
*/
int
gen860t_init_fpga(void)
int gen860t_init_fpga (void)
{
DECLARE_GLOBAL_DATA_PTR;
int i;
PRINTF("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n",
__FUNCTION__, __LINE__, gd->reloc_off);
fpga_init(gd->reloc_off);
fpga_selectmap_init();
PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off);
fpga_init (gd->reloc_off);
fpga_selectmap_init ();
for(i=0; i < CONFIG_FPGA_COUNT; i++) {
PRINTF("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
fpga_add(fpga_xilinx, &fpga[i]);
for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
fpga_add (fpga_xilinx, &fpga[i]);
}
return 1;
return 1;
}
/*
* Set the FPGA's active-low SelectMap program line to the specified level
*/
int
fpga_pgm_fn(int assert, int flush, int cookie)
int fpga_pgm_fn (int assert, int flush, int cookie)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
PRINTF("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
if (assert) {
immap->im_ioport.iop_padat &= ~(0x8000 >> FPGA_PROGRAM_BIT_NUM);
PRINTF("asserted\n");
}
else {
immap->im_ioport.iop_padat |= (0x8000 >> FPGA_PROGRAM_BIT_NUM);
PRINTF("deasserted\n");
immap->im_ioport.iop_padat &=
~(0x8000 >> FPGA_PROGRAM_BIT_NUM);
PRINTF ("asserted\n");
} else {
immap->im_ioport.iop_padat |=
(0x8000 >> FPGA_PROGRAM_BIT_NUM);
PRINTF ("deasserted\n");
}
return assert;
}
@ -238,18 +231,16 @@ fpga_pgm_fn(int assert, int flush, int cookie)
* Test the state of the active-low FPGA INIT line. Return 1 on INIT
* asserted (low).
*/
int
fpga_init_fn(int cookie)
int fpga_init_fn (int cookie)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
PRINTF("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
if(immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) {
PRINTF("high\n");
PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) {
PRINTF ("high\n");
return 0;
}
else {
PRINTF("low\n");
} else {
PRINTF ("low\n");
return 1;
}
}
@ -258,18 +249,16 @@ fpga_init_fn(int cookie)
/*
* Test the state of the active-high FPGA DONE pin
*/
int
fpga_done_fn(int cookie)
int fpga_done_fn (int cookie)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
PRINTF("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) {
PRINTF("high\n");
PRINTF ("high\n");
return FPGA_SUCCESS;
}
else {
PRINTF("low\n");
} else {
PRINTF ("low\n");
return FPGA_FAIL;
}
}
@ -278,43 +267,40 @@ fpga_done_fn(int cookie)
/*
* Read FPGA SelectMap data.
*/
int
fpga_read_data_fn(unsigned char *data, int cookie)
int fpga_read_data_fn (unsigned char *data, int cookie)
{
vu_char *p = (vu_char *)SELECTMAP_BASE;
vu_char *p = (vu_char *) SELECTMAP_BASE;
*data = *p;
#if 0
PRINTF("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int)data, data);
PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data);
#endif
return (int)data;
return (int) data;
}
/*
* Write data to the FPGA SelectMap port
*/
int
fpga_write_data_fn(unsigned char data, int flush, int cookie)
int fpga_write_data_fn (unsigned char data, int flush, int cookie)
{
vu_char *p = (vu_char *)SELECTMAP_BASE;
vu_char *p = (vu_char *) SELECTMAP_BASE;
#if 0
PRINTF("%s: Write Data 0x%x\n", __FUNCTION__, (int)data);
PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data);
#endif
*p = data;
return (int)data;
return (int) data;
}
/*
* Abort and FPGA operation
*/
int
fpga_abort_fn(int cookie)
int fpga_abort_fn (int cookie)
{
PRINTF("%s:%d: FPGA program sequence aborted\n",
__FUNCTION__, __LINE__);
PRINTF ("%s:%d: FPGA program sequence aborted\n",
__FUNCTION__, __LINE__);
return FPGA_FAIL;
}
@ -324,11 +310,10 @@ fpga_abort_fn(int cookie)
* FPGA reset is asserted to keep the FPGA from starting up after
* configuration.
*/
int
fpga_pre_config_fn(int cookie)
int fpga_pre_config_fn (int cookie)
{
PRINTF("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
fpga_reset(TRUE);
PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
fpga_reset (TRUE);
return 0;
}
@ -337,22 +322,21 @@ fpga_pre_config_fn(int cookie)
* FPGA post configuration function. Blip the FPGA reset line and then see if
* the FPGA appears to be running.
*/
int
fpga_post_config_fn(int cookie)
int fpga_post_config_fn (int cookie)
{
int rc;
PRINTF("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
fpga_reset(TRUE);
udelay(1000);
fpga_reset(FALSE);
PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
fpga_reset (TRUE);
udelay (1000);
fpga_reset (FALSE);
udelay (1000);
/*
* Use the FPGA,s inverting bus test register to do a simple test of the
* processor interface.
*/
rc = test_fpga_ibtr();
rc = test_fpga_ibtr ();
return rc;
}
@ -367,32 +351,27 @@ fpga_post_config_fn(int cookie)
* going low during configuration, so there is no need for a separate error
* function.
*/
int
fpga_clk_fn(int assert_clk, int flush, int cookie)
int fpga_clk_fn (int assert_clk, int flush, int cookie)
{
return assert_clk;
}
int
fpga_cs_fn(int assert_cs, int flush, int cookie)
int fpga_cs_fn (int assert_cs, int flush, int cookie)
{
return assert_cs;
}
int
fpga_wr_fn(int assert_write, int flush, int cookie)
int fpga_wr_fn (int assert_write, int flush, int cookie)
{
return assert_write;
}
int
fpga_err_fn(int cookie)
int fpga_err_fn (int cookie)
{
return 0;
}
int
fpga_busy_fn(int cookie)
int fpga_busy_fn (int cookie)
{
return 0;
}

145
board/gen860t/gen860t.c
View File

@ -94,7 +94,7 @@ const uint sdram_upm_table[] = {
0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
/* exception (offset 0x3C in upm ram) */
};
};
const uint selectmap_upm_table[] = {
/* single read (offset 0x00 in upm ram) */
@ -124,63 +124,61 @@ const uint selectmap_upm_table[] = {
/*
* Check board identity. Always successful (gives information only)
*/
int
checkboard(void)
int checkboard (void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned char *s;
unsigned char buf[64];
int i;
unsigned char *s;
unsigned char buf[64];
int i;
i = getenv_r("board_id", buf, sizeof(buf));
s = (i>0) ? buf : NULL;
i = getenv_r ("board_id", buf, sizeof (buf));
s = (i > 0) ? buf : NULL;
if (s) {
printf("%s ", s);
printf ("%s ", s);
} else {
printf("<unknown> ");
printf ("<unknown> ");
}
i = getenv_r("serial#", buf, sizeof(buf));
s = (i>0) ? buf : NULL;
i = getenv_r ("serial#", buf, sizeof (buf));
s = (i > 0) ? buf : NULL;
if (s) {
printf("S/N %s\n", s);
printf ("S/N %s\n", s);
} else {
printf("S/N <unknown>\n");
printf ("S/N <unknown>\n");
}
printf("CPU at %s MHz, ",strmhz(buf, gd->cpu_clk));
printf("local bus at %s MHz\n", strmhz(buf, gd->bus_clk));
return (0);
printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk));
printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk));
return (0);
}
/*
* Initialize SDRAM
*/
long int
initdram(int board_type)
long int initdram (int board_type)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
upmconfig(UPMA,
(uint *)sdram_upm_table,
sizeof(sdram_upm_table) / sizeof(uint)
);
upmconfig (UPMA,
(uint *) sdram_upm_table,
sizeof (sdram_upm_table) / sizeof (uint)
);
/*
* Setup MAMR register
*/
memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
/*
* Setup MAMR register
*/
memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
/*
* Map CS1* to SDRAM bank
*/
memctl->memc_or1 = CFG_OR1;
memctl->memc_br1 = CFG_BR1;
/*
* Map CS1* to SDRAM bank
*/
memctl->memc_or1 = CFG_OR1;
memctl->memc_br1 = CFG_BR1;
/*
* Perform SDRAM initialization sequence:
@ -193,31 +191,31 @@ initdram(int board_type)
* Program SDRAM for standard operation, sequential burst, burst length
* of 4, CAS latency of 2.
*/
memctl->memc_mar = 0x00000000;
memctl->memc_mar = 0x00000000;
memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
MCR_MLCF(0) | UPMA_NOP_ADDR;
udelay(200);
memctl->memc_mar = 0x00000000;
MCR_MLCF (0) | UPMA_NOP_ADDR;
udelay (200);
memctl->memc_mar = 0x00000000;
memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
MCR_MLCF(4) | UPMA_PRECHARGE_ADDR;
MCR_MLCF (4) | UPMA_PRECHARGE_ADDR;
memctl->memc_mar = 0x00000000;
memctl->memc_mar = 0x00000000;
memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
MCR_MLCF(2) | UPM_REFRESH_ADDR;
MCR_MLCF (2) | UPM_REFRESH_ADDR;
memctl->memc_mar = 0x00000088;
memctl->memc_mar = 0x00000088;
memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
MCR_MLCF(1) | UPMA_MRS_ADDR;
MCR_MLCF (1) | UPMA_MRS_ADDR;
memctl->memc_mar = 0x00000000;
memctl->memc_mar = 0x00000000;
memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
MCR_MLCF(0) | UPMA_NOP_ADDR;
MCR_MLCF (0) | UPMA_NOP_ADDR;
/*
* Enable refresh
*/
memctl->memc_mamr |= MAMR_PTAE;
memctl->memc_mamr |= MAMR_PTAE;
return (SDRAM_SIZE);
return (SDRAM_SIZE);
}
/*
@ -225,42 +223,39 @@ initdram(int board_type)
* The DOC lives in the CS2* space
*/
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
extern void
doc_probe(ulong physadr);
extern void doc_probe (ulong physadr);
void
doc_init(void)
void doc_init (void)
{
printf("Probing at 0x%.8x: ", DOC_BASE);
doc_probe(DOC_BASE);
printf ("Probing at 0x%.8x: ", DOC_BASE);
doc_probe (DOC_BASE);
}
#endif
/*
* Miscellaneous intialization
*/
int
misc_init_r (void)
int misc_init_r (void)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
/*
* Set up UPMB to handle the Virtex FPGA SelectMap interface
*/
upmconfig(UPMB, (uint *)selectmap_upm_table,
sizeof(selectmap_upm_table) / sizeof(uint));
upmconfig (UPMB, (uint *) selectmap_upm_table,
sizeof (selectmap_upm_table) / sizeof (uint));
memctl->memc_mbmr = 0x0;
memctl->memc_mbmr = 0x0;
config_mpc8xx_ioports(immr);
config_mpc8xx_ioports (immr);
#if (CONFIG_COMMANDS & CFG_CMD_MII)
mii_init();
mii_init ();
#endif
#if (CONFIG_FPGA)
gen860t_init_fpga();
gen860t_init_fpga ();
#endif
return 0;
}
@ -268,8 +263,7 @@ misc_init_r (void)
/*
* Final init hook before entering command loop.
*/
int
last_stage_init(void)
int last_stage_init (void)
{
#if !defined(CONFIG_SC)
unsigned char buf[256];
@ -278,15 +272,15 @@ last_stage_init(void)
/*
* Turn the beeper volume all the way down in case this is a warm boot.
*/
set_beeper_volume(-64);
init_beeper();
set_beeper_volume (-64);
init_beeper ();
/*
* Read the environment to see what to do with the beeper
*/
i = getenv_r("beeper", buf, sizeof(buf));
i = getenv_r ("beeper", buf, sizeof (buf));
if (i > 0) {
do_beeper(buf);
do_beeper (buf);
}
#endif
return 0;
@ -295,11 +289,10 @@ last_stage_init(void)
/*
* Stub to make POST code happy. Can't self-poweroff, so just hang.
*/
void
board_poweroff(void)
void board_poweroff (void)
{
puts("### Please power off the board ###\n");
while (1);
puts ("### Please power off the board ###\n");
while (1);
}
#ifdef CONFIG_POST
@ -307,9 +300,9 @@ board_poweroff(void)
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
int post_hotkeys_pressed (void)
{
return 0; /* No hotkeys supported */
return 0; /* No hotkeys supported */
}
#endif

194
board/gen860t/ioport.c
View File

@ -199,16 +199,16 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
* Configure the MPC8XX I/O ports per the ioport configuration table
* (taken from ./cpu/mpc8260/cpu_init.c)
*/
void
config_mpc8xx_ioports(volatile immap_t *immr)
void config_mpc8xx_ioports (volatile immap_t * immr)
{
int portnum;
int portnum;
for (portnum = 0; portnum < NUM_PORTS; portnum++) {
for (portnum = 0; portnum < NUM_PORTS; portnum++) {
uint pmsk = 0, ppar = 0, psor = 0, pdir = 0;
uint podr = 0, pdat = 0, pint = 0;
uint msk = 1;
mpc8xx_iop_conf_t *iopc = (mpc8xx_iop_conf_t *)&iop_conf_tab[portnum][0];
mpc8xx_iop_conf_t *iopc =
(mpc8xx_iop_conf_t *) & iop_conf_tab[portnum][0];
mpc8xx_iop_conf_t *eiopc = iopc + PORT_BITS;
/*
@ -216,104 +216,132 @@ config_mpc8xx_ioports(volatile immap_t *immr)
* in the configuration tables.
*/
if (portnum != 1) {
iopc = (mpc8xx_iop_conf_t *)&iop_conf_tab[portnum][2];
iopc = (mpc8xx_iop_conf_t *) &
iop_conf_tab[portnum][2];
}
/*
* NOTE: index 0 refers to pin 17, index 17 refers to pin 0
*/
while (iopc < eiopc) {
if (iopc->conf) {
if (iopc->conf) {
pmsk |= msk;
if (iopc->ppar) ppar |= msk;
if (iopc->psor) psor |= msk;
if (iopc->pdir) pdir |= msk;
if (iopc->podr) podr |= msk;
if (iopc->pdat) pdat |= msk;
if (iopc->pint) pint |= msk;
}
msk <<= 1;
iopc++;
if (iopc->ppar)
ppar |= msk;
if (iopc->psor)
psor |= msk;
if (iopc->pdir)
pdir |= msk;
if (iopc->podr)
podr |= msk;
if (iopc->pdat)
pdat |= msk;
if (iopc->pint)
pint |= msk;
}
msk <<= 1;
iopc++;
}
PRINTF("%s:%d:\n portnum=%d ", __FUNCTION__, __LINE__, portnum);
PRINTF ("%s:%d:\n portnum=%d ", __FUNCTION__, __LINE__,
portnum);
#ifdef IOPORT_DEBUG
switch(portnum) {
case 0: printf("(A)\n"); break;
case 1: printf("(B)\n"); break;
case 2: printf("(C)\n"); break;
case 3: printf("(D)\n"); break;
default: printf("(?)\n"); break;
switch (portnum) {
case 0:
printf ("(A)\n");
break;
case 1:
printf ("(B)\n");
break;
case 2:
printf ("(C)\n");
break;
case 3:
printf ("(D)\n");
break;
default:
printf ("(?)\n");
break;
}
#endif
PRINTF(" ppar=0x%.8x pdir=0x%.8x podr=0x%.8x\n"
" pdat=0x%.8x psor=0x%.8x pint=0x%.8x pmsk=0x%.8x\n",
ppar, pdir, podr, pdat, psor, pint, pmsk);
PRINTF (" ppar=0x%.8x pdir=0x%.8x podr=0x%.8x\n"
" pdat=0x%.8x psor=0x%.8x pint=0x%.8x pmsk=0x%.8x\n",
ppar, pdir, podr, pdat, psor, pint, pmsk);
/*
* Have to handle the ioports on a port-by-port basis since there
* are three different flavors.
*/
if (pmsk != 0) {
uint tpmsk = ~pmsk;
uint tpmsk = ~pmsk;
if (0 == portnum) { /* port A */
immr->im_ioport.iop_papar &= tpmsk;
immr->im_ioport.iop_padat =
(immr->im_ioport.iop_padat & tpmsk) | pdat;
immr->im_ioport.iop_padir =
(immr->im_ioport.iop_padir & tpmsk) | pdir;
immr->im_ioport.iop_paodr =
(immr->im_ioport.iop_paodr & tpmsk) | podr;
immr->im_ioport.iop_papar |= ppar;
}
else if (1 == portnum) { /* port B */
immr->im_cpm.cp_pbpar &= tpmsk;
immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & tpmsk) | pdat;
immr->im_cpm.cp_pbdir = (immr->im_cpm.cp_pbdir & tpmsk) | pdir;
immr->im_cpm.cp_pbodr = (immr->im_cpm.cp_pbodr & tpmsk) | podr;
immr->im_cpm.cp_pbpar |= ppar;
}
else if (2 == portnum) { /* port C */
immr->im_ioport.iop_pcpar &= tpmsk;
immr->im_ioport.iop_pcdat =
(immr->im_ioport.iop_pcdat & tpmsk) | pdat;
immr->im_ioport.iop_pcdir =
(immr->im_ioport.iop_pcdir & tpmsk) | pdir;
immr->im_ioport.iop_pcint =
(immr->im_ioport.iop_pcint & tpmsk) | pint;
immr->im_ioport.iop_pcso =
(immr->im_ioport.iop_pcso & tpmsk) | psor;
immr->im_ioport.iop_pcpar |= ppar;
}
else if (3 == portnum) { /* port D */
immr->im_ioport.iop_pdpar &= tpmsk;
immr->im_ioport.iop_pddat =
(immr->im_ioport.iop_pddat & tpmsk) | pdat;
immr->im_ioport.iop_pddir =
(immr->im_ioport.iop_pddir & tpmsk) | pdir;
immr->im_ioport.iop_pdpar |= ppar;
if (0 == portnum) { /* port A */
immr->im_ioport.iop_papar &= tpmsk;
immr->im_ioport.iop_padat =
(immr->im_ioport.
iop_padat & tpmsk) | pdat;
immr->im_ioport.iop_padir =
(immr->im_ioport.
iop_padir & tpmsk) | pdir;
immr->im_ioport.iop_paodr =
(immr->im_ioport.
iop_paodr & tpmsk) | podr;
immr->im_ioport.iop_papar |= ppar;
} else if (1 == portnum) { /* port B */
immr->im_cpm.cp_pbpar &= tpmsk;
immr->im_cpm.cp_pbdat =
(immr->im_cpm.
cp_pbdat & tpmsk) | pdat;
immr->im_cpm.cp_pbdir =
(immr->im_cpm.
cp_pbdir & tpmsk) | pdir;
immr->im_cpm.cp_pbodr =
(immr->im_cpm.
cp_pbodr & tpmsk) | podr;
immr->im_cpm.cp_pbpar |= ppar;
} else if (2 == portnum) { /* port C */
immr->im_ioport.iop_pcpar &= tpmsk;
immr->im_ioport.iop_pcdat =
(immr->im_ioport.
iop_pcdat & tpmsk) | pdat;
immr->im_ioport.iop_pcdir =
(immr->im_ioport.
iop_pcdir & tpmsk) | pdir;
immr->im_ioport.iop_pcint =
(immr->im_ioport.
iop_pcint & tpmsk) | pint;
immr->im_ioport.iop_pcso =
(immr->im_ioport.
iop_pcso & tpmsk) | psor;
immr->im_ioport.iop_pcpar |= ppar;
} else if (3 == portnum) { /* port D */
immr->im_ioport.iop_pdpar &= tpmsk;
immr->im_ioport.iop_pddat =
(immr->im_ioport.
iop_pddat & tpmsk) | pdat;
immr->im_ioport.iop_pddir =
(immr->im_ioport.
iop_pddir & tpmsk) | pdir;
immr->im_ioport.iop_pdpar |= ppar;
}
}
}
}
PRINTF("%s:%d: Port A:\n papar=0x%.4x padir=0x%.4x"
" paodr=0x%.4x\n padat=0x%.4x\n", __FUNCTION__, __LINE__,
immr->im_ioport.iop_papar, immr->im_ioport.iop_padir,
immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat);
PRINTF("%s:%d: Port B:\n pbpar=0x%.8x pbdir=0x%.8x"
" pbodr=0x%.8x\n pbdat=0x%.8x\n", __FUNCTION__, __LINE__,
immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir,
immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat);
PRINTF("%s:%d: Port C:\n pcpar=0x%.4x pcdir=0x%.4x"
" pcdat=0x%.4x\n pcso=0x%.4x pcint=0x%.4x\n ",
__FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar,
immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat,
immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint);
PRINTF("%s:%d: Port D:\n pdpar=0x%.4x pddir=0x%.4x"
" pddat=0x%.4x\n", __FUNCTION__, __LINE__,
immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir,
immr->im_ioport.iop_pddat);
PRINTF ("%s:%d: Port A:\n papar=0x%.4x padir=0x%.4x"
" paodr=0x%.4x\n padat=0x%.4x\n", __FUNCTION__, __LINE__,
immr->im_ioport.iop_papar, immr->im_ioport.iop_padir,
immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat);
PRINTF ("%s:%d: Port B:\n pbpar=0x%.8x pbdir=0x%.8x"
" pbodr=0x%.8x\n pbdat=0x%.8x\n", __FUNCTION__, __LINE__,
immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir,
immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat);
PRINTF ("%s:%d: Port C:\n pcpar=0x%.4x pcdir=0x%.4x"
" pcdat=0x%.4x\n pcso=0x%.4x pcint=0x%.4x\n ",
__FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar,
immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat,
immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint);
PRINTF ("%s:%d: Port D:\n pdpar=0x%.4x pddir=0x%.4x"
" pddat=0x%.4x\n", __FUNCTION__, __LINE__,
immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir,
immr->im_ioport.iop_pddat);
}
/* vim: set ts=4 sw=4 tw=78: */

378
board/gw8260/gw8260.c
View File

@ -212,16 +212,17 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* */
/* */
/*********************************************************************/
int checkboard(void)
int checkboard (void)
{
char *str;
puts ("Board: Advent Networks gw8260\n");
char *str;
str = getenv("serial#");
if (str != NULL) {
printf("SN: %s\n", str);
}
return 0;
puts ("Board: Advent Networks gw8260\n");
str = getenv ("serial#");
if (str != NULL) {
printf ("SN: %s\n", str);
}
return 0;
}
@ -246,30 +247,31 @@ int checkboard(void)
/* May cloober fr0. */
/* */
/*********************************************************************/
static void move64(unsigned long long *src, unsigned long long *dest)
static void move64 (unsigned long long *src, unsigned long long *dest)
{
asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
"stfd 0, 0(4)" /* *dest = fpr0 */
: : : "fr0" ); /* Clobbers fr0 */
return;
asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
"stfd 0, 0(4)" /* *dest = fpr0 */
: : : "fr0"); /* Clobbers fr0 */
return;
}
#if defined (CFG_DRAM_TEST_DATA)
unsigned long long pattern[]= {
0xaaaaaaaaaaaaaaaa,
0xcccccccccccccccc,
0xf0f0f0f0f0f0f0f0,
0xff00ff00ff00ff00,
0xffff0000ffff0000,
0xffffffff00000000,
0x00000000ffffffff,
0x0000ffff0000ffff,
0x00ff00ff00ff00ff,
0x0f0f0f0f0f0f0f0f,
0x3333333333333333,
0x5555555555555555};
unsigned long long pattern[] = {
0xaaaaaaaaaaaaaaaa,
0xcccccccccccccccc,
0xf0f0f0f0f0f0f0f0,
0xff00ff00ff00ff00,
0xffff0000ffff0000,
0xffffffff00000000,
0x00000000ffffffff,
0x0000ffff0000ffff,
0x00ff00ff00ff00ff,
0x0f0f0f0f0f0f0f0f,
0x3333333333333333,
0x5555555555555555
};
/*********************************************************************/
/* NAME: mem_test_data() - test data lines for shorts and opens */
@ -315,34 +317,34 @@ unsigned long long pattern[]= {
/* Assumes only one one SDRAM bank */
/* */
/*********************************************************************/
int mem_test_data(void)
int mem_test_data (void)
{
unsigned long long * pmem =
(unsigned long long *)CFG_SDRAM_BASE ;
unsigned long long temp64;
int num_patterns = sizeof(pattern)/ sizeof(pattern[0]);
int i;
unsigned int hi, lo;
unsigned long long *pmem = (unsigned long long *) CFG_SDRAM_BASE;
unsigned long long temp64;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
unsigned int hi, lo;
for ( i = 0; i < num_patterns; i++) {
move64(&(pattern[i]), pmem);
move64(pmem, &temp64);
for (i = 0; i < num_patterns; i++) {
move64 (&(pattern[i]), pmem);
move64 (pmem, &temp64);
/* hi = (temp64>>32) & 0xffffffff; */
/* lo = temp64 & 0xffffffff; */
/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
/* hi = (temp64>>32) & 0xffffffff; */
/* lo = temp64 & 0xffffffff; */
/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
hi = (pattern[i]>>32) & 0xffffffff;
lo = pattern[i] & 0xffffffff;
/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
hi = (pattern[i] >> 32) & 0xffffffff;
lo = pattern[i] & 0xffffffff;
/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
if (temp64 != pattern[i]){
printf ("\n Data Test Failed, pattern 0x%08x%08x", hi, lo);
return 1;
if (temp64 != pattern[i]) {
printf ("\n Data Test Failed, pattern 0x%08x%08x",
hi, lo);
return 1;
}
}
}
return 0;
return 0;
}
#endif /* CFG_DRAM_TEST_DATA */
@ -368,25 +370,26 @@ int mem_test_data(void)
/* */
/* */
/*********************************************************************/
int mem_test_address(void)
int mem_test_address (void)
{
volatile unsigned int * pmem = (volatile unsigned int *)CFG_SDRAM_BASE ;
const unsigned int size = (CFG_SDRAM_SIZE * 1024 * 1024)/4;
unsigned int i;
volatile unsigned int *pmem =
(volatile unsigned int *) CFG_SDRAM_BASE;
const unsigned int size = (CFG_SDRAM_SIZE * 1024 * 1024) / 4;
unsigned int i;
/* write address to each location */
for ( i = 0; i < size; i++) {
pmem[i] = i;
}
/* verify each loaction */
for ( i = 0; i < size; i++) {
if (pmem[i] != i) {
printf("\n Address Test Failed at 0x%x", i);
return 1;
/* write address to each location */
for (i = 0; i < size; i++) {
pmem[i] = i;
}
}
return 0;
/* verify each loaction */
for (i = 0; i < size; i++) {
if (pmem[i] != i) {
printf ("\n Address Test Failed at 0x%x", i);
return 1;
}
}
return 0;
}
#endif /* CFG_DRAM_TEST_ADDRESS */
@ -418,39 +421,35 @@ int mem_test_address(void)
/* */
/* */
/*********************************************************************/
int mem_march(volatile unsigned long long * base,
unsigned int size,
unsigned long long rmask,
unsigned long long wmask,
short read,
short write)
int mem_march (volatile unsigned long long *base,
unsigned int size,
unsigned long long rmask,
unsigned long long wmask, short read, short write)
{
unsigned int i;
unsigned long long temp;
unsigned int hitemp, lotemp, himask, lomask;
unsigned int i;
unsigned long long temp;
unsigned int hitemp, lotemp, himask, lomask;
for (i = 0 ; i < size ; i++) {
if (read != 0) {
/* temp = base[i]; */
move64 ((unsigned long long *)&(base[i]), &temp);
if (rmask != temp) {
hitemp = (temp>>32) & 0xffffffff;
lotemp = temp & 0xffffffff;
himask = (rmask>>32) & 0xffffffff;
lomask = rmask & 0xffffffff;
for (i = 0; i < size; i++) {
if (read != 0) {
/* temp = base[i]; */
move64 ((unsigned long long *) &(base[i]), &temp);
if (rmask != temp) {
hitemp = (temp >> 32) & 0xffffffff;
lotemp = temp & 0xffffffff;
himask = (rmask >> 32) & 0xffffffff;
lomask = rmask & 0xffffffff;
printf("\n Walking one's test failed: address = 0x%08x,"
"\n\texpected 0x%08x%08x, found 0x%08x%08x",
i<<3, himask, lomask, hitemp, lotemp);
return 1;
}
printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
return 1;
}
}
if (write != 0) {
/* base[i] = wmask; */
move64 (&wmask, (unsigned long long *) &(base[i]));
}
}
if ( write != 0 ) {
/* base[i] = wmask; */
move64 (&wmask, (unsigned long long *)&(base[i]));
}
}
return 0;
return 0;
}
#endif /* CFG_DRAM_TEST_WALK */
@ -480,43 +479,44 @@ int mem_march(volatile unsigned long long * base,
/* */
/* */
/*********************************************************************/
int mem_test_walk(void)
int mem_test_walk (void)
{
unsigned long long mask;
volatile unsigned long long * pmem =
(volatile unsigned long long *)CFG_SDRAM_BASE ;
const unsigned long size = (CFG_SDRAM_SIZE * 1024 * 1024)/8;
unsigned long long mask;
volatile unsigned long long *pmem =
(volatile unsigned long long *) CFG_SDRAM_BASE;
const unsigned long size = (CFG_SDRAM_SIZE * 1024 * 1024) / 8;
unsigned int i;
mask = 0x01;
unsigned int i;
printf("Initial Pass");
mem_march(pmem,size,0x0,0x1,0,1);
mask = 0x01;
printf("\b\b\b\b\b\b\b\b\b\b\b\b");
printf(" ");
printf("\b\b\b\b\b\b\b\b\b\b\b\b");
printf ("Initial Pass");
mem_march (pmem, size, 0x0, 0x1, 0, 1);
for (i = 0 ; i < 63 ; i++) {
printf("Pass %2d", i+2);
if ( mem_march(pmem,size, mask,mask << 1, 1, 1) != 0 ){
/*printf("mask: 0x%x, pass: %d, ", mask, i);*/
return 1;
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
printf (" ");
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
for (i = 0; i < 63; i++) {
printf ("Pass %2d", i + 2);
if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
/*printf("mask: 0x%x, pass: %d, ", mask, i); */
return 1;
}
mask = mask << 1;
printf ("\b\b\b\b\b\b\b");
}
mask = mask<<1;
printf("\b\b\b\b\b\b\b");
}
printf("Last Pass");
if (mem_march(pmem, size, 0, mask, 0, 1) != 0) {
/* printf("mask: 0x%x", mask); */
return 1;
}
printf("\b\b\b\b\b\b\b\b\b");
printf(" ");
printf("\b\b\b\b\b\b\b\b\b");
printf ("Last Pass");
if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
/* printf("mask: 0x%x", mask); */
return 1;
}
printf ("\b\b\b\b\b\b\b\b\b");
printf (" ");
printf ("\b\b\b\b\b\b\b\b\b");
return 0;
return 0;
}
/*********************************************************************/
@ -542,46 +542,46 @@ int mem_test_walk(void)
/* */
/* */
/*********************************************************************/
int testdram(void)
int testdram (void)
{
char *s;
int rundata, runaddress, runwalk;
char *s;
int rundata, runaddress, runwalk;
s = getenv ("testdramdata");
rundata = (s && (*s == 'y')) ? 1 : 0;
s = getenv ("testdramaddress");
runaddress = (s && (*s == 'y')) ? 1 : 0;
s = getenv ("testdramwalk");
runwalk = (s && (*s == 'y')) ? 1 : 0;
s = getenv ("testdramdata");
rundata = (s && (*s == 'y')) ? 1 : 0;
s = getenv ("testdramaddress");
runaddress = (s && (*s == 'y')) ? 1 : 0;
s = getenv ("testdramwalk");
runwalk = (s && (*s == 'y')) ? 1 : 0;
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf("Testing RAM ... ");
}
#ifdef CFG_DRAM_TEST_DATA
if (rundata == 1) {
if (mem_test_data() == 1){
return 1;
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf ("Testing RAM ... ");
}
#ifdef CFG_DRAM_TEST_DATA
if (rundata == 1) {
if (mem_test_data () == 1) {
return 1;
}
}
}
#endif
#ifdef CFG_DRAM_TEST_ADDRESS
if (runaddress == 1) {
if (mem_test_address() == 1){
return 1;
if (runaddress == 1) {
if (mem_test_address () == 1) {
return 1;
}
}
}
#endif
#ifdef CFG_DRAM_TEST_WALK
if (runwalk == 1) {
if (mem_test_walk() == 1){
return 1;
if (runwalk == 1) {
if (mem_test_walk () == 1) {
return 1;
}
}
}
#endif
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf("passed");
}
return 0;
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf ("passed");
}
return 0;
}
#endif /* CFG_DRAM_TEST */
@ -606,52 +606,52 @@ int testdram(void)
/* */
/* */
/*********************************************************************/
long int initdram(int board_type)
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar c = 0, *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);
ulong psdmr = CFG_PSDMR;
int i;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8);
ulong psdmr = CFG_PSDMR;
int i;
/*
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
*
* "At system reset, initialization software must set up the
* programmable parameters in the memory controller banks registers
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
* system software should execute the following initialization sequence
* for each SDRAM device.
*
* 1. Issue a PRECHARGE-ALL-BANKS command
* 2. Issue eight CBR REFRESH commands
* 3. Issue a MODE-SET command to initialize the mode register
*
* The initial commands are executed by setting P/LSDMR[OP] and
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
*/
/*
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
*
* "At system reset, initialization software must set up the
* programmable parameters in the memory controller banks registers
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
* system software should execute the following initialization sequence
* for each SDRAM device.
*
* 1. Issue a PRECHARGE-ALL-BANKS command
* 2. Issue eight CBR REFRESH commands
* 3. Issue a MODE-SET command to initialize the mode register
*
* The initial commands are executed by setting P/LSDMR[OP] and
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
*/
memctl->memc_psrt = CFG_PSRT;
memctl->memc_mptpr = CFG_MPTPR;
memctl->memc_psrt = CFG_PSRT;
memctl->memc_mptpr = CFG_MPTPR;
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
*ramaddr = c;
memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
for (i = 0; i < 8; i++){
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
*ramaddr = c;
}
memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
*ramaddr = c;
memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*ramaddr = c;
memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
for (i = 0; i < 8; i++) {
*ramaddr = c;
}
memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
*ramaddr = c;
/* return total ram size */
return (CFG_SDRAM0_SIZE * 1024 * 1024);
memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*ramaddr = c;
/* return total ram size */
return (CFG_SDRAM0_SIZE * 1024 * 1024);
}
/*********************************************************************/

2
board/m5272c3/Makefile
View File

@ -28,7 +28,7 @@ LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $^
$(AR) crv $@ $(OBJS)
#########################################################################

2
board/m5272c3/config.mk
View File

@ -22,4 +22,4 @@
# MA 02111-1307 USA
#
TEXT_BASE = 0x3e0000
TEXT_BASE = 0xffe00000

31
board/m5272c3/m5272c3.c
View File

@ -22,14 +22,31 @@
*/
#include <common.h>
#include <asm/m5272.h>
#include <asm/immap_5272.h>
int checkboard (void)
{
puts ("MOTOROLA MCF5272C3 Evaluation Board\n");
int checkboard (void) {
puts ("Board: ");
puts("MOTOROLA MCF5272C3 EVB\n");
return 0;
}
};
long int initdram (int board_type)
{
return 0x400000;
long int initdram (int board_type) {
volatile sdramctrl_t * sdp = (sdramctrl_t *)(CFG_MBAR + MCFSIM_SDCR);
sdp->sdram_sdtr = 0xf539;
sdp->sdram_sdcr = 0x4211;
/* Dummy write to start SDRAM */
*((volatile unsigned long *)0) = 0;
return CFG_SDRAM_SIZE * 1024 * 1024;
};
int testdram (void) {
/* TODO: XXX XXX XXX */
printf ("DRAM test not implemented!\n");
return (0);
}

27
board/m5272c3/u-boot.lds
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2003
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -22,7 +22,7 @@
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
@ -56,15 +56,14 @@ SECTIONS
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/coldfire/start.o (.text)
common/dlmalloc.o (.text)
lib_generic/string.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
cpu/mcf52x2/start.o (.text)
lib_m68k/traps.o (.text)
cpu/mcf52x2/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset; */
common/environment.o(.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
@ -85,9 +84,12 @@ SECTIONS
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
@ -108,6 +110,11 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;

130
board/m5272c3/u-boot.lds.debug
View File

@ -1,130 +0,0 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
ppc/vsprintf.o (.text)
ppc/crc32.o (.text)
. = env_offset;
common/environment.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

2
board/m5282evb/Makefile
View File

@ -28,7 +28,7 @@ LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $^
$(AR) crv $@ $(OBJS)
#########################################################################

2
board/m5282evb/config.mk
View File

@ -22,4 +22,4 @@
# MA 02111-1307 USA
#
TEXT_BASE = 0x3e0000
TEXT_BASE = 0x20000

12
board/m5282evb/u-boot.lds
View File

@ -22,7 +22,7 @@
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
@ -56,7 +56,7 @@ SECTIONS
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/coldfire/start.o (.text)
cpu/mcf52x2/start.o (.text)
common/dlmalloc.o (.text)
lib_generic/string.o (.text)
lib_generic/vsprintf.o (.text)
@ -85,9 +85,11 @@ SECTIONS
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
@ -108,6 +110,10 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;

130
board/m5282evb/u-boot.lds.debug
View File

@ -1,130 +0,0 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
ppc/vsprintf.o (.text)
ppc/crc32.o (.text)
. = env_offset;
common/environment.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

2
board/ppmc8260/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := ppmc8260.o strataflash.o
OBJS := ppmc8260.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)

364
board/siemens/IAD210/atm.h
View File

@ -1,9 +1,9 @@
typedef unsigned char uint8;
typedef unsigned char uint8;
typedef unsigned short uint16;
typedef unsigned int uint32;
typedef volatile unsigned char vuint8;
typedef unsigned int uint32;
typedef volatile unsigned char vuint8;
typedef volatile unsigned short vuint16;
typedef volatile unsigned int vuint32;
typedef volatile unsigned int vuint32;
#define DPRAM_ATM CFG_IMMR + 0x3000
@ -19,7 +19,7 @@ typedef volatile unsigned int vuint32;
#define NUM_AP_ENTRIES (NUM_CONNECTIONS+1)
#define NUM_MPHYPT_ENTRIES 1
#define NUM_APCP_ENTRIES 1
#define NUM_APCT_PRIO_1_ENTRIES 146 /* Determines minimum rate */
#define NUM_APCT_PRIO_1_ENTRIES 146 /* Determines minimum rate */
#define NUM_TQ_ENTRIES 12
#define SIZE_OF_CT_ENTRY 64
@ -31,16 +31,16 @@ typedef volatile unsigned int vuint32;
#define SIZE_OF_APCT_ENTRY 2
#define SIZE_OF_TQ_ENTRY 2
#define CT_BASE ((ATM_DPRAM_BEGIN + 63) & 0xFFC0) /*64*/
#define TCTE_BASE (CT_BASE + NUM_CT_ENTRIES * SIZE_OF_CT_ENTRY) /*32*/
#define APCP_BASE (TCTE_BASE + NUM_TCTE_ENTRIES * SIZE_OF_TCTE_ENTRY) /*32*/
#define AM_BEGIN (APCP_BASE + NUM_APCP_ENTRIES * SIZE_OF_APCP_ENTRY) /*4*/
#define CT_BASE ((ATM_DPRAM_BEGIN + 63) & 0xFFC0) /*64 */
#define TCTE_BASE (CT_BASE + NUM_CT_ENTRIES * SIZE_OF_CT_ENTRY) /*32 */
#define APCP_BASE (TCTE_BASE + NUM_TCTE_ENTRIES * SIZE_OF_TCTE_ENTRY) /*32 */
#define AM_BEGIN (APCP_BASE + NUM_APCP_ENTRIES * SIZE_OF_APCP_ENTRY) /*4 */
#define AM_BASE (AM_BEGIN + (NUM_AM_ENTRIES - 1) * SIZE_OF_AM_ENTRY)
#define AP_BEGIN (AM_BEGIN + NUM_AM_ENTRIES * SIZE_OF_AM_ENTRY) /*2*/
#define AP_BEGIN (AM_BEGIN + NUM_AM_ENTRIES * SIZE_OF_AM_ENTRY) /*2 */
#define AP_BASE (AP_BEGIN + (NUM_AP_ENTRIES - 1) * SIZE_OF_AP_ENTRY)
#define MPHYPT_BASE (AP_BEGIN + NUM_AP_ENTRIES * SIZE_OF_AP_ENTRY) /*2*/
#define APCT_PRIO_1_BASE (MPHYPT_BASE + NUM_MPHYPT_ENTRIES * SIZE_OF_MPHYPT_ENTRY) /*2*/
#define TQ_BASE (APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * SIZE_OF_APCT_ENTRY) /*2*/
#define MPHYPT_BASE (AP_BEGIN + NUM_AP_ENTRIES * SIZE_OF_AP_ENTRY) /*2 */
#define APCT_PRIO_1_BASE (MPHYPT_BASE + NUM_MPHYPT_ENTRIES * SIZE_OF_MPHYPT_ENTRY) /*2 */
#define TQ_BASE (APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * SIZE_OF_APCT_ENTRY) /*2 */
#define ATM_DPRAM_SIZE ((TQ_BASE + NUM_TQ_ENTRIES * SIZE_OF_TQ_ENTRY) - ATM_DPRAM_BEGIN)
#define CT_PTR(base) ((struct ct_entry_t *)((char *)(base) + 0x2000 + CT_BASE))
@ -55,62 +55,62 @@ typedef volatile unsigned int vuint32;
#define TQ_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + TQ_BASE))
/* SAR registers */
#define RBDBASE(base) ((vuint32 *)(base + 0x3F00)) /* Base address of RxBD-List */
#define SRFCR(base) ((vuint8 *)(base + 0x3F04)) /* DMA Receive function code */
#define SRSTATE(base) ((vuint8 *)(base + 0x3F05)) /* DMA Receive status */
#define MRBLR(base) ((vuint16 *)(base + 0x3F06)) /* Init to 0 for ATM */
#define RSTATE(base) ((vuint32 *)(base + 0x3F08)) /* Do not write to */
#define R_CNT(base) ((vuint16 *)(base + 0x3F10)) /* Do not write to */
#define STFCR(base) ((vuint8 *)(base + 0x3F12)) /* DMA Transmit function code */
#define STSTATE(base) ((vuint8 *)(base + 0x3F13)) /* DMA Transmit status */
#define TBDBASE(base) ((vuint32 *)(base + 0x3F14)) /* Base address of TxBD-List */
#define TSTATE(base) ((vuint32 *)(base + 0x3F18)) /* Do not write to */
#define COMM_CH(base) ((vuint16 *)(base + 0x3F1C)) /* Command channel */
#define STCHNUM(base) ((vuint16 *)(base + 0x3F1E)) /* Do not write to */
#define T_CNT(base) ((vuint16 *)(base + 0x3F20)) /* Do not write to */
#define CTBASE(base) ((vuint16 *)(base + 0x3F22)) /* Base address of Connection-table */
#define ECTBASE(base) ((vuint32 *)(base + 0x3F24)) /* Valid only for external Conn.-table */
#define INTBASE(base) ((vuint32 *)(base + 0x3F28)) /* Base address of Interrupt-table */
#define INTPTR(base) ((vuint32 *)(base + 0x3F2C)) /* Pointer to Interrupt-queue */
#define C_MASK(base) ((vuint32 *)(base + 0x3F30)) /* CRC-mask */
#define SRCHNUM(base) ((vuint16 *)(base + 0x3F34)) /* Do not write to */
#define INT_CNT(base) ((vuint16 *)(base + 0x3F36)) /* Interrupt-Counter */
#define INT_ICNT(base) ((vuint16 *)(base + 0x3F38)) /* Interrupt threshold */
#define TSTA(base) ((vuint16 *)(base + 0x3F3A)) /* Time-stamp-address */
#define OLDLEN(base) ((vuint16 *)(base + 0x3F3C)) /* Do not write to */
#define SMRBLR(base) ((vuint16 *)(base + 0x3F3E)) /* SAR max RXBuffer length */
#define EHEAD(base) ((vuint32 *)(base + 0x3F40)) /* Valid for serial mode */
#define EPAYLOAD(base) ((vuint32 *)(base + 0x3F44)) /* Valid for serial mode */
#define TQBASE(base) ((vuint16 *)(base + 0x3F48)) /* Base address of Tx queue */
#define TQEND(base) ((vuint16 *)(base + 0x3F4A)) /* End address of Tx queue */
#define TQAPTR(base) ((vuint16 *)(base + 0x3F4C)) /* TQ APC pointer */
#define TQTPTR(base) ((vuint16 *)(base + 0x3F4E)) /* TQ Tx pointer */
#define APCST(base) ((vuint16 *)(base + 0x3F50)) /* APC status */
#define APCPTR(base) ((vuint16 *)(base + 0x3F52)) /* APC parameter pointer */
#define HMASK(base) ((vuint32 *)(base + 0x3F54)) /* Header mask */
#define AMBASE(base) ((vuint16 *)(base + 0x3F58)) /* Address match table base */
#define AMEND(base) ((vuint16 *)(base + 0x3F5A)) /* Address match table end */
#define APBASE(base) ((vuint16 *)(base + 0x3F5C)) /* Address match parameter */
#define FLBASE(base) ((vuint32 *)(base + 0x3F54)) /* First-level table base */
#define SLBASE(base) ((vuint32 *)(base + 0x3F58)) /* Second-level table base */
#define FLMASK(base) ((vuint16 *)(base + 0x3F5C)) /* First-level mask */
#define ECSIZE(base) ((vuint16 *)(base + 0x3F5E)) /* Valid for extended mode */
#define APCT_REAL(base) ((vuint32 *)(base + 0x3F60)) /* APC 32 bit counter */
#define R_PTR(base) ((vuint32 *)(base + 0x3F64)) /* Do not write to */
#define RTEMP(base) ((vuint32 *)(base + 0x3F68)) /* Do not write to */
#define T_PTR(base) ((vuint32 *)(base + 0x3F6C)) /* Do not write to */
#define TTEMP(base) ((vuint32 *)(base + 0x3F70)) /* Do not write to */
#define RBDBASE(base) ((vuint32 *)(base + 0x3F00)) /* Base address of RxBD-List */
#define SRFCR(base) ((vuint8 *)(base + 0x3F04)) /* DMA Receive function code */
#define SRSTATE(base) ((vuint8 *)(base + 0x3F05)) /* DMA Receive status */
#define MRBLR(base) ((vuint16 *)(base + 0x3F06)) /* Init to 0 for ATM */
#define RSTATE(base) ((vuint32 *)(base + 0x3F08)) /* Do not write to */
#define R_CNT(base) ((vuint16 *)(base + 0x3F10)) /* Do not write to */
#define STFCR(base) ((vuint8 *)(base + 0x3F12)) /* DMA Transmit function code */
#define STSTATE(base) ((vuint8 *)(base + 0x3F13)) /* DMA Transmit status */
#define TBDBASE(base) ((vuint32 *)(base + 0x3F14)) /* Base address of TxBD-List */
#define TSTATE(base) ((vuint32 *)(base + 0x3F18)) /* Do not write to */
#define COMM_CH(base) ((vuint16 *)(base + 0x3F1C)) /* Command channel */
#define STCHNUM(base) ((vuint16 *)(base + 0x3F1E)) /* Do not write to */
#define T_CNT(base) ((vuint16 *)(base + 0x3F20)) /* Do not write to */
#define CTBASE(base) ((vuint16 *)(base + 0x3F22)) /* Base address of Connection-table */
#define ECTBASE(base) ((vuint32 *)(base + 0x3F24)) /* Valid only for external Conn.-table */
#define INTBASE(base) ((vuint32 *)(base + 0x3F28)) /* Base address of Interrupt-table */
#define INTPTR(base) ((vuint32 *)(base + 0x3F2C)) /* Pointer to Interrupt-queue */
#define C_MASK(base) ((vuint32 *)(base + 0x3F30)) /* CRC-mask */
#define SRCHNUM(base) ((vuint16 *)(base + 0x3F34)) /* Do not write to */
#define INT_CNT(base) ((vuint16 *)(base + 0x3F36)) /* Interrupt-Counter */
#define INT_ICNT(base) ((vuint16 *)(base + 0x3F38)) /* Interrupt threshold */
#define TSTA(base) ((vuint16 *)(base + 0x3F3A)) /* Time-stamp-address */
#define OLDLEN(base) ((vuint16 *)(base + 0x3F3C)) /* Do not write to */
#define SMRBLR(base) ((vuint16 *)(base + 0x3F3E)) /* SAR max RXBuffer length */
#define EHEAD(base) ((vuint32 *)(base + 0x3F40)) /* Valid for serial mode */
#define EPAYLOAD(base) ((vuint32 *)(base + 0x3F44)) /* Valid for serial mode */
#define TQBASE(base) ((vuint16 *)(base + 0x3F48)) /* Base address of Tx queue */
#define TQEND(base) ((vuint16 *)(base + 0x3F4A)) /* End address of Tx queue */
#define TQAPTR(base) ((vuint16 *)(base + 0x3F4C)) /* TQ APC pointer */
#define TQTPTR(base) ((vuint16 *)(base + 0x3F4E)) /* TQ Tx pointer */
#define APCST(base) ((vuint16 *)(base + 0x3F50)) /* APC status */
#define APCPTR(base) ((vuint16 *)(base + 0x3F52)) /* APC parameter pointer */
#define HMASK(base) ((vuint32 *)(base + 0x3F54)) /* Header mask */
#define AMBASE(base) ((vuint16 *)(base + 0x3F58)) /* Address match table base */
#define AMEND(base) ((vuint16 *)(base + 0x3F5A)) /* Address match table end */
#define APBASE(base) ((vuint16 *)(base + 0x3F5C)) /* Address match parameter */
#define FLBASE(base) ((vuint32 *)(base + 0x3F54)) /* First-level table base */
#define SLBASE(base) ((vuint32 *)(base + 0x3F58)) /* Second-level table base */
#define FLMASK(base) ((vuint16 *)(base + 0x3F5C)) /* First-level mask */
#define ECSIZE(base) ((vuint16 *)(base + 0x3F5E)) /* Valid for extended mode */
#define APCT_REAL(base) ((vuint32 *)(base + 0x3F60)) /* APC 32 bit counter */
#define R_PTR(base) ((vuint32 *)(base + 0x3F64)) /* Do not write to */
#define RTEMP(base) ((vuint32 *)(base + 0x3F68)) /* Do not write to */
#define T_PTR(base) ((vuint32 *)(base + 0x3F6C)) /* Do not write to */
#define TTEMP(base) ((vuint32 *)(base + 0x3F70)) /* Do not write to */
/* ESAR registers */
#define FMCTIMESTMP(base) ((vuint32 *)(base + 0x3F80)) /* Perf.Mon.Timestamp */
#define FMCTEMPLATE(base) ((vuint32 *)(base + 0x3F84)) /* Perf.Mon.Template */
#define PMPTR(base) ((vuint16 *)(base + 0x3F88)) /* Perf.Mon.Table */
#define PMCHANNEL(base) ((vuint16 *)(base + 0x3F8A)) /* Perf.Mon.Channel */
#define MPHYST(base) ((vuint16 *)(base + 0x3F90)) /* Multi-PHY Status */
#define TCTEBASE(base) ((vuint16 *)(base + 0x3F92)) /* Internal TCT Extension Base */
#define ETCTEBASE(base) ((vuint32 *)(base + 0x3F94)) /* External TCT Extension Base */
#define COMM_CH2(base) ((vuint32 *)(base + 0x3F98)) /* 2nd command channel word */
#define STATBASE(base) ((vuint16 *)(base + 0x3F9C)) /* Statistics table pointer */
#define FMCTIMESTMP(base) ((vuint32 *)(base + 0x3F80)) /* Perf.Mon.Timestamp */
#define FMCTEMPLATE(base) ((vuint32 *)(base + 0x3F84)) /* Perf.Mon.Template */
#define PMPTR(base) ((vuint16 *)(base + 0x3F88)) /* Perf.Mon.Table */
#define PMCHANNEL(base) ((vuint16 *)(base + 0x3F8A)) /* Perf.Mon.Channel */
#define MPHYST(base) ((vuint16 *)(base + 0x3F90)) /* Multi-PHY Status */
#define TCTEBASE(base) ((vuint16 *)(base + 0x3F92)) /* Internal TCT Extension Base */
#define ETCTEBASE(base) ((vuint32 *)(base + 0x3F94)) /* External TCT Extension Base */
#define COMM_CH2(base) ((vuint32 *)(base + 0x3F98)) /* 2nd command channel word */
#define STATBASE(base) ((vuint16 *)(base + 0x3F9C)) /* Statistics table pointer */
/* UTOPIA Mode Register */
#define UTMODE(base) (CAST(vuint32 *)(base + 0x0978))
@ -139,108 +139,104 @@ typedef volatile unsigned int vuint32;
#define NUM_INT_ENTRIES 80
#define SIZE_OF_INT_ENTRY 4
struct apc_params_t
{
vuint16 apct_base1; /* APC Table - First Priority Base pointer */
vuint16 apct_end1; /* First APC Table - Length */
vuint16 apct_ptr1; /* First APC Table Pointer */
vuint16 apct_sptr1; /* APC Table First Priority Service pointer */
vuint16 etqbase; /* Enhanced Transmit Queue Base pointer */
vuint16 etqend; /* Enhanced Transmit Queue End pointer */
vuint16 etqaptr; /* Enhanced Transmit Queue APC pointer */
vuint16 etqtptr; /* Enhanced Transmit Queue Transmitter pointer */
vuint16 apc_mi; /* APC - Max Iteration */
vuint16 ncits; /* Number of Cells In TimeSlot */
vuint16 apcnt; /* APC - N Timer */
vuint16 reserved1; /* reserved */
vuint16 eapcst; /* APC status */
vuint16 ptp_counter; /* PTP queue length */
vuint16 ptp_txch; /* PTP channel */
vuint16 reserved2; /* reserved */
struct apc_params_t {
vuint16 apct_base1; /* APC Table - First Priority Base pointer */
vuint16 apct_end1; /* First APC Table - Length */
vuint16 apct_ptr1; /* First APC Table Pointer */
vuint16 apct_sptr1; /* APC Table First Priority Service pointer */
vuint16 etqbase; /* Enhanced Transmit Queue Base pointer */
vuint16 etqend; /* Enhanced Transmit Queue End pointer */
vuint16 etqaptr; /* Enhanced Transmit Queue APC pointer */
vuint16 etqtptr; /* Enhanced Transmit Queue Transmitter pointer */
vuint16 apc_mi; /* APC - Max Iteration */
vuint16 ncits; /* Number of Cells In TimeSlot */
vuint16 apcnt; /* APC - N Timer */
vuint16 reserved1; /* reserved */
vuint16 eapcst; /* APC status */
vuint16 ptp_counter; /* PTP queue length */
vuint16 ptp_txch; /* PTP channel */
vuint16 reserved2; /* reserved */
};
struct ct_entry_t
{
/* RCT */
unsigned fhnt : 1;
unsigned pm_rct : 1;
unsigned reserved0 : 6;
unsigned hec : 1;
unsigned clp : 1;
unsigned cng_ncrc : 1;
unsigned inf_rct : 1;
unsigned cngi_ptp : 1;
unsigned cdis_rct : 1;
unsigned aal_rct : 2;
uint16 rbalen;
uint32 rcrc;
uint32 rb_ptr;
uint16 rtmlen;
uint16 rbd_ptr;
uint16 rbase;
uint16 tstamp;
uint16 imask;
unsigned ft : 2;
unsigned nim : 1;
unsigned reserved1 : 2;
unsigned rpmt : 6;
unsigned reserved2 : 5;
uint8 reserved3[8];
/* TCT */
unsigned reserved4 : 1;
unsigned pm_tct : 1;
unsigned reserved5 : 6;
unsigned pc : 1;
unsigned reserved6 : 2;
unsigned inf_tct : 1;
unsigned cr10 : 1;
unsigned cdis_tct : 1;
unsigned aal_tct : 2;
uint16 tbalen;
uint32 tcrc;
uint32 tb_ptr;
uint16 ttmlen;
uint16 tbd_ptr;
uint16 tbase;
unsigned reserved7 : 5;
unsigned tpmt : 6;
unsigned reserved8 : 3;
unsigned avcf : 1;
unsigned act : 1;
uint32 chead;
uint16 apcl;
uint16 apcpr;
unsigned out : 1;
unsigned bnr : 1;
unsigned tservice : 2;
unsigned apcp : 12;
uint16 apcpf;
struct ct_entry_t {
/* RCT */
unsigned fhnt:1;
unsigned pm_rct:1;
unsigned reserved0:6;
unsigned hec:1;
unsigned clp:1;
unsigned cng_ncrc:1;
unsigned inf_rct:1;
unsigned cngi_ptp:1;
unsigned cdis_rct:1;
unsigned aal_rct:2;
uint16 rbalen;
uint32 rcrc;
uint32 rb_ptr;
uint16 rtmlen;
uint16 rbd_ptr;
uint16 rbase;
uint16 tstamp;
uint16 imask;
unsigned ft:2;
unsigned nim:1;
unsigned reserved1:2;
unsigned rpmt:6;
unsigned reserved2:5;
uint8 reserved3[8];
/* TCT */
unsigned reserved4:1;
unsigned pm_tct:1;
unsigned reserved5:6;
unsigned pc:1;
unsigned reserved6:2;
unsigned inf_tct:1;
unsigned cr10:1;
unsigned cdis_tct:1;
unsigned aal_tct:2;
uint16 tbalen;
uint32 tcrc;
uint32 tb_ptr;
uint16 ttmlen;
uint16 tbd_ptr;
uint16 tbase;
unsigned reserved7:5;
unsigned tpmt:6;
unsigned reserved8:3;
unsigned avcf:1;
unsigned act:1;
uint32 chead;
uint16 apcl;
uint16 apcpr;
unsigned out:1;
unsigned bnr:1;
unsigned tservice:2;
unsigned apcp:12;
uint16 apcpf;
};
struct tcte_entry_t
{
unsigned res1 : 4;
unsigned scr : 12;
uint16 scrf;
uint16 bt;
uint16 buptrh;
uint32 buptrl;
unsigned vbr2 : 1;
unsigned res2 : 15;
uint16 oobr;
uint16 res3[8];
struct tcte_entry_t {
unsigned res1:4;
unsigned scr:12;
uint16 scrf;
uint16 bt;
uint16 buptrh;
uint32 buptrl;
unsigned vbr2:1;
unsigned res2:15;
uint16 oobr;
uint16 res3[8];
};
#define SIZE_OF_RBD 12
#define SIZE_OF_TBD 12
struct atm_bd_t
{
vuint16 flags;
vuint16 length;
unsigned char * buffer_ptr;
vuint16 cpcs_uu_cpi;
vuint16 reserved;
struct atm_bd_t {
vuint16 flags;
vuint16 length;
unsigned char *buffer_ptr;
vuint16 cpcs_uu_cpi;
vuint16 reserved;
};
/* BD flags */
@ -259,35 +255,33 @@ struct atm_bd_t
#define LEN_ERROR 0x0002
#define CRC_ERROR 0x0001
struct atm_connection_t
{
struct atm_bd_t * rbd_ptr;
int num_rbd;
struct atm_bd_t * tbd_ptr;
int num_tbd;
struct ct_entry_t * ct_ptr;
struct tcte_entry_t * tcte_ptr;
void * drv;
void (* notify)(void * drv, int event);
struct atm_connection_t {
struct atm_bd_t *rbd_ptr;
int num_rbd;
struct atm_bd_t *tbd_ptr;
int num_tbd;
struct ct_entry_t *ct_ptr;
struct tcte_entry_t *tcte_ptr;
void *drv;
void (*notify) (void *drv, int event);
};
struct atm_driver_t
{
int loaded;
int started;
char * csram;
int csram_size;
uint32 * am_top;
uint16 * ap_top;
uint32 * int_reload_ptr;
uint32 * int_serv_ptr;
struct atm_bd_t * rbd_base_ptr;
struct atm_bd_t * tbd_base_ptr;
unsigned linerate_in_bps;
struct atm_driver_t {
int loaded;
int started;
char *csram;
int csram_size;
uint32 *am_top;
uint16 *ap_top;
uint32 *int_reload_ptr;
uint32 *int_serv_ptr;
struct atm_bd_t *rbd_base_ptr;
struct atm_bd_t *tbd_base_ptr;
unsigned linerate_in_bps;
};
extern struct atm_connection_t g_conn[NUM_CONNECTIONS];
extern struct atm_driver_t g_atm;
extern int atmLoad(void);
extern void atmUnload(void);
extern int atmLoad (void);
extern void atmUnload (void);

118
board/siemens/SCM/fpga_scm.c
View File

@ -28,77 +28,77 @@
#include "../common/fpga.h"
fpga_t fpga_list[] = {
{ "FIOX" , CFG_FIOX_BASE ,
CFG_PD_FIOX_INIT , CFG_PD_FIOX_PROG , CFG_PD_FIOX_DONE },
{ "FDOHM", CFG_FDOHM_BASE,
CFG_PD_FDOHM_INIT, CFG_PD_FDOHM_PROG, CFG_PD_FDOHM_DONE }
{"FIOX", CFG_FIOX_BASE,
CFG_PD_FIOX_INIT, CFG_PD_FIOX_PROG, CFG_PD_FIOX_DONE}
,
{"FDOHM", CFG_FDOHM_BASE,
CFG_PD_FDOHM_INIT, CFG_PD_FDOHM_PROG, CFG_PD_FDOHM_DONE}
};
int fpga_count = sizeof(fpga_list) / sizeof(fpga_t);
int fpga_count = sizeof (fpga_list) / sizeof (fpga_t);
ulong fpga_control (fpga_t* fpga, int cmd)
ulong fpga_control (fpga_t * fpga, int cmd)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
switch (cmd) {
case FPGA_INIT_IS_HIGH:
immr->im_ioport.iop_pdird &= ~fpga->init_mask; /* input */
return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1:0;
switch (cmd) {
case FPGA_INIT_IS_HIGH:
immr->im_ioport.iop_pdird &= ~fpga->init_mask; /* input */
return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1 : 0;
case FPGA_INIT_SET_LOW:
immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
immr->im_ioport.iop_pdatd &= ~fpga->init_mask;
break;
case FPGA_INIT_SET_LOW:
immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
immr->im_ioport.iop_pdatd &= ~fpga->init_mask;
break;
case FPGA_INIT_SET_HIGH:
immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
immr->im_ioport.iop_pdatd |= fpga->init_mask;
break;
case FPGA_INIT_SET_HIGH:
immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
immr->im_ioport.iop_pdatd |= fpga->init_mask;
break;
case FPGA_PROG_SET_LOW:
immr->im_ioport.iop_pdatd &= ~fpga->prog_mask;
break;
case FPGA_PROG_SET_LOW:
immr->im_ioport.iop_pdatd &= ~fpga->prog_mask;
break;
case FPGA_PROG_SET_HIGH:
immr->im_ioport.iop_pdatd |= fpga->prog_mask;
break;
case FPGA_PROG_SET_HIGH:
immr->im_ioport.iop_pdatd |= fpga->prog_mask;
break;
case FPGA_DONE_IS_HIGH:
return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1:0;
case FPGA_DONE_IS_HIGH:
return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1 : 0;
case FPGA_READ_MODE:
break;
case FPGA_READ_MODE:
break;
case FPGA_LOAD_MODE:
break;
case FPGA_LOAD_MODE:
break;
case FPGA_GET_ID:
if (fpga->conf_base == CFG_FIOX_BASE) {
ulong ver =
*(volatile ulong *) (fpga->conf_base + 0x10);
return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0);
} else if (fpga->conf_base == CFG_FDOHM_BASE) {
return (*(volatile ushort *) fpga->conf_base) & 0xff;
} else {
return *(volatile ulong *) fpga->conf_base;
}
case FPGA_INIT_PORTS:
immr->im_ioport.iop_ppard &= ~fpga->init_mask; /* INIT I/O */
immr->im_ioport.iop_psord &= ~fpga->init_mask;
immr->im_ioport.iop_pdird &= ~fpga->init_mask;
immr->im_ioport.iop_ppard &= ~fpga->prog_mask; /* PROG Output */
immr->im_ioport.iop_psord &= ~fpga->prog_mask;
immr->im_ioport.iop_pdird |= fpga->prog_mask;
immr->im_ioport.iop_ppard &= ~fpga->done_mask; /* DONE Input */
immr->im_ioport.iop_psord &= ~fpga->done_mask;
immr->im_ioport.iop_pdird &= ~fpga->done_mask;
break;
case FPGA_GET_ID:
if (fpga->conf_base == CFG_FIOX_BASE) {
ulong ver = *(volatile ulong *)(fpga->conf_base + 0x10);
return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0);
}
else if (fpga->conf_base == CFG_FDOHM_BASE) {
return (*(volatile ushort *)fpga->conf_base) & 0xff;
}
else {
return *(volatile ulong *)fpga->conf_base;
}
case FPGA_INIT_PORTS:
immr->im_ioport.iop_ppard &= ~fpga->init_mask; /* INIT I/O */
immr->im_ioport.iop_psord &= ~fpga->init_mask;
immr->im_ioport.iop_pdird &= ~fpga->init_mask;
immr->im_ioport.iop_ppard &= ~fpga->prog_mask; /* PROG Output */
immr->im_ioport.iop_psord &= ~fpga->prog_mask;
immr->im_ioport.iop_pdird |= fpga->prog_mask;
immr->im_ioport.iop_ppard &= ~fpga->done_mask; /* DONE Input */
immr->im_ioport.iop_psord &= ~fpga->done_mask;
immr->im_ioport.iop_pdird &= ~fpga->done_mask;
break;
}
return 0;
return 0;
}

2
common/cmd_mii.c
View File

@ -54,7 +54,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
unsigned short data;
int rcode = 0;
#ifdef CONFIG_8xx
#if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2)
mii_init ();
#endif

87
cpu/coldfire/cpu.c
View File

@ -1,87 +0,0 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#ifdef CONFIG_M5272
#include <asm/m5272.h>
#endif
#ifdef CONFIG_M5282
#include <asm/m5282.h>
#endif
#include <asm/cache.h>
int do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
return 0;
}
unsigned long get_tbclk (void)
{
return CFG_HZ;
}
int checkcpu (void)
{
#ifdef CONFIG_M5272
puts ("MOTOROLA Coldfire MCF5272\n");
#endif
#ifdef CONFIG_M5282
puts ("MOTOROLA Coldfire MCF5282\n");
#endif
return 0;
}
void do_exception (void)
{
printf ("\n\n*** Unexpected exception ... Reset Board! ***\n");
for (;;);
}
void do_buserror (void)
{
printf ("\n\n*** Bus error ... Reset Board! ***\n");
for (;;);
}
void do_addresserror (void)
{
printf ("\n\n*** Address error ... Reset Board! ***\n");
for (;;);
}
void trap_init (ulong value)
{
extern void buserror_handler (void);
extern void addresserror_handler (void);
extern void exception_handler (void);
unsigned long *vec = 0;
int i;
vec[2] = buserror_handler;
vec[3] = addresserror_handler;
for (i = 4; i < 256; i++) {
vec[i] = exception_handler;
}
}

296
cpu/coldfire/fec.c
View File

@ -1,296 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <commproc.h>
#include <net.h>
#include <command.h>
/**************************************************************
*
* FEC Ethernet Initialization Routine
*
*************************************************************/
#define FEC_ECNTRL_ETHER_EN 0x00000002
#define FEC_ECNTRL_RESET 0x00000001
#define FEC_RCNTRL_BC_REJ 0x00000010
#define FEC_RCNTRL_PROM 0x00000008
#define FEC_RCNTRL_MII_MODE 0x00000004
#define FEC_RCNTRL_DRT 0x00000002
#define FEC_RCNTRL_LOOP 0x00000001
#define FEC_TCNTRL_FDEN 0x00000004
#define FEC_TCNTRL_HBC 0x00000002
#define FEC_TCNTRL_GTS 0x00000001
#define FEC_RESET_DELAY 50000
/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH 1520
#define TX_BUF_CNT 2
#define TOUT_LOOP 100
#define PKT_MAXBUF_SIZE 1518
#define PKT_MINBUF_SIZE 64
#define PKT_MAXBLR_SIZE 1520
#ifdef CONFIG_M5272
#define FEC_ADDR 0x10000840
#endif
#ifdef CONFIG_M5282
#define FEC_ADDR 0x40001000
#endif
#undef ET_DEBUG
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
static char txbuf[DBUF_LENGTH];
static uint rxIdx; /* index of the current RX buffer */
static uint txIdx; /* index of the current TX buffer */
/*
* FEC Ethernet Tx and Rx buffer descriptors allocated at the
* immr->udata_bd address on Dual-Port RAM
* Provide for Double Buffering
*/
typedef volatile struct CommonBufferDescriptor {
cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
} RTXBD;
static RTXBD *rtx = 0x380000;
int eth_send (volatile void *packet, int length)
{
int j, rc;
volatile fec_t *fecp = FEC_ADDR;
/* section 16.9.23.3
* Wait for ready
*/
j = 0;
while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
&& (j < TOUT_LOOP)) {
udelay (1);
j++;
}
if (j >= TOUT_LOOP) {
printf ("TX not ready\n");
}
rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
rtx->txbd[txIdx].cbd_datlen = length;
rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
/* Activate transmit Buffer Descriptor polling */
fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
j = 0;
while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
&& (j < TOUT_LOOP)) {
udelay (1);
j++;
}
if (j >= TOUT_LOOP) {
printf ("TX timeout\n");
}
#ifdef ET_DEBUG
printf ("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
__FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc,
(rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2);
#endif
/* return only status bits */ ;
rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
txIdx = (txIdx + 1) % TX_BUF_CNT;
return rc;
}
int eth_rx (void)
{
int length;
volatile fec_t *fecp = FEC_ADDR;
for (;;) {
/* section 16.9.23.2 */
if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
length = -1;
break; /* nothing received - leave for() loop */
}
length = rtx->rxbd[rxIdx].cbd_datlen;
if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
#ifdef ET_DEBUG
printf ("%s[%d] err: %x\n",
__FUNCTION__, __LINE__,
rtx->rxbd[rxIdx].cbd_sc);
#endif
} else {
/* Pass the packet up to the protocol layers. */
NetReceive (NetRxPackets[rxIdx], length - 4);
}
/* Give the buffer back to the FEC. */
rtx->rxbd[rxIdx].cbd_datlen = 0;
/* wrap around buffer index when necessary */
if ((rxIdx + 1) >= PKTBUFSRX) {
rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
rxIdx = 0;
} else {
rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
rxIdx++;
}
/* Try to fill Buffer Descriptors */
fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
}
return length;
}
int eth_init (bd_t * bd)
{
int i;
volatile fec_t *fecp = FEC_ADDR;
/* Whack a reset.
* A delay is required between a reset of the FEC block and
* initialization of other FEC registers because the reset takes
* some time to complete. If you don't delay, subsequent writes
* to FEC registers might get killed by the reset routine which is
* still in progress.
*/
fecp->fec_ecntrl = FEC_ECNTRL_RESET;
for (i = 0;
(fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
++i) {
udelay (1);
}
if (i == FEC_RESET_DELAY) {
printf ("FEC_RESET_DELAY timeout\n");
return 0;
}
/* We use strictly polling mode only
*/
fecp->fec_imask = 0;
/* Clear any pending interrupt */
fecp->fec_ievent = 0xffffffff;
/* Set station address */
#define ea bd->bi_enetaddr
fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) |
(ea[2] << 8) | (ea[3]);
fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16);
#undef ea
/* Clear multicast address hash table
*/
fecp->fec_hash_table_high = 0;
fecp->fec_hash_table_low = 0;
/* Set maximum receive buffer size.
*/
fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
/*
* Setup Buffers and Buffer Desriptors
*/
rxIdx = 0;
txIdx = 0;
/*
* Setup Receiver Buffer Descriptors (13.14.24.18)
* Settings:
* Empty, Wrap
*/
for (i = 0; i < PKTBUFSRX; i++) {
rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
rtx->rxbd[i].cbd_datlen = 0; /* Reset */
rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
}
rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
/*
* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
* Settings:
* Last, Tx CRC
*/
for (i = 0; i < TX_BUF_CNT; i++) {
rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
rtx->txbd[i].cbd_datlen = 0; /* Reset */
rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
}
rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
/* Set receive and transmit descriptor base
*/
fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
/* Enable MII mode
*/
/* Half duplex mode */
fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16) | FEC_RCNTRL_MII_MODE;
fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16) | FEC_RCNTRL_MII_MODE;
fecp->fec_x_cntrl = 0;
fecp->fec_mii_speed = 0;
/* Now enable the transmit and receive processing
*/
fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
/* And last, try to fill Rx Buffer Descriptors */
fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
return 1;
}
void eth_halt (void)
{
volatile fec_t *fecp = FEC_ADDR;
fecp->fec_ecntrl = 0;
}
#endif

127
cpu/coldfire/interrupts.c
View File

@ -1,127 +0,0 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#ifdef CONFIG_M5272
#include <asm/m5272.h>
#endif
#ifdef CONFIG_M5282
#include <asm/m5282.h>
#endif
#include <asm/mcftimer.h>
#include <asm/processor.h>
#include <commproc.h>
static ulong timestamp;
static unsigned short lastinc;
void coldfire_timer_init (void)
{
volatile unsigned short *timerp;
timerp = (volatile unsigned short *) (MCF_MBAR + MCFTIMER_BASE4);
timestamp = 0;
#ifdef CONFIG_M5272
/* Set up TIMER 4 as poll clock */
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_DISABLE;
timerp[MCFTIMER_TRR] = lastinc = 0;
timerp[MCFTIMER_TMR] = (65 << 8) | MCFTIMER_TMR_CLK1 |
MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE;
#endif
#ifdef CONFIG_M5282
/* Set up TIMER 4 as poll clock */
timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
timerp[MCFTIMER_PMR] = lastinc = 0;
timerp[MCFTIMER_PCSR] =
(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
#endif
}
void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
{
}
void irq_free_handler (int vec)
{
}
int interrupt_init (void)
{
coldfire_timer_init ();
return 0;
}
void enable_interrupts ()
{
}
int disable_interrupts ()
{
return 0;
}
void set_timer (ulong t)
{
volatile unsigned short *timerp;
timerp = (volatile unsigned short *) (MCF_MBAR + MCFTIMER_BASE4);
timestamp = 0;
#ifdef CONFIG_M5272
timerp[MCFTIMER_TRR] = lastinc = 0;
#endif
#ifdef CONFIG_M5282
timerp[MCFTIMER_PMR] = lastinc = 0;
#endif
}
ulong get_timer (ulong base)
{
unsigned short now, diff;
volatile unsigned short *timerp;
timerp = (volatile unsigned short *) (MCF_MBAR + MCFTIMER_BASE4);
#ifdef CONFIG_M5272
now = timerp[MCFTIMER_TCN];
diff = (now - lastinc);
#endif
#ifdef CONFIG_M5282
now = timerp[MCFTIMER_PCNTR];
diff = -(now - lastinc);
#endif
timestamp += diff;
lastinc = now;
return timestamp - base;
}
void wait_ticks (unsigned long ticks)
{
set_timer (0);
while (get_timer (0) < ticks);
}

168
cpu/coldfire/serial.c
View File

@ -1,168 +0,0 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <commproc.h>
#include <command.h>
#ifdef CONFIG_M5272
#include <asm/m5272.h>
#endif
#ifdef CONFIG_M5282
#include <asm/m5282.h>
#endif
#include <asm/mcfuart.h>
#define DoubleClock(a) ((double)(MCF_CLK) / 32.0 / (double)(a))
void rs_serial_setbaudrate (int port, int baudrate)
{
#ifdef CONFIG_M5272
volatile unsigned char *uartp;
double clock, fraction;
if (port == 0)
uartp = (volatile unsigned char *) (MCF_MBAR + MCFUART_BASE1);
else
uartp = (volatile unsigned char *) (MCF_MBAR + MCFUART_BASE2);
clock = DoubleClock (baudrate); /* Set baud above */
fraction = ((clock - (int) clock) * 16.0) + 0.5;
uartp[MCFUART_UBG1] = (((int) clock >> 8) & 0xff); /* set msb baud */
uartp[MCFUART_UBG2] = ((int) clock & 0xff); /* set lsb baud */
uartp[MCFUART_UFPD] = ((int) fraction & 0xf); /* set baud fraction adjust */
#endif
}
void rs_serial_init (int port, int baudrate)
{
volatile unsigned char *uartp;
double clock, fraction;
/*
* Reset UART, get it into known state...
*/
if (port == 0)
uartp = (volatile unsigned char *) (MCF_MBAR + MCFUART_BASE1);
else
uartp = (volatile unsigned char *) (MCF_MBAR + MCFUART_BASE2);
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */
/*
* Set port for CONSOLE_BAUD_RATE, 8 data bits, 1 stop bit, no parity.
*/
uartp[MCFUART_UMR] = MCFUART_MR1_PARITYNONE | MCFUART_MR1_CS8;
uartp[MCFUART_UMR] = MCFUART_MR2_STOP1;
rs_serial_setbaudrate (port, baudrate);
uartp[MCFUART_UCSR] =
MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER;
uartp[MCFUART_UCR] = MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE;
return;
}
/****************************************************************************/
/*
* Output a single character, using UART polled mode.
* This is used for console output.
*/
void rs_put_char (char ch)
{
volatile unsigned char *uartp;
int i;
uartp = (volatile unsigned char *) (MCF_MBAR + MCFUART_BASE1);
for (i = 0; (i < 0x10000); i++) {
if (uartp[MCFUART_USR] & MCFUART_USR_TXREADY)
break;
}
uartp[MCFUART_UTB] = ch;
return;
}
int rs_is_char (void)
{
volatile unsigned char *uartp;
uartp = (volatile unsigned char *) (MCF_MBAR + MCFUART_BASE1);
return ((uartp[MCFUART_USR] & MCFUART_USR_RXREADY) ? 1 : 0);
}
int rs_get_char (void)
{
volatile unsigned char *uartp;
uartp = (volatile unsigned char *) (MCF_MBAR + MCFUART_BASE1);
return (uartp[MCFUART_URB]);
}
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
rs_serial_setbaudrate (0, gd->bd->bi_baudrate);
}
int serial_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
rs_serial_init (0, gd->bd->bi_baudrate);
return 0;
}
void serial_putc (const char c)
{
if (c == '\n')
serial_putc ('\r');
rs_put_char (c);
}
void serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
int serial_getc (void)
{
while (!rs_is_char ());
return rs_get_char ();
}
int serial_tstc ()
{
return rs_is_char ();
}

165
cpu/coldfire/start.S
View File

@ -1,165 +0,0 @@
/*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000-2003 Wolfgang Denk <wd@denx.de>
* Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include "version.h"
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
#endif
#define MCF_MBAR 0x10000000
#define MEM_BUILTIN_ADDR 0x20000000
#define MEM_BUILTIN_SIZE 0x1000
#define DRAM_ADDR 0x0
#define DRAM_SIZE 0x400000
.text
.globl _start
_start:
nop
nop
move.w #0x2700,%sr
move.l #0, %d0
movec %d0, %VBR
#ifdef CONFIG_M5272
move.l #(MCF_MBAR+1), %d0
move.c %d0, %MBAR
move.l #(MEM_BUILTIN_ADDR+1), %d0
movec %d0, %RAMBAR0
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #0x0000c000, %d0 /* Setup cache mask */
movec %d0, %ACR0 /* Enable cache */
move.l #0xff00c000, %d0 /* Setup cache mask */
movec %d0, %ACR1 /* Enable cache */
move.l #0x80000100, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
#endif
move.l #_sbss,%a0
move.l #_ebss,%d0
1:
clr.l (%a0)+
cmp.l %a0,%d0
bne.s 1b
/* move.l #MEM_BUILTIN_ADDR+MEM_BUILTIN_SIZE, %sp */
move.l #DRAM_ADDR+DRAM_SIZE, %sp
clr.l %sp@-
jsr board_init_f
.globl exception_handler
exception_handler:
move.w #0x2700,%sr
lea %sp@(-60),%sp
movem.l %d0-%d7/%a0-%a6,%sp@
jsr do_exception
movem.l %sp@,%d0-%d7/%a0-%a6
lea %sp@(60),%sp
rte
.globl buserror_handler
buserror_handler:
move.w #0x2700,%sr
lea %sp@(-60),%sp
movem.l %d0-%d7/%a0-%a6,%sp@
jsr do_buserror
movem.l %sp@,%d0-%d7/%a0-%a6
lea %sp@(60),%sp
rte
.globl addresserror_handler
addresserror_handler:
move.w #0x2700,%sr
lea %sp@(-60),%sp
movem.l %d0-%d7/%a0-%a6,%sp@
jsr do_buserror
movem.l %sp@,%d0-%d7/%a0-%a6
lea %sp@(60),%sp
rte
.globl get_endaddr
get_endaddr:
movel #_end,%d0
rts
#ifdef CONFIG_M5272
.globl icache_enable
icache_enable:
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #0x0000c000, %d0 /* Setup cache mask */
movec %d0, %ACR0 /* Enable cache */
move.l #0xff00c000, %d0 /* Setup cache mask */
movec %d0, %ACR1 /* Enable cache */
move.l #0x80000100, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
moveq #1, %d0
move.l %d0, icache_state
rts
.globl icache_disable
icache_disable:
move.l #0x00000100, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
clr.l %d0 /* Setup cache mask */
movec %d0, %ACR0 /* Enable cache */
movec %d0, %ACR1 /* Enable cache */
moveq #0, %d0
move.l %d0, icache_state
rts
#endif
#ifdef CONFIG_M5282
.globl icache_enable
icache_enable:
rts
.globl icache_disable
icache_disable:
rts
#endif
.globl icache_status
icache_status:
move.l icache_state, %d0
rts
.data
icache_state:
.long 1
.globl version_string
version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"

6
cpu/coldfire/Makefile → cpu/mcf52x2/Makefile
View File

@ -1,5 +1,5 @@
#
# (C) Copyright 2000-2003
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@ -28,12 +28,12 @@ include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
START =
OBJS = kgdb.o serial.o interrupts.o cpu.o speed.o cpu_init.o fec.o
OBJS = serial.o interrupts.o cpu.o speed.o cpu_init.o fec.o
all: .depend $(START) $(LIB)
$(LIB): $(OBJS)
$(AR) crv $@ $(OBJS) kgdb.o
$(AR) crv $@ $(OBJS)
#########################################################################

9
cpu/coldfire/config.mk → cpu/mcf52x2/config.mk
View File

@ -1,5 +1,7 @@
#
# (C) Copyright 2000-2003
# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@ -21,6 +23,5 @@
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS +=
PLATFORM_CPPFLAGS += -m5200
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
PLATFORM_CPPFLAGS += -m5307

123
cpu/mcf52x2/cpu.c Normal file
View File

@ -0,0 +1,123 @@
/*
* (C) Copyright 2003
* Josef Baumgartner <josef.baumgartner@telex.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#ifdef CONFIG_M5272
#include <asm/immap_5272.h>
#include <asm/m5272.h>
#endif
#ifdef CONFIG_M5282
#endif
#ifdef CONFIG_M5272
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
volatile wdog_t * wdp = (wdog_t *)(CFG_MBAR + MCFSIM_WRRR);
wdp->wdog_wrrr = 0;
udelay (1000);
/* enable watchdog, set timeout to 0 and wait */
wdp->wdog_wrrr = 1;
while (1);
/* we don't return! */
return 0;
};
int checkcpu(void) {
ulong *dirp = (ulong *)(CFG_MBAR + MCFSIM_DIR);
uchar msk;
char *suf;
puts ("CPU: ");
msk = (*dirp > 28) & 0xf;
switch (msk) {
case 0x2: suf = "1K75N"; break;
case 0x4: suf = "3K75N"; break;
default:
suf = NULL;
printf ("MOTOROLA MCF5272 (Mask:%01x)\n", msk);
break;
}
if (suf)
printf ("MOTOROLA MCF5272 %s\n", suf);
return 0;
};
#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
void watchdog_reset (void)
{
volatile immap_t * regp = (volatile immap_t *)CFG_MBAR;
regp->wdog_reg.wdog_wcr = 0;
}
int watchdog_disable (void)
{
volatile immap_t *regp = (volatile immap_t *)CFG_MBAR;
regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */
regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */
regp->wdog_reg.wdog_wrrr = 0; /* disable watchdog timer */
puts ("WATCHDOG:disabled\n");
return (0);
}
int watchdog_init (void)
{
volatile immap_t *regp = (volatile immap_t *)CFG_MBAR;
regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */
/* set timeout and enable watchdog */
regp->wdog_reg.wdog_wrrr = ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */
puts ("WATCHDOG:enabled\n");
return (0);
}
#endif /* #ifdef CONFIG_WATCHDOG */
#endif /* #ifdef CONFIG_M5272 */
#ifdef CONFIG_M5282
int checkcpu (void)
{
puts ("CPU: MOTOROLA Coldfire MCF5282\n");
return 0;
}
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
return 0;
};
#endif

144
cpu/mcf52x2/cpu_init.c Normal file
View File

@ -0,0 +1,144 @@
/*
* (C) Copyright 2003
* Josef Baumgartner <josef.baumgartner@telex.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#ifdef CONFIG_M5272
#include <asm/m5272.h>
#include <asm/immap_5272.h>
#endif
#ifdef CONFIG_M5282
#include <asm/m5282.h>
#include <asm/immap_5282.h>
#endif
#ifdef CONFIG_M5272
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f (void)
{
/* if we come from RAM we assume the CPU is
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
volatile immap_t *regp = (immap_t *)CFG_MBAR;
volatile unsigned char *mbar;
mbar = (volatile unsigned char *) CFG_MBAR;
regp->sysctrl_reg.sc_scr = CFG_SCR;
regp->sysctrl_reg.sc_spr = CFG_SPR;
/* Setup Ports: */
regp->gpio_reg.gpio_pacnt = CFG_PACNT;
regp->gpio_reg.gpio_paddr = CFG_PADDR;
regp->gpio_reg.gpio_padat = CFG_PADAT;
regp->gpio_reg.gpio_pbcnt = CFG_PBCNT;
regp->gpio_reg.gpio_pbddr = CFG_PBDDR;
regp->gpio_reg.gpio_pbdat = CFG_PBDAT;
regp->gpio_reg.gpio_pdcnt = CFG_PDCNT;
/* Memory Controller: */
regp->csctrl_reg.cs_br0 = CFG_BR0_PRELIM;
regp->csctrl_reg.cs_or0 = CFG_OR0_PRELIM;
#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
regp->csctrl_reg.cs_br1 = CFG_BR1_PRELIM;
regp->csctrl_reg.cs_or1 = CFG_OR1_PRELIM;
#endif
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
regp->csctrl_reg.cs_br2 = CFG_BR2_PRELIM;
regp->csctrl_reg.cs_or2 = CFG_OR2_PRELIM;
#endif
#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
regp->csctrl_reg.cs_br3 = CFG_BR3_PRELIM;
regp->csctrl_reg.cs_or3 = CFG_OR3_PRELIM;
#endif
#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
regp->csctrl_reg.cs_br4 = CFG_BR4_PRELIM;
regp->csctrl_reg.cs_or4 = CFG_OR4_PRELIM;
#endif
#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
regp->csctrl_reg.cs_br5 = CFG_BR5_PRELIM;
regp->csctrl_reg.cs_or5 = CFG_OR5_PRELIM;
#endif
#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
regp->csctrl_reg.cs_br6 = CFG_BR6_PRELIM;
regp->csctrl_reg.cs_or6 = CFG_OR6_PRELIM;
#endif
#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
regp->csctrl_reg.cs_br7 = CFG_BR7_PRELIM;
regp->csctrl_reg.cs_or7 = CFG_OR7_PRELIM;
#endif
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
/* enable instruction cache now */
icache_enable();
}
/*
* initialize higher level parts of CPU like timers
*/
int cpu_init_r (void)
{
return (0);
}
#endif /* #ifdef CONFIG_M5272 */
#ifdef CONFIG_M5282
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f (void)
{
}
/*
* initialize higher level parts of CPU like timers
*/
int cpu_init_r (void)
{
return (0);
}
#endif

558
cpu/mcf52x2/fec.c Normal file
View File

@ -0,0 +1,558 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <asm/fec.h>
#ifdef CONFIG_M5272
#include <asm/m5272.h>
#include <asm/immap_5272.h>
#endif
#ifdef CONFIG_M5282
#include <asm/m5282.h>
#include <asm/immap_5282.h>
#endif
#include <net.h>
#include <command.h>
#ifdef CONFIG_M5272
#define FEC_ADDR (CFG_MBAR + 0x840)
#endif
#ifdef CONFIG_M5282
#define FEC_ADDR (CFG_MBAR + 0x1000)
#endif
#undef ET_DEBUG
#undef MII_DEBUG
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
#ifdef CFG_DISCOVER_PHY
#include <miiphy.h>
static void mii_discover_phy (void);
#endif
/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH 1520
#define TX_BUF_CNT 2
#define TOUT_LOOP 100
#define PKT_MAXBUF_SIZE 1518
#define PKT_MINBUF_SIZE 64
#define PKT_MAXBLR_SIZE 1520
static char txbuf[DBUF_LENGTH];
static uint rxIdx; /* index of the current RX buffer */
static uint txIdx; /* index of the current TX buffer */
/*
* FEC Ethernet Tx and Rx buffer descriptors allocated at the
* immr->udata_bd address on Dual-Port RAM
* Provide for Double Buffering
*/
typedef volatile struct CommonBufferDescriptor {
cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
} RTXBD;
static RTXBD *rtx = NULL;
int eth_send (volatile void *packet, int length)
{
int j, rc;
volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
/* section 16.9.23.3
* Wait for ready
*/
j = 0;
while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
&& (j < TOUT_LOOP)) {
udelay (1);
j++;
}
if (j >= TOUT_LOOP) {
printf ("TX not ready\n");
}
rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
rtx->txbd[txIdx].cbd_datlen = length;
rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
/* Activate transmit Buffer Descriptor polling */
fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
j = 0;
while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
&& (j < TOUT_LOOP)) {
udelay (1);
j++;
}
if (j >= TOUT_LOOP) {
printf ("TX timeout\n");
}
#ifdef ET_DEBUG
printf ("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
__FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc,
(rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2);
#endif
/* return only status bits */ ;
rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
txIdx = (txIdx + 1) % TX_BUF_CNT;
return rc;
}
int eth_rx (void)
{
int length;
volatile fec_t *fecp = (fec_t *) FEC_ADDR;
for (;;) {
/* section 16.9.23.2 */
if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
length = -1;
break; /* nothing received - leave for() loop */
}
length = rtx->rxbd[rxIdx].cbd_datlen;
if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
#ifdef ET_DEBUG
printf ("%s[%d] err: %x\n",
__FUNCTION__, __LINE__,
rtx->rxbd[rxIdx].cbd_sc);
#endif
} else {
/* Pass the packet up to the protocol layers. */
NetReceive (NetRxPackets[rxIdx], length - 4);
}
/* Give the buffer back to the FEC. */
rtx->rxbd[rxIdx].cbd_datlen = 0;
/* wrap around buffer index when necessary */
if ((rxIdx + 1) >= PKTBUFSRX) {
rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
rxIdx = 0;
} else {
rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
rxIdx++;
}
/* Try to fill Buffer Descriptors */
fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
}
return length;
}
/**************************************************************
*
* FEC Ethernet Initialization Routine
*
*************************************************************/
#define FEC_ECNTRL_ETHER_EN 0x00000002
#define FEC_ECNTRL_RESET 0x00000001
#define FEC_RCNTRL_BC_REJ 0x00000010
#define FEC_RCNTRL_PROM 0x00000008
#define FEC_RCNTRL_MII_MODE 0x00000004
#define FEC_RCNTRL_DRT 0x00000002
#define FEC_RCNTRL_LOOP 0x00000001
#define FEC_TCNTRL_FDEN 0x00000004
#define FEC_TCNTRL_HBC 0x00000002
#define FEC_TCNTRL_GTS 0x00000001
#define FEC_RESET_DELAY 50000
int eth_init (bd_t * bd)
{
int i;
volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
/* Whack a reset.
* A delay is required between a reset of the FEC block and
* initialization of other FEC registers because the reset takes
* some time to complete. If you don't delay, subsequent writes
* to FEC registers might get killed by the reset routine which is
* still in progress.
*/
fecp->fec_ecntrl = FEC_ECNTRL_RESET;
for (i = 0;
(fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
++i) {
udelay (1);
}
if (i == FEC_RESET_DELAY) {
printf ("FEC_RESET_DELAY timeout\n");
return 0;
}
/* We use strictly polling mode only
*/
fecp->fec_imask = 0;
/* Clear any pending interrupt */
fecp->fec_ievent = 0xffffffff;
/* Set station address */
#define ea bd->bi_enetaddr
fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) |
(ea[2] << 8) | (ea[3]);
fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16);
#ifdef ET_DEBUG
printf ("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n",
ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]);
#endif
#undef ea
/* Clear multicast address hash table
*/
fecp->fec_hash_table_high = 0;
fecp->fec_hash_table_low = 0;
/* Set maximum receive buffer size.
*/
fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
/*
* Setup Buffers and Buffer Desriptors
*/
rxIdx = 0;
txIdx = 0;
if (!rtx) {
rtx = (RTXBD *) CFG_ENET_BD_BASE;
}
/*
* Setup Receiver Buffer Descriptors (13.14.24.18)
* Settings:
* Empty, Wrap
*/
for (i = 0; i < PKTBUFSRX; i++) {
rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
rtx->rxbd[i].cbd_datlen = 0; /* Reset */
rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
}
rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
/*
* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
* Settings:
* Last, Tx CRC
*/
for (i = 0; i < TX_BUF_CNT; i++) {
rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
rtx->txbd[i].cbd_datlen = 0; /* Reset */
rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
}
rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
/* Set receive and transmit descriptor base
*/
fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
/* Enable MII mode
*/
#if 0 /* Full duplex mode */
fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
#else /* Half duplex mode */
fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
fecp->fec_x_cntrl = 0;
#endif
/* Set MII speed */
fecp->fec_mii_speed = 0x0e;
/* Configure port B for MII.
*/
/* port initialization was already made in cpu_init_f() */
/* Now enable the transmit and receive processing
*/
fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
#ifdef CFG_DISCOVER_PHY
/* wait for the PHY to wake up after reset */
mii_discover_phy ();
#endif
/* And last, try to fill Rx Buffer Descriptors */
fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
return 1;
}
void eth_halt (void)
{
volatile fec_t *fecp = (fec_t *) FEC_ADDR;
fecp->fec_ecntrl = 0;
}
#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
static int phyaddr = -1; /* didn't find a PHY yet */
static uint phytype;
/* Make MII read/write commands for the FEC.
*/
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
(REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
(REG & 0x1f) << 18) | \
(VAL & 0xffff))
/* Interrupt events/masks.
*/
#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
/* PHY identification
*/
#define PHY_ID_LXT970 0x78100000 /* LXT970 */
#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
#define PHY_ID_QS6612 0x01814400 /* QS6612 */
#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
/* send command to phy using mii, wait for result */
static uint mii_send (uint mii_cmd)
{
uint mii_reply;
volatile fec_t *ep = (fec_t *) (FEC_ADDR);
ep->fec_mii_data = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->fec_ievent & FEC_ENET_MII)); /* spin until done */
mii_reply = ep->fec_mii_data; /* result from phy */
ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf ("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
#if defined(CFG_DISCOVER_PHY)
static void mii_discover_phy (void)
{
#define MAX_PHY_PASSES 11
uint phyno;
int pass;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay (10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf ("PHY type 0x%x pass %d type ", phytype, pass);
#endif
if (phytype != 0xffff) {
phyaddr = phyno;
phytype <<= 16;
phytype |= mii_send (mk_mii_read (phyno,
PHY_PHYIDR2));
#ifdef ET_DEBUG
printf ("PHY @ 0x%x pass %d type ", phyno,
pass);
switch (phytype & 0xfffffff0) {
case PHY_ID_LXT970:
printf ("LXT970\n");
break;
case PHY_ID_LXT971:
printf ("LXT971\n");
break;
case PHY_ID_82555:
printf ("82555\n");
break;
case PHY_ID_QS6612:
printf ("QS6612\n");
break;
case PHY_ID_AMD79C784:
printf ("AMD79C784\n");
break;
case PHY_ID_LSI80225B:
printf ("LSI L80225/B\n");
break;
default:
printf ("0x%08x\n", phytype);
break;
}
#endif
}
}
}
if (phyaddr < 0) {
printf ("No PHY device found.\n");
}
}
#endif /* CFG_DISCOVER_PHY */
#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
static int mii_init_done = 0;
/****************************************************************************
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
****************************************************************************
*/
void mii_init (void)
{
volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
int i;
if (mii_init_done != 0) {
return;
}
/* Whack a reset.
* A delay is required between a reset of the FEC block and
* initialization of other FEC registers because the reset takes
* some time to complete. If you don't delay, subsequent writes
* to FEC registers might get killed by the reset routine which is
* still in progress.
*/
fecp->fec_ecntrl = FEC_ECNTRL_RESET;
for (i = 0;
(fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
++i) {
udelay (1);
}
if (i == FEC_RESET_DELAY) {
printf ("FEC_RESET_DELAY timeout\n");
return;
}
/* We use strictly polling mode only
*/
fecp->fec_imask = 0;
/* Clear any pending interrupt
*/
fecp->fec_ievent = 0xffffffff;
/* Set MII speed */
fecp->fec_mii_speed = 0x0e;
/* Configure port B for MII.
*/
/* port initialization was already made in cpu_init_f() */
/* Now enable the transmit and receive processing */
fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
mii_init_done = 1;
}
/*****************************************************************************
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send (mk_mii_read (addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf ("0x%04x\n", *value);
#endif
return 0;
}
int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send (mk_mii_write (addr, reg, value));
#ifdef MII_DEBUG
printf ("0x%04x\n", value);
#endif
return 0;
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) */
#endif /* CFG_CMD_NET, FEC_ENET */

174
cpu/mcf52x2/interrupts.c Normal file
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@ -0,0 +1,174 @@
/*
* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <asm/processor.h>
#ifdef CONFIG_M5272
#include <asm/m5272.h>
#include <asm/immap_5272.h>
#endif
#ifdef CONFIG_M5282
#include <asm/m5282.h>
#include <asm/immap_5282.h>
#endif
#define NR_IRQS 31
/*
* Interrupt vector functions.
*/
struct interrupt_action {
interrupt_handler_t *handler;
void *arg;
}
static struct interrupt_action irq_vecs[NR_IRQS];
static __inline__ unsigned short get_sr (void)
{
unsigned short sr;
asm volatile ("move.w %%sr,%0":"=r" (sr):);
return sr;
}
static __inline__ void set_sr (unsigned short sr)
{
asm volatile ("move.w %0,%%sr"::"r" (sr));
}
/************************************************************************/
/*
* Install and free an interrupt handler
*/
void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
{
#ifdef CONFIG_M5272
volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
#endif
int vec_base = 0;
#ifdef CONFIG_M5272
vec_base = intp->int_pivr & 0xe0;
#endif
if ((vec < vec_base) || (vec > vec_base + NR_IRQS)) {
printf ("irq_install_handler: wrong interrupt vector %d\n",
vec);
return;
}
irq_vecs[vec - vec_base].handler = handler;
irq_vecs[vec - vec_base].arg = arg;
}
void irq_free_handler (int vec)
{
#ifdef CONFIG_M5272
volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
#endif
int vec_base = 0;
#ifdef CONFIG_M5272
vec_base = intp->int_pivr & 0xe0;
#endif
if ((vec < vec_base) || (vec > vec_base + NR_IRQS)) {
return;
}
irq_vecs[vec - vec_base].handler = NULL;
irq_vecs[vec - vec_base].arg = NULL;
}
void enable_interrupts (void)
{
unsigned short sr;
sr = get_sr ();
set_sr (sr & ~0x0700);
}
int disable_interrupts (void)
{
unsigned short sr;
sr = get_sr ();
set_sr (sr | 0x0700);
return ((sr & 0x0700) == 0); /* return TRUE, if interrupts were enabled before */
}
void int_handler (struct pt_regs *fp)
{
#ifdef CONFIG_M5272
volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
#endif
int vec, vec_base = 0;
vec = (fp->vector >> 2) & 0xff;
#ifdef CONFIG_M5272
vec_base = intp->int_pivr & 0xe0;
#endif
if (irq_vecs[vec - vec_base].handler != NULL) {
irq_vecs[vec -
vec_base].handler (irq_vecs[vec - vec_base].arg);
} else {
printf ("\nBogus External Interrupt Vector %ld\n", vec);
}
}
#ifdef CONFIG_M5272
int interrupt_init (void)
{
volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
/* disable all external interrupts */
intp->int_icr1 = 0x88888888;
intp->int_icr2 = 0x88888888;
intp->int_icr3 = 0x88888888;
intp->int_icr4 = 0x88888888;
intp->int_pitr = 0x00000000;
/* initialize vector register */
intp->int_pivr = 0x40;
enable_interrupts ();
return 0;
}
#endif
#ifdef CONFIG_M5282
int interrupt_init (void)
{
return 0;
}
#endif

159
cpu/mcf52x2/serial.c Normal file
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@ -0,0 +1,159 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/mcfuart.h>
#ifdef CONFIG_M5272
#include <asm/m5272.h>
#endif
#ifdef CONFIG_M5282
#include <asm/m5282.h>
#endif
#define DoubleClock(a) ((double)(CFG_CLK) / 32.0 / (double)(a))
void rs_serial_setbaudrate(int port,int baudrate)
{
#ifdef CONFIG_M5272
volatile unsigned char *uartp;
double clock, fraction;
if (port == 0)
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
else
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
clock = DoubleClock(baudrate); /* Set baud above */
fraction = ((clock - (int)clock) * 16.0) + 0.5;
uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */
uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */
uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */
#endif
};
void rs_serial_init(int port,int baudrate)
{
volatile unsigned char *uartp;
/*
* Reset UART, get it into known state...
*/
if (port == 0)
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
else
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */
/*
* Set port for CONSOLE_BAUD_RATE, 8 data bits, 1 stop bit, no parity.
*/
uartp[MCFUART_UMR] = MCFUART_MR1_PARITYNONE | MCFUART_MR1_CS8;
uartp[MCFUART_UMR] = MCFUART_MR2_STOP1;
rs_serial_setbaudrate(port,baudrate);
uartp[MCFUART_UCSR] = MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER;
uartp[MCFUART_UCR] = MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE;
return;
}
/****************************************************************************/
/*
* Output a single character, using UART polled mode.
* This is used for console output.
*/
void rs_put_char(char ch)
{
volatile unsigned char *uartp;
int i;
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
for (i = 0; (i < 0x10000); i++) {
if (uartp[MCFUART_USR] & MCFUART_USR_TXREADY)
break;
}
uartp[MCFUART_UTB] = ch;
return;
}
int rs_is_char(void)
{
volatile unsigned char *uartp;
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
return((uartp[MCFUART_USR] & MCFUART_USR_RXREADY) ? 1 : 0);
}
int rs_get_char(void)
{
volatile unsigned char *uartp;
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
return(uartp[MCFUART_URB]);
}
void serial_setbrg(void) {
DECLARE_GLOBAL_DATA_PTR;
rs_serial_setbaudrate(0,gd->bd->bi_baudrate);
}
int serial_init(void) {
DECLARE_GLOBAL_DATA_PTR;
rs_serial_init(0,gd->baudrate);
return 0;
}
void serial_putc(const char c) {
if (c == '\n')
serial_putc ('\r');
rs_put_char(c);
}
void serial_puts (const char *s) {
while (*s) {
serial_putc(*s++);
}
}
int serial_getc(void) {
while(!rs_is_char());
return rs_get_char();
}
int serial_tstc() {
return rs_is_char();
}

18
cpu/coldfire/speed.c → cpu/mcf52x2/speed.c
View File

@ -1,6 +1,6 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* (C) Copyright 2003
* Josef Baumgartner <josef.baumgartner@telex.de>
*
* See file CREDITS for list of people who contributed to this
* project.
@ -24,12 +24,14 @@
#include <common.h>
#include <asm/processor.h>
ulong get_gclk_freq (void)
/*
* get_clocks() fills in gd->cpu_clock and gd->bus_clk
*/
int get_clocks (void)
{
return 0;
}
DECLARE_GLOBAL_DATA_PTR;
ulong get_bus_freq (ulong gclk_freq)
{
return 0;
gd->cpu_clk = CFG_CLK;
gd->bus_clk = gd->cpu_clk;
return (0);
}

316
cpu/mcf52x2/start.S Normal file
View File

@ -0,0 +1,316 @@
/*
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include "version.h"
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
#endif
#define _START _start
#define _FAULT _fault
#define SAVE_ALL \
move.w #0x2700,%sr; /* disable intrs */ \
subl #60,%sp; /* space for 15 regs */ \
moveml %d0-%d7/%a0-%a6,%sp@; \
#define RESTORE_ALL \
moveml %sp@,%d0-%d7/%a0-%a6; \
addl #60,%sp; /* space for 15 regs */ \
rte
/* If we come from a pre-loader we don't need an initial exception
* table.
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
.text
/*
* Vector table. This is used for initial platform startup.
* These vectors are to catch any un-intended traps.
*/
_vectors:
.long 0x00000000, _START
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
#endif
.text
.globl _start
_start:
nop
nop
move.w #0x2700,%sr
/* if we come from a pre-loader we have no exception table and
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
move.l #CFG_FLASH_BASE, %d0
movec %d0, %VBR
#endif
#ifdef CONFIG_M5272
move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
move.c %d0, %MBAR
move.l #(CFG_INIT_RAM_ADDR + 1), %d0
movec %d0, %RAMBAR0
#endif
#ifdef CONFIG_M5282
/* Initialize IPSBAR */
move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
move.l %d0, 0x40000000
/* Initialize FLASHBAR: locate internal Flash and validate it */
move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
movec %d0, %RAMBAR0
/* Initialize RAMBAR1: locate SRAM and validate it */
move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#endif
/* invalidate and disable cache */
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
movec %d0, %ACR1
/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
clr.l %sp@-
move.l #__got_start, %a5 /* put relocation table address to a5 */
bsr cpu_init_f /* run low-level CPU init code (from flash) */
bsr board_init_f /* run low-level board init code (from flash) */
/* board_init_f() does not return
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
*/
.globl relocate_code
relocate_code:
link.w %a6,#0
move.l 8(%a6), %sp /* set new stack pointer */
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
move.l #CFG_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
/* copy the code to RAM */
1:
move.l (%a1)+, (%a3)+
cmp.l %a1,%a2
bgt.s 1b
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
move.l %a0, %a1
add.l #(in_ram - CFG_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
clear_bss:
/*
* Now clear BSS segment
*/
move.l %a0, %a1
add.l #(_sbss - CFG_MONITOR_BASE),%a1
move.l %a0, %d1
add.l #(_ebss - CFG_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
bgt.s 6b
/*
* fix got table in RAM
*/
move.l %a0, %a1
add.l #(__got_start - CFG_MONITOR_BASE),%a1
move.l %a1,%a5 /* * fix got pointer register a5 */
move.l %a0, %a2
add.l #(__got_end - CFG_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
sub.l #_start,%d1
add.l %a0,%d1
move.l %d1,(%a1)+
cmp.l %a2, %a1
bne 7b
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
add.l #(board_init_r - CFG_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
jsr (%a1)
/*------------------------------------------------------------------------------*/
/* exception code */
.globl _fault
_fault:
jmp _fault
.globl _exc_handler
_exc_handler:
SAVE_ALL
movel %sp,%sp@-
bsr exc_handler
addql #4,%sp
RESTORE_ALL
.globl _int_handler
_int_handler:
SAVE_ALL
movel %sp,%sp@-
bsr int_handler
addql #4,%sp
RESTORE_ALL
/*------------------------------------------------------------------------------*/
/* cache functions */
#ifdef CONFIG_M5272
.globl icache_enable
icache_enable:
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #0x0000c000, %d0 /* Setup cache mask */
movec %d0, %ACR0 /* Enable cache */
move.l #0xff00c000, %d0 /* Setup cache mask */
movec %d0, %ACR1 /* Enable cache */
move.l #0x80000100, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
moveq #1, %d0
move.l %d0, icache_state
rts
#endif
#ifdef CONFIG_M5282
.globl icache_enable
icache_enable:
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #0x0000c000, %d0 /* Setup cache mask */
movec %d0, %ACR0 /* Enable cache */
move.l #0xff00c000, %d0 /* Setup cache mask */
movec %d0, %ACR1 /* Enable cache */
move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/
movec %d0, %CACR /* Enable cache */
moveq #1, %d0
move.l %d0, icache_state
rts
#endif
.globl icache_disable
icache_disable:
move.l #0x00000100, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
clr.l %d0 /* Setup cache mask */
movec %d0, %ACR0 /* Enable cache */
movec %d0, %ACR1 /* Enable cache */
moveq #0, %d0
move.l %d0, icache_state
rts
.globl icache_status
icache_status:
move.l icache_state, %d0
rts
.data
icache_state:
.long 1
/*------------------------------------------------------------------------------*/
.globl version_string
version_string:
.ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii CONFIG_IDENT_STRING, "\0"

133
doc/README.m68k Normal file
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@ -0,0 +1,133 @@
U-Boot for Motorola M68K
Last Update: January 12, 2004
====================================================================
This file contains status information for the port of U-Boot to the
Motorola M68K series of CPUs.
1. OVERVIEW
-----------
Bernhard Kuhn ported U-Boot 0.4.0 to the Motorola Coldfire
architecture. The patches of Bernhard support the MCF5272 and
MCF5282. A great disadvantage of these patches was that they needed
a pre-bootloader to start u-boot. Because of this, a new port was
created which no longer needs a first stage booter.
Although this port is intended to cover all M68k processors, only
the parts for the Motorola Coldfire MCF5272 and MCF5282 are
implemented at the moment. Additional CPUs and boards will be
hopefully added soon!
2. SUPPORTED CPUs
-----------------
2.1 Motorola Coldfire MCF5272
-----------------------------
CPU specific code is located in: cpu/mcf52x2
2.1 Motorola Coldfire MCF5282
-----------------------------
CPU specific code is located in: cpu/mcf52x2
At the moment the code isn't fully implemented and still needs a pre-loader!
The preloader must initialize the processor and then start u-boot. The board
must be configured for a pre-loader (see 4.1)
U-boot is configured to run at 0x20000 at default. This can be configured by
change TEXT_BASE in board/m5282evb/config.mk and CFG_MONITOR_BASE in
include/configs/M5282EVB.h.
3. SUPPORTED BOARDs
-------------------
3.1 Motorola M5272C3 EVB
------------------------
Board specific code is located in: board/m5272c3
To configure the board, type: make M5272C3_config
U-Boot Memory Map:
------------------
0xffe00000 - 0xffe3ffff u-boot
0xffe04000 - 0xffe05fff environment (embedded in u-boot!)
0xffe40000 - 0xffffffff free for linux/applications
3.2 Motorola M5282 EVB
------------------------
Board specific code is located in: board/m5282evb
To configure the board, type: make M5272C3_config
4. CONFIGURATION OPTIONS/SETTINGS
----------------------------------
4.1 Configuration to use a pre-loader
-------------------------------------
If u-boot should be loaded to RAM and started by a pre-loader
CONFIG_MONITOR_IS_IN_RAM must be defined. If it is defined the
initial vector table and basic processor initialization will not
be compiled in. The start address of u-boot must be adjusted in
the boards config header file (CFG_MONITOR_BASE) and Makefile
(TEXT_BASE) to the load address.
4.1 MCF5272 specific Options/Settings
-------------------------------------
CONFIG_MCF52x2 -- defined for all MCF52x2 CPUs
CONFIG_M5272 -- defined for all Motorola MCF5272 CPUs
CONFIG_MONITOR_IS_IN_RAM
-- defined if u-boot is loaded by a pre-loader
CFG_MBAR -- defines the base address of the MCF5272 configuration registers
CFG_INIT_RAM_ADDR
-- defines the base address of the MCF5272 internal SRAM
CFG_ENET_BD_BASE
-- defines the base addres of the FEC buffer descriptors
CFG_SCR -- defines the contents of the System Configuration Register
CFG_SPR -- defines the contents of the System Protection Register
CFG_BRx_PRELIM -- defines the contents of the Chip Select Base Registers
CFG_ORx_PRELIM -- defines the contents of the Chip Select Option Registers
CFG_PxDDR -- defines the contents of the Data Direction Registers
CFG_PxDAT -- defines the contents of the Data Registers
CFG_PXCNT -- defines the contents of the Port Configuration Registers
4.2 MCF5282 specific Options/Settings
-------------------------------------
CONFIG_MCF52x2 -- defined for all MCF52x2 CPUs
CONFIG_M5282 -- defined for all Motorola MCF5282 CPUs
CONFIG_MONITOR_IS_IN_RAM
-- defined if u-boot is loaded by a pre-loader
CFG_MBAR -- defines the base address of the MCF5282 internal register space
CFG_INIT_RAM_ADDR
-- defines the base address of the MCF5282 internal SRAM
CFG_INT_FLASH_BASE
-- defines the base address of the MCF5282 internal Flash memory
CFG_ENET_BD_BASE
-- defines the base addres of the FEC buffer descriptors
5. COMPILER
-----------
To create U-Boot the gcc-2.95.3 compiler set (m68k-elf-20030314) from uClinux.org was used.
You can download it from: http://www.uclinux.org/pub/uClinux/m68k-elf-tools/
Regards,
Josef
<josef.baumgartner@telex.de>

843
drivers/cfi_flash.c
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File diff suppressed because it is too large Load Diff

10
examples/Makefile
View File

@ -41,6 +41,10 @@ ifeq ($(ARCH),nios)
LOAD_ADDR = 0x01000000 -L $(gcclibdir)/m32 -T nios.lds
endif
ifeq ($(ARCH),m68k)
LOAD_ADDR = 0x20000 -L $(clibdir)
endif
include $(TOPDIR)/config.mk
SREC = hello_world.srec
@ -56,11 +60,6 @@ SREC += sched.srec
BIN += sched.bin sched
endif
ifeq ($(ARCH),m68k)
SREC =
BIN =
endif
# The following example is pretty 8xx specific...
ifeq ($(CPU),mpc8xx)
SREC += timer.srec
@ -94,6 +93,7 @@ LIBCOBJS= stubs.o
LIBOBJS = $(LIBAOBJS) $(LIBCOBJS)
gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
clibdir := $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`)
CPPFLAGS += -I..

16
examples/stubs.c
View File

@ -78,6 +78,22 @@ gd_t *global_data;
" jmp %%g0\n" \
" nop \n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x) : "r0");
#elif defined(CONFIG_M68K)
/*
* d7 holds the pointer to the global_data, a0 is a call-clobbered
* register
*/
#define EXPORT_FUNC(x) \
asm volatile ( \
" .globl " #x "\n" \
#x ":\n" \
" move.l %%d7, %%a0\n" \
" adda.l %0, %%a0\n" \
" move.l (%%a0), %%a0\n" \
" adda.l %1, %%a0\n" \
" move.l (%%a0), %%a0\n" \
" jmp (%%a0)\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "a0");
#else
#error stubs definition missing for this architecture
#endif

18
include/asm-m68k/bitops.h Normal file
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@ -0,0 +1,18 @@
/*
* bitops.h: Bit string operations on the m68k
*/
#ifndef _M68K_BITOPS_H
#define _M68K_BITOPS_H
#include <linux/config.h>
#include <asm/byteorder.h>
extern void set_bit(int nr, volatile void *addr);
extern void clear_bit(int nr, volatile void *addr);
extern void change_bit(int nr, volatile void *addr);
extern int test_and_set_bit(int nr, volatile void *addr);
extern int test_and_clear_bit(int nr, volatile void *addr);
extern int test_and_change_bit(int nr, volatile void *addr);
#endif /* _M68K_BITOPS_H */

7
include/asm-m68k/byteorder.h Normal file
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@ -0,0 +1,7 @@
#ifndef _M68K_BYTEORDER_H
#define _M68K_BYTEORDER_H
#include <asm/types.h>
#include <linux/byteorder/big_endian.h>
#endif /* _M68K_BYTEORDER_H */

86
include/asm-m68k/fec.h Normal file
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@ -0,0 +1,86 @@
/*
* fec.h -- Fast Ethernet Controller definitions
*
* Some definitions copied from commproc.h for MPC8xx:
* MPC8xx Communication Processor Module.
* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef fec_h
#define fec_h
/* Buffer descriptors used FEC.
*/
typedef struct cpm_buf_desc {
ushort cbd_sc; /* Status and Control */
ushort cbd_datlen; /* Data length in buffer */
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
#define BD_SC_BR ((ushort)0x0020) /* Break received */
#define BD_SC_FR ((ushort)0x0010) /* Framing error */
#define BD_SC_PR ((ushort)0x0008) /* Parity error */
#define BD_SC_OV ((ushort)0x0002) /* Overrun */
#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
/* Buffer descriptor control/status used by Ethernet receive.
*/
#define BD_ENET_RX_EMPTY ((ushort)0x8000)
#define BD_ENET_RX_WRAP ((ushort)0x2000)
#define BD_ENET_RX_INTR ((ushort)0x1000)
#define BD_ENET_RX_LAST ((ushort)0x0800)
#define BD_ENET_RX_FIRST ((ushort)0x0400)
#define BD_ENET_RX_MISS ((ushort)0x0100)
#define BD_ENET_RX_LG ((ushort)0x0020)
#define BD_ENET_RX_NO ((ushort)0x0010)
#define BD_ENET_RX_SH ((ushort)0x0008)
#define BD_ENET_RX_CR ((ushort)0x0004)
#define BD_ENET_RX_OV ((ushort)0x0002)
#define BD_ENET_RX_CL ((ushort)0x0001)
#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
/* Buffer descriptor control/status used by Ethernet transmit.
*/
#define BD_ENET_TX_READY ((ushort)0x8000)
#define BD_ENET_TX_PAD ((ushort)0x4000)
#define BD_ENET_TX_WRAP ((ushort)0x2000)
#define BD_ENET_TX_INTR ((ushort)0x1000)
#define BD_ENET_TX_LAST ((ushort)0x0800)
#define BD_ENET_TX_TC ((ushort)0x0400)
#define BD_ENET_TX_DEF ((ushort)0x0200)
#define BD_ENET_TX_HB ((ushort)0x0100)
#define BD_ENET_TX_LC ((ushort)0x0080)
#define BD_ENET_TX_RL ((ushort)0x0040)
#define BD_ENET_TX_RCMASK ((ushort)0x003c)
#define BD_ENET_TX_UN ((ushort)0x0002)
#define BD_ENET_TX_CSL ((ushort)0x0001)
#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
#endif /* fec_h */

7
include/asm-m68k/global_data.h
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2002-2003
* (C) Copyright 2002 - 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -48,6 +48,7 @@ typedef struct global_data {
#ifdef CONFIG_BOARD_TYPES
unsigned long board_type;
#endif
void **jt; /* Standalone app jump table */
} gd_t;
/*
@ -56,7 +57,11 @@ typedef struct global_data {
#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#if 0
extern gd_t *global_data;
#define DECLARE_GLOBAL_DATA_PTR gd_t *gd = global_data
#else
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("d7")
#endif
#endif /* __ASM_GBL_DATA_H */

447
include/asm-m68k/immap_5272.h Normal file
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@ -0,0 +1,447 @@
/*
* MCF5272 Internal Memory Map
*
* Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5272__
#define __IMMAP_5272__
/* System configuration registers
*/
typedef struct sys_ctrl {
uint sc_mbar;
ushort sc_scr;
ushort sc_spr;
uint sc_pmr;
char res1[2];
ushort sc_alpr;
uint sc_dir;
char res2[12];
} sysctrl_t;
/* Interrupt module registers
*/
typedef struct int_ctrl {
uint int_icr1;
uint int_icr2;
uint int_icr3;
uint int_icr4;
uint int_isr;
uint int_pitr;
uint int_piwr;
uchar res1[3];
uchar int_pivr;
} intctrl_t;
/* Chip select module registers.
*/
typedef struct cs_ctlr {
uint cs_br0;
uint cs_or0;
uint cs_br1;
uint cs_or1;
uint cs_br2;
uint cs_or2;
uint cs_br3;
uint cs_or3;
uint cs_br4;
uint cs_or4;
uint cs_br5;
uint cs_or5;
uint cs_br6;
uint cs_or6;
uint cs_br7;
uint cs_or7;
} csctrl_t;
/* GPIO port registers
*/
typedef struct gpio_ctrl {
uint gpio_pacnt;
ushort gpio_paddr;
ushort gpio_padat;
uint gpio_pbcnt;
ushort gpio_pbddr;
ushort gpio_pbdat;
uchar res1[4];
ushort gpio_pcddr;
ushort gpio_pcdat;
uint gpio_pdcnt;
uchar res2[4];
} gpio_t;
/* QSPI module registers
*/
typedef struct qspi_ctrl {
ushort qspi_qmr;
uchar res1[2];
ushort qspi_qdlyr;
uchar res2[2];
ushort qspi_qwr;
uchar res3[2];
ushort qspi_qir;
uchar res4[2];
ushort qspi_qar;
uchar res5[2];
ushort qspi_qdr;
uchar res6[10];
} qspi_t;
/* PWM module registers
*/
typedef struct pwm_ctrl {
uchar pwm_pwcr0;
uchar res1[3];
uchar pwm_pwcr1;
uchar res2[3];
uchar pwm_pwcr2;
uchar res3[7];
uchar pwm_pwwd0;
uchar res4[3];
uchar pwm_pwwd1;
uchar res5[3];
uchar pwm_pwwd2;
uchar res6[7];
} pwm_t;
/* DMA module registers
*/
typedef struct dma_ctrl {
ulong dma_dmr;
uchar res1[2];
ushort dma_dir;
ulong dma_dbcr;
ulong dma_dsar;
ulong dma_ddar;
uchar res2[12];
} dma_t;
/* UART module registers
*/
typedef struct uart_ctrl {
uchar uart_umr;
uchar res1[3];
uchar uart_usr_ucsr;
uchar res2[3];
uchar uart_ucr;
uchar res3[3];
uchar uart_urb_utb;
uchar res4[3];
uchar uart_uipcr_uacr;
uchar res5[3];
uchar uart_uisr_uimr;
uchar res6[3];
uchar uart_udu;
uchar res7[3];
uchar uart_udl;
uchar res8[3];
uchar uart_uabu;
uchar res9[3];
uchar uart_uabl;
uchar res10[3];
uchar uart_utf;
uchar res11[3];
uchar uart_urf;
uchar res12[3];
uchar uart_ufpd;
uchar res13[3];
uchar uart_uip;
uchar res14[3];
uchar uart_uop1;
uchar res15[3];
uchar uart_uop0;
uchar res16[3];
} uart_t;
/* SDRAM controller registers, offset: 0x180
*/
typedef struct sdram_ctrl {
uchar res1[2];
ushort sdram_sdcr;
uchar res2[2];
ushort sdram_sdtr;
uchar res3[120];
} sdramctrl_t;
/* Timer module registers
*/
typedef struct timer_ctrl {
ushort timer_tmr;
ushort res1;
ushort timer_trr;
ushort res2;
ushort timer_tcap;
ushort res3;
ushort timer_tcn;
ushort res4;
ushort timer_ter;
uchar res5[14];
} timer_t;
/* Watchdog registers
*/
typedef struct wdog_ctrl {
ushort wdog_wrrr;
ushort res1;
ushort wdog_wirr;
ushort res2;
ushort wdog_wcr;
ushort res3;
ushort wdog_wer;
uchar res4[114];
} wdog_t;
/* PLIC module registers
*/
typedef struct plic_ctrl {
ulong plic_p0b1rr;
ulong plic_p1b1rr;
ulong plic_p2b1rr;
ulong plic_p3b1rr;
ulong plic_p0b2rr;
ulong plic_p1b2rr;
ulong plic_p2b2rr;
ulong plic_p3b2rr;
uchar plic_p0drr;
uchar plic_p1drr;
uchar plic_p2drr;
uchar plic_p3drr;
uchar res1[4];
ulong plic_p0b1tr;
ulong plic_p1b1tr;
ulong plic_p2b1tr;
ulong plic_p3b1tr;
ulong plic_p0b2tr;
ulong plic_p1b2tr;
ulong plic_p2b2tr;
ulong plic_p3b2tr;
uchar plic_p0dtr;
uchar plic_p1dtr;
uchar plic_p2dtr;
uchar plic_p3dtr;
uchar res2[4];
ushort plic_p0cr;
ushort plic_p1cr;
ushort plic_p2cr;
ushort plic_p3cr;
ushort plic_p0icr;
ushort plic_p1icr;
ushort plic_p2icr;
ushort plic_p3icr;
ushort plic_p0gmr;
ushort plic_p1gmr;
ushort plic_p2gmr;
ushort plic_p3gmr;
ushort plic_p0gmt;
ushort plic_p1gmt;
ushort plic_p2gmt;
ushort plic_p3gmt;
uchar res3;
uchar plic_pgmts;
uchar plic_pgmta;
uchar res4;
uchar plic_p0gcir;
uchar plic_p1gcir;
uchar plic_p2gcir;
uchar plic_p3gcir;
uchar plic_p0gcit;
uchar plic_p1gcit;
uchar plic_p2gcit;
uchar plic_p3gcit;
uchar res5[3];
uchar plic_pgcitsr;
uchar res6[3];
uchar plic_pdcsr;
ushort plic_p0psr;
ushort plic_p1psr;
ushort plic_p2psr;
ushort plic_p3psr;
ushort plic_pasr;
uchar res7;
uchar plic_plcr;
ushort res8;
ushort plic_pdrqr;
ushort plic_p0sdr;
ushort plic_p1sdr;
ushort plic_p2sdr;
ushort plic_p3sdr;
ushort res9;
ushort plic_pcsr;
uchar res10[1184];
} plic_t;
/* Fast ethernet controller registers
*/
typedef struct fec {
uint fec_ecntrl; /* ethernet control register */
uint fec_ievent; /* interrupt event register */
uint fec_imask; /* interrupt mask register */
uint fec_ivec; /* interrupt level and vector status */
uint fec_r_des_active; /* Rx ring updated flag */
uint fec_x_des_active; /* Tx ring updated flag */
uint res3[10]; /* reserved */
uint fec_mii_data; /* MII data register */
uint fec_mii_speed; /* MII speed control register */
uint res4[17]; /* reserved */
uint fec_r_bound; /* end of RAM (read-only) */
uint fec_r_fstart; /* Rx FIFO start address */
uint res5[6]; /* reserved */
uint fec_x_fstart; /* Tx FIFO start address */
uint res7[21]; /* reserved */
uint fec_r_cntrl; /* Rx control register */
uint fec_r_hash; /* Rx hash register */
uint res8[14]; /* reserved */
uint fec_x_cntrl; /* Tx control register */
uint res9[0x9e]; /* reserved */
uint fec_addr_low; /* lower 32 bits of station address */
uint fec_addr_high; /* upper 16 bits of station address */
uint fec_hash_table_high; /* upper 32-bits of hash table */
uint fec_hash_table_low; /* lower 32-bits of hash table */
uint fec_r_des_start; /* beginning of Rx descriptor ring */
uint fec_x_des_start; /* beginning of Tx descriptor ring */
uint fec_r_buff_size; /* Rx buffer size */
uint res2[9]; /* reserved */
uchar fec_fifo[960]; /* fifo RAM */
} fec_t;
/* USB module registers
*/
typedef struct usb {
ushort res1;
ushort usb_fnr;
ushort res2;
ushort usb_fnmr;
ushort res3;
ushort usb_rfmr;
ushort res4;
ushort usb_rfmmr;
uchar res5[3];
uchar usb_far;
ulong usb_asr;
ulong usb_drr1;
ulong usb_drr2;
ushort res6;
ushort usb_specr;
ushort res7;
ushort usb_ep0sr;
ulong usb_iep0cfg;
ulong usb_oep0cfg;
ulong usb_ep1cfg;
ulong usb_ep2cfg;
ulong usb_ep3cfg;
ulong usb_ep4cfg;
ulong usb_ep5cfg;
ulong usb_ep6cfg;
ulong usb_ep7cfg;
ulong usb_ep0ctl;
ushort res8;
ushort usb_ep1ctl;
ushort res9;
ushort usb_ep2ctl;
ushort res10;
ushort usb_ep3ctl;
ushort res11;
ushort usb_ep4ctl;
ushort res12;
ushort usb_ep5ctl;
ushort res13;
ushort usb_ep6ctl;
ushort res14;
ushort usb_ep7ctl;
ulong usb_ep0isr;
ushort res15;
ushort usb_ep1isr;
ushort res16;
ushort usb_ep2isr;
ushort res17;
ushort usb_ep3isr;
ushort res18;
ushort usb_ep4isr;
ushort res19;
ushort usb_ep5isr;
ushort res20;
ushort usb_ep6isr;
ushort res21;
ushort usb_ep7isr;
ulong usb_ep0imr;
ushort res22;
ushort usb_ep1imr;
ushort res23;
ushort usb_ep2imr;
ushort res24;
ushort usb_ep3imr;
ushort res25;
ushort usb_ep4imr;
ushort res26;
ushort usb_ep5imr;
ushort res27;
ushort usb_ep6imr;
ushort res28;
ushort usb_ep7imr;
ulong usb_ep0dr;
ulong usb_ep1dr;
ulong usb_ep2dr;
ulong usb_ep3dr;
ulong usb_ep4dr;
ulong usb_ep5dr;
ulong usb_ep6dr;
ulong usb_ep7dr;
ushort res29;
ushort usb_ep0dpr;
ushort res30;
ushort usb_ep1dpr;
ushort res31;
ushort usb_ep2dpr;
ushort res32;
ushort usb_ep3dpr;
ushort res33;
ushort usb_ep4dpr;
ushort res34;
ushort usb_ep5dpr;
ushort res35;
ushort usb_ep6dpr;
ushort res36;
ushort usb_ep7dpr;
uchar res37[788];
uchar usb_cfgram[1024];
} usb_t;
/* Internal memory map.
*/
typedef struct immap {
sysctrl_t sysctrl_reg; /* System configuration registers */
intctrl_t intctrl_reg; /* Interrupt controller registers */
csctrl_t csctrl_reg; /* Chip select controller registers */
gpio_t gpio_reg; /* GPIO controller registers */
qspi_t qspi_reg; /* QSPI controller registers */
pwm_t pwm_reg; /* Pulse width modulation registers */
dma_t dma_reg; /* DMA registers */
uart_t uart_reg[2]; /* UART registers */
sdramctrl_t sdram_reg; /* SDRAM controller registers */
timer_t timer_reg[4]; /* Timer registers */
wdog_t wdog_reg; /* Watchdog registers */
plic_t plic_reg; /* Physical layer interface registers */
fec_t fec_reg; /* Fast ethernet controller registers */
usb_t usb_reg; /* USB controller registers */
} immap_t;
#endif /* __IMMAP_5272__ */

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/*
* MCF5282 Internal Memory Map
*
* Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5282__
#define __IMMAP_5282__
/* Fast ethernet controller registers
*/
typedef struct fec {
uint fec_ecntrl; /* ethernet control register */
uint fec_ievent; /* interrupt event register */
uint fec_imask; /* interrupt mask register */
uint fec_ivec; /* interrupt level and vector status */
uint fec_r_des_active; /* Rx ring updated flag */
uint fec_x_des_active; /* Tx ring updated flag */
uint res3[10]; /* reserved */
uint fec_mii_data; /* MII data register */
uint fec_mii_speed; /* MII speed control register */
uint res4[17]; /* reserved */
uint fec_r_bound; /* end of RAM (read-only) */
uint fec_r_fstart; /* Rx FIFO start address */
uint res5[6]; /* reserved */
uint fec_x_fstart; /* Tx FIFO start address */
uint res7[21]; /* reserved */
uint fec_r_cntrl; /* Rx control register */
uint fec_r_hash; /* Rx hash register */
uint res8[14]; /* reserved */
uint fec_x_cntrl; /* Tx control register */
uint res9[0x9e]; /* reserved */
uint fec_addr_low; /* lower 32 bits of station address */
uint fec_addr_high; /* upper 16 bits of station address */
uint fec_hash_table_high; /* upper 32-bits of hash table */
uint fec_hash_table_low; /* lower 32-bits of hash table */
uint fec_r_des_start; /* beginning of Rx descriptor ring */
uint fec_x_des_start; /* beginning of Tx descriptor ring */
uint fec_r_buff_size; /* Rx buffer size */
uint res2[9]; /* reserved */
uchar fec_fifo[960]; /* fifo RAM */
} fec_t;
#endif /* __IMMAP_5282__ */

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/*
* mcf5272.h -- Definitions for Motorola Coldfire 5272
*
* Based on mcf5272sim.h of uCLinux distribution:
* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef mcf5272_h
#define mcf5272_h
/****************************************************************************/
/*
* Size of internal RAM
*/
#define INT_RAM_SIZE 4096
/*
* Define the 5272 SIM register set addresses.
*/
#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */
#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/
#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */
#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */
#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */
#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */
#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */
#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */
#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */
#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */
#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */
#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */
#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */
#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */
#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */
#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */
#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */
#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */
#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */
#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */
#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */
#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */
#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */
#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */
#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */
#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */
#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */
#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */
#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */
#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */
#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */
#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */
#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */
#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */
#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */
#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */
#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */
#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */
#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */
#endif /* mcf5272_h */

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/*
* mcf5282.h -- Definitions for Motorola Coldfire 5282
*
* Based on mcf5282sim.h of uCLinux distribution:
* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/****************************************************************************/
#ifndef m5282_h
#define m5282_h
/****************************************************************************/
/*
* Size of internal RAM
*/
#define INT_RAM_SIZE 65536
/*
* Define the 5282 SIM register set addresses.
*/
#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
#define MCFINTC_IRLR 0x18 /* */
#define MCFINTC_IACKL 0x19 /* */
#define MCFINTC_ICR0 0x40 /* Base ICR register */
#define MCFINT_UART0 13 /* Interrupt number for UART0 */
#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
#define MCF5282_GPIO_PUAPAR 0x10005C
/****************************************************************************/
#endif /* m5282_h */

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/*
* mcftimer.h -- ColdFire internal TIMER support defines.
*
* Based on mcftimer.h of uCLinux distribution:
* (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/****************************************************************************/
#ifndef mcftimer_h
#define mcftimer_h
/****************************************************************************/
#include <linux/config.h>
/*
* Get address specific defines for this ColdFire member.
*/
#if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */
#elif defined(CONFIG_M5272)
#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */
#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */
#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */
#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */
#elif defined(CONFIG_M5282)
#define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */
#define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */
#define MCFTIMER_BASE4 0x180000 /* Base address of TIMER3 */
#endif
/*
* Define the TIMER register set addresses.
*/
#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */
#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */
#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */
#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */
#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
/*
* Define the TIMER register set addresses for 5282.
*/
#define MCFTIMER_PCSR 0
#define MCFTIMER_PMR 1
#define MCFTIMER_PCNTR 2
/*
* Bit definitions for the Timer Mode Register (TMR).
* Register bit flags are common accross ColdFires.
*/
#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */
#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */
#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */
#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */
#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */
#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */
#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */
#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */
#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */
#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */
#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */
#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */
#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */
#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */
#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */
/*
* Bit definitions for the Timer Event Registers (TER).
*/
#define MCFTIMER_TER_CAP 0x01 /* Capture event */
#define MCFTIMER_TER_REF 0x02 /* Refernece event */
/*
* Bit definitions for the 5282 PIT Control and Status Register (PCSR).
*/
#define MCFTIMER_PCSR_EN 0x0001
#define MCFTIMER_PCSR_RLD 0x0002
#define MCFTIMER_PCSR_PIF 0x0004
#define MCFTIMER_PCSR_PIE 0x0008
#define MCFTIMER_PCSR_OVW 0x0010
#define MCFTIMER_PCSR_HALTED 0x0020
#define MCFTIMER_PCSR_DOZE 0x0040
/****************************************************************************/
#endif /* mcftimer_h */

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/*
* mcfuart.h -- ColdFire internal UART support defines.
*
* File copied from mcfuart.h of uCLinux distribution:
* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/****************************************************************************/
#ifndef mcfuart_h
#define mcfuart_h
/****************************************************************************/
#include <linux/config.h>
/*
* Define the base address of the UARTS within the MBAR address
* space.
*/
#if defined(CONFIG_M5272)
#define MCFUART_BASE1 0x100 /* Base address of UART1 */
#define MCFUART_BASE2 0x140 /* Base address of UART2 */
#elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
#if defined(CONFIG_NETtel)
#define MCFUART_BASE1 0x180 /* Base address of UART1 */
#define MCFUART_BASE2 0x140 /* Base address of UART2 */
#else
#define MCFUART_BASE1 0x140 /* Base address of UART1 */
#define MCFUART_BASE2 0x180 /* Base address of UART2 */
#endif
#elif defined(CONFIG_M5282)
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
#define MCFUART_BASE2 0x240 /* Base address of UART2 */
#define MCFUART_BASE3 0x280 /* Base address of UART3 */
#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
#if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
#else
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
#endif
#endif
/*
* Define the ColdFire UART register set addresses.
*/
#define MCFUART_UMR 0x00 /* Mode register (r/w) */
#define MCFUART_USR 0x04 /* Status register (r) */
#define MCFUART_UCSR 0x04 /* Clock Select (w) */
#define MCFUART_UCR 0x08 /* Command register (w) */
#define MCFUART_URB 0x0c /* Receiver Buffer (r) */
#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
#define MCFUART_UISR 0x14 /* Interrup Status (r) */
#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
#ifdef CONFIG_M5272
#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
#else
#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
#endif
#define MCFUART_UIPR 0x34 /* Input Port (r) */
#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
/*
* Define bit flags in Mode Register 1 (MR1).
*/
#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */
#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */
#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */
#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */
#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */
#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */
#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */
#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */
#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */
/*
* Define bit flags in Mode Register 2 (MR2).
*/
#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */
#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */
#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */
#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */
#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */
#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */
/*
* Define bit flags in Status Register (USR).
*/
#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */
#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */
#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */
#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */
#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */
#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */
#define MCFUART_USR_RXFULL 0x02 /* Receiver full */
#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */
#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
/*
* Define bit flags in Clock Select Register (UCSR).
*/
#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */
#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */
#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */
#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */
#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */
/*
* Define bit flags in Command Register (UCR).
*/
#define MCFUART_UCR_CMDNULL 0x00 /* No command */
#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */
#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */
#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */
#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */
#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */
#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */
#define MCFUART_UCR_TXNULL 0x00 /* No TX command */
#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */
#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */
#define MCFUART_UCR_RXNULL 0x00 /* No RX command */
#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */
#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */
/*
* Define bit flags in Input Port Change Register (UIPCR).
*/
#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */
#define MCFUART_UIPCR_CTS 0x01 /* CTS value */
/*
* Define bit flags in Input Port Register (UIP).
*/
#define MCFUART_UIPR_CTS 0x01 /* CTS value */
/*
* Define bit flags in Output Port Registers (UOP).
* Clear bit by writing to UOP0, set by writing to UOP1.
*/
#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */
/*
* Define bit flags in the Auxiliary Control Register (UACR).
*/
#define MCFUART_UACR_IEC 0x01 /* Input enable control */
/*
* Define bit flags in Interrupt Status Register (UISR).
* These same bits are used for the Interrupt Mask Register (UIMR).
*/
#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */
#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */
#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */
#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */
#ifdef CONFIG_M5272
/*
* Define bit flags in the Transmitter FIFO Register (UTF).
*/
#define MCFUART_UTF_TXB 0x1f /* transmitter data level */
#define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */
#define MCFUART_UTF_TXS 0xc0 /* transmitter status */
/*
* Define bit flags in the Receiver FIFO Register (URF).
*/
#define MCFUART_URF_RXB 0x1f /* receiver data level */
#define MCFUART_URF_FULL 0x20 /* receiver fifo full */
#define MCFUART_URF_RXS 0xc0 /* receiver status */
#endif
/****************************************************************************/
#endif /* mcfuart_h */

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#ifndef __ASM_M68K_PROCESSOR_H
#define __ASM_M68K_PROCESSOR_H
#include <asm/ptrace.h>
#include <asm/types.h>
#define _GLOBAL(n)\
.globl n;\
n:
/* Macros for setting and retrieving special purpose registers */
#define setvbr(v) asm volatile("movec %0,%%VBR" : : "r" (v))
#ifndef __ASSEMBLY__
#endif /* ifndef ASSEMBLY*/
#endif /* __ASM_M68K_PROCESSOR_H */

144
include/asm-m68k/ptrace.h
View File

@ -1,107 +1,59 @@
/*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _M68K_PTRACE_H
#define _M68K_PTRACE_H
/*
* This struct defines the way the registers are stored on the
* kernel stack during a system call or other kernel entry.
*
* this should only contain volatile regs
* since we can keep non-volatile in the thread_struct
* should set this up when only volatiles are saved
* by intr code.
*
* Since this is going on the stack, *CARE MUST BE TAKEN* to insure
* that the overall structure is a multiple of 16 bytes in length.
*
* Note that the offsets of the fields in this struct correspond with
* the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c.
* kernel stack during an exception.
*/
#include <linux/config.h>
#ifndef __ASSEMBLY__
#ifdef CONFIG_M68K64BRIDGE
#define M68K_REG unsigned long /*long*/
#else
#define M68K_REG unsigned long
#endif
struct pt_regs {
M68K_REG gpr[32];
M68K_REG nip;
M68K_REG msr;
M68K_REG orig_gpr3; /* Used for restarting system calls */
M68K_REG ctr;
M68K_REG link;
M68K_REG xer;
M68K_REG ccr;
M68K_REG mq; /* 601 only (not used at present) */
/* Used on APUS to hold IPL value. */
M68K_REG trap; /* Reason for being here */
M68K_REG dar; /* Fault registers */
M68K_REG dsisr;
M68K_REG result; /* Result of a system call */
ulong d0;
ulong d1;
ulong d2;
ulong d3;
ulong d4;
ulong d5;
ulong d6;
ulong d7;
ulong a0;
ulong a1;
ulong a2;
ulong a3;
ulong a4;
ulong a5;
ulong a6;
#if defined(CONFIG_M5272) || defined(CONFIG_M5282)
unsigned format : 4; /* frame format specifier */
unsigned vector : 12; /* vector offset */
unsigned short sr;
unsigned long pc;
#else
unsigned short sr;
unsigned long pc;
#endif
};
#endif
#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
#endif /* #ifndef __ASSEMBLY__ */
/* Size of stack frame allocated when calling signal handler. */
#define __SIGNAL_FRAMESIZE 64
#define instruction_pointer(regs) ((regs)->nip)
#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
/*
* Offsets used by 'ptrace' system call interface.
* These can't be changed without breaking binary compatibility
* with MkLinux, etc.
*/
#define PT_R0 0
#define PT_R1 1
#define PT_R2 2
#define PT_R3 3
#define PT_R4 4
#define PT_R5 5
#define PT_R6 6
#define PT_R7 7
#define PT_R8 8
#define PT_R9 9
#define PT_R10 10
#define PT_R11 11
#define PT_R12 12
#define PT_R13 13
#define PT_R14 14
#define PT_R15 15
#define PT_R16 16
#define PT_R17 17
#define PT_R18 18
#define PT_R19 19
#define PT_R20 20
#define PT_R21 21
#define PT_R22 22
#define PT_R23 23
#define PT_R24 24
#define PT_R25 25
#define PT_R26 26
#define PT_R27 27
#define PT_R28 28
#define PT_R29 29
#define PT_R30 30
#define PT_R31 31
#define PT_NIP 32
#define PT_MSR 33
#ifdef __KERNEL__
#define PT_ORIG_R3 34
#endif
#define PT_CTR 35
#define PT_LNK 36
#define PT_XER 37
#define PT_CCR 38
#define PT_MQ 39
#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
#define PT_FPR31 (PT_FPR0 + 2*31)
#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
#endif
#endif /* #ifndef _M68K_PTRACE_H */

23
include/asm-m68k/u-boot.h
View File

@ -38,10 +38,11 @@ typedef struct bd_info {
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
unsigned long bi_mbar_base; /* base of internal registers */
unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_ip_addr; /* IP Address */
unsigned char bi_enetaddr[6]; /* Ethernet adress */
unsigned char bi_enetaddr[6]; /* Ethernet adress */
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
@ -49,21 +50,5 @@ typedef struct bd_info {
} bd_t;
#endif /* __ASSEMBLY__ */
/* The following data structure is placed in DPRAM to allow for a
* minimum set of global variables during system initialization
* (until we have set up the memory controller so that we can use
* RAM).
*
* Keep it *SMALL* and remember to set CFG_INIT_DATA_SIZE > sizeof(init_data_t)
*/
typedef struct init_data {
unsigned long cpu_clk; /* VCOOUT = CPU clock in Hz! */
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long relocated; /* Relocat. offset when running in RAM */
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_LCD
unsigned long lcd_base; /* Base address of LCD frambuffer mem */
#endif
} init_data_t;
#endif /* __U_BOOT_H__ */

3
include/common.h
View File

@ -397,9 +397,10 @@ void get_sys_info ( sys_info_t * );
#if defined(CONFIG_8xx) || defined(CONFIG_8260)
void cpu_init_f (volatile immap_t *immr);
#endif
#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx)
#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2)
void cpu_init_f (void);
#endif
int cpu_init_r (void);
#if defined(CONFIG_8260)
int prt_8260_rsr (void);

217
include/configs/M5272C3.h
View File

@ -1,40 +1,189 @@
#ifndef _CONFIG_M5272C3_H
#define _CONFIG_M5272C3_H
/*
* Configuation settings for the Motorola MC5272C3 board.
*
* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) )
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5
/*
* board/config.h - configuration options, board specific
*/
#define CFG_MAX_FLASH_SECT 11
#define CFG_CACHELINE_SIZE 16
#define CFG_MALLOC_LEN (256 << 10)
#define CFG_INIT_RAM_ADDR 0x20000000
#define CFG_INIT_RAM_SIZE 0x1000
#define CFG_INIT_DATA_OFFSET 0
#define CONFIG_BAUDRATE 19200
#define CFG_MONITOR_BASE 0x3e0000
#define CFG_MONITOR_LEN 0x20000
#define CFG_SDRAM_BASE 0
#define CFG_FLASH_BASE 0xffe00000
#define CFG_PROMPT "MCF5272C3> "
#define CFG_CBSIZE 1024
#define CFG_MAXARGS 64
#define CFG_LOAD_ADDR 0x20000
#define CFG_BOOTMAPSZ 0
#define CFG_BARGSIZE CFG_CBSIZE
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#define CFG_ENV_ADDR 0xffe04000
#define CFG_ENV_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_PBSIZE 1024
#define CFG_MAX_FLASH_BANKS 1
#define CFG_MEMTEST_START 0x400
#define CFG_MEMTEST_END 0x380000
#define CFG_HZ 1000000
#define CFG_FLASH_ERASE_TOUT 10000000
#ifndef _M5272C3_H
#define _M5272C3_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5272 /* define processor type */
#define FEC_ENET
#define CONFIG_M5272
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#endif /* _CONFIG_M5272C3_H */
#define CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CFG_ENV_OFFSET 0x4000
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_IS_EMBEDDED 1
#else
#define CFG_ENV_ADDR 0xffe04000
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#endif
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) | \
CFG_CMD_MII)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5
#define CFG_PROMPT "-> "
#define CFG_LONGHELP /* undef to save memory */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x20000
#define CFG_MEMTEST_START 0x400
#define CFG_MEMTEST_END 0x380000
#define CFG_HZ 1000
#define CFG_CLK 66000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CFG_MBAR 0x10000000 /* Register Base Addrs */
#define CFG_SCR 0x0003;
#define CFG_SPR 0xffff;
#define CFG_DISCOVER_PHY
#define CFG_ENET_BD_BASE 0x380000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */
#define CFG_FLASH_BASE 0xffe00000
#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CFG_MONITOR_BASE 0x20000
#else
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
#endif
#define CFG_MONITOR_LEN 0x20000
#define CFG_MALLOC_LEN (256 << 10)
#define CFG_BOOTPARAMS_LEN 64*1024
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 1000
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
#define CFG_BR0_PRELIM 0xFFE00201
#define CFG_OR0_PRELIM 0xFFE00014
#define CFG_BR1_PRELIM 0
#define CFG_OR1_PRELIM 0
#define CFG_BR2_PRELIM 0x30000001
#define CFG_OR2_PRELIM 0xFFF80000
#define CFG_BR3_PRELIM 0
#define CFG_OR3_PRELIM 0
#define CFG_BR4_PRELIM 0
#define CFG_OR4_PRELIM 0
#define CFG_BR5_PRELIM 0
#define CFG_OR5_PRELIM 0
#define CFG_BR6_PRELIM 0
#define CFG_OR6_PRELIM 0
#define CFG_BR7_PRELIM 0x00000701
#define CFG_OR7_PRELIM 0xFFC0007C
/*-----------------------------------------------------------------------
* Port configuration
*/
#define CFG_PACNT 0x00000000
#define CFG_PADDR 0x0000
#define CFG_PADAT 0x0000
#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */
#define CFG_PBDDR 0x0000
#define CFG_PBDAT 0x0000
#define CFG_PDCNT 0x00000000
#endif /* _M5272C3_H */

175
include/configs/M5282EVB.h
View File

@ -1,40 +1,151 @@
/*
* Configuation settings for the Motorola MC5282EVB board.
*
* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _CONFIG_M5282EVB_H
#define _CONFIG_M5282EVB_H
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) )
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5
#define CFG_MAX_FLASH_SECT 35
#define CFG_CACHELINE_SIZE 16
#define CFG_MALLOC_LEN (256 << 10)
#define CFG_INIT_RAM_ADDR 0x20000000
#define CFG_INIT_RAM_SIZE 0x1000
#define CFG_INIT_DATA_OFFSET 0
#define CONFIG_BAUDRATE 19200
#define CFG_MONITOR_BASE 0x3e0000
#define CFG_MONITOR_LEN 0x20000
#define CFG_SDRAM_BASE 0
#define CFG_FLASH_BASE 0xffe00000
#define CFG_PROMPT "M5282EVB> "
#define CFG_CBSIZE 1024
#define CFG_MAXARGS 64
#define CFG_LOAD_ADDR 0x20000
#define CFG_BOOTMAPSZ 0
#define CFG_BARGSIZE CFG_CBSIZE
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#define CFG_ENV_ADDR 0xffe04000
#define CFG_ENV_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_PBSIZE 1024
#define CFG_MAX_FLASH_BANKS 1
#define CFG_MEMTEST_START 0x400
#define CFG_MEMTEST_END 0x380000
#define CFG_HZ 1000000
#define CFG_FLASH_ERASE_TOUT 10000000
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5282 /* define processor type */
#define FEC_ENET
#define CONFIG_M5282
#define CONFIG_BAUDRATE 19200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#define CFG_ENV_ADDR 0xffe04000
#define CFG_ENV_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5
#define CFG_PROMPT "-> "
#define CFG_LONGHELP /* undef to save memory */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x20000
#define CFG_MEMTEST_START 0x400
#define CFG_MEMTEST_END 0x380000
#define CFG_HZ 1000000
#define CFG_CLK 64000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CFG_MBAR 0x40000000
#undef CFG_DISCOVER_PHY
#define CFG_ENET_BD_BASE 0x380000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */
#define CFG_FLASH_BASE 0xffe00000
#define CFG_INT_FLASH_BASE 0xf0000000
/* If M5282 port is fully implemented the monitor base will be behind
* the vector table. */
/* #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) */
#define CFG_MONITOR_BASE 0x20000
#define CFG_MONITOR_LEN 0x20000
#define CFG_MALLOC_LEN (256 << 10)
#define CFG_BOOTPARAMS_LEN 64*1024
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_SECT 35
#define CFG_MAX_FLASH_BANKS 1
#define CFG_FLASH_ERASE_TOUT 10000000
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
/*-----------------------------------------------------------------------
* Port configuration
*/
#endif /* _CONFIG_M5282EVB_H */

1
include/configs/ppmc8260.h
View File

@ -445,6 +445,7 @@
*/
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_FLASH_INCREMENT 0 /* there is only one bank */

12
include/flash.h
View File

@ -44,6 +44,7 @@ typedef struct {
ulong buffer_write_tout; /* maximum buffer write timeout */
ushort vendor; /* the primary vendor id */
ushort cmd_reset; /* Vendor specific reset command */
ushort interface; /* used for x8/x16 adjustments */
#endif
} flash_info_t;
@ -61,6 +62,14 @@ typedef struct {
#define FLASH_CFI_BY16 0x02
#define FLASH_CFI_BY32 0x04
#define FLASH_CFI_BY64 0x08
/* convert between bit value and numeric value */
#define CFI_FLASH_SHIFT_WIDTH 3
/*
* Values for the flash device interface
*/
#define FLASH_CFI_X8 0x00
#define FLASH_CFI_X16 0x01
#define FLASH_CFI_X8X16 0x02
/* convert between bit value and numeric value */
#define CFI_FLASH_SHIFT_WIDTH 3
@ -185,6 +194,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
#define FUJI_ID_29F800BA 0x22582258 /* MBM29F800BA ID (8M) */
#define FUJI_ID_29F800TA 0x22D622D6 /* MBM29F800TA ID (8M) */
#define FUJI_ID_29LV650UE 0x22d722d7 /* MBM29LV650UE/651UE ID (8M = 128 x 32kWord) */
#define SST_ID_xF200A 0x27892789 /* 39xF200A ID ( 2M = 128K x 16 ) */
#define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */
@ -340,6 +350,8 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
#define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */
#define FLASH_AMDL163B 0x00B3
#define FLASH_FUJLV650 0x00B4 /* Fujitsu MBM 29LV650UE/651UE */
#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */

42
lib_m68k/Makefile Normal file
View File

@ -0,0 +1,42 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(ARCH).a
AOBJS =
COBJS = cache.o traps.o time.o board.o m68k_linux.o
OBJS = $(AOBJS) $(COBJS)
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
$(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
sinclude .depend
#########################################################################

602
lib_m68k/board.c
View File

@ -1,5 +1,8 @@
/*
* (C) Copyright 2000-2003
* (C) Copyright 2003
* Josef Baumgartner <josef.baumgartner@telex.de>
*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -26,7 +29,11 @@
#include <command.h>
#include <malloc.h>
#include <devices.h>
#include <syscall.h>
#ifdef CONFIG_M5272
#include <asm/immap_5272.h>
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE)
#include <ide.h>
#endif
@ -54,18 +61,8 @@ static char *failed = "*** failed ***\n";
extern flash_info_t flash_info[];
#endif
#if defined(CFG_ENV_IS_IN_FLASH)
# ifndef CFG_ENV_ADDR
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
# endif
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
# if (CFG_ENV_ADDR >= CFG_MONITOR_BASE) && \
(CFG_ENV_ADDR+CFG_ENV_SIZE) < (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
# define ENV_IS_EMBEDDED
# endif
#endif /* CFG_ENV_IS_IN_FLASH */
#include <environment.h>
#if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \
(CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \
defined(CFG_ENV_IS_IN_NVRAM)
@ -74,12 +71,30 @@ extern flash_info_t flash_info[];
#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN
#endif
extern ulong __init_end;
extern ulong _end;
extern void timer_init(void);
#if defined(CONFIG_WATCHDOG)
# define INIT_FUNC_WATCHDOG_INIT watchdog_init,
# define WATCHDOG_DISABLE watchdog_disable
extern int watchdog_init(void);
extern int watchdog_disable(void);
#else
# define INIT_FUNC_WATCHDOG_INIT /* undef */
# define WATCHDOG_DISABLE /* undef */
#endif /* CONFIG_WATCHDOG */
ulong monitor_flash_len;
/*
* Begin and End of memory area for malloc(), and current "brk"
*/
static ulong mem_malloc_start = 0;
static ulong mem_malloc_end = 0;
static ulong mem_malloc_brk = 0;
static ulong mem_malloc_start = 0;
static ulong mem_malloc_end = 0;
static ulong mem_malloc_brk = 0;
/************************************************************************
* Utilities *
@ -89,13 +104,18 @@ static ulong mem_malloc_brk = 0;
/*
* The Malloc area is immediately below the monitor copy in DRAM
*/
static void mem_malloc_init (ulong dest_addr)
static void mem_malloc_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
ulong dest_addr = CFG_MONITOR_BASE + gd->reloc_off;
mem_malloc_end = dest_addr;
mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN;
mem_malloc_brk = mem_malloc_start;
memset ((void *) mem_malloc_start, 0,
memset ((void *) mem_malloc_start,
0,
mem_malloc_end - mem_malloc_start);
}
@ -104,50 +124,106 @@ void *sbrk (ptrdiff_t increment)
ulong old = mem_malloc_brk;
ulong new = old + increment;
if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
if ((new < mem_malloc_start) ||
(new > mem_malloc_end) ) {
return (NULL);
}
mem_malloc_brk = new;
return ((void *) old);
return ((void *)old);
}
char *strmhz (char *buf, long hz)
char *strmhz(char *buf, long hz)
{
long l, n;
long m;
long l, n;
long m;
n = hz / 1000000L;
n = hz / 1000000L;
l = sprintf (buf, "%ld", n);
l = sprintf (buf, "%ld", n);
m = (hz % 1000000L) / 1000L;
m = (hz % 1000000L) / 1000L;
if (m != 0)
sprintf (buf + l, ".%03ld", m);
if (m != 0)
sprintf (buf+l, ".%03ld", m);
return (buf);
return (buf);
}
static void syscalls_init (int reloc_off)
/*
* All attempts to come up with a "common" initialization sequence
* that works for all boards and architectures failed: some of the
* requirements are just _too_ different. To get rid of the resulting
* mess of board dependend #ifdef'ed code we now make the whole
* initialization sequence configurable to the user.
*
* The requirements for any new initalization function is simple: it
* receives a pointer to the "global data" structure as it's only
* argument, and returns an integer return code, where 0 means
* "continue" and != 0 means "fatal error, hang the system".
*/
typedef int (init_fnc_t) (void);
/************************************************************************
* Init Utilities *
************************************************************************
* Some of this code should be moved into the core functions,
* but let's get it working (again) first...
*/
static int init_baudrate (void)
{
ulong *addr;
DECLARE_GLOBAL_DATA_PTR;
addr = (ulong *) syscall_tbl;
syscall_tbl[SYSCALL_MALLOC] = (void *) malloc;
syscall_tbl[SYSCALL_FREE] = (void *) free;
uchar tmp[64]; /* long enough for environment variables */
int i = getenv_r ("baudrate", tmp, sizeof (tmp));
syscall_tbl[SYSCALL_INSTALL_HDLR] = (void *) irq_install_handler;
syscall_tbl[SYSCALL_FREE_HDLR] = (void *) irq_free_handler;
addr = (ulong *) 0xc00; /* syscall ISR addr */
/* patch ISR code */
*addr++ |= (ulong) syscall_tbl >> 16;
*addr++ |= (ulong) syscall_tbl & 0xFFFF;
*addr++ |= NR_SYSCALLS >> 16;
*addr++ |= NR_SYSCALLS & 0xFFFF;
gd->baudrate = (i > 0)
? (int) simple_strtoul (tmp, NULL, 10)
: CONFIG_BAUDRATE;
return (0);
}
/***********************************************************************/
static int init_func_ram (void)
{
DECLARE_GLOBAL_DATA_PTR;
int board_type = 0; /* use dummy arg */
puts ("DRAM: ");
if ((gd->ram_size = initdram (board_type)) > 0) {
print_size (gd->ram_size, "\n");
return (0);
}
puts (failed);
return (1);
}
/***********************************************************************/
/************************************************************************
* Initialization sequence *
************************************************************************
*/
init_fnc_t *init_sequence[] = {
env_init,
init_baudrate,
serial_init,
console_init_f,
display_options,
checkcpu,
checkboard,
init_func_ram,
#if defined(CFG_DRAM_TEST)
testdram,
#endif /* CFG_DRAM_TEST */
INIT_FUNC_WATCHDOG_INIT
NULL, /* Terminate this list */
};
/************************************************************************
*
* This is the first part of the initialization sequence that is
@ -164,133 +240,147 @@ static void syscalls_init (int reloc_off)
************************************************************************
*/
gd_t *global_data;
static gd_t gdata;
static bd_t bdata;
void board_init_f (ulong bootflag)
void
board_init_f (ulong bootflag)
{
DECLARE_GLOBAL_DATA_PTR;
DECLARE_GLOBAL_DATA_PTR;
bd_t *bd;
ulong reg, len, addr, addr_sp, dram_size;
int i, baudrate, board_type;
char *s, *e;
ulong len, addr, addr_sp;
gd_t *id;
init_fnc_t **init_fnc_ptr;
#ifdef CONFIG_PRAM
int i;
ulong reg;
uchar tmp[64]; /* long enough for environment variables */
#endif
/* Pointer to initial global data area */
gd = global_data = &gdata;
bd = gd->bd = &bdata;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
init_timebase ();
env_init ();
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
i = getenv_r ("baudrate", tmp, sizeof (tmp));
baudrate =
(i > 0) ? (int) simple_strtoul (tmp, NULL,
10) : CONFIG_BAUDRATE;
bd->bi_baudrate = baudrate; /* Console Baudrate */
/* set up serial port */
serial_init ();
/* Initialize the console (before the relocation) */
console_init_f ();
#ifdef DEBUG
if (sizeof (init_data_t) > CFG_INIT_DATA_SIZE) {
printf ("PANIC: sizeof(init_data_t)=%d > CFG_INIT_DATA_SIZE=%d\n", sizeof (init_data_t), CFG_INIT_DATA_SIZE);
hang ();
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0) {
hang ();
}
}
#endif /* DEBUG */
/* now we can use standard printf/puts/getc/tstc functions */
display_options ();
puts ("CPU: "); /* Check CPU */
if (checkcpu () < 0) {
puts (failed);
hang ();
}
puts ("Board: "); /* Check Board */
if ((board_type = checkboard ()) < 0) {
puts (failed);
hang ();
}
puts ("DRAM: ");
if ((dram_size = initdram (board_type)) > 0) {
printf ("%2ld MB\n", dram_size >> 20);
} else {
puts (failed);
hang ();
}
#if defined(CFG_DRAM_TEST)
if (testdram () != 0) {
hang ();
}
#endif /* CFG_DRAM_TEST */
/*
* Now that we have DRAM mapped and working, we can
* relocate the code and continue running from DRAM.
*
* Reserve memory at end of RAM for (top down in that order):
* - protected RAM
* - LCD framebuffer
* - monitor code
* - board info struct
* - protected RAM
* - LCD framebuffer
* - monitor code
* - board info struct
*/
len = get_endaddr () - CFG_MONITOR_BASE;
len = (ulong)&_end - CFG_MONITOR_BASE;
if (len > CFG_MONITOR_LEN) {
printf ("*** u-boot size %ld > reserved memory (%d)\n",
len, CFG_MONITOR_LEN);
hang ();
}
addr = CFG_SDRAM_BASE + gd->ram_size;
if (CFG_MONITOR_LEN > len)
len = CFG_MONITOR_LEN;
#ifdef CONFIG_LOGBUFFER
/* reserve kernel log buffer */
addr -= (LOGBUFF_RESERVE);
debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr);
#endif
addr = CFG_SDRAM_BASE + dram_size;
#ifdef CONFIG_PRAM
/*
* reserve protected RAM
*/
i = getenv_r ("pram", tmp, sizeof (tmp));
reg = (i > 0) ? simple_strtoul (tmp, NULL, 10) : CONFIG_PRAM;
addr -= (reg << 10); /* size is in kB */
debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
#endif /* CONFIG_PRAM */
/*
* reserve memory for U-Boot code, data & bss
* round down to next 4 kB limit
*/
addr -= len;
addr &= ~(4096 - 1);
debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
/*
* reserve memory for malloc() arena
*/
addr_sp = addr - TOTAL_MALLOC_LEN;
debug ("Reserving %dk for malloc() at: %08lx\n",
TOTAL_MALLOC_LEN >> 10, addr_sp);
/*
* (permanently) allocate a Board Info struct
* and a permanent copy of the "global" data
*/
addr_sp -= sizeof (bd_t);
bd = (bd_t *) addr_sp;
gd->bd = bd;
debug ("Reserving %d Bytes for Board Info at: %08lx\n",
sizeof (bd_t), addr_sp);
addr_sp -= sizeof (gd_t);
id = (gd_t *) addr_sp;
debug ("Reserving %d Bytes for Global Data at: %08lx\n",
sizeof (gd_t), addr_sp);
/* Reserve memory for boot params. */
addr_sp -= CFG_BOOTPARAMS_LEN;
bd->bi_boot_params = addr_sp;
debug ("Reserving %dk for boot parameters at: %08lx\n",
CFG_BOOTPARAMS_LEN >> 10, addr_sp);
/*
* Finally, we set up a new (bigger) stack.
*
* Leave some safety gap for SP, force alignment on 16 byte boundary
* Clear initial stack frame
*/
addr_sp -= 16;
addr_sp &= ~0xF;
*((ulong *) addr_sp)-- = 0;
*((ulong *) addr_sp)-- = 0;
debug ("Stack Pointer at: %08lx\n", addr_sp);
/*
* Save local variables to board info struct
*/
bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */
bd->bi_memsize = dram_size; /* size of DRAM memory in bytes */
bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */
bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */
bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */
i = getenv_r ("ethaddr", tmp, sizeof (tmp));
s = (i > 0) ? tmp : NULL;
bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */
for (reg = 0; reg < 6; ++reg) {
bd->bi_enetaddr[reg] = s ? simple_strtoul (s, &e, 16) : 0;
if (s)
s = (*e) ? e + 1 : e;
}
bd->bi_intfreq = get_gclk_freq (); /* Internal Freq, in Hz */
bd->bi_busfreq = get_bus_freq (get_gclk_freq ()); /* Bus Freq, in Hz */
WATCHDOG_RESET ();
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
#ifdef CFG_EXTBDINFO
strncpy (bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
strncpy (bd->bi_r_version, PPCBOOT_VERSION,
sizeof (bd->bi_r_version));
bd->bi_procfreq = get_gclk_freq (); /* Processor Speed, In Hz */
bd->bi_plb_busfreq = bd->bi_busfreq;
strncpy (bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version));
#endif
board_init_final (addr);
WATCHDOG_RESET ();
#ifdef CONFIG_POST
post_bootmode_init();
post_run (NULL, POST_ROM | post_bootmode_get(0));
#endif
WATCHDOG_RESET();
memcpy (id, (void *)gd, sizeof (gd_t));
debug ("Start relocate of code from %08x to %08lx\n", CFG_MONITOR_BASE, addr);
relocate_code (addr_sp, id, addr);
/* NOTREACHED - jump_to_ram() does not return */
}
/************************************************************************
*
* This is the next part if the initialization sequence: we are now
@ -300,61 +390,123 @@ void board_init_f (ulong bootflag)
*
************************************************************************
*/
void board_init_final (ulong dest_addr)
void board_init_r (gd_t *id, ulong dest_addr)
{
DECLARE_GLOBAL_DATA_PTR;
char *s;
cmd_tbl_t *cmdtp;
ulong flash_size;
char *s, *e;
bd_t *bd;
int i;
extern void malloc_bin_reloc (void);
#ifndef CFG_ENV_IS_NOWHERE
extern char * env_name_spec;
#endif
#ifndef CFG_NO_FLASH
ulong flash_size;
#endif
gd = id; /* initialize RAM version of global data */
bd = gd->bd;
/* icache_enable(); /XX* it's time to enable the instruction cache */
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
WATCHDOG_RESET ();
gd->reloc_off = dest_addr - CFG_MONITOR_BASE;
monitor_flash_len = (ulong)&__init_end - dest_addr;
/*
* We have to relocate the command table manually
*/
for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
ulong addr;
addr = (ulong) (cmdtp->cmd) + gd->reloc_off;
#if 0
printf ("Command \"%s\": 0x%08lx => 0x%08lx\n",
cmdtp->name, (ulong) (cmdtp->cmd), addr);
#endif
cmdtp->cmd =
(int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
addr = (ulong)(cmdtp->name) + gd->reloc_off;
cmdtp->name = (char *)addr;
if (cmdtp->usage) {
addr = (ulong)(cmdtp->usage) + gd->reloc_off;
cmdtp->usage = (char *)addr;
}
#ifdef CFG_LONGHELP
if (cmdtp->help) {
addr = (ulong)(cmdtp->help) + gd->reloc_off;
cmdtp->help = (char *)addr;
}
#endif
}
/* there are some other pointer constants we must deal with */
#ifndef CFG_ENV_IS_NOWHERE
env_name_spec += gd->reloc_off;
#endif
WATCHDOG_RESET ();
#ifdef CONFIG_LOGBUFFER
logbuff_init_ptrs ();
#endif
#ifdef CONFIG_POST
post_output_backlog ();
post_reloc ();
#endif
WATCHDOG_RESET();
#if 0
/* instruction cache enabled in cpu_init_f() for faster relocation */
icache_enable (); /* it's time to enable the instruction cache */
#endif
/*
* Setup trap handlers
*/
trap_init (dest_addr);
trap_init (0);
#if !defined(CFG_NO_FLASH)
puts ("FLASH: ");
if ((flash_size = flash_init ()) > 0) {
#ifdef CFG_FLASH_CHECKSUM
if (flash_size >= (1 << 20)) {
printf ("%2ld MB", flash_size >> 20);
} else {
printf ("%2ld kB", flash_size >> 10);
}
# ifdef CFG_FLASH_CHECKSUM
print_size (flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
s = getenv ("flashchecksum");
if (s && (*s == 'y')) {
printf (" CRC: %08lX",
crc32 (0,
(const unsigned char *) CFG_FLASH_BASE,
flash_size)
);
crc32 (0,
(const unsigned char *) CFG_FLASH_BASE,
flash_size)
);
}
putc ('\n');
#else
if (flash_size >= (1 << 20)) {
printf ("%2ld MB\n", flash_size >> 20);
} else {
printf ("%2ld kB\n", flash_size >> 10);
}
#endif /* CFG_FLASH_CHECKSUM */
# else /* !CFG_FLASH_CHECKSUM */
print_size (flash_size, "\n");
# endif /* CFG_FLASH_CHECKSUM */
} else {
puts (failed);
hang ();
}
bd->bi_flashstart = CFG_FLASH_BASE; /* update start of FLASH memory */
bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
bd->bi_flashoffset = 0x10000; /* reserved area for startup monitor */
bd->bi_flashstart = CFG_FLASH_BASE; /* update start of FLASH memory */
bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
bd->bi_flashoffset = 0;
#else /* CFG_NO_FLASH */
bd->bi_flashsize = 0;
bd->bi_flashstart = 0;
bd->bi_flashoffset = 0;
#endif /* !CFG_NO_FLASH */
WATCHDOG_RESET ();
@ -364,7 +516,8 @@ void board_init_final (ulong dest_addr)
WATCHDOG_RESET ();
/* initialize malloc() area */
mem_malloc_init (dest_addr);
mem_malloc_init ();
malloc_bin_reloc ();
#ifdef CONFIG_SPI
# if !defined(CFG_ENV_IS_IN_EEPROM)
@ -376,36 +529,35 @@ void board_init_final (ulong dest_addr)
/* relocate environment function pointers etc. */
env_relocate ();
/*
* Fill in missing fields of bd_info.
* We do this here, where we have "normal" access to the
* environment; we used to do this still running from ROM,
* where had to use getenv_r(), which can be pretty slow when
* the environment is in EEPROM.
*/
s = getenv ("ethaddr");
for (i = 0; i < 6; ++i) {
bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
if (s)
s = (*e) ? e + 1 : e;
}
/* IP Address */
bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
WATCHDOG_RESET ();
/* allocate syscalls table (console_init_r will fill it in */
syscall_tbl = (void **) malloc (NR_SYSCALLS * sizeof (void *));
/** leave this here (after malloc(), environment and PCI are working) **/
/* Initialize devices */
devices_init ();
/* Initialize the jump table for applications */
jumptable_init ();
/* Initialize the console (after the relocation and devices init) */
#if (CONFIG_COMMANDS & CFG_CMD_NET) && ( \
defined(CONFIG_CCM) || \
defined(CONFIG_EP8260) || \
defined(CONFIG_IP860) || \
defined(CONFIG_IVML24) || \
defined(CONFIG_IVMS8) || \
defined(CONFIG_LWMON) || \
defined(CONFIG_MPC8260ADS) || \
defined(CONFIG_PCU_E) || \
defined(CONFIG_RPXSUPER) || \
defined(CONFIG_SPD823TS) )
WATCHDOG_RESET ();
# ifdef DEBUG
puts ("Reset Ethernet PHY\n");
# endif
reset_phy ();
#endif
console_init_r ();
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
WATCHDOG_RESET ();
@ -413,11 +565,28 @@ void board_init_final (ulong dest_addr)
kgdb_init ();
#endif
debug ("U-Boot relocated to %08lx\n", dest_addr);
/*
* Enable Interrupts
*/
interrupt_init ();
/* Must happen after interrupts are initialized since
* an irq handler gets installed
*/
timer_init();
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
serial_buffered_init();
#endif
#ifdef CONFIG_STATUS_LED
status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
#endif
udelay (20);
set_timer (0);
/* Insert function pointers now that we have relocated the code */
@ -434,10 +603,25 @@ void board_init_final (ulong dest_addr)
WATCHDOG_RESET ();
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
WATCHDOG_RESET ();
puts ("Net: ");
eth_initialize (bd);
puts ("DOC: ");
doc_init ();
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
WATCHDOG_RESET ();
puts ("NAND:");
nand_init(); /* go init the NAND */
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
WATCHDOG_RESET();
eth_init(bd);
#endif
#ifdef CONFIG_POST
post_run (NULL, POST_RAM | post_bootmode_get(0));
#endif
#ifdef CONFIG_LAST_STAGE_INIT
@ -455,26 +639,51 @@ void board_init_final (ulong dest_addr)
bedbug_init ();
#endif
#ifdef CONFIG_PRAM
#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
/*
* Export available size of memory for Linux,
* taking into account the protected RAM at top of memory
*/
{
ulong pram;
char *s;
uchar memsz[32];
#ifdef CONFIG_PRAM
char *s;
if ((s = getenv ("pram")) != NULL) {
pram = simple_strtoul (s, NULL, 10);
} else {
pram = CONFIG_PRAM;
}
#else
pram=0;
#endif
#ifdef CONFIG_LOGBUFFER
/* Also take the logbuffer into account (pram is in kB) */
pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024;
#endif
sprintf (memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
setenv ("mem", memsz);
}
#endif
#ifdef CONFIG_MODEM_SUPPORT
{
extern int do_mdm_init;
do_mdm_init = gd->do_mdm_init;
}
#endif
#ifdef CONFIG_WATCHDOG
/* disable watchdog if environment is set */
if ((s = getenv ("watchdog")) != NULL) {
if (strncmp (s, "off", 3) == 0) {
WATCHDOG_DISABLE ();
}
}
#endif /* CONFIG_WATCHDOG*/
/* Initialization complete - start the monitor */
/* main_loop() can return to retry autoboot, if so just run it again. */
@ -486,7 +695,8 @@ void board_init_final (ulong dest_addr)
/* NOTREACHED - no way out of command loop except booting */
}
void hang (void)
void hang(void)
{
puts ("### ERROR ### Please RESET the board ###\n");
for (;;);

11
cpu/coldfire/fec.h → lib_m68k/cache.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -21,8 +21,9 @@
* MA 02111-1307 USA
*/
#ifndef _FEC_H_
#define _FEC_H_
#include <common.h>
#endif /* _FEC_H_ */
void flush_cache (ulong start_addr, ulong size)
{
/* Must be implemented for all M68k processors with copy-back data cache */
}

83
lib_m68k/extable.c
View File

@ -1,83 +0,0 @@
/*
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
/*
* The exception table consists of pairs of addresses: the first is the
* address of an instruction that is allowed to fault, and the second is
* the address at which the program should continue. No registers are
* modified, so it is entirely up to the continuation code to figure out
* what to do.
*
* All the routines below use bits of fixup code that are out of line
* with the main instruction path. This means when everything is well,
* we don't even have to jump over them. Further, they do not intrude
* on our cache or tlb entries.
*/
struct exception_table_entry {
unsigned long insn, fixup;
};
extern const struct exception_table_entry __start___ex_table[];
extern const struct exception_table_entry __stop___ex_table[];
static inline unsigned long
search_one_table (const struct exception_table_entry *first,
const struct exception_table_entry *last,
unsigned long value)
{
while (first <= last) {
const struct exception_table_entry *mid;
long diff;
mid = (last - first) / 2 + first;
diff = mid->insn - value;
if (diff == 0)
return mid->fixup;
else if (diff < 0)
first = mid + 1;
else
last = mid - 1;
}
return 0;
}
int ex_tab_message = 1;
unsigned long search_exception_table (unsigned long addr)
{
unsigned long ret;
/* There is only the kernel to search. */
ret = search_one_table (__start___ex_table, __stop___ex_table - 1,
addr);
if (ex_tab_message)
printf ("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret);
if (ret)
return ret;
return 0;
}

16
lib_m68k/m68k_linux.c
View File

@ -12,26 +12,25 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
#include <command.h>
#include <cmd_boot.h>
#include <image.h>
#include <zlib.h>
#include <asm/byteorder.h>
#define PHYSADDR(x) x
#define LINUX_MAX_ENVS 256
#define LINUX_MAX_ARGS 256
#define LINUX_MAX_ENVS 256
#define LINUX_MAX_ARGS 256
#ifdef CONFIG_SHOW_BOOT_PROGRESS
# include <status_led.h>
@ -42,6 +41,8 @@
extern image_header_t header; /* from cmd_bootm.c */
extern int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
static int linux_argc;
static char **linux_argv;
@ -52,7 +53,6 @@ static int linux_env_idx;
static void linux_params_init (ulong start, char *commandline);
static void linux_env_set (char *env_name, char *env_val);
void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
ulong addr, ulong * len_ptr, int verify)
{
@ -123,9 +123,9 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
SHOW_BOOT_PROGRESS (11);
if ((hdr->ih_os != IH_OS_LINUX) ||
(hdr->ih_arch != IH_CPU_MIPS) ||
(hdr->ih_arch != IH_CPU_M68K) ||
(hdr->ih_type != IH_TYPE_RAMDISK)) {
printf ("No Linux MIPS Ramdisk Image\n");
printf ("No Linux M68K Ramdisk Image\n");
SHOW_BOOT_PROGRESS (-13);
do_reset (cmdtp, flag, argc, argv);
}

182
lib_m68k/time.c
View File

@ -1,5 +1,7 @@
/*
* (C) Copyright 2000-2003
* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -12,7 +14,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -23,65 +25,149 @@
#include <common.h>
#include <asm/mcftimer.h>
/* ------------------------------------------------------------------------- */
#ifdef CONFIG_M5272
#include <asm/m5272.h>
#include <asm/immap_5272.h>
#endif
#ifdef CONFIG_M5282
#include <asm/m5282.h>
#endif
static ulong timestamp;
#ifdef CONFIG_M5282
static unsigned short lastinc;
#endif
#if defined(CONFIG_M5272)
/*
* This function is intended for SHORT delays only.
* It will overflow at around 10 seconds @ 400MHz,
* or 20 seconds @ 200MHz.
*/
unsigned long usec2ticks(unsigned long usec)
{
ulong ticks;
if (usec < 1000) {
ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
} else {
ticks = ((usec / 10) * (get_tbclk() / 100000));
}
return (ticks);
}
/* ------------------------------------------------------------------------- */
/*
* We implement the delay by converting the delay (the number of
* microseconds to wait) into a number of time base ticks; then we
* watch the time base until it has incremented by that amount.
* We use timer 3 which is running with a period of 1 us
*/
void udelay(unsigned long usec)
{
ulong ticks = usec2ticks (usec);
volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE3);
uint start, now, tmp;
wait_ticks (ticks);
while (usec > 0) {
if (usec > 65000)
tmp = 65000;
else
tmp = usec;
usec = usec - tmp;
/* Set up TIMER 3 as timebase clock */
timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
timerp->timer_tcn = 0;
/* set period to 1 us */
timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE;
start = now = timerp->timer_tcn;
while (now < start + tmp)
now = timerp->timer_tcn;
}
}
/* ------------------------------------------------------------------------- */
void mcf_timer_interrupt (void * not_used){
volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
unsigned long ticks2usec(unsigned long ticks)
/* check for timer 4 interrupts */
if ((intp->int_isr & 0x01000000) != 0) {
return;
}
/* reset timer */
timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
timestamp ++;
}
void timer_init (void) {
volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
timestamp = 0;
/* Set up TIMER 4 as clock */
timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
/* initialize and enable timer 4 interrupt */
irq_install_handler (72, mcf_timer_interrupt, 0);
intp->int_icr1 |= 0x0000000d;
timerp->timer_tcn = 0;
timerp->timer_trr = 1000; /* Interrupt every ms */
/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
}
void reset_timer (void)
{
ulong tbclk = get_tbclk();
/* usec = ticks * 1000000 / tbclk
* Multiplication would overflow at ~4.2e3 ticks,
* so we break it up into
* usec = ( ( ticks * 1000) / tbclk ) * 1000;
*/
ticks *= 1000L;
ticks /= tbclk;
ticks *= 1000L;
return ((ulong)ticks);
timestamp = 0;
}
/* ------------------------------------------------------------------------- */
int init_timebase (void)
ulong get_timer (ulong base)
{
/* FIXME!! */
return 0;
return (timestamp - base);
}
/* ------------------------------------------------------------------------- */
void set_timer (ulong t)
{
timestamp = t;
}
#endif
#if defined(CONFIG_M5282)
void udelay(unsigned long usec)
{
}
void timer_init (void)
{
volatile unsigned short *timerp;
timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
timestamp = 0;
/* Set up TIMER 4 as poll clock */
timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
timerp[MCFTIMER_PMR] = lastinc = 0;
timerp[MCFTIMER_PCSR] =
(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
}
void set_timer (ulong t)
{
volatile unsigned short *timerp;
timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
timestamp = 0;
timerp[MCFTIMER_PMR] = lastinc = 0;
}
ulong get_timer (ulong base)
{
unsigned short now, diff;
volatile unsigned short *timerp;
timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
now = timerp[MCFTIMER_PCNTR];
diff = -(now - lastinc);
timestamp += diff;
lastinc = now;
return timestamp - base;
}
void wait_ticks (unsigned long ticks)
{
set_timer (0);
while (get_timer (0) < ticks);
}
#endif

76
lib_m68k/traps.c Normal file
View File

@ -0,0 +1,76 @@
/*
* (C) Copyright 2003
* Josef Baumgartner <josef.baumgartner@telex.de>
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/processor.h>
extern void _exc_handler(void);
extern void _int_handler(void);
static void show_frame(struct pt_regs *fp)
{
printf ("Vector Number: %d Format: %02x Fault Status: %01x\n\n", (fp->vector & 0x3fc) >> 2,
fp->format, (fp->vector & 0x3) | ((fp->vector & 0xc00) >> 8));
printf ("PC: %08lx SR: %08lx SP: %08lx\n", fp->pc, (long) fp->sr, (long) fp);
printf ("D0: %08lx D1: %08lx D2: %08lx D3: %08lx\n",
fp->d0, fp->d1, fp->d2, fp->d3);
printf ("D4: %08lx D5: %08lx D6: %08lx D7: %08lx\n",
fp->d4, fp->d5, fp->d6, fp->d7);
printf ("A0: %08lx A1: %08lx A2: %08lx A3: %08lx\n",
fp->a0, fp->a1, fp->a2, fp->a3);
printf ("A4: %08lx A5: %08lx A6: %08lx\n",
fp->a4, fp->a5, fp->a6);
}
void exc_handler(struct pt_regs *fp) {
printf("\n\n*** Unexpected exception ***\n");
show_frame (fp);
printf("\n*** Please Reset Board! ***\n");
for(;;);
}
void trap_init(ulong value) {
unsigned long *vec = (ulong *)value;
int i;
for(i = 2; i < 25; i++) {
vec[i] = (unsigned long)_exc_handler;
}
for(i = 25; i < 32; i++) {
vec[i] = (unsigned long)_int_handler;
}
for(i = 32; i < 64; i++) {
vec[i] = (unsigned long)_exc_handler;
}
for(i = 64; i < 256; i++) {
vec[i] = (unsigned long)_int_handler;
}
setvbr(value); /* set vector base register to new table */
}