sysmo-bts
/
barebox
9
0
Fork 0
Code Releases Activity

Initial e500v2 start up code 

This is the first part of the start-up code. The source code origin is
U-boot and is slightly modified to have e500v2 CPU support in 32-bit
mode only.
It includes the power-up entry point, CPU initialization code and
exports definition for D-cache flush and I-cache invalidate.

Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Renaud Barbier 2012-05-17 17:49:44 +01:00 committed by Sascha Hauer
parent 16e2a4295d
commit ac28dd8620
3 changed files with 1089 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/ppc/cpu-85xx/resetvec.S Normal file
View File

@ -0,0 +1,2 @@
.section .resetvec,"ax"
b _start_e500

1085
arch/ppc/cpu-85xx/start.S Normal file
View File

File diff suppressed because it is too large Load Diff

2
arch/ppc/include/asm/cache.h
View File

@ -31,6 +31,8 @@
extern void flush_dcache_range(unsigned long start, unsigned long stop);
extern void clean_dcache_range(unsigned long start, unsigned long stop);
extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
extern void flush_dcache(void);
extern void invalidate_icache(void);
#ifdef CFG_INIT_RAM_LOCK
extern void unlock_ram_in_cache(void);
#endif /* CFG_INIT_RAM_LOCK */