sysmo-bts
/
barebox
9
0
Fork 0
Code Releases Activity

ARM: i.MX: ccxmx51: detect SDRAM size by board id 

This partly reverts:

commit 697e02b74f
Author: Alexander Shiyan <shc_work@mail.ru>
Date:   Tue Jan 22 15:08:31 2013 +0400

    ARM: ccmx51: Remove SDRAM size settings

    This patch removes SDRAM memory size setting from board due
    to auto detect last one by ESDCTL.

    Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
    Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The board originally configured the SDRAM controller for the
maximum size and detected the usable SDRAM size by reading the
board id. This became broken after switching to automatic SDRAM
size detection by reading back ESDCTL values.

This patch brings back the old behaviour.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer 2013-04-26 23:48:36 +02:00
parent ef0299f172
commit a7ae099b36
3 changed files with 39 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

55
arch/arm/boards/ccxmx51/ccxmx51.c
View File

@ -46,30 +46,31 @@
#include <mach/clock-imx51_53.h>
#include <mach/imx5.h>
#include <mach/revision.h>
#include <mach/esdctl.h>
#include "ccxmx51.h"
static struct ccxmx51_ident ccxmx51_ids[] = {
/* 0x00 */ { "Unknown", 0, 0, 0, 0 },
/* 0x01 */ { "Not supported", 0, 0, 0, 0 },
/* 0x02 */ { "i.MX515@800MHz, Wireless, PHY, Ext. Eth, Accel", 0, 1, 1, 1 },
/* 0x03 */ { "i.MX515@800MHz, PHY, Ext. Eth, Accel", 0, 1, 1, 0 },
/* 0x04 */ { "i.MX515@600MHz, Wireless, PHY, Ext. Eth, Accel", 1, 1, 1, 1 },
/* 0x05 */ { "i.MX515@600MHz, PHY, Ext. Eth, Accel", 1, 1, 1, 0 },
/* 0x06 */ { "i.MX515@800MHz, Wireless, PHY, Accel", 0, 1, 0, 1 },
/* 0x07 */ { "i.MX515@800MHz, PHY, Accel", 0, 1, 0, 0 },
/* 0x08 */ { "i.MX515@800MHz, Wireless, PHY, Accel", 0, 1, 0, 1 },
/* 0x09 */ { "i.MX515@800MHz, PHY, Accel", 0, 1, 0, 0 },
/* 0x0a */ { "i.MX515@600MHz, Wireless, PHY, Accel", 1, 1, 0, 1 },
/* 0x0b */ { "i.MX515@600MHz, PHY, Accel", 1, 1, 0, 0 },
/* 0x0c */ { "i.MX515@800MHz, Wireless, PHY, Accel", 0, 1, 0, 1 },
/* 0x0d */ { "i.MX512@800MHz", 0, 0, 0, 0 },
/* 0x0e */ { "i.MX515@800MHz, Wireless, PHY, Accel", 0, 1, 0, 1 },
/* 0x0f */ { "i.MX515@600MHz, PHY, Accel", 1, 1, 0, 0 },
/* 0x10 */ { "i.MX515@600MHz, Wireless, PHY, Accel", 1, 1, 0, 1 },
/* 0x11 */ { "i.MX515@800MHz, PHY, Accel", 0, 1, 0, 0 },
/* 0x12 */ { "i.MX515@600MHz, Wireless, PHY, Accel", 1, 1, 0, 1 },
/* 0x13 */ { "i.MX515@800MHz, PHY, Accel", 0, 1, 0, 0 },
/* 0x00 */ { "Unknown", 0, 0, 0, 0, 0 },
/* 0x01 */ { "Not supported", 0, 0, 0, 0, 0 },
/* 0x02 */ { "i.MX515@800MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 0, 1, 1, 1 },
/* 0x03 */ { "i.MX515@800MHz, PHY, Ext. Eth, Accel", SZ_512M, 0, 1, 1, 0 },
/* 0x04 */ { "i.MX515@600MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 1, 1, 1, 1 },
/* 0x05 */ { "i.MX515@600MHz, PHY, Ext. Eth, Accel", SZ_512M, 1, 1, 1, 0 },
/* 0x06 */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_512M, 0, 1, 0, 1 },
/* 0x07 */ { "i.MX515@800MHz, PHY, Accel", SZ_512M, 0, 1, 0, 0 },
/* 0x08 */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_256M, 0, 1, 0, 1 },
/* 0x09 */ { "i.MX515@800MHz, PHY, Accel", SZ_256M, 0, 1, 0, 0 },
/* 0x0a */ { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_256M, 1, 1, 0, 1 },
/* 0x0b */ { "i.MX515@600MHz, PHY, Accel", SZ_256M, 1, 1, 0, 0 },
/* 0x0c */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_128M, 0, 1, 0, 1 },
/* 0x0d */ { "i.MX512@800MHz", SZ_128M, 0, 0, 0, 0 },
/* 0x0e */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_512M, 0, 1, 0, 1 },
/* 0x0f */ { "i.MX515@600MHz, PHY, Accel", SZ_128M, 1, 1, 0, 0 },
/* 0x10 */ { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_128M, 1, 1, 0, 1 },
/* 0x11 */ { "i.MX515@800MHz, PHY, Accel", SZ_128M, 0, 1, 0, 0 },
/* 0x12 */ { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_512M, 1, 1, 0, 1 },
/* 0x13 */ { "i.MX515@800MHz, PHY, Accel", SZ_512M, 0, 1, 0, 0 },
};
struct ccxmx51_ident *ccxmx51_id;
@ -339,6 +340,18 @@ static int ccxmx51_power_init(void)
return 0;
}
/*
* On this board the SDRAM is always configured for 512Mib. The real
* size is determined by the board id read from the IIM module.
*/
static int ccxm51_sdram_fixup(void)
{
imx_esdctl_disable();
return 0;
}
postcore_initcall(ccxm51_sdram_fixup);
static int ccxmx51_devices_init(void)
{
u8 hwid[6];
@ -368,6 +381,8 @@ static int ccxmx51_devices_init(void)
break;
}
printf("Module Serial : %c%d\n", manloc, ((hwid[2] & 0x3f) << 24) | (hwid[3] << 16) | (hwid[4] << 8) | hwid[5]);
if ((ccxmx51_id->mem_sz - SZ_128M) > 0)
arm_add_mem_device("ram1", MX51_CSD0_BASE_ADDR + SZ_128M, ccxmx51_id->mem_sz - SZ_128M);
}
imx51_add_uart1();

1
arch/arm/boards/ccxmx51/ccxmx51.h
View File

@ -23,6 +23,7 @@ struct ccxmx51_hwid {
struct ccxmx51_ident {
const char *id_string;
const int mem_sz;
const char industrial;
const char eth0;
const char eth1;

4
arch/arm/boards/ccxmx51/lowlevel.c
View File

@ -1,9 +1,11 @@
#include <common.h>
#include <mach/esdctl.h>
#include <asm/barebox-arm.h>
#include <asm/barebox-arm-head.h>
#include <mach/imx51-regs.h>
void __naked barebox_arm_reset_vector(void)
{
arm_cpu_lowlevel_init();
imx51_barebox_entry(0);
barebox_arm_entry(MX51_CSD0_BASE_ADDR, SZ_128M, 0);
}