add Support for Freescale MX35 3Stack Board
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
7d304edb7a
commit
9a252f1ac9
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@ -12,6 +12,7 @@ config ARCH_TEXT_BASE
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default 0x87f00000 if MACH_PCM037
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default 0x23f00000 if MACH_AT91SAM9260_EK
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default 0x23f00000 if MACH_PM9263
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default 0x80000000 if MACH_FREESCALE_MX35_3STACK
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config BOARDINFO
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default "Synertronixx scb9328" if MACH_SCB9328
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@ -21,6 +22,7 @@ config BOARDINFO
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default "Phytec phyCORE-i.MX31" if MACH_PCM037
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default "Atmel 91SAM9260-EK" if MACH_AT91SAM9260_EK
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default "Ronetix PM9263" if MACH_PM9263
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default "Freescale MX35 3Stack" if MACH_FREESCALE_MX35_3STACK
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config BOARD_LINKER_SCRIPT
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bool
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@ -132,6 +134,15 @@ config MACH_IMX27ADS
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Say Y here if you are using the Freescale i.MX27ads board equipped
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with a Freescale i.MX27 Processor
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config MACH_FREESCALE_MX35_3STACK
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bool "Freescale MX35 3stack"
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select HAS_CFI
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select ARCH_IMX35
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select MACH_HAS_LOWLEVEL_INIT
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help
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Say Y here if you are using the Freescale MX35 3stack board equipped
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with a Freescale i.MX35 Processor
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config MACH_ECO920
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bool "eco920"
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select HAS_AT91_ETHER
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@ -17,6 +17,7 @@ board-$(CONFIG_MACH_PCM037) := pcm037
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board-$(CONFIG_MACH_OMAP) := omap
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board-$(CONFIG_MACH_AT91SAM9260_EK):= at91sam9260ek
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board-$(CONFIG_MACH_PM9263) := pm9263
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board-$(CONFIG_MACH_FREESCALE_MX35_3STACK) := freescale-mx35-3-stack
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# FIXME "cpu-y" never used on ARM!
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cpu-$(CONFIG_ARM920T) := arm920t
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@ -0,0 +1,217 @@
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/*
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <net.h>
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#include <cfi_flash.h>
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#include <init.h>
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#include <environment.h>
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#include <asm/arch/imx-regs.h>
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#include <fec.h>
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#include <asm/arch/gpio.h>
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#include <asm/armlinux.h>
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#include <asm/mach-types.h>
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#include <asm/arch/pmic.h>
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#include <partition.h>
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#include <fs.h>
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#include <fcntl.h>
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#include <nand.h>
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#include <spi/spi.h>
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#include <asm/io.h>
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#include <asm/arch/imx-nand.h>
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static struct device_d cfi_dev = {
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.name = "cfi_flash",
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.id = "nor0",
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.map_base = 0xa0000000,
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.size = 64 * 1024 * 1024,
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};
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static struct device_d sdram_dev = {
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.name = "ram",
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.id = "ram0",
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.map_base = 0x80000000,
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.size = 128 * 1024 * 1024,
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.type = DEVICE_TYPE_DRAM,
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};
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static struct fec_platform_data fec_info = {
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.xcv_type = MII100,
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};
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static struct device_d fec_dev = {
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.name = "fec_imx27",
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.id = "eth0",
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.map_base = 0x50038000,
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.platform_data = &fec_info,
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.type = DEVICE_TYPE_ETHER,
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};
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/*
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* SMSC 9217 network controller
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*/
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static struct device_d smc911x_dev = {
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.name = "smc911x",
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.id = "eth0",
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.map_base = IMX_CS5_BASE,
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.size = IMX_CS5_RANGE, /* area size */
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.type = DEVICE_TYPE_ETHER,
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};
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static int f3s_devices_init(void)
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{
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imx_gpio_mode(MUX_FEC_TX_CLK_FEC_TX_CLK);
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imx_gpio_mode(MUX_FEC_RX_CLK_FEC_RX_CLK);
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imx_gpio_mode(MUX_FEC_RX_DV_FEC_RX_DV);
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imx_gpio_mode(MUX_FEC_COL_FEC_COL);
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imx_gpio_mode(MUX_FEC_TX_EN_FEC_TX_EN);
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imx_gpio_mode(MUX_FEC_MDC_FEC_MDC);
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imx_gpio_mode(MUX_FEC_MDIO_FEC_MDIO);
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imx_gpio_mode(MUX_FEC_TX_ERR_FEC_TX_ERR);
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imx_gpio_mode(MUX_FEC_RX_ERR_FEC_RX_ERR);
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imx_gpio_mode(MUX_FEC_CRS_FEC_CRS);
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imx_gpio_mode(MUX_FEC_RDATA0_FEC_RDATA0);
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imx_gpio_mode(MUX_FEC_TDATA0_FEC_TDATA0);
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imx_gpio_mode(MUX_FEC_RDATA1_FEC_RDATA1);
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imx_gpio_mode(MUX_FEC_TDATA1_FEC_TDATA1);
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imx_gpio_mode(MUX_FEC_RDATA2_FEC_RDATA2);
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imx_gpio_mode(MUX_FEC_TDATA2_FEC_TDATA2);
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imx_gpio_mode(MUX_FEC_RDATA3_FEC_RDATA3);
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imx_gpio_mode(MUX_FEC_TDATA3_FEC_TDATA3);
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register_device(&cfi_dev);
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register_device(&sdram_dev);
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register_device(&smc911x_dev);
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/* FEC is currently broken. It seems to work
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* shortly but after a few moments the board
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* goes to nirvana
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*/
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// register_device(&fec_dev);
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/*
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* Create partitions that should be
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* not touched by any regular user
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*/
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#ifdef CONFIG_PARTITION
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dev_add_partition(&cfi_dev, 0x00000, 0x40000, PARTITION_FIXED, "self"); /* ourself */
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dev_add_partition(&cfi_dev, 0x40000, 0x20000, PARTITION_FIXED, "env"); /* environment */
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#endif
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armlinux_set_bootparams((void *)0x80000100);
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armlinux_set_architecture(MACH_TYPE_PCM037); /* FIXME */
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return 0;
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}
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device_initcall(f3s_devices_init);
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static struct device_d f3s_serial_device = {
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.name = "imx_serial",
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.id = "cs0",
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.map_base = IMX_UART1_BASE,
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.size = 4096,
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.type = DEVICE_TYPE_CONSOLE,
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};
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static int f3s_console_init(void)
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{
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register_device(&f3s_serial_device);
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return 0;
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}
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console_initcall(f3s_console_init);
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static int f3s_core_setup(void)
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{
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u32 tmp;
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writel(0x0000D843, CSCR_U(5)); /* CS5: smc9117 */
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writel(0x22252521, CSCR_L(5));
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writel(0x22220A00, CSCR_A(5));
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/* FIXME: The rest is currently done in Assembler. Remove assembler
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* config once the board is running stable
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*/
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return 0;
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/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, IMX_AIPS1_BASE);
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writel(0x77777777, IMX_AIPS1_BASE + 0x4);
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writel(0x77777777, IMX_AIPS2_BASE);
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writel(0x77777777, IMX_AIPS2_BASE + 0x4);
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/*
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* Clear the on and off peripheral modules Supervisor Protect bit
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* for SDMA to access them. Did not change the AIPS control registers
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* (offset 0x20) access type
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*/
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writel(0x0, IMX_AIPS1_BASE + 0x40);
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writel(0x0, IMX_AIPS1_BASE + 0x44);
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writel(0x0, IMX_AIPS1_BASE + 0x48);
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writel(0x0, IMX_AIPS1_BASE + 0x4C);
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tmp = readl(IMX_AIPS1_BASE + 0x50);
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tmp &= 0x00FFFFFF;
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writel(tmp, IMX_AIPS1_BASE + 0x50);
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writel(0x0, IMX_AIPS2_BASE + 0x40);
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writel(0x0, IMX_AIPS2_BASE + 0x44);
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writel(0x0, IMX_AIPS2_BASE + 0x48);
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writel(0x0, IMX_AIPS2_BASE + 0x4C);
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tmp = readl(IMX_AIPS2_BASE + 0x50);
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tmp &= 0x00FFFFFF;
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writel(tmp, IMX_AIPS2_BASE + 0x50);
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/* MAX (Multi-Layer AHB Crossbar Switch) setup */
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/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
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#define MAX_PARAM1 0x00302154
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x0); /* for S0 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
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/* SGPCR - always park on last master */
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writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */
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writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */
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writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */
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writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */
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writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */
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/* MGPCR - restore default values */
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writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */
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writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */
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writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */
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writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */
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writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */
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writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */
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return 0;
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}
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core_initcall(f3s_core_setup);
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@ -0,0 +1,4 @@
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/** @page 3stack Freescale MX35 3-Stack Board
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*/
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@ -0,0 +1,3 @@
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obj-y += lowlevel_init.o
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obj-y += 3stack.o
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@ -0,0 +1,24 @@
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/**
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* @file
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* @brief Global defintions for the ARM i.MX27 based pcm038
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#endif /* __CONFIG_H */
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@ -0,0 +1,36 @@
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#!/bin/sh
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if [ -z "$part" -o -z "$image" ]; then
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echo "define \$part and \$image"
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exit 1
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fi
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if [ \! -e "$part" ]; then
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echo "Partition $part does not exist"
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exit 1
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fi
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if [ $# = 1 ]; then
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image=$1
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fi
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if [ x$ip = xdhcp ]; then
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dhcp
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fi
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ping $eth0.serverip
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if [ $? -ne 0 ] ; then
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echo "update aborted"
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exit 1
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fi
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unprotect $part
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echo
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echo "erasing partition $part"
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erase $part
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echo
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echo "flashing $image to $part"
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echo
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tftp $image $part
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@ -0,0 +1,47 @@
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#!/bin/sh
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. /env/config
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if [ x$1 = xnand ]; then
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root=nand
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kernel=nand
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fi
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if [ x$1 = xnet ]; then
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root=net
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kernel=net
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fi
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if [ x$1 = xnor ]; then
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root=nor
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kernel=nor
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fi
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if [ x$ip = xdhcp ]; then
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bootargs="$bootargs ip=dhcp"
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else
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bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
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fi
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if [ x$root = xnand ]; then
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bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
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elif [ x$root = xnor ]; then
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bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2"
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else
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bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
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fi
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bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;imx_nand:$nand_parts"
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if [ $kernel = net ]; then
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if [ x$ip = xdhcp ]; then
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dhcp
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fi
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tftp $uimage uImage || exit 1
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bootm uImage
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elif [ $kernel = nor ]; then
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bootm /dev/nor0.kernel
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else
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bootm /dev/nand0.kernel.bb
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fi
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@ -0,0 +1 @@
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nand -a /dev/nand0.*
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@ -0,0 +1,37 @@
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#!/bin/sh
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PATH=/env/bin
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export PATH
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. /env/config
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if [ -e /dev/nor0 ]; then
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addpart /dev/nor0 $nor_parts
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fi
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if [ -e /dev/nand0 ]; then
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addpart /dev/nand0 $nand_parts
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# Uh, oh, hush first expands wildcards and then starts executing
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# commands. What a bug!
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source /env/bin/hush_hack
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fi
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#if [ -z $eth0.ethaddr ]; then
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# while [ -z $eth0.ethaddr ]; do
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# readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
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# done
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# echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
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#fi
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echo
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echo -n "Hit any key to stop autoboot: "
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timeout -a $autoboot_timeout
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if [ $? != 0 ]; then
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echo
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echo "type update_kernel nand|nor [<imagename>] to update kernel into flash"
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echo "type update_root nand|nor [<imagename>] to update rootfs into flash"
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echo
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exit
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fi
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boot
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@ -0,0 +1,15 @@
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#!/bin/sh
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. /env/config
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image=$uimage
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if [ x$1 = xnand ]; then
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part=/dev/nand0.kernel.bb
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elif [ x$1 = xnor ]; then
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part=/dev/nor0.kernel
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else
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echo "usage: $0 nor|nand [imagename]"
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exit 1
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fi
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. /env/bin/_update $2
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@ -0,0 +1,16 @@
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#!/bin/sh
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. /env/config
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image=$uimage
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if [ x$1 = xnand ]; then
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part=/dev/nand0.root.bb
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elif [ x$1 = xnor ]; then
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part=/dev/nor0.root
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else
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echo "usage: $0 nor|nand [imagename]"
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exit 1
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fi
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. /env/bin/_update $2
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@ -0,0 +1,28 @@
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#!/bin/sh
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|
||||
# can be either 'net', 'nor' or 'nand''
|
||||
kernel=net
|
||||
root=net
|
||||
|
||||
uimage=uImage-pcm038
|
||||
jffs2=root-pcm038.jffs2
|
||||
|
||||
autoboot_timeout=3
|
||||
|
||||
nfsroot="/ptx/work/octopus/rsc/svn/oselas/bsp/phytec/phyCORE-i.MX27/OSELAS.BSP-Phytec-phyCORE-i.MX27-trunk/root"
|
||||
bootargs="console=ttymxc0,115200"
|
||||
|
||||
nor_parts="256k(uboot)ro,128k(ubootenv),1536k(kernel),-(root)"
|
||||
rootpart_nor="/dev/mtdblock3"
|
||||
|
||||
nand_parts="256k(uboot)ro,128k(ubootenv),1536k(kernel),-(root)"
|
||||
rootpart_nand="/dev/mtdblock7"
|
||||
|
||||
# use 'dhcp' to do dhcp in uboot and in kernel
|
||||
ip=dhcp
|
||||
|
||||
# or set your networking parameters here
|
||||
#eth0.ipaddr=a.b.c.d
|
||||
#eth0.netmask=a.b.c.d
|
||||
#eth0.gateway=a.b.c.d
|
||||
#eth0.serverip=a.b.c.d
|
||||
|
|
@ -0,0 +1,449 @@
|
|||
/*
|
||||
* For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
|
||||
* Applications Processor Reference Manual, Rev. 0.2".
|
||||
*
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define writel(val, reg) \
|
||||
ldr r0, =reg; \
|
||||
ldr r1, =val; \
|
||||
str r1, [r0];
|
||||
#define IIM_BASE_ADDR 0x53FF0000
|
||||
#define SDRAM_BASE_ADDR CSD0_BASE_ADDR
|
||||
#define CSD0_BASE_ADDR 0x80000000
|
||||
#define IIM_SREV_OFF 0x24
|
||||
#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
|
||||
#define AIPS1_BASE_ADDR 0x43F00000
|
||||
#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
|
||||
#define AIPS2_BASE_ADDR 0x53F00000
|
||||
#define MAX_BASE_ADDR 0x43F04000
|
||||
#define CLKCTL_BASE_ADDR 0x43F0C000
|
||||
#define ESDCTL_BASE 0xB8001000
|
||||
#define M3IF_BASE 0xB8003000
|
||||
#define IOMUXC_BASE_ADDR 0x43FAC000
|
||||
#define MPCTL_PARAM_399 (((1-1) << 26) + ((16-1) << 16) + (8 << 10) + (5 << 0))
|
||||
#define MPCTL_PARAM_532 ((1 << 31) + ((1-1) << 26) + ((12-1) << 16) + (11 << 10) + (1 << 0))
|
||||
#define PPCTL_PARAM_300 (((1-1) << 26) + ((4-1) << 16) + (6 << 10) + (1 << 0))
|
||||
#define SDRAM_SIZE 0x08000000
|
||||
#define CCM_BASE_ADDR 0x53F80000
|
||||
#define IPU_CTRL_BASE_ADDR 0x53FC0000
|
||||
#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50)
|
||||
#define WEIM_BASE_ADDR 0xB8002000
|
||||
#define WEIM_CTRL_CS0 WEIM_BASE_ADDR
|
||||
|
||||
ARM_PPMRR: .word 0x40000015
|
||||
L2CACHE_PARAM: .word 0x00030024
|
||||
IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
|
||||
AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
|
||||
AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
|
||||
AIPS1_PARAM_W: .word 0x77777777
|
||||
MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
|
||||
MAX_PARAM1: .word 0x00302154
|
||||
CLKCTL_BASE_ADDR_W: .word CLKCTL_BASE_ADDR
|
||||
ESDCTL_BASE_W: .word ESDCTL_BASE
|
||||
M3IF_BASE_W: .word M3IF_BASE
|
||||
RAM_PARAM1_MDDR: .word 0x00000400
|
||||
RAM_PARAM2_MDDR: .word 0x00000333
|
||||
RAM_PARAM3_MDDR: .word 0x02000400
|
||||
.word 0x02000000
|
||||
RAM_PARAM4_MDDR: .word 0x04000000
|
||||
RAM_PARAM5_MDDR: .word 0x06000000
|
||||
RAM_PARAM6_MDDR: .word 0x00000233
|
||||
.word 0x00000033
|
||||
RAM_PARAM7_MDDR: .word 0x02000780
|
||||
ESDCTL_0x92220000: .word 0x92220000
|
||||
ESDCTL_0xA2220000: .word 0xA2220000
|
||||
ESDCTL_0xB2220000: .word 0xB2220000
|
||||
ESDCTL_0x82226080: .word 0x82226080
|
||||
ESDCTL_CONFIG: .word 0x007FFC3F //DDR2
|
||||
.word 0x00295729 //MDDR
|
||||
ESDCTL_DELAY5: .word 0x00F49F00
|
||||
IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
|
||||
CCM_CCMR_W: .word 0x003F4208
|
||||
//CCM_PDR0_W: .word 0x00801000
|
||||
CCM_PDR0_W: .word 0x00801c00
|
||||
MPCTL_PARAM_399_W: .word MPCTL_PARAM_399
|
||||
MPCTL_PARAM_532_W: .word MPCTL_PARAM_532
|
||||
PPCTL_PARAM_W: .word PPCTL_PARAM_300
|
||||
MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
|
||||
CONST_0x0FFF: .word 0x0FFF
|
||||
CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
|
||||
IPU_CTRL_BASE_ADDR_W: .word IPU_CTRL_BASE_ADDR
|
||||
WEIM_CTRL_CS5_W: .word WEIM_CTRL_CS5
|
||||
WEIM_CTRL_CS0_W: .word WEIM_CTRL_CS0
|
||||
CS0_CSCRU_0x0000CC03: .word 0x0000DCF6
|
||||
CS0_CSCRL_0xA0330D01: .word 0x444A4541
|
||||
CS0_CSCRA_0x00220800: .word 0x44443302
|
||||
CS5_CSCRU_0x0000D843: .word 0x0000D843
|
||||
CS5_CSCRL_0x22252521: .word 0x22252521
|
||||
CS5_CSCRA_0x22220A00: .word 0x22220A00
|
||||
|
||||
#define L2CC_BASE_ADDR 0x30000000
|
||||
#define L2_CACHE_CTL_REG 0x100
|
||||
#define L2_CACHE_AUX_CTL_REG 0x104
|
||||
#define L2_CACHE_DBG_CTL_REG 0xF40
|
||||
#define L2_CACHE_INV_WAY_REG 0x77C
|
||||
|
||||
/* Assuming 24MHz input clock */
|
||||
/* PD MFD MFI MFN */
|
||||
#define MPCTL_PARAM_399 (((1-1) << 26) + ((16-1) << 16) + (8 << 10) + (5 << 0))
|
||||
#define MPCTL_PARAM_532 ((1 << 31) + ((1-1) << 26) + ((12-1) << 16) + (11 << 10) + (1 << 0))
|
||||
#define MPCTL_PARAM_665 (((1-1) << 26) + ((48-1) << 16) + (13 << 10) + (41 << 0))
|
||||
#define PPCTL_PARAM_300 (((1-1) << 26) + ((4-1) << 16) + (6 << 10) + (1 << 0))
|
||||
|
||||
#define M3IF_BASE 0xB8003000
|
||||
|
||||
#define UNALIGNED_ACCESS_ENABLE
|
||||
#define LOW_INT_LATENCY_ENABLE
|
||||
#define BRANCH_PREDICTION_ENABLE
|
||||
|
||||
.globl board_init_lowlevel
|
||||
board_init_lowlevel:
|
||||
mov r10, lr
|
||||
|
||||
mrc 15, 0, r1, c1, c0, 0
|
||||
bic r1, r1, #(0x3<<21)
|
||||
bic r1, r1, #(0x3<<11)
|
||||
bic r1, r1, #0x5
|
||||
|
||||
bic r1, r1, #(1<<3)
|
||||
|
||||
#ifndef BRANCH_PREDICTION_ENABLE
|
||||
mrc 15, 0, r0, c1, c0, 1
|
||||
bic r0, r0, #7
|
||||
mcr 15, 0, r0, c1, c0, 1
|
||||
#else
|
||||
mrc 15, 0, r0, c1, c0, 1
|
||||
orr r0, r0, #7
|
||||
mcr 15, 0, r0, c1, c0, 1
|
||||
orr r1, r1, #(1<<11)
|
||||
#endif
|
||||
|
||||
#ifdef UNALIGNED_ACCESS_ENABLE
|
||||
orr r1, r1, #(1<<22)
|
||||
#endif
|
||||
|
||||
#ifdef LOW_INT_LATENCY_ENABLE
|
||||
orr r1, r1, #(1<<21)
|
||||
#endif
|
||||
mcr 15, 0, r1, c1, c0, 0
|
||||
|
||||
#ifdef BRANCH_PREDICTION_ENABLE
|
||||
mov r0, #0
|
||||
mcr 15, 0, r0, c15, c2, 4
|
||||
#endif
|
||||
|
||||
mov r0, #0
|
||||
mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
|
||||
mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
|
||||
mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
|
||||
|
||||
/* Also setup the Peripheral Port Remap register inside the core */
|
||||
ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
|
||||
mcr p15, 0, r0, c15, c2, 4
|
||||
|
||||
/*** L2 Cache setup/invalidation/disable ***/
|
||||
/* Disable L2 cache first */
|
||||
mov r0, #L2CC_BASE_ADDR
|
||||
ldr r2, [r0, #L2_CACHE_CTL_REG]
|
||||
bic r2, r2, #0x1
|
||||
str r2, [r0, #L2_CACHE_CTL_REG]
|
||||
/*
|
||||
* Configure L2 Cache:
|
||||
* - 128k size(16k way)
|
||||
* - 8-way associativity
|
||||
* - 0 ws TAG/VALID/DIRTY
|
||||
* - 4 ws DATA R/W
|
||||
*/
|
||||
ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
|
||||
and r1, r1, #0xFE000000
|
||||
ldr r2, L2CACHE_PARAM
|
||||
orr r1, r1, r2
|
||||
str r1, [r0, #L2_CACHE_AUX_CTL_REG]
|
||||
/* Workaournd for DDR issue:WT*/
|
||||
ldr r1, [r0, #L2_CACHE_DBG_CTL_REG]
|
||||
orr r1, r1, #2
|
||||
str r1, [r0, #L2_CACHE_DBG_CTL_REG]
|
||||
|
||||
/* Invalidate L2 */
|
||||
mov r1, #0x000000FF
|
||||
str r1, [r0, #L2_CACHE_INV_WAY_REG]
|
||||
L2_loop:
|
||||
/* Poll Invalidate By Way register */
|
||||
ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
|
||||
cmp r2, #0
|
||||
bne L2_loop
|
||||
/*** End of L2 operations ***/
|
||||
|
||||
/*
|
||||
* End of ARM1136 init
|
||||
*/
|
||||
|
||||
/*
|
||||
* Set all MPROTx to be non-bufferable, trusted for R/W,
|
||||
* not forced to user-mode.
|
||||
*/
|
||||
ldr r0, AIPS1_CTRL_BASE_ADDR_W
|
||||
ldr r1, AIPS1_PARAM_W
|
||||
str r1, [r0, #0x00]
|
||||
str r1, [r0, #0x04]
|
||||
ldr r0, AIPS2_CTRL_BASE_ADDR_W
|
||||
str r1, [r0, #0x00]
|
||||
str r1, [r0, #0x04]
|
||||
|
||||
/*
|
||||
* Clear the on and off peripheral modules Supervisor Protect bit
|
||||
* for SDMA to access them. Did not change the AIPS control registers
|
||||
* (offset 0x20) access type
|
||||
*/
|
||||
ldr r0, AIPS1_CTRL_BASE_ADDR_W
|
||||
ldr r1, =0x0
|
||||
str r1, [r0, #0x40]
|
||||
str r1, [r0, #0x44]
|
||||
str r1, [r0, #0x48]
|
||||
str r1, [r0, #0x4C]
|
||||
ldr r1, [r0, #0x50]
|
||||
and r1, r1, #0x00FFFFFF
|
||||
str r1, [r0, #0x50]
|
||||
|
||||
ldr r0, AIPS2_CTRL_BASE_ADDR_W
|
||||
ldr r1, =0x0
|
||||
str r1, [r0, #0x40]
|
||||
str r1, [r0, #0x44]
|
||||
str r1, [r0, #0x48]
|
||||
str r1, [r0, #0x4C]
|
||||
ldr r1, [r0, #0x50]
|
||||
and r1, r1, #0x00FFFFFF
|
||||
str r1, [r0, #0x50]
|
||||
|
||||
ldr r0, MAX_BASE_ADDR_W
|
||||
/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
|
||||
ldr r1, MAX_PARAM1
|
||||
str r1, [r0, #0x000] /* for S0 */
|
||||
str r1, [r0, #0x100] /* for S1 */
|
||||
str r1, [r0, #0x200] /* for S2 */
|
||||
str r1, [r0, #0x300] /* for S3 */
|
||||
str r1, [r0, #0x400] /* for S4 */
|
||||
/* SGPCR - always park on last master */
|
||||
ldr r1, =0x10
|
||||
str r1, [r0, #0x010] /* for S0 */
|
||||
str r1, [r0, #0x110] /* for S1 */
|
||||
str r1, [r0, #0x210] /* for S2 */
|
||||
str r1, [r0, #0x310] /* for S3 */
|
||||
str r1, [r0, #0x410] /* for S4 */
|
||||
/* MGPCR - restore default values */
|
||||
ldr r1, =0x0
|
||||
str r1, [r0, #0x800] /* for M0 */
|
||||
str r1, [r0, #0x900] /* for M1 */
|
||||
str r1, [r0, #0xA00] /* for M2 */
|
||||
str r1, [r0, #0xB00] /* for M3 */
|
||||
str r1, [r0, #0xC00] /* for M4 */
|
||||
str r1, [r0, #0xD00] /* for M5 */
|
||||
|
||||
ldr r1, M3IF_BASE_W
|
||||
/*
|
||||
* M3IF Control Register (M3IFCTL)
|
||||
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[3] = USB not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
|
||||
* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
|
||||
* ------------
|
||||
* 0x00000040
|
||||
*/
|
||||
ldr r0, =0x00000040
|
||||
str r0, [r1] /* M3IF control reg */
|
||||
|
||||
#if 1
|
||||
ldr r0, CCM_BASE_ADDR_W
|
||||
|
||||
/* default CLKO to 1/32 of the ARM core*/
|
||||
ldr r1, [r0, #CCM_COSR]
|
||||
bic r1, r1, #0x00000FF00
|
||||
bic r1, r1, #0x0000000FF
|
||||
mov r2, #0x00006C00
|
||||
add r2, r2, #0x67
|
||||
orr r1, r1, r2
|
||||
str r1, [r0, #CCM_COSR]
|
||||
|
||||
ldr r2, CCM_CCMR_W
|
||||
str r2, [r0, #CCM_CCMR]
|
||||
|
||||
/* check clock path */
|
||||
ldr r2, [r0, #CCM_PDR0]
|
||||
tst r2, #0x1
|
||||
ldrne r3, MPCTL_PARAM_532_W /* consumer path*/
|
||||
ldreq r3, MPCTL_PARAM_399_W /* auto path*/
|
||||
|
||||
/*Set MPLL , arm clock and ahb clock*/
|
||||
str r3, [r0, #CCM_MPCTL]
|
||||
|
||||
ldr r1, PPCTL_PARAM_W
|
||||
str r1, [r0, #CCM_PPCTL]
|
||||
|
||||
ldr r1, [r0, #CCM_PDR0]
|
||||
orr r1, r1, #0x800000
|
||||
str r1, [r0, #CCM_PDR0]
|
||||
|
||||
ldr r1, CCM_PDR0_W
|
||||
str r1, [r0, #CCM_PDR0]
|
||||
|
||||
ldr r1, [r0, #CCM_CGR0]
|
||||
orr r1, r1, #0x00300000
|
||||
str r1, [r0, #CCM_CGR0]
|
||||
|
||||
ldr r1, [r0, #CCM_CGR1]
|
||||
orr r1, r1, #0x00000C00
|
||||
orr r1, r1, #0x00000003
|
||||
str r1, [r0, #CCM_CGR1]
|
||||
#endif
|
||||
|
||||
/* Skip SDRAM initialization if we run from RAM */
|
||||
cmp pc, #0x80000000
|
||||
bls 1f
|
||||
cmp pc, #0x90000000
|
||||
bhi 1f
|
||||
|
||||
mov pc, lr
|
||||
|
||||
1:
|
||||
ldr r0, ESDCTL_BASE_W
|
||||
mov r3, #0x2000
|
||||
str r3, [r0, #0x0]
|
||||
str r3, [r0, #0x8]
|
||||
|
||||
mov r12, #0x00
|
||||
mov r2, #0x00
|
||||
mov r1, #IMX_SDRAM_CS0
|
||||
|
||||
ldr r0, ESDCTL_BASE_W
|
||||
mov r3, #0x2000
|
||||
str r3, [r0, #0x0]
|
||||
str r3, [r0, #0x8]
|
||||
|
||||
mov r12, #0x00
|
||||
mov r2, #0x00
|
||||
mov r1, #IMX_SDRAM_CS0
|
||||
bl setup_sdram_bank
|
||||
cmp r3, #0x0
|
||||
orreq r12, r12, #1
|
||||
eorne r2, r2, #0x1
|
||||
blne setup_sdram_bank
|
||||
|
||||
cmp r12, #0
|
||||
movne r3, #L2CC_BASE_ADDR
|
||||
ldrne r4, [r3, #L2_CACHE_AUX_CTL_REG]
|
||||
orrne r4, r4, #0x1000
|
||||
strne r4, [r3, #L2_CACHE_AUX_CTL_REG]
|
||||
|
||||
ldr r3, ESDCTL_DELAY5
|
||||
str r3, [r0, #0x30]
|
||||
ret:
|
||||
mov pc,r10
|
||||
|
||||
/*
|
||||
* r0: control base, r1: ram bank base
|
||||
* r2: ddr type(0:DDR2, 1:MDDR) r3, r4: working
|
||||
*/
|
||||
setup_sdram_bank:
|
||||
|
||||
mov r3, #0xE /*0xA + 0x4*/
|
||||
tst r2, #0x1
|
||||
orreq r3, r3, #0x300 /*DDR2*/
|
||||
str r3, [r0, #0x10]
|
||||
bic r3, r3, #0x00A
|
||||
str r3, [r0, #0x10]
|
||||
beq 2f
|
||||
|
||||
mov r3, #0x20000
|
||||
1: subs r3, r3, #1
|
||||
bne 1b
|
||||
|
||||
2: adr r4, ESDCTL_CONFIG
|
||||
tst r2, #0x1
|
||||
ldreq r3, [r4, #0x0]
|
||||
ldrne r3, [r4, #0x4]
|
||||
cmp r1, #IMX_SDRAM_CS1
|
||||
strlo r3, [r0, #0x4]
|
||||
strhs r3, [r0, #0xC]
|
||||
|
||||
ldr r3, ESDCTL_0x92220000
|
||||
strlo r3, [r0, #0x0]
|
||||
strhs r3, [r0, #0x8]
|
||||
mov r3, #0xDA
|
||||
ldr r4, RAM_PARAM1_MDDR
|
||||
strb r3, [r1, r4]
|
||||
|
||||
tst r2, #0x1
|
||||
bne skip_set_mode
|
||||
|
||||
cmp r1, #IMX_SDRAM_CS1
|
||||
ldr r3, ESDCTL_0xB2220000
|
||||
strlo r3, [r0, #0x0]
|
||||
strhs r3, [r0, #0x8]
|
||||
mov r3, #0xDA
|
||||
ldr r4, RAM_PARAM4_MDDR
|
||||
strb r3, [r1, r4]
|
||||
ldr r4, RAM_PARAM5_MDDR
|
||||
strb r3, [r1, r4]
|
||||
ldr r4, RAM_PARAM3_MDDR
|
||||
strb r3, [r1, r4]
|
||||
ldr r4, RAM_PARAM2_MDDR
|
||||
strb r3, [r1, r4]
|
||||
|
||||
ldr r3, ESDCTL_0x92220000
|
||||
strlo r3, [r0, #0x0]
|
||||
strhs r3, [r0, #0x8]
|
||||
mov r3, #0xDA
|
||||
ldr r4, RAM_PARAM1_MDDR
|
||||
strb r3, [r1, r4]
|
||||
|
||||
skip_set_mode:
|
||||
cmp r1, #IMX_SDRAM_CS1
|
||||
ldr r3, ESDCTL_0xA2220000
|
||||
strlo r3, [r0, #0x0]
|
||||
strhs r3, [r0, #0x8]
|
||||
mov r3, #0xDA
|
||||
strb r3, [r1]
|
||||
strb r3, [r1]
|
||||
|
||||
ldr r3, ESDCTL_0xB2220000
|
||||
strlo r3, [r0, #0x0]
|
||||
strhs r3, [r0, #0x8]
|
||||
adr r4, RAM_PARAM6_MDDR
|
||||
tst r2, #0x1
|
||||
ldreq r4, [r4, #0x0]
|
||||
ldrne r4, [r4, #0x4]
|
||||
mov r3, #0xDA
|
||||
strb r3, [r1, r4]
|
||||
ldreq r4, RAM_PARAM7_MDDR
|
||||
streqb r3, [r1, r4]
|
||||
adr r4, RAM_PARAM3_MDDR
|
||||
ldreq r4, [r4, #0x0]
|
||||
ldrne r4, [r4, #0x4]
|
||||
strb r3, [r1, r4]
|
||||
|
||||
cmp r1, #IMX_SDRAM_CS1
|
||||
ldr r3, ESDCTL_0x82226080
|
||||
strlo r3, [r0, #0x0]
|
||||
strhs r3, [r0, #0x8]
|
||||
|
||||
tst r2, #0x1
|
||||
moveq r4, #0x20000
|
||||
movne r4, #0x200
|
||||
1: subs r4, r4, #1
|
||||
bne 1b
|
||||
|
||||
str r3, [r1, #0x100]
|
||||
ldr r4, [r1, #0x100]
|
||||
cmp r3, r4
|
||||
movne r3, #1
|
||||
moveq r3, #0
|
||||
mov pc, lr
|
||||
|
||||
Loading…
Reference in New Issue