imx6: ocotp: Add On-Chip OTP registers write support
FUSEs (OTP registers) can be written via /dev/imx-ocotp character device.
For example, writing MAC 12:34:56:78:9A:BC can be performed as
> mw -l -d /dev/imx-ocotp 0x8c 0x00001234
> mw -l -d /dev/imx-ocotp 0x88 0x56789ABC
and reading as
> md -l -s /dev/imx-ocotp 0x88+8
00000088: 56789ABC 00001234
, where 0x88 (0x22*4) and 0x8C (0x23*4) are offsets of MAC OTP registers.
Notice: FUSEs are PROM, so "0" (unprogrammed) bits
can be replaced with "1" (but not vice versa) only once.
Also, for MAC there are convinient parameters:
> ocotp0.permanent_write_enable=1
> ocotp0.mac_addr=12:34:56:78:9A:BC
imx_ocotp 21bc000.ocotp: reloading shadow registers...
imx_ocotp 21bc000.ocotp: reloading shadow registers...
> echo $ocotp0.mac_addr
12:34:56:78:9A:BC
Signed-off-by: Uladzimir Bely <u.bely@sam-solutions.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Uladzimir Bely
Sascha Hauer
parent
e0afbe3f84
commit
825fca396f
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@ -630,6 +630,16 @@ config IMX_OCOTP
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only supported functionality is reading the MAC address and assigning
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it to an ethernet device.
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config IMX_OCOTP_WRITE
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bool
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prompt "Enable write support of i.MX6 CPUs OTP fuses"
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depends on IMX_OCOTP
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help
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This adds write support to IMX6 On-Chip OTP registers.
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Example of set MAC to 12:34:56:78:9A:BC (2 words with offset 0x22 * 4):
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mw -l -d /dev/imx-ocotp 0x8C 0x00001234
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mw -l -d /dev/imx-ocotp 0x88 0x56789ABC
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endmenu
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endif
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@ -433,6 +433,7 @@ static int imx6_ccm_probe(struct device_d *dev)
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clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI5_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg_per], MX6_GPT_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg], MX6_ENET_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg], MX6_OCOTP_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[usdhc1_podf], MX6_USDHC1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[usdhc2_podf], MX6_USDHC2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[usdhc3_podf], MX6_USDHC3_BASE_ADDR, NULL);
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@ -25,6 +25,8 @@
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#include <net.h>
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#include <io.h>
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#include <of.h>
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#include <clock.h>
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#include <linux/clk.h>
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/*
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* a single MAC address reference has the form
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@ -32,6 +34,292 @@
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*/
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#define MAC_ADDRESS_PROPLEN (2 * sizeof(__be32))
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/* OCOTP Registers offsets */
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#define OCOTP_CTRL_SET 0x04
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#define OCOTP_CTRL_CLR 0x08
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#define OCOTP_TIMING 0x10
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#define OCOTP_DATA 0x20
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#define OCOTP_READ_CTRL 0x30
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#define OCOTP_READ_FUSE_DATA 0x40
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/* OCOTP Registers bits and masks */
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#define OCOTP_CTRL_WR_UNLOCK 16
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#define OCOTP_CTRL_WR_UNLOCK_KEY 0x3E77
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#define OCOTP_CTRL_WR_UNLOCK_MASK 0xFFFF0000
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#define OCOTP_CTRL_ADDR 0
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#define OCOTP_CTRL_ADDR_MASK 0x0000007F
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#define OCOTP_CTRL_BUSY (1 << 8)
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#define OCOTP_CTRL_ERROR (1 << 9)
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#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 10)
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#define OCOTP_TIMING_STROBE_READ 16
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#define OCOTP_TIMING_STROBE_READ_MASK 0x003F0000
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#define OCOTP_TIMING_RELAX 12
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#define OCOTP_TIMING_RELAX_MASK 0x0000F000
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#define OCOTP_TIMING_STROBE_PROG 0
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#define OCOTP_TIMING_STROBE_PROG_MASK 0x00000FFF
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#define OCOTP_READ_CTRL_READ_FUSE 0x00000001
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#define BF(value, field) (((value) << field) & field##_MASK)
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/* Other definitions */
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#define FUSE_REGS_COUNT (16 * 8)
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#define IMX6_OTP_DATA_ERROR_VAL 0xBADABADA
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#define DEF_RELAX 20
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#define MAC_OFFSET (0x22 * 4)
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#define MAC_BYTES 8
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struct ocotp_priv {
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struct cdev cdev;
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void __iomem *base;
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struct clk *clk;
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struct device_d dev;
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int permanent_write_enable;
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int sense_enable;
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char ethaddr[6];
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};
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static int imx6_ocotp_set_timing(struct ocotp_priv *priv)
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{
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u32 clk_rate;
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u32 relax, strobe_read, strobe_prog;
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u32 timing;
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clk_rate = clk_get_rate(priv->clk);
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relax = clk_rate / (1000000000 / DEF_RELAX) - 1;
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strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1;
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strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1;
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timing = BF(relax, OCOTP_TIMING_RELAX);
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timing |= BF(strobe_read, OCOTP_TIMING_STROBE_READ);
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timing |= BF(strobe_prog, OCOTP_TIMING_STROBE_PROG);
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writel(timing, priv->base + OCOTP_TIMING);
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return 0;
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}
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static int imx6_ocotp_wait_busy(u32 flags, struct ocotp_priv *priv)
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{
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uint64_t start = get_time_ns();
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while ((OCOTP_CTRL_BUSY | OCOTP_CTRL_ERROR | flags) &
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readl(priv->base)) {
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if (is_timeout(start, MSECOND)) {
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/* Clear ERROR bit */
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writel(OCOTP_CTRL_ERROR, priv->base + OCOTP_CTRL_CLR);
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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static int imx6_ocotp_prepare(struct ocotp_priv *priv)
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{
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int ret;
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ret = imx6_ocotp_set_timing(priv);
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if (ret)
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return ret;
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ret = imx6_ocotp_wait_busy(0, priv);
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if (ret)
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return ret;
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return 0;
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}
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static int fuse_read_addr(u32 addr, u32 *pdata, struct ocotp_priv *priv)
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{
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u32 ctrl_reg;
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int ret;
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ctrl_reg = readl(priv->base);
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ctrl_reg &= ~OCOTP_CTRL_ADDR_MASK;
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ctrl_reg &= ~OCOTP_CTRL_WR_UNLOCK_MASK;
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ctrl_reg |= BF(addr, OCOTP_CTRL_ADDR);
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writel(ctrl_reg, priv->base);
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writel(OCOTP_READ_CTRL_READ_FUSE, priv->base + OCOTP_READ_CTRL);
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ret = imx6_ocotp_wait_busy(0, priv);
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if (ret)
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return ret;
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*pdata = readl(priv->base + OCOTP_READ_FUSE_DATA);
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return 0;
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}
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int imx6_ocotp_read_one_u32(u32 index, u32 *pdata, struct ocotp_priv *priv)
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{
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int ret;
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ret = imx6_ocotp_prepare(priv);
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if (ret) {
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dev_err(priv->cdev.dev, "failed to prepare read fuse 0x%08x\n",
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index);
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return ret;
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}
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ret = fuse_read_addr(index, pdata, priv);
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if (ret) {
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dev_err(priv->cdev.dev, "failed to read fuse 0x%08x\n", index);
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return ret;
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}
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if (readl(priv->base) & OCOTP_CTRL_ERROR) {
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dev_err(priv->cdev.dev, "bad read status at fuse 0x%08x\n", index);
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return -EFAULT;
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}
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return 0;
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}
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static ssize_t imx6_ocotp_cdev_read(struct cdev *cdev, void *buf,
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size_t count, loff_t offset, unsigned long flags)
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{
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u32 index;
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ssize_t read_count = 0;
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int ret, i;
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struct ocotp_priv *priv = container_of(cdev, struct ocotp_priv, cdev);
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index = offset >> 2;
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count >>= 2;
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if (count > (FUSE_REGS_COUNT - index))
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count = FUSE_REGS_COUNT - index - 1;
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for (i = index; i < (index + count); i++) {
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if (priv->sense_enable) {
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ret = imx6_ocotp_read_one_u32(i, buf, priv);
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if (ret)
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return ret;
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} else {
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*(u32 *)buf = readl(priv->base + 0x400 + i * 0x10);
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}
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buf += 4;
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read_count++;
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}
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return read_count << 2;
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}
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static int fuse_blow_addr(u32 addr, u32 value, struct ocotp_priv *priv)
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{
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u32 ctrl_reg;
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int ret;
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/* Control register */
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ctrl_reg = readl(priv->base);
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ctrl_reg &= ~OCOTP_CTRL_ADDR_MASK;
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ctrl_reg |= BF(addr, OCOTP_CTRL_ADDR);
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ctrl_reg |= BF(OCOTP_CTRL_WR_UNLOCK_KEY, OCOTP_CTRL_WR_UNLOCK);
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writel(ctrl_reg, priv->base);
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writel(value, priv->base + OCOTP_DATA);
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ret = imx6_ocotp_wait_busy(0, priv);
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if (ret)
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return ret;
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/* Write postamble */
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udelay(2000);
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return 0;
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}
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static int imx6_ocotp_reload_shadow(struct ocotp_priv *priv)
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{
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dev_info(priv->cdev.dev, "reloading shadow registers...\n");
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writel(OCOTP_CTRL_RELOAD_SHADOWS, priv->base + OCOTP_CTRL_SET);
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udelay(1);
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return imx6_ocotp_wait_busy(OCOTP_CTRL_RELOAD_SHADOWS, priv);
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}
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int imx6_ocotp_blow_one_u32(u32 index, u32 data, u32 *pfused_value,
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struct ocotp_priv *priv)
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{
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int ret;
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ret = imx6_ocotp_prepare(priv);
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if (ret) {
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dev_err(priv->cdev.dev, "prepare to write failed\n");
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return ret;
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}
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ret = fuse_blow_addr(index, data, priv);
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if (ret) {
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dev_err(priv->cdev.dev, "fuse blow failed\n");
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return ret;
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}
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if (readl(priv->base) & OCOTP_CTRL_ERROR) {
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dev_err(priv->cdev.dev, "bad write status\n");
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return -EFAULT;
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}
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ret = imx6_ocotp_read_one_u32(index, pfused_value, priv);
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return ret;
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}
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static ssize_t imx6_ocotp_cdev_write(struct cdev *cdev, const void *buf,
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size_t count, loff_t offset, unsigned long flags)
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{
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struct ocotp_priv *priv = cdev->priv;
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int index, i;
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ssize_t write_count = 0;
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const u32 *data;
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u32 pfuse;
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int ret;
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/* We could do better, but currently this is what's implemented */
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if (offset & 0x3 || count & 0x3) {
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dev_err(cdev->dev, "only u32 aligned writes allowed\n");
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return -EINVAL;
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}
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index = offset >> 2;
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count >>= 2;
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if (count > (FUSE_REGS_COUNT - index))
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count = FUSE_REGS_COUNT - index - 1;
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data = buf;
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for (i = index; i < (index + count); i++) {
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if (priv->permanent_write_enable) {
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ret = imx6_ocotp_blow_one_u32(i, *data,
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&pfuse, priv);
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if (ret < 0) {
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goto out;
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}
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} else {
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writel(*data, priv->base + 0x400 + i * 0x10);
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}
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data++;
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write_count++;
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}
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ret = 0;
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out:
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if (priv->permanent_write_enable)
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imx6_ocotp_reload_shadow(priv);
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return ret < 0 ? ret : (write_count << 2);
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}
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static struct file_operations imx6_ocotp_ops = {
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.read = imx6_ocotp_cdev_read,
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.write = imx6_ocotp_cdev_write,
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.lseek = dev_lseek_default,
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};
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static void imx_ocotp_init_dt(struct device_d *dev, void __iomem *base)
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{
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char mac[6];
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@ -70,9 +358,43 @@ static void imx_ocotp_init_dt(struct device_d *dev, void __iomem *base)
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}
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}
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static int imx_ocotp_get_mac(struct param_d *param, void *priv)
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{
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struct ocotp_priv *ocotp_priv = priv;
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char buf[8];
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int i;
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imx6_ocotp_cdev_read(&ocotp_priv->cdev, buf, MAC_BYTES, MAC_OFFSET, 0);
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for (i = 0; i < 6; i++)
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ocotp_priv->ethaddr[i] = buf[5 - i];
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return 0;
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}
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static int imx_ocotp_set_mac(struct param_d *param, void *priv)
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{
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struct ocotp_priv *ocotp_priv = priv;
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char buf[8];
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int i, ret;
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for (i = 0; i < 6; i++)
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buf[5 - i] = ocotp_priv->ethaddr[i];
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buf[6] = 0; buf[7] = 0;
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ret = imx6_ocotp_cdev_write(&ocotp_priv->cdev, buf, MAC_BYTES, MAC_OFFSET, 0);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int imx_ocotp_probe(struct device_d *dev)
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{
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void __iomem *base;
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struct ocotp_priv *priv;
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struct cdev *cdev;
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int ret = 0;
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base = dev_request_mem_region(dev, 0);
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if (!base)
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@ -80,6 +402,40 @@ static int imx_ocotp_probe(struct device_d *dev)
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imx_ocotp_init_dt(dev, base);
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priv = xzalloc(sizeof(*priv));
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priv->base = base;
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priv->clk = clk_get(dev, NULL);
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if (IS_ERR(priv->clk))
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return PTR_ERR(priv->clk);
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cdev = &priv->cdev;
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cdev->dev = dev;
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cdev->ops = &imx6_ocotp_ops;
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cdev->priv = priv;
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cdev->size = 192;
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cdev->name = "imx-ocotp";
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if (cdev->name == NULL)
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return -ENOMEM;
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ret = devfs_create(cdev);
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if (ret < 0)
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return ret;
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strcpy(priv->dev.name, "ocotp");
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priv->dev.parent = dev;
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register_device(&priv->dev);
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if (IS_ENABLED(CONFIG_IMX_OCOTP_WRITE)) {
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dev_add_param_bool(&(priv->dev), "permanent_write_enable",
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NULL, NULL, &priv->permanent_write_enable, NULL);
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}
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dev_add_param_mac(&(priv->dev), "mac_addr", imx_ocotp_set_mac,
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imx_ocotp_get_mac, priv->ethaddr, priv);
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dev_add_param_bool(&(priv->dev), "sense_enable", NULL, NULL, &priv->sense_enable, priv);
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return 0;
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}
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