Split S3C generic and S3C24xx specific code
Signed-off-by: Alexey Galakhov <agalakhov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Alexey Galakhov
Sascha Hauer
parent
5ef3ecd922
commit
7a05b45b4b
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@ -1,3 +1,4 @@
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obj-y += s3c-timer.o generic.o
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obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o
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obj-$(CONFIG_S3C_LOWLEVEL_INIT) += lowlevel-init.o
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obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
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obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o mem-s3c24x0.o
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obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)
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@ -25,65 +25,9 @@
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#include <config.h>
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#include <common.h>
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#include <init.h>
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#include <clock.h>
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#include <io.h>
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#include <sizes.h>
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#include <mach/s3c-iomap.h>
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#include <mach/s3c-generic.h>
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#include <mach/s3c-busctl.h>
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#include <mach/s3c24xx-gpio.h>
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/**
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* Calculate the amount of connected and available memory
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* @return Memory size in bytes
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*/
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uint32_t s3c24xx_get_memory_size(void)
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{
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uint32_t reg, size;
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/*
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* detect the current memory size
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*/
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reg = readl(S3C_BANKSIZE);
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switch (reg & 0x7) {
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case 0:
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size = SZ_32M;
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break;
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case 1:
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size = SZ_64M;
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break;
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case 2:
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size = SZ_128M;
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break;
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case 4:
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size = SZ_2M;
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break;
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case 5:
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size = SZ_4M;
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break;
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case 6:
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size = SZ_8M;
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break;
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default:
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size = SZ_16M;
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break;
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}
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/*
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* Is bank7 also configured for SDRAM usage?
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*/
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if ((readl(S3C_BANKCON7) & (0x3 << 15)) == (0x3 << 15))
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size <<= 1; /* also count this bank */
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return size;
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}
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void s3c24xx_disable_second_sdram_bank(void)
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{
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writel(readl(S3C_BANKCON7) & ~(0x3 << 15), S3C_BANKCON7);
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writel(readl(S3C_MISCCR) | (1 << 18), S3C_MISCCR); /* disable its clock */
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}
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#define S3C_WTCON (S3C_WATCHDOG_BASE)
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#define S3C_WTDAT (S3C_WATCHDOG_BASE + 0x04)
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@ -105,60 +49,3 @@ void __noreturn reset_cpu(unsigned long addr)
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;
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}
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EXPORT_SYMBOL(reset_cpu);
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/**
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@page dev_s3c24xx_arch Samsung's S3C24xx Platforms in barebox
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@section s3c24xx_boards Boards using S3C24xx Processors
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@li @subpage arch/arm/boards/a9m2410/a9m2410.c
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@li @subpage arch/arm/boards/a9m2440/a9m2440.c
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@section s3c24xx_arch Documentation for S3C24xx Architectures Files
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@li @subpage arch/arm/mach-s3c24xx/generic.c
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@section s3c24xx_mem_map SDRAM Memory Map
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SDRAM starts at address 0x3000.0000 up to the available amount of connected
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SDRAM memory. Physically this CPU can handle up to 256MiB (two areas with
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up to 128MiB each).
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@subsection s3c24xx_mem_generic_map Generic Map
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- 0x0000.0000 Start of the internal SRAM when booting from NAND flash memory or CS signal to a NOR flash memory.
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- 0x0800.0000 Start of I/O space.
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- 0x3000.0000 Start of SDRAM area.
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- 0x3000.0100 Start of the TAG list area.
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- 0x3000.8000 Start of the linux kernel (physical address).
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- 0x4000.0000 Start of internal SRAM, when booting from NOR flash memory
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- 0x4800.0000 Start of the internal I/O area
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@section s3c24xx_asm_arm include/asm-arm/arch-s3c24xx directory guidelines
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All S3C24xx common headers are located here.
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@note Do not add board specific header files/information here.
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*/
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/** @page dev_s3c24xx_mach Samsung's S3C24xx based platforms
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@par barebox Map
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The location of the @a barebox itself depends on the available amount of
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installed SDRAM memory:
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- 0x30fc.0000 Start of @a barebox when 16MiB SDRAM is available
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- 0x31fc.0000 Start of @a barebox when 32MiB SDRAM is available
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- 0x33fc.0000 Start of @a barebox when 64MiB SDRAM is available
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Adjust the @p CONFIG_TEXT_BASE/CONFIG_ARCH_TEXT_BASE symbol in accordance to
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the available memory.
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@note The RAM based filesystem and the stack resides always below the
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@a barebox start address.
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@li @subpage dev_s3c24xx_wd_handling
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@li @subpage dev_s3c24xx_pll_handling
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@li @subpage dev_s3c24xx_sdram_handling
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@li @subpage dev_s3c24xx_nandboot_handling
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*/
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@ -1,5 +1,6 @@
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/*
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* Copyright (C) 2011 Juergen Beisert, Pengutronix
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -10,22 +11,19 @@
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef __MACH_S3C_CLOCKS_H
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# define __MACH_S3C_CLOCKS_H
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#define __MACH_S3C_CLOCKS_H
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#ifdef CONFIG_ARCH_S3C24xx
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# define S3C_LOCKTIME (S3C_CLOCK_POWER_BASE)
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# define S3C_MPLLCON (S3C_CLOCK_POWER_BASE + 0x4)
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# define S3C_UPLLCON (S3C_CLOCK_POWER_BASE + 0x8)
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# define S3C_CLKCON (S3C_CLOCK_POWER_BASE + 0xc)
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# define S3C_CLKSLOW (S3C_CLOCK_POWER_BASE + 0x10)
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# define S3C_CLKDIVN (S3C_CLOCK_POWER_BASE + 0x14)
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# define S3C_MPLLCON_GET_MDIV(x) ((((x) >> 12) & 0xff) + 8)
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# define S3C_MPLLCON_GET_PDIV(x) ((((x) >> 4) & 0x3f) + 2)
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# define S3C_MPLLCON_GET_SDIV(x) ((x) & 0x3)
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# include <mach/s3c24xx-clocks.h>
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#endif
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#endif /* __MACH_S3C_CLOCKS_H */
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@ -33,6 +33,7 @@ uint32_t s3c_get_uclk(void);
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unsigned s3c_get_uart_clk(unsigned src);
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#ifdef CONFIG_ARCH_S3C24xx
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uint32_t s3c24xx_get_memory_size(void);
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void s3c24xx_disable_second_sdram_bank(void);
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#endif
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@ -1,5 +1,6 @@
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/*
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* Copyright (C) 2009 Juergen Beisert, Pengutronix
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -18,52 +19,6 @@
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*
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*/
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/* S3C2410 device base addresses */
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#define S3C_MEMCTL_BASE 0x48000000
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#define S3C2410_USB_HOST_BASE 0x49000000
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#define S3C2410_INTERRUPT_BASE 0x4A000000
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#define S3C2410_DMA_BASE 0x4B000000
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#define S3C_CLOCK_POWER_BASE 0x4C000000
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#define S3C2410_LCD_BASE 0x4D000000
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#define S3C24X0_NAND_BASE 0x4E000000
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#define S3C_UART_BASE 0x50000000
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#define S3C_TIMER_BASE 0x51000000
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#define S3C2410_USB_DEVICE_BASE 0x52000140
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#define S3C_WATCHDOG_BASE 0x53000000
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#define S3C2410_I2C_BASE 0x54000000
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#define S3C2410_I2S_BASE 0x55000000
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#define S3C_GPIO_BASE 0x56000000
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#define S3C2410_RTC_BASE 0x57000000
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#define S3C2410_ADC_BASE 0x58000000
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#define S3C2410_SPI_BASE 0x59000000
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#define S3C2410_SDI_BASE 0x5A000000
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/* external IO space */
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#define S3C_CS0_BASE 0x00000000
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#define S3C_CS1_BASE 0x08000000
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#define S3C_CS2_BASE 0x10000000
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#define S3C_CS3_BASE 0x18000000
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#define S3C_CS4_BASE 0x20000000
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#define S3C_CS5_BASE 0x28000000
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#define S3C_CS6_BASE 0x30000000
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#define S3C_SDRAM_BASE S3C_CS6_BASE
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#define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x10000000)
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/*
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* if we are booting from NAND, its internal SRAM occures at
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* a different address than without this feature
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*/
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#ifdef CONFIG_S3C_NAND_BOOT
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# define NFC_RAM_AREA 0x00000000
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#else
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# define NFC_RAM_AREA 0x40000000
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#ifdef CONFIG_ARCH_S3C24xx
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# include <mach/s3c24xx-iomap.h>
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#endif
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#define NFC_RAM_SIZE 4096
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#define S3C_UART1_BASE (S3C_UART_BASE)
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#define S3C_UART1_SIZE 0x4000
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#define S3C_UART2_BASE (S3C_UART_BASE + 0x4000)
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#define S3C_UART2_SIZE 0x4000
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#define S3C_UART3_BASE (S3C_UART_BASE + 0x8000)
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#define S3C_UART3_SIZE 0x4000
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@ -0,0 +1,24 @@
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/*
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* Copyright (C) 2011 Juergen Beisert, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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# define S3C_LOCKTIME (S3C_CLOCK_POWER_BASE)
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# define S3C_MPLLCON (S3C_CLOCK_POWER_BASE + 0x4)
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# define S3C_UPLLCON (S3C_CLOCK_POWER_BASE + 0x8)
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# define S3C_CLKCON (S3C_CLOCK_POWER_BASE + 0xc)
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# define S3C_CLKSLOW (S3C_CLOCK_POWER_BASE + 0x10)
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# define S3C_CLKDIVN (S3C_CLOCK_POWER_BASE + 0x14)
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# define S3C_MPLLCON_GET_MDIV(x) ((((x) >> 12) & 0xff) + 8)
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# define S3C_MPLLCON_GET_PDIV(x) ((((x) >> 4) & 0x3f) + 2)
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# define S3C_MPLLCON_GET_SDIV(x) ((x) & 0x3)
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@ -12,8 +12,8 @@
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* GNU General Public License for more details.
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*/
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#ifndef __MACH_S3C24XX_GPIO_H
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# define __MACH_S3C24XX_GPIO_H
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#ifndef __MACH_GPIO_S3C24X0_H
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# define __MACH_GPIO_S3C24X0_H
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#define S3C_GPACON (S3C_GPIO_BASE)
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#define S3C_GPADAT (S3C_GPIO_BASE + 0x04)
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@ -74,4 +74,4 @@
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# define S3C_DSC1 (S3C_GPIO_BASE + 0xc8)
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#endif
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#endif /* __MACH_S3C24XX_GPIO_H */
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#endif /* __MACH_GPIO_S3C24X0_H */
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@ -0,0 +1,69 @@
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/*
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* Copyright (C) 2009 Juergen Beisert, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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* MA 02111-1307 USA
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*
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*/
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/* S3C2410 device base addresses */
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#define S3C_MEMCTL_BASE 0x48000000
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#define S3C2410_USB_HOST_BASE 0x49000000
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#define S3C2410_INTERRUPT_BASE 0x4A000000
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#define S3C2410_DMA_BASE 0x4B000000
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#define S3C_CLOCK_POWER_BASE 0x4C000000
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#define S3C2410_LCD_BASE 0x4D000000
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#define S3C24X0_NAND_BASE 0x4E000000
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#define S3C_UART_BASE 0x50000000
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#define S3C_TIMER_BASE 0x51000000
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#define S3C2410_USB_DEVICE_BASE 0x52000140
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#define S3C_WATCHDOG_BASE 0x53000000
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#define S3C2410_I2C_BASE 0x54000000
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#define S3C2410_I2S_BASE 0x55000000
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#define S3C_GPIO_BASE 0x56000000
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#define S3C2410_RTC_BASE 0x57000000
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#define S3C2410_ADC_BASE 0x58000000
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#define S3C2410_SPI_BASE 0x59000000
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#define S3C2410_SDI_BASE 0x5A000000
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/* external IO space */
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#define S3C_CS0_BASE 0x00000000
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#define S3C_CS1_BASE 0x08000000
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#define S3C_CS2_BASE 0x10000000
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#define S3C_CS3_BASE 0x18000000
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#define S3C_CS4_BASE 0x20000000
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#define S3C_CS5_BASE 0x28000000
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#define S3C_CS6_BASE 0x30000000
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#define S3C_SDRAM_BASE S3C_CS6_BASE
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#define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x10000000)
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/*
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* if we are booting from NAND, its internal SRAM occures at
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* a different address than without this feature
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*/
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#ifdef CONFIG_S3C_NAND_BOOT
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# define NFC_RAM_AREA 0x00000000
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#else
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# define NFC_RAM_AREA 0x40000000
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#endif
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#define NFC_RAM_SIZE 4096
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#define S3C_UART1_BASE (S3C_UART_BASE)
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#define S3C_UART1_SIZE 0x4000
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#define S3C_UART2_BASE (S3C_UART_BASE + 0x4000)
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#define S3C_UART2_SIZE 0x4000
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#define S3C_UART3_BASE (S3C_UART_BASE + 0x8000)
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#define S3C_UART3_SIZE 0x4000
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@ -0,0 +1,143 @@
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/*
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* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
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/**
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* @file
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* @brief Basic clock, sdram and timer handling for S3C24xx CPUs
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*/
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#include <config.h>
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#include <common.h>
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#include <init.h>
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#include <clock.h>
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#include <io.h>
|
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#include <sizes.h>
|
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#include <mach/s3c-iomap.h>
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#include <mach/s3c-generic.h>
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#include <mach/s3c-busctl.h>
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#include <mach/s3c24xx-gpio.h>
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/**
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* Calculate the amount of connected and available memory
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* @return Memory size in bytes
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*/
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uint32_t s3c24xx_get_memory_size(void)
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{
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uint32_t reg, size;
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/*
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* detect the current memory size
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*/
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reg = readl(S3C_BANKSIZE);
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switch (reg & 0x7) {
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case 0:
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size = SZ_32M;
|
||||
break;
|
||||
case 1:
|
||||
size = SZ_64M;
|
||||
break;
|
||||
case 2:
|
||||
size = SZ_128M;
|
||||
break;
|
||||
case 4:
|
||||
size = SZ_2M;
|
||||
break;
|
||||
case 5:
|
||||
size = SZ_4M;
|
||||
break;
|
||||
case 6:
|
||||
size = SZ_8M;
|
||||
break;
|
||||
default:
|
||||
size = SZ_16M;
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Is bank7 also configured for SDRAM usage?
|
||||
*/
|
||||
if ((readl(S3C_BANKCON7) & (0x3 << 15)) == (0x3 << 15))
|
||||
size <<= 1; /* also count this bank */
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
void s3c24xx_disable_second_sdram_bank(void)
|
||||
{
|
||||
writel(readl(S3C_BANKCON7) & ~(0x3 << 15), S3C_BANKCON7);
|
||||
writel(readl(S3C_MISCCR) | (1 << 18), S3C_MISCCR); /* disable its clock */
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@page dev_s3c24xx_arch Samsung's S3C24xx Platforms in barebox
|
||||
|
||||
@section s3c24xx_boards Boards using S3C24xx Processors
|
||||
|
||||
@li @subpage arch/arm/boards/a9m2410/a9m2410.c
|
||||
@li @subpage arch/arm/boards/a9m2440/a9m2440.c
|
||||
|
||||
@section s3c24xx_arch Documentation for S3C24xx Architectures Files
|
||||
|
||||
@li @subpage arch/arm/mach-s3c24xx/generic.c
|
||||
|
||||
@section s3c24xx_mem_map SDRAM Memory Map
|
||||
|
||||
SDRAM starts at address 0x3000.0000 up to the available amount of connected
|
||||
SDRAM memory. Physically this CPU can handle up to 256MiB (two areas with
|
||||
up to 128MiB each).
|
||||
|
||||
@subsection s3c24xx_mem_generic_map Generic Map
|
||||
- 0x0000.0000 Start of the internal SRAM when booting from NAND flash memory or CS signal to a NOR flash memory.
|
||||
- 0x0800.0000 Start of I/O space.
|
||||
- 0x3000.0000 Start of SDRAM area.
|
||||
- 0x3000.0100 Start of the TAG list area.
|
||||
- 0x3000.8000 Start of the linux kernel (physical address).
|
||||
- 0x4000.0000 Start of internal SRAM, when booting from NOR flash memory
|
||||
- 0x4800.0000 Start of the internal I/O area
|
||||
|
||||
@section s3c24xx_asm_arm include/asm-arm/arch-s3c24xx directory guidelines
|
||||
All S3C24xx common headers are located here.
|
||||
|
||||
@note Do not add board specific header files/information here.
|
||||
*/
|
||||
|
||||
/** @page dev_s3c24xx_mach Samsung's S3C24xx based platforms
|
||||
|
||||
@par barebox Map
|
||||
|
||||
The location of the @a barebox itself depends on the available amount of
|
||||
installed SDRAM memory:
|
||||
|
||||
- 0x30fc.0000 Start of @a barebox when 16MiB SDRAM is available
|
||||
- 0x31fc.0000 Start of @a barebox when 32MiB SDRAM is available
|
||||
- 0x33fc.0000 Start of @a barebox when 64MiB SDRAM is available
|
||||
|
||||
Adjust the @p CONFIG_TEXT_BASE/CONFIG_ARCH_TEXT_BASE symbol in accordance to
|
||||
the available memory.
|
||||
|
||||
@note The RAM based filesystem and the stack resides always below the
|
||||
@a barebox start address.
|
||||
|
||||
@li @subpage dev_s3c24xx_wd_handling
|
||||
@li @subpage dev_s3c24xx_pll_handling
|
||||
@li @subpage dev_s3c24xx_sdram_handling
|
||||
@li @subpage dev_s3c24xx_nandboot_handling
|
||||
*/
|
||||
Loading…
Reference in New Issue