sysmo-bts
/
barebox
9
0
Fork 0
Code Releases Activity

Merge branch 'for-next/openrisc'

This commit is contained in:
Sascha Hauer 2012-10-03 21:11:53 +02:00
parent bee8dddbfc 83507f2891
commit 6a64024148
5 changed files with 67 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/openrisc/Makefile
View File

@ -1,7 +1,5 @@
CPPFLAGS += -D__OR1K__ -ffixed-r10 -mhard-mul -mhard-div
LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
board-$(CONFIG_GENERIC) := generic
KALLSYMS += --symbol-prefix=_
@ -20,6 +18,4 @@ common-y += $(BOARD)
common-y += arch/openrisc/lib/
common-y += arch/openrisc/cpu/
common-y += $(LIBGCC)
lds-y += arch/openrisc/cpu/barebox.lds

1
arch/openrisc/lib/Makefile
View File

@ -4,3 +4,4 @@ obj-y += cpuinfo.o
obj-y += muldi3.o
obj-y += lshrdi3.o
obj-y += ashldi3.o
obj-y += ashrdi3.o

59
arch/openrisc/lib/ashrdi3.S Normal file
View File

@ -0,0 +1,59 @@
/*
* (C) Copyright 2012 - Franck JULLIEN <elec4fun@gmail.com>
*
* Extracted from gcc generated assembly.
*
* Extended precision shifts.
*
* R3/R4 (MSW, LSW) has 64 bit value
* R5 has shift count
* result in R11/R12
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
.globl __ashrdi3
__ashrdi3:
l.sfeqi r5,0x0 /* if count = 0, go out */
l.bf out
l.addi r6,r0,0x20 /* r6 = 32 */
l.sub r6,r6,r5 /* r6 = 32 - count */
l.sfgtsi r6,0x0 /* if count >= 32 */
l.bnf more_than_32 /* branch to more_than_32 */
l.nop 0x0
less_than_32:
l.sll r6,r3,r6 /* r6 gets the bits moved from MSW to LSW */
l.srl r4,r4,r5 /* shift LSW */
l.sra r5,r3,r5 /* shift MSW to r5 */
l.or r4,r6,r4 /* LSW gets bits shifted from MSW */
l.ori r3,r5,0x0 /* r3 = MSW */
out:
l.ori r11,r3,0x0
l.jr r9
l.ori r12,r4,0x0
more_than_32:
l.srai r5,r3,0x1f /* r5 = MSW sign extended */
l.sub r4,r0,r6 /* r4 = -r6, the number of bits above 32 */
l.sra r4,r3,r4 /* LSW gets bits shifted from MSB */
l.j out /* go out */
l.ori r3,r5,0x0 /* r3 = MSW */

2
common/image.c
View File

@ -61,6 +61,8 @@ static table_entry_t arch_name[] = {
{ IH_ARCH_SPARC64, "sparc64", "SPARC 64 Bit", },
{ IH_ARCH_BLACKFIN, "blackfin", "Blackfin", },
{ IH_ARCH_AVR32, "avr32", "AVR32", },
{ IH_ARCH_NDS32, "nds32", "NDS32", },
{ IH_ARCH_OPENRISC, "or1k", "OpenRISC 1000",},
{ -1, "", "", },
};

5
include/image.h
View File

@ -85,6 +85,9 @@
#define IH_ARCH_BLACKFIN 16 /* Blackfin */
#define IH_ARCH_AVR32 17 /* AVR32 */
#define IH_ARCH_LINUX 18 /* Linux */
#define IH_ARCH_SANDBOX 19 /* Sandbox architecture (test only) */
#define IH_ARCH_NDS32 20 /* ANDES Technology - NDS32 */
#define IH_ARCH_OPENRISC 21 /* OpenRISC 1000 */
#if defined(__PPC__)
#define IH_ARCH IH_ARCH_PPC
@ -102,6 +105,8 @@
#define IH_ARCH IH_ARCH_MICROBLAZE
#elif defined(__nios2__)
#define IH_ARCH IH_ARCH_NIOS2
#elif defined(__OR1K__)
#define IH_ARCH IH_ARCH_OPENRISC
#elif defined(__blackfin__)
#define IH_ARCH IH_ARCH_BLACKFIN
#elif defined(__avr32__)