MPC85xx start-up support code
This patch adds initialization functions used by the e500v2 start-up code and board specific code (L2 cache initialization). Other functions help identify the CPU or return the programmed memory size. Finally, the Makefile and Kconfig file are added. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Renaud Barbier
Sascha Hauer
parent
75b3324e07
commit
61cce55e64
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@ -0,0 +1,41 @@
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if ARCH_MPC85XX
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config TEXT_BASE
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hex
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default 0xeff80000 if P2020RDB
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config BOARDINFO
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default "P2020_RDB" if P2020RDB
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config MPC85xx
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bool
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default y if P2020RDB
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choice
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prompt "Select your board"
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config P2020RDB
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bool "P2020RDB"
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help
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Say Y here if you are using the Freescale P2020RDB
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endchoice
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endif
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if P2020RDB
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config P2020
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bool
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default y
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config BOOKE
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bool
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default y
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config E500
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bool
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default y
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config FSL_ELBC
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bool
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default y
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endif
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@ -0,0 +1,8 @@
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obj-y += cpuid.o
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obj-y += cpu.o
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obj-y += cpu_init.o
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obj-y += fsl_lbc.o
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obj-y += fsl_law.o
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obj-y += speed.o
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obj-y +=time.o
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obj-$(CONFIG_MP) += mp.o
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/*
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* Copyright 2012 GE Intelligent Platforms, Inc
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* Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
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* (C) Copyright 2002, 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <mach/mmu.h>
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#include <mach/immap_85xx.h>
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void __noreturn reset_cpu(unsigned long addr)
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{
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void __iomem *regs = (void __iomem *)MPC85xx_GUTS_ADDR;
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/* Everything after the first generation of PQ3 parts has RSTCR */
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out_be32(regs + MPC85xx_GUTS_RSTCR_OFFSET, 0x2); /* HRESET_REQ */
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udelay(100);
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while (1)
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;
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}
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long int initdram(int board_type)
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{
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phys_size_t dram_size = 0;
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dram_size = fixed_sdram();
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dram_size = e500_setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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return dram_size;
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}
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/*
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* Return the memory size based on the configuration registers.
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*/
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phys_size_t fsl_get_effective_memsize(void)
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{
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void __iomem *regs = (void __iomem *)(MPC85xx_DDR_ADDR);
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phys_size_t sdram_size;
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uint san , ean;
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uint reg;
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int ix;
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sdram_size = 0;
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for (ix = 0; ix < CFG_CHIP_SELECTS_PER_CTRL; ix++) {
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if (in_be32(regs + DDR_OFF(CS0_CONFIG) + (ix * 8)) &
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SDRAM_CFG_MEM_EN) {
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reg = in_be32(regs + DDR_OFF(CS0_BNDS) + (ix * 8));
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/* start address */
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san = (reg & 0x0fff00000) >> 16;
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/* end address */
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ean = (reg & 0x00000fff);
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sdram_size = ((ean - san + 1) << 24);
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}
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}
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return sdram_size;
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}
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@ -0,0 +1,127 @@
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/*
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* Copyright 2012 GE Intelligent Platforms, Inc.
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*
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* Copyright 2007-2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2003 Motorola Inc.
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* Modified by Xianghua Xiao, X.Xiao@motorola.com
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/processor.h>
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#include <asm/fsl_law.h>
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#include <mach/mpc85xx.h>
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#include <mach/mmu.h>
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#include <mach/immap_85xx.h>
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static void fsl_setup_ccsrbar(void)
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{
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u32 temp;
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u32 mas0, mas1, mas2, mas3, mas7;
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u32 *ccsr_virt = (u32 *)(CFG_CCSRBAR + 0x1000);
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mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);
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mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);
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mas2 = FSL_BOOKE_MAS2(CFG_CCSRBAR + 0x1000, MAS2_I|MAS2_G);
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mas3 = FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, MAS3_SW|MAS3_SR);
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mas7 = FSL_BOOKE_MAS7(CFG_CCSRBAR_DEFAULT);
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e500_write_tlb(mas0, mas1, mas2, mas3, mas7);
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temp = in_be32(ccsr_virt);
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out_be32(ccsr_virt, CFG_CCSRBAR_PHYS >> 12);
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temp = in_be32((u32 *)CFG_CCSRBAR);
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}
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int fsl_l2_cache_init(void)
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{
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void __iomem *l2cache = (void __iomem *)MPC85xx_L2_ADDR;
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uint cache_ctl;
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uint svr, ver;
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u32 l2siz_field;
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svr = get_svr();
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ver = SVR_SOC_VER(svr);
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asm("msync;isync");
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cache_ctl = in_be32(l2cache + MPC85xx_L2_CTL_OFFSET);
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l2siz_field = (cache_ctl >> 28) & 0x3;
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switch (l2siz_field) {
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case 0x0:
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return -1;
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break;
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case 0x1:
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cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, L2SRAM=0 */
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break;
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case 0x2:
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/* set L2E=1, L2I=1, & L2SRAM=0 */
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cache_ctl = 0xc0000000;
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break;
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case 0x3:
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/* set L2E=1, L2I=1, & L2SRAM=0 */
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cache_ctl = 0xc0000000;
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break;
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}
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if (!(in_be32(l2cache + MPC85xx_L2_CTL_OFFSET) & MPC85xx_L2CTL_L2E)) {
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asm("msync;isync");
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/* invalidate & enable */
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out_be32(l2cache + MPC85xx_L2_CTL_OFFSET, cache_ctl);
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asm("msync;isync");
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}
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return 0;
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}
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void cpu_init_early_f(void)
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{
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u32 mas0, mas1, mas2, mas3, mas7;
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mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0);
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mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);
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mas2 = FSL_BOOKE_MAS2(CFG_CCSRBAR, MAS2_I|MAS2_G);
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mas3 = FSL_BOOKE_MAS3(CFG_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
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mas7 = FSL_BOOKE_MAS7(CFG_CCSRBAR_PHYS);
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e500_write_tlb(mas0, mas1, mas2, mas3, mas7);
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/* set up CCSR if we want it moved */
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if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS)
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fsl_setup_ccsrbar();
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fsl_init_laws();
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e500_invalidate_tlb(0);
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e500_init_tlbs();
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}
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void cpu_init_f(void)
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{
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e500_disable_tlb(14);
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e500_disable_tlb(15);
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fsl_init_early_memctl_regs();
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}
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@ -0,0 +1,73 @@
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/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
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* arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
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* cpu specific common code for 85xx/86xx processors.
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <mach/immap_85xx.h>
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struct cpu_type cpu_type_list[] = {
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CPU_TYPE_ENTRY(P2020, P2020, 2),
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CPU_TYPE_ENTRY(P2020, P2020_E, 2),
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};
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struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 1);
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struct cpu_type *identify_cpu(u32 ver)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) {
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if (cpu_type_list[i].soc_ver == ver)
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return &cpu_type_list[i];
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}
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return &cpu_type_unknown;
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}
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int fsl_cpu_numcores(void)
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{
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void __iomem *pic = (void __iomem *)MPC8xxx_PIC_ADDR;
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struct cpu_type *cpu;
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uint svr;
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uint ver;
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int tmp;
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svr = get_svr();
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ver = SVR_SOC_VER(svr);
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cpu = identify_cpu(ver);
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/* better to query feature reporting register than just assume 1 */
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if (cpu == &cpu_type_unknown) {
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tmp = in_be32(pic + MPC85xx_PIC_FRR_OFFSET);
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tmp = (tmp & MPC8xxx_PICFRR_NCPU_MASK) >>
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MPC8xxx_PICFRR_NCPU_SHIFT;
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tmp += 1;
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} else {
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tmp = cpu->num_cores;
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}
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return tmp;
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}
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