Make S3C24xx config options available for all S3Cs
Signed-off-by: Alexey Galakhov <agalakhov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
parent
fd0e39fe55
commit
5ef3ecd922
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@ -136,7 +136,7 @@ static int a9m2410_devices_init(void)
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device_initcall(a9m2410_devices_init);
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device_initcall(a9m2410_devices_init);
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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#ifdef CONFIG_S3C_NAND_BOOT
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void __bare_init nand_boot(void)
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void __bare_init nand_boot(void)
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{
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{
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s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
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s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
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@ -115,7 +115,7 @@
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#define A9M2410_TWRPH1 1
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#define A9M2410_TWRPH1 1
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/* needed in the generic NAND boot code only */
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/* needed in the generic NAND boot code only */
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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#ifdef CONFIG_S3C_NAND_BOOT
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# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2410_TACLS, A9M2410_TWRPH0, A9M2410_TWRPH1)
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# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2410_TACLS, A9M2410_TWRPH0, A9M2410_TWRPH1)
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#endif
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#endif
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@ -28,7 +28,7 @@ board_init_lowlevel:
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bl s3c24x0_sdram_init
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bl s3c24x0_sdram_init
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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#ifdef CONFIG_S3C_NAND_BOOT
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mov lr, r10 /* restore the link register */
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mov lr, r10 /* restore the link register */
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/* up to here we are running from the internal SRAM area */
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/* up to here we are running from the internal SRAM area */
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b s3c24x0_nand_boot /* does return directly to our caller into SDRAM */
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b s3c24x0_nand_boot /* does return directly to our caller into SDRAM */
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@ -155,7 +155,7 @@ static int a9m2440_devices_init(void)
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device_initcall(a9m2440_devices_init);
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device_initcall(a9m2440_devices_init);
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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#ifdef CONFIG_S3C_NAND_BOOT
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void __bare_init nand_boot(void)
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void __bare_init nand_boot(void)
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{
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{
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s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
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s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
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@ -66,7 +66,7 @@
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#define A9M2440_TWRPH1 1
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#define A9M2440_TWRPH1 1
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/* needed in the generic NAND boot code only */
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/* needed in the generic NAND boot code only */
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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#ifdef CONFIG_S3C_NAND_BOOT
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# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1)
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# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1)
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#endif
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#endif
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@ -232,7 +232,7 @@ board_init_lowlevel:
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bl sdram_init
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bl sdram_init
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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#ifdef CONFIG_S3C_NAND_BOOT
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mov lr, r10 /* restore the link register */
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mov lr, r10 /* restore the link register */
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/* up to here we are running from the internal SRAM area */
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/* up to here we are running from the internal SRAM area */
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b s3c24x0_nand_boot /* does return directly to our caller into SDRAM */
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b s3c24x0_nand_boot /* does return directly to our caller into SDRAM */
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@ -66,7 +66,7 @@
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#define MINI2440_TWRPH1 1
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#define MINI2440_TWRPH1 1
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/* needed in the generic NAND boot code only */
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/* needed in the generic NAND boot code only */
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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#ifdef CONFIG_S3C_NAND_BOOT
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# define BOARD_DEFAULT_NAND_TIMING \
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# define BOARD_DEFAULT_NAND_TIMING \
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CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0, MINI2440_TWRPH1)
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CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0, MINI2440_TWRPH1)
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#endif
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#endif
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@ -30,7 +30,7 @@ board_init_lowlevel:
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bl s3c24x0_sdram_init
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bl s3c24x0_sdram_init
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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#ifdef CONFIG_S3C_NAND_BOOT
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mov lr, r10 /* restore the link register */
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mov lr, r10 /* restore the link register */
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/* up to here we are running from the internal SRAM area */
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/* up to here we are running from the internal SRAM area */
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b s3c24x0_nand_boot /* does return directly to our caller into SDRAM */
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b s3c24x0_nand_boot /* does return directly to our caller into SDRAM */
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@ -326,7 +326,7 @@ static int mini2440_devices_init(void)
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device_initcall(mini2440_devices_init);
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device_initcall(mini2440_devices_init);
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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#ifdef CONFIG_S3C_NAND_BOOT
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void __bare_init nand_boot(void)
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void __bare_init nand_boot(void)
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{
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{
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s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
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s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
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@ -1,5 +1,5 @@
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CONFIG_ARCH_S3C24xx=y
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CONFIG_ARCH_S3C24xx=y
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CONFIG_S3C24XX_NAND_BOOT=y
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CONFIG_S3C_NAND_BOOT=y
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CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
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CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
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CONFIG_BROKEN=y
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CONFIG_BROKEN=y
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CONFIG_EXPERIMENTAL=y
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CONFIG_EXPERIMENTAL=y
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@ -1,7 +1,7 @@
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CONFIG_ARCH_S3C24xx=y
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CONFIG_ARCH_S3C24xx=y
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CONFIG_MACH_A9M2440=y
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CONFIG_MACH_A9M2440=y
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CONFIG_S3C24XX_SDRAM_INIT=y
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CONFIG_S3C_SDRAM_INIT=y
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CONFIG_S3C24XX_NAND_BOOT=y
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CONFIG_S3C_NAND_BOOT=y
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CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
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CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
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CONFIG_BROKEN=y
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CONFIG_BROKEN=y
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CONFIG_EXPERIMENTAL=y
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CONFIG_EXPERIMENTAL=y
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@ -1,7 +1,7 @@
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CONFIG_ARCH_S3C24xx=y
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CONFIG_ARCH_S3C24xx=y
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CONFIG_MACH_MINI2440=y
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CONFIG_MACH_MINI2440=y
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CONFIG_MINI2440_VIDEO_N35=y
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CONFIG_MINI2440_VIDEO_N35=y
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CONFIG_S3C24XX_NAND_BOOT=y
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CONFIG_S3C_NAND_BOOT=y
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CONFIG_AEABI=y
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CONFIG_AEABI=y
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CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
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CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
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CONFIG_TEXT_BASE=0x33e00000
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CONFIG_TEXT_BASE=0x33e00000
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@ -30,8 +30,8 @@ config MACH_A9M2410
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bool "Digi A9M2410"
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bool "Digi A9M2410"
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select CPU_S3C2410
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select CPU_S3C2410
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select MACH_HAS_LOWLEVEL_INIT
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select MACH_HAS_LOWLEVEL_INIT
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select S3C24XX_PLL_INIT
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select S3C_PLL_INIT
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select S3C24XX_SDRAM_INIT
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select S3C_SDRAM_INIT
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help
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help
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Say Y here if you are using Digi's Connect Core 9M equipped
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Say Y here if you are using Digi's Connect Core 9M equipped
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with a Samsung S3C2410 Processor
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with a Samsung S3C2410 Processor
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@ -40,7 +40,7 @@ config MACH_A9M2440
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bool "Digi A9M2440"
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bool "Digi A9M2440"
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select CPU_S3C2440
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select CPU_S3C2440
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select MACH_HAS_LOWLEVEL_INIT
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select MACH_HAS_LOWLEVEL_INIT
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select S3C24XX_PLL_INIT
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select S3C_PLL_INIT
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help
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help
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Say Y here if you are using Digi's Connect Core 9M equipped
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Say Y here if you are using Digi's Connect Core 9M equipped
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with a Samsung S3C2440 Processor
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with a Samsung S3C2440 Processor
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@ -50,8 +50,8 @@ config MACH_MINI2440
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select CPU_S3C2440
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select CPU_S3C2440
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select MACH_HAS_LOWLEVEL_INIT
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select MACH_HAS_LOWLEVEL_INIT
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select MACH_DO_LOWLEVEL_INIT
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select MACH_DO_LOWLEVEL_INIT
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select S3C24XX_PLL_INIT
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select S3C_PLL_INIT
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select S3C24XX_SDRAM_INIT
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select S3C_SDRAM_INIT
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select HAS_DM9000
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select HAS_DM9000
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help
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help
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Say Y here if you are using Mini 2440 dev board equipped
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Say Y here if you are using Mini 2440 dev board equipped
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@ -78,29 +78,31 @@ source arch/arm/boards/mini2440/Kconfig
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endmenu
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endmenu
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menu "S3C24X0 Features "
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endif
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config S3C24XX_LOW_LEVEL_INIT
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menu "S3C Features "
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config S3C_LOWLEVEL_INIT
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bool
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bool
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config S3C24XX_PLL_INIT
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config S3C_PLL_INIT
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bool
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bool
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prompt "Reconfigure PLL"
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prompt "Reconfigure PLL"
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select S3C24XX_LOW_LEVEL_INIT
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select S3C_LOWLEVEL_INIT
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help
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help
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This adds generic code to reconfigure the internal PLL very early
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This adds generic code to reconfigure the internal PLL very early
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after reset.
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after reset.
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config S3C24XX_SDRAM_INIT
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config S3C_SDRAM_INIT
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bool
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bool
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prompt "Initialize SDRAM"
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prompt "Initialize SDRAM"
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select S3C24XX_LOW_LEVEL_INIT
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select S3C_LOWLEVEL_INIT
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help
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help
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This adds generic code to configure the SDRAM controller after reset.
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This adds generic code to configure the SDRAM controller after reset.
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The initialisation will be skipped if the code is already running
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The initialisation will be skipped if the code is already running
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from SDRAM.
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from SDRAM.
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config S3C24XX_NAND_BOOT
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config S3C_NAND_BOOT
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bool
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bool
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prompt "Booting from NAND"
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prompt "Booting from NAND"
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select MTD
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select MTD
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@ -113,5 +115,3 @@ config S3C24XX_NAND_BOOT
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endmenu
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endmenu
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endif
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endif
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endif
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@ -1,3 +1,3 @@
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obj-y += s3c-timer.o generic.o
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obj-y += s3c-timer.o generic.o
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obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o
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obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o
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obj-$(CONFIG_S3C24XX_LOW_LEVEL_INIT) += lowlevel-init.o
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obj-$(CONFIG_S3C_LOWLEVEL_INIT) += lowlevel-init.o
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@ -54,7 +54,7 @@
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* if we are booting from NAND, its internal SRAM occures at
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* if we are booting from NAND, its internal SRAM occures at
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* a different address than without this feature
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* a different address than without this feature
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*/
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*/
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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#ifdef CONFIG_S3C_NAND_BOOT
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# define NFC_RAM_AREA 0x00000000
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# define NFC_RAM_AREA 0x00000000
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#else
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#else
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# define NFC_RAM_AREA 0x40000000
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# define NFC_RAM_AREA 0x40000000
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@ -18,7 +18,7 @@
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*
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*
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*/
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*/
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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#ifdef CONFIG_S3C_NAND_BOOT
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extern void s3c24x0_nand_load_image(void*, int, int);
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extern void s3c24x0_nand_load_image(void*, int, int);
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#endif
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#endif
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@ -70,7 +70,7 @@ routine very early in your board_init_lowlevel routine.
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* Note: Do not use "r10" here in this code
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* Note: Do not use "r10" here in this code
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*/
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*/
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#ifdef CONFIG_S3C24XX_PLL_INIT
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#ifdef CONFIG_S3C_PLL_INIT
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.section ".text_bare_init.s3c24x0_pll_init","ax"
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.section ".text_bare_init.s3c24x0_pll_init","ax"
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@ -146,7 +146,7 @@ shared with all other system on chip components. Most of the time this
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configuration is to slow for the CPU and to fast for the other components.
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configuration is to slow for the CPU and to fast for the other components.
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PLL reprogramming can be done in the machine specific manner very early when
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PLL reprogramming can be done in the machine specific manner very early when
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the CONFIG_S3C24XX_PLL_INIT and CONFIG_MACH_HAS_LOWLEVEL_INIT symbols are
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the CONFIG_S3C_PLL_INIT and CONFIG_MACH_HAS_LOWLEVEL_INIT symbols are
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defined. The board must provide a board_init_lowlevel() assembler function in
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defined. The board must provide a board_init_lowlevel() assembler function in
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this case and calling the s3c24x0_pll_init() assembler function.
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this case and calling the s3c24x0_pll_init() assembler function.
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@ -184,7 +184,7 @@ With m = MDIV + 8, p = PDIV + 2 and s = SDIV.
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/* ----------------------------------------------------------------------- */
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/* ----------------------------------------------------------------------- */
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#ifdef CONFIG_S3C24XX_SDRAM_INIT
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#ifdef CONFIG_S3C_SDRAM_INIT
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.section ".text_bare_init.s3c24x0_sdram_init","ax"
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.section ".text_bare_init.s3c24x0_sdram_init","ax"
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@ -225,7 +225,7 @@ SDRAMDATA:
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The SDRAM controller is very simple and its initialisation requires only a
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The SDRAM controller is very simple and its initialisation requires only a
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few steps. barebox provides a generic routine to do this step.
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few steps. barebox provides a generic routine to do this step.
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Enable CONFIG_S3C24XX_SDRAM_INIT and CONFIG_MACH_HAS_LOWLEVEL_INIT to be able
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Enable CONFIG_S3C_SDRAM_INIT and CONFIG_MACH_HAS_LOWLEVEL_INIT to be able
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to call the generic s3c24x0_sdram_init() assembler function from within the
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to call the generic s3c24x0_sdram_init() assembler function from within the
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machine specific board_init_lowlevel() assembler function.
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machine specific board_init_lowlevel() assembler function.
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@ -245,7 +245,7 @@ Define in the machine specific config.h the following list of symbols:
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/* ----------------------------------------------------------------------- */
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/* ----------------------------------------------------------------------- */
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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#ifdef CONFIG_S3C_NAND_BOOT
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.section ".text_bare_init.s3c24x0_nand_boot","ax"
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.section ".text_bare_init.s3c24x0_nand_boot","ax"
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@ -284,7 +284,7 @@ s3c24x0_nand_boot:
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@page dev_s3c24xx_nandboot_handling Booting from NAND
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@page dev_s3c24xx_nandboot_handling Booting from NAND
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To be able to boot from NAND memory only, enable the S3C24x0 NAND driver. Also
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To be able to boot from NAND memory only, enable the S3C24x0 NAND driver. Also
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enable CONFIG_S3C24XX_NAND_BOOT and CONFIG_MACH_HAS_LOWLEVEL_INIT to be
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enable CONFIG_S3C_NAND_BOOT and CONFIG_MACH_HAS_LOWLEVEL_INIT to be
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able to call the s3c24x0_nand_boot() assembler routine from within the
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able to call the s3c24x0_nand_boot() assembler routine from within the
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machine specific board_init_lowlevel() assembler function.
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machine specific board_init_lowlevel() assembler function.
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#include <io.h>
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#include <io.h>
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#include <asm-generic/errno.h>
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#include <asm-generic/errno.h>
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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#ifdef CONFIG_S3C_NAND_BOOT
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# define __nand_boot_init __bare_init
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# define __nand_boot_init __bare_init
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# ifndef BOARD_DEFAULT_NAND_TIMING
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# ifndef BOARD_DEFAULT_NAND_TIMING
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# define BOARD_DEFAULT_NAND_TIMING 0x0737
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# define BOARD_DEFAULT_NAND_TIMING 0x0737
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* Define this symbol for testing purpose. It will add a command to read an
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* Define this symbol for testing purpose. It will add a command to read an
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* image from the NAND like it the boot strap code will do.
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* image from the NAND like it the boot strap code will do.
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*/
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*/
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#define CONFIG_NAND_S3C24XX_BOOT_DEBUG
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#define CONFIG_NAND_S3C_BOOT_DEBUG
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/* NAND controller's register */
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/* NAND controller's register */
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@ -497,7 +497,7 @@ static struct driver_d s3c24x0_nand_driver = {
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.probe = s3c24x0_nand_probe,
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.probe = s3c24x0_nand_probe,
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};
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};
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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#ifdef CONFIG_S3C_NAND_BOOT
|
||||||
|
|
||||||
static void __nand_boot_init wait_for_completion(void __iomem *host)
|
static void __nand_boot_init wait_for_completion(void __iomem *host)
|
||||||
{
|
{
|
||||||
|
@ -603,7 +603,7 @@ void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page)
|
||||||
disable_nand_controller(host);
|
disable_nand_controller(host);
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_NAND_S3C24XX_BOOT_DEBUG
|
#ifdef CONFIG_NAND_S3C_BOOT_DEBUG
|
||||||
#include <command.h>
|
#include <command.h>
|
||||||
|
|
||||||
static int do_nand_boot_test(int argc, char *argv[])
|
static int do_nand_boot_test(int argc, char *argv[])
|
||||||
|
@ -636,7 +636,7 @@ BAREBOX_CMD_START(nand_boot_test)
|
||||||
BAREBOX_CMD_END
|
BAREBOX_CMD_END
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* CONFIG_S3C24XX_NAND_BOOT */
|
#endif /* CONFIG_S3C_NAND_BOOT */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Main initialization routine
|
* Main initialization routine
|
||||||
|
|
Loading…
Reference in New Issue