011-OMAP-add-silicon
[Patch 11/17] U-Boot-V2:ARM:OMAP3: Add support for OMAP3 Silicon files This patch introduces support for OMAP3430 - provides for generic OMAP3 files. Signed-off-by: Nishanth Menon<x0nishan@ti.com>
This commit is contained in:
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053034d182
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#
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# OMAP Architecture specific features
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#
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# (C) Copyright 2008
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# Texas Instruments, <www.ti.com>
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# Nishanth Menon <x0nishan@ti.com>
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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menu "OMAP Features"
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depends on ARCH_OMAP
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choice
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prompt "Select OMAP Variant"
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config ARCH_OMAP3
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bool "OMAP3"
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select ARMCORTEXA8
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select ARCH_HAS_LOWLEVEL_INIT
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select OMAP_CLOCK_SOURCE_S32K
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help
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Say Y here if you are using Texas Instrument's OMAP343x based platform
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endchoice
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config OMAP_CONFIG_STACKSIZE
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prompt "STACKSIZE"
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hex
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default 0x00020000
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help
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Select the Stack Size when defaults are used
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config OMAP_MALLOC_LEN
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prompt "MALLOC LENGTH"
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hex
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default 0x00001000
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help
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Select the Malloc Length when defaults are used
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config OMAP3_CLOCK_CONFIG
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depends on ARCH_OMAP
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bool "Clock Configuration"
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help
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Say Y here if you like to have OMAP3 Clock configuration done.
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### Generic Clock configurations to be enabled by Mach - invisible to enable.
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config OMAP_CLOCK_UART
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bool
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config OMAP_CLOCK_UART2
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bool
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config OMAP_CLOCK_UART3
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bool
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config OMAP_CLOCK_I2C
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bool
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# Blind enable all possible clocks.. think twice before you do this.
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config OMAP_CLOCK_ALL
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bool
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config OMAP_CLOCK_SOURCE_S32K
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bool
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config OMAP3_CLOCK_CONFIG
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prompt "Clock Configuration"
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bool
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depends on ARCH_OMAP3
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default y
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help
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Say Y here if you like to have OMAP3 Clock configuration done.
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config OMAP3_COPY_CLOCK_SRAM
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prompt "SRAM copy of Clock code"
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bool
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depends on OMAP3_CLOCK_CONFIG
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default y
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help
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Say Y here if you like to have initial OMAP3 Clock configuration done from SRAM.
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endmenu
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@ -0,0 +1,25 @@
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# OMAP Architecture Makefile
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#
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# (C) Copyright 2008
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# Texas Instruments, <www.ti.com>
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# Nishanth Menon <x0nishan@ti.com>
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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obj-$(CONFIG_ARCH_OMAP) += syslib.o
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obj-$(CONFIG_OMAP_CLOCK_SOURCE_S32K) += s32k_clksource.o
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obj-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o
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obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock_core.o omap3_clock.o
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/**
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* @file
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* @brief Provide Architecture level Initialization
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*
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* FileName: arch/arm/mach-omap/omap3_core.S
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*
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* This provides OMAP3 Architecture initialization. Among these,
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* @li OMAP ROM Code is located in SRAM, we can piggy back on
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* the same addresses
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* @li If clock initialization is required, call the same.
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* @li Setup a temporary SRAM stack which is necessary to call C
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* functions.
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* @li Call architecture initialization function a_init
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*
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* arch_init_lowlevel is enabled if CONFIG_ARCH_HAS_LOWLEVEL_INIT is defined
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* cpy_clk_code is called if CONFIG_OMAP3_COPY_CLOCK_SRAM is defined
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*/
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/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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* Nishanth Menon <x0nishan@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/arch/silicon.h>
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#include <asm/arch/wdt.h>
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#include <asm/arch/clocks.h>
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#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT
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.globl arch_init_lowlevel
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arch_init_lowlevel:
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/* Copy vectors to mask ROM indirect addr */
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mov r0, pc /* Store the current pc address */
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sub r0, r0, #8 /* Reduce offset */
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ldr r1, arch_start /* Load the link address for arch_int */
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ldr r2, uboot_start /* load the link address of start_init*/
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sub r1, r1, r2 /* get the offset */
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/* subtract the offset from PC of arch=Current start */
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sub r0, r0, r1
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mov r2, #OMAP_SRAM_INTVECT_COPYSIZE /* r2 <- size to copy */
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add r2, r0, r2 /* r2 <- source end address */
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ldr r1, SRAM_INTVECT /* build vect addr */
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next:
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ldmia r0!, {r3-r10} /* copy from source address [r0] */
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stmia r1!, {r3-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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ble next /* loop until equal */
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#ifdef CONFIG_OMAP3_COPY_CLOCK_SRAM
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/* No need to copy/exec the clock code - DPLL adjust already done
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* in Perip/NAND/oneNAND Boot.
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* Put dpll adjust code behind vectors. r1 has address to copy to
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*/
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bl cpy_clk_code
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#endif
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ldr r1, SRAM_INTVECT /* build vect addr */
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/* Read the interrupt vector base address */
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mrc p15, #0, r0, c12, c0, #0
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/* Clear the vector base 4:0 is reserved. */
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and r0, r0, #0xF
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/* Store the SRAM_INTVECT address */
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orr r0, r0, r1
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/* Store the new vector address */
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mcr p15, #0, r0, c12, c0, #0
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/* Setup a temporary stack so that we can call C functions */
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ldr sp, SRAM_STACK
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str ip, [sp] /* stash old link register */
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str lr, [sp] /* stash current link register */
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mov ip, lr /* save link reg across call */
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bl a_init /* Architecture init */
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ldr lr, [sp] /* restore current link register */
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ldr ip, [sp] /* restore save ip */
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/* back to arch calling code */
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mov pc, lr
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arch_start:
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.word arch_init_lowlevel
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uboot_start:
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.word _start
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SRAM_INTVECT:
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.word OMAP_SRAM_INTVECT
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SRAM_STACK:
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.word OMAP_SRAM_STACK
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#endif /* CONFIG_ARCH_HAS_LOWLEVEL_INIT */
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/**
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* @file
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* @brief Provide Generic implementations for OMAP3 architecture
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*
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* FileName: arch/arm/mach-omap/omap3_generic.c
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*
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* This file contains the generic implementations of various OMAP3
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* relevant functions
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* For more info on OMAP34XX, see http://focus.ti.com/pdfs/wtbu/swpu114g.pdf
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*
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* Important one is @ref a_init which is architecture init code.
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* The implemented functions are present in sys_info.h
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*
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* Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz
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*/
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/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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* Nishanth Menon <x0nishan@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/io.h>
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#include <asm/arch/silicon.h>
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#include <asm/arch/gpmc.h>
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#include <asm/arch/sdrc.h>
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#include <asm/arch/control.h>
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#include <asm/arch/omap3-smx.h>
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#include <asm/arch/clocks.h>
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#include <asm/arch/wdt.h>
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#include <asm/arch/sys_info.h>
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#include <asm/arch/syslib.h>
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/**
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* @brief Reset the CPU
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*
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* In case of crashes, reset the CPU
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*
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* @param[in] addr -Cause of crash
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*
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* @return void
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*/
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void reset_cpu(ulong addr)
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{
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/* FIXME: Enable WDT and cause reset */
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hang();
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}
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EXPORT_SYMBOL(reset_cpu);
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/**
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* @brief Low level CPU type
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*
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* @return CPU_3430
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*/
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u32 get_cpu_type(void)
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{
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/* FIXME: need to get register defines for 3430 */
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return CPU_3430;
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}
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/**
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* @brief Extract the OMAP ES rev
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*
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* @return CPU_ES version
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*/
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u32 get_cpu_rev(void)
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{
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u32 idcode_val;
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idcode_val = __raw_readl(IDCODE_REG);
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if ((idcode_val & (HAWKEYE_MASK | VERSION_MASK)) == HAWKEYE_ES2_1)
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return CPU_ES2P1;
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if ((idcode_val & HAWKEYE_MASK) == HAWKEYE_ES2)
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return CPU_ES2;
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/* unsupported! */
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return CPU_ES1;
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}
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/**
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* @brief Get size of chip select 0/1
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*
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* @param[in] offset give the offset if we need CS1
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*
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* @return return the sdram size.
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*/
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u32 get_sdr_cs_size(u32 offset)
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{
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u32 size;
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/* get ram size field */
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size = __raw_readl(SDRC_REG(MCFG_0) + offset) >> 8;
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size &= 0x3FF; /* remove unwanted bits */
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size *= 2 * (1024 * 1024); /* find size in MB */
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return size;
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}
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/**
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* @brief Get the initial SYSBOOT value
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*
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* SYSBOOT is useful to know which state OMAP booted from.
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*
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* @return - Return the value of SYSBOOT.
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*/
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inline u32 get_sysboot_value(void)
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{
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return (0x0000003F & __raw_readl(CONTROL_REG(STATUS)));
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}
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/**
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* @brief Return the current CS0 base address
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*
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* Return current address hardware will be
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* fetching from. The below effectively gives what is correct, its a bit
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* mis-leading compared to the TRM. For the most general case the mask
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* needs to be also taken into account this does work in practice.
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*
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* @return base address
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*/
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u32 get_gpmc0_base(void)
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{
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u32 b;
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b = __raw_readl(GPMC_REG(CONFIG7_0));
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b &= 0x1F; /* keep base [5:0] */
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b = b << 24; /* ret 0x0b000000 */
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return b;
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}
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/**
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* @brief Get the upper address of current execution
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*
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* we can use this to figure out if we are running in SRAM /
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* XIP Flash or in SDRAM
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*
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* @return base address
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*/
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u32 get_base(void)
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{
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u32 val;
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__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
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val &= 0xF0000000;
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val >>= 28;
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return val;
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}
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/**
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* @brief Are we running in Flash XIP?
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*
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* If the base is in GPMC address space, we probably are!
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*
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* @return 1 if we are running in XIP mode, else return 0
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*/
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u32 running_in_flash(void)
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{
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if (get_base() < 4)
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return 1; /* in flash */
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return 0; /* running in SRAM or SDRAM */
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}
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/**
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* @brief Are we running in OMAP internal SRAM?
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*
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* If in SRAM address, then yes!
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*
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* @return 1 if we are running in SRAM, else return 0
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*/
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u32 running_in_sram(void)
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{
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if (get_base() == 4)
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return 1; /* in SRAM */
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return 0; /* running in FLASH or SDRAM */
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}
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/**
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* @brief Are we running in SDRAM?
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*
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* if we are not in GPMC nor in SRAM address space,
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* we are in SDRAM execution area
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*
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* @return 1 if we are running from SDRAM, else return 0
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*/
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u32 running_in_sdram(void)
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{
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if (get_base() > 4)
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return 1; /* in sdram */
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return 0; /* running in SRAM or FLASH */
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}
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EXPORT_SYMBOL(running_in_sdram);
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/**
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* @brief Is this an XIP type device or a stream one
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*
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* Sysboot bits 4-0 specify type. Bit 5, sys mem/perif
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*
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* @return Boot type
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*/
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u32 get_boot_type(void)
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{
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u32 v;
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v = get_sysboot_value() & ((0x1 << 4) | (0x1 << 3) | (0x1 << 2) |
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(0x1 << 1) | (0x1 << 0));
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return v;
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}
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/**
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* @brief What type of device are we?
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*
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* are we on a GP/HS/EMU/TEST device?
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*
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* @return device type
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*/
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u32 get_device_type(void)
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{
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int mode;
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mode = __raw_readl(CONTROL_REG(STATUS)) & (DEVICE_MASK);
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return (mode >>= 8);
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}
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/**
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* @brief Setup security registers for access
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*
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* This can be done for GP Device only. for HS/EMU devices, read TRM.
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*
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* @return void
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*/
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static void secure_unlock_mem(void)
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{
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/* Permission values for registers -Full fledged permissions to all */
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#define UNLOCK_1 0xFFFFFFFF
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#define UNLOCK_2 0x00000000
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#define UNLOCK_3 0x0000FFFF
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/* Protection Module Register Target APE (PM_RT) */
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__raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
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__raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
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__raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
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__raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
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__raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
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__raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
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__raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
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__raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
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__raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
|
||||
__raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
|
||||
__raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
|
||||
|
||||
/* IVA Changes */
|
||||
__raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
|
||||
__raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
|
||||
__raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
|
||||
|
||||
__raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Come out of secure mode
|
||||
* If chip is EMU and boot type is external configure
|
||||
* secure registers and exit secure world general use.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void secureworld_exit(void)
|
||||
{
|
||||
unsigned long i;
|
||||
|
||||
/* configrue non-secure access control register */
|
||||
__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
|
||||
/* enabling co-processor CP10 and CP11 accesses in NS world */
|
||||
__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
|
||||
/* allow allocation of locked TLBs and L2 lines in NS world */
|
||||
/* allow use of PLE registers in NS world also */
|
||||
__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
|
||||
__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
|
||||
|
||||
/* Enable ASA in ACR register */
|
||||
__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
|
||||
__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
|
||||
__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
|
||||
|
||||
/* Exiting secure world */
|
||||
__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
|
||||
__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
|
||||
__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Shut down the watchdogs
|
||||
*
|
||||
* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
|
||||
* either taken care of by ROM (HS/EMU) or not accessible (GP).
|
||||
* We need to take care of WD2-MPU or take a PRCM reset. WD3
|
||||
* should not be running and does not generate a PRCM reset.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void watchdog_init(void)
|
||||
{
|
||||
int pending = 1;
|
||||
|
||||
sr32(CM_REG(FCLKEN_WKUP), 5, 1, 1);
|
||||
sr32(CM_REG(ICLKEN_WKUP), 5, 1, 1);
|
||||
wait_on_value((0x1 << 5), 0x20, CM_REG(IDLEST_WKUP), 5);
|
||||
|
||||
__raw_writel(WDT_DISABLE_CODE1, WDT_REG(WSPR));
|
||||
|
||||
do {
|
||||
pending = __raw_readl(WDT_REG(WWPS));
|
||||
} while (pending);
|
||||
|
||||
__raw_writel(WDT_DISABLE_CODE2, WDT_REG(WSPR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write to AuxCR desired value using SMI.
|
||||
* general use.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void setup_auxcr(void)
|
||||
{
|
||||
unsigned long i;
|
||||
volatile unsigned int j;
|
||||
/* Save r0, r12 and restore them after usage */
|
||||
__asm__ __volatile__("mov %0, r12":"=r"(j));
|
||||
__asm__ __volatile__("mov %0, r0":"=r"(i));
|
||||
|
||||
/* GP Device ROM code API usage here */
|
||||
/* r12 = AUXCR Write function and r0 value */
|
||||
__asm__ __volatile__("mov r12, #0x3");
|
||||
__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
|
||||
/* Enabling ASA */
|
||||
__asm__ __volatile__("orr r0, r0, #0x10");
|
||||
/* SMI instruction to call ROM Code API */
|
||||
__asm__ __volatile__(".word 0xE1600070");
|
||||
__asm__ __volatile__("mov r0, %0":"=r"(i));
|
||||
__asm__ __volatile__("mov r12, %0":"=r"(j));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Try to unlock the SRAM for general use
|
||||
*
|
||||
* If chip is GP/EMU(special) type, unlock the SRAM for
|
||||
* general use.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void try_unlock_memory(void)
|
||||
{
|
||||
int mode;
|
||||
int in_sdram = running_in_sdram();
|
||||
|
||||
/* if GP device unlock device SRAM for general use */
|
||||
/* secure code breaks for Secure/Emulation device - HS/E/T */
|
||||
mode = get_device_type();
|
||||
if (mode == GP_DEVICE)
|
||||
secure_unlock_mem();
|
||||
/* If device is EMU and boot is XIP external booting
|
||||
* Unlock firewalls and disable L2 and put chip
|
||||
* out of secure world
|
||||
*/
|
||||
/* Assuming memories are unlocked by the demon who put us in SDRAM */
|
||||
if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
|
||||
&& (!in_sdram)) {
|
||||
secure_unlock_mem();
|
||||
secureworld_exit();
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief OMAP3 Architecture specific Initialization
|
||||
*
|
||||
* Does early system init of disabling the watchdog, enable
|
||||
* memory and configuring the clocks.
|
||||
*
|
||||
* prcm_init is called only if CONFIG_OMAP3_CLOCK_CONFIG is defined.
|
||||
* We depend on link time clean up to remove a_init if no caller exists.
|
||||
*
|
||||
* @warning Called path is with SRAM stack
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
void a_init(void)
|
||||
{
|
||||
watchdog_init();
|
||||
|
||||
try_unlock_memory();
|
||||
|
||||
/* Writing to AuxCR in U-boot using SMI for GP DEV */
|
||||
/* Currently SMI in Kernel on ES2 devices seems to have an isse
|
||||
* Once that is resolved, we can postpone this config to kernel
|
||||
*/
|
||||
if (get_device_type() == GP_DEVICE)
|
||||
setup_auxcr();
|
||||
|
||||
sdelay(100);
|
||||
|
||||
#ifdef CONFIG_OMAP3_CLOCK_CONFIG
|
||||
prcm_init();
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Uart port register read function for OMAP3
|
||||
*
|
||||
* @param base base address of UART
|
||||
* @param reg_idx register index
|
||||
*
|
||||
* @return character read from register
|
||||
*/
|
||||
unsigned int omap_uart_read(unsigned long base, unsigned char reg_idx)
|
||||
{
|
||||
unsigned int *reg_addr = (unsigned int *)base;
|
||||
reg_addr += reg_idx;
|
||||
return __raw_readb(reg_addr);
|
||||
}
|
||||
EXPORT_SYMBOL(omap_uart_read);
|
||||
|
||||
/**
|
||||
* @brief Uart port register write function for OMAP3
|
||||
*
|
||||
* @param val value to write
|
||||
* @param base base address of UART
|
||||
* @param reg_idx register index
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
void omap_uart_write(unsigned int val, unsigned long base,
|
||||
unsigned char reg_idx)
|
||||
{
|
||||
unsigned int *reg_addr = (unsigned int *)base;
|
||||
reg_addr += reg_idx;
|
||||
__raw_writeb(val, reg_addr);
|
||||
}
|
||||
EXPORT_SYMBOL(omap_uart_write);
|
|
@ -0,0 +1,97 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Provide OMAP independent utility APIs
|
||||
*
|
||||
* FileName: arch/arm/mach-omap/syslib.c
|
||||
*
|
||||
* Provide APIs which can be used from platform/architecture code
|
||||
* to operate on
|
||||
*
|
||||
* Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz
|
||||
*/
|
||||
/*
|
||||
* (C) Copyright 2006-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/syslib.h>
|
||||
|
||||
/**
|
||||
* @brief simple spin loop
|
||||
*
|
||||
* Will be constant time as its generally used in bypass conditions only.
|
||||
* This is necessary until timers are accessible. if you need timed delays
|
||||
* use @ref mdelay or @udelay instead
|
||||
*
|
||||
* @param[in] loops number of loops
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
void sdelay(unsigned long loops)
|
||||
{
|
||||
__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
|
||||
"bne 1b":"=r" (loops):"0"(loops));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear & set a value in a bit range for a 32 bit address
|
||||
*
|
||||
* @param[in] addr Address to set/read from
|
||||
* @param[in] start_bit Where to put the value
|
||||
* @param[in] num_bits number of bits the value should be set
|
||||
* @param[in] value the value to set
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
|
||||
{
|
||||
u32 tmp, msk = 0;
|
||||
msk = 1 << num_bits;
|
||||
--msk;
|
||||
tmp = __raw_readl(addr) & ~(msk << start_bit);
|
||||
tmp |= value << start_bit;
|
||||
__raw_writel(tmp, addr);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief common routine to allow waiting for changes in volatile regs.
|
||||
*
|
||||
* @param[in] read_bit_mask the bit mask to read
|
||||
* @param[in] match_value match to which value
|
||||
* @param[in] read_addr address to read from
|
||||
* @param[in] bound max iterations
|
||||
*
|
||||
* @return 1 if match_value is found, else if bound iterations reached,
|
||||
* returns 0
|
||||
*/
|
||||
u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
|
||||
{
|
||||
u32 i = 0, val;
|
||||
do {
|
||||
++i;
|
||||
val = __raw_readl(read_addr) & read_bit_mask;
|
||||
if (val == match_value)
|
||||
return 1;
|
||||
if (i == bound)
|
||||
return 0;
|
||||
} while (1);
|
||||
}
|
||||
|
Loading…
Reference in New Issue