tegra: disable IDDQ for PLL_X on Tegra124
This is an additional power down control. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -0,0 +1,19 @@
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/*
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* Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* Register definitions */
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#define CRC_PLLX_MISC_3 0x518
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#define CRC_PLLX_MISC_3_IDDQ (1 << 3)
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@ -25,6 +25,7 @@
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#include <mach/tegra20-pmc.h>
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#include <mach/tegra30-car.h>
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#include <mach/tegra30-flow.h>
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#include <mach/tegra124-car.h>
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/* instruct the PMIC to enable the CPU power rail */
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static void enable_maincomplex_powerrail(void)
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@ -107,6 +108,14 @@ static void init_pllx(void)
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chiptype = tegra_get_chiptype();
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/* disable IDDQ on T124 */
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if (chiptype == TEGRA124) {
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reg = readl(TEGRA_CLK_RESET_BASE + CRC_PLLX_MISC_3);
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reg &= ~CRC_PLLX_MISC_3_IDDQ;
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writel(reg, TEGRA_CLK_RESET_BASE + CRC_PLLX_MISC_3);
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tegra_ll_delay_usec(2);
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}
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osc_freq = (readl(TEGRA_CLK_RESET_BASE + CRC_OSC_CTRL) &
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CRC_OSC_CTRL_OSC_FREQ_MASK) >> CRC_OSC_CTRL_OSC_FREQ_SHIFT;
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