sysmo-bts
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barebox
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Merge branch 'next'

This commit is contained in:
Sascha Hauer 2011-12-07 12:03:13 +01:00
parent 61b62f6d33 8b3d10265d
commit 0ee6847f7b
235 changed files with 12742 additions and 7688 deletions
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2
MAKEALL
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@ -234,7 +234,7 @@ then
CONFIG="./${CONFIG}"
fi
source "${CONFIG}"
. "${CONFIG}"
fi
[ -d "${LOGDIR}" ] || mkdir ${LOGDIR} || exit 1

5
arch/arm/Kconfig
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@ -62,6 +62,10 @@ config ARCH_NOMADIK
config ARCH_OMAP
bool "TI OMAP"
config ARCH_PXA
bool "Intel/Marvell PXA based"
select GENERIC_GPIO
config ARCH_S3C24xx
bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443"
select CPU_ARM920T
@ -81,6 +85,7 @@ source arch/arm/mach-mxs/Kconfig
source arch/arm/mach-netx/Kconfig
source arch/arm/mach-nomadik/Kconfig
source arch/arm/mach-omap/Kconfig
source arch/arm/mach-pxa/Kconfig
source arch/arm/mach-s3c24xx/Kconfig
source arch/arm/mach-versatile/Kconfig

4
arch/arm/Makefile
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@ -27,6 +27,7 @@ arch-$(CONFIG_CPU_32v4T) :=-D__LINUX_ARM_ARCH__=4 -march=armv4t
# This selects how we optimise for the processor.
tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM926T) :=-mtune=arm9tdmi
tune-$(CONFIG_CPU_XSCALE) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
ifeq ($(CONFIG_AEABI),y)
CFLAGS_ABI :=-mabi=aapcs-linux -mno-thumb-interwork
@ -50,6 +51,7 @@ machine-$(CONFIG_ARCH_MXS) := mxs
machine-$(CONFIG_ARCH_NOMADIK) := nomadik
machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_OMAP) := omap
machine-$(CONFIG_ARCH_PXA) := pxa
machine-$(CONFIG_ARCH_S3C24xx) := s3c24xx
machine-$(CONFIG_ARCH_VERSATILE) := versatile
@ -64,6 +66,7 @@ board-$(CONFIG_MACH_AT91SAM9263EK) := at91sam9263ek
board-$(CONFIG_MACH_AT91SAM9G10EK) := at91sam9261ek
board-$(CONFIG_MACH_AT91SAM9G20EK) := at91sam9260ek
board-$(CONFIG_MACH_AT91SAM9M10G45EK) := at91sam9m10g45ek
board-$(CONFIG_MACH_DSS11) := dss11
board-$(CONFIG_MACH_EDB9301) := edb93xx
board-$(CONFIG_MACH_EDB9302) := edb93xx
board-$(CONFIG_MACH_EDB9302A) := edb93xx
@ -103,6 +106,7 @@ board-$(CONFIG_MACH_CHUMBY) := chumby_falconwing
board-$(CONFIG_MACH_TX28) := karo-tx28
board-$(CONFIG_MACH_FREESCALE_MX51_PDK) := freescale-mx51-pdk
board-$(CONFIG_MACH_FREESCALE_MX53_LOCO) := freescale-mx53-loco
board-$(CONFIG_MACH_FREESCALE_MX53_SMD) := freescale-mx53-smd
board-$(CONFIG_MACH_GUF_CUPID) := guf-cupid
board-$(CONFIG_MACH_MINI2440) := mini2440
board-$(CONFIG_MACH_USB_A9260) := usb-a926x

1
arch/arm/boards/dss11/Makefile Normal file
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@ -0,0 +1 @@
obj-y += init.o

6
arch/arm/boards/dss11/config.h Normal file
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@ -0,0 +1,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#endif /* __CONFIG_H */

42
arch/arm/boards/dss11/env/config vendored Normal file
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@ -0,0 +1,42 @@
#!/bin/sh
# use 'dhcp' to do dhcp in barebox and in kernel
# use 'none' if you want to skip kernel ip autoconfiguration
ip=dhcp
# or set your networking parameters here
#eth0.ipaddr=a.b.c.d
#eth0.netmask=a.b.c.d
#eth0.gateway=a.b.c.d
#eth0.serverip=a.b.c.d
# can be either 'nfs', 'tftp' or 'nand'
kernel_loc=tftp
# can be either 'net', 'nand' or 'initrd'
rootfs_loc=net
# can be either 'jffs2' or 'ubifs'
rootfs_type=ubifs
rootfsimage=root.$rootfs_type
# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
#kernelimage_type=zimage
#kernelimage=zImage
kernelimage_type=uimage
kernelimage=uImage
#kernelimage_type=raw
#kernelimage=Image
#kernelimage_type=raw_lzo
#kernelimage=Image.lzo
nand_device=atmel_nand
nand_parts="128k(bootstrap),512k(barebox)ro,512k(barebox-env),2M(kernel-rescue),2M(kernel-prod),32M(rootfs-rescue),200M(rootfs-prod),-(config)"
rootfs_mtdblock_nand=4
autoboot_timeout=3
bootargs="console=ttyS0,115200"
# set a fancy prompt (if support is compiled in)
PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "

156
arch/arm/boards/dss11/init.c Normal file
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@ -0,0 +1,156 @@
/*
* Copyright (C) 2011 Michael Grzeschik <mgr@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <net.h>
#include <mci.h>
#include <init.h>
#include <environment.h>
#include <fec.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <partition.h>
#include <fs.h>
#include <fcntl.h>
#include <asm/io.h>
#include <asm/hardware.h>
#include <nand.h>
#include <linux/mtd/nand.h>
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <mach/sam9_smc.h>
#include <gpio.h>
#include <mach/io.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
static struct atmel_nand_data nand_pdata = {
.ale = 21,
.cle = 22,
/* .det_pin = ... not connected */
.ecc_mode = NAND_ECC_HW,
.rdy_pin = AT91_PIN_PC13,
.enable_pin = AT91_PIN_PC14,
.bus_width_16 = 1,
};
static struct sam9_smc_config dss11_nand_smc_config = {
.ncs_read_setup = 0,
.nrd_setup = 1,
.ncs_write_setup = 0,
.nwe_setup = 1,
.ncs_read_pulse = 3,
.nrd_pulse = 3,
.ncs_write_pulse = 3,
.nwe_pulse = 3,
.read_cycle = 5,
.write_cycle = 5,
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
.tdf_cycles = 2,
};
static void dss11_add_device_nand(void)
{
/* setup bus-width (16) */
dss11_nand_smc_config.mode |= AT91_SMC_DBW_16;
/* configure chip-select 3 (NAND) */
sam9_smc_configure(3, &dss11_nand_smc_config);
at91_add_device_nand(&nand_pdata);
}
static struct at91_ether_platform_data macb_pdata = {
.phy_addr = 0,
.flags = AT91SAM_ETX2_ETX3_ALTERNATIVE,
};
static void dss11_phy_reset(void)
{
unsigned long rstc;
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
at91_set_gpio_input(AT91_PIN_PA14, 0);
at91_set_gpio_input(AT91_PIN_PA15, 0);
at91_set_gpio_input(AT91_PIN_PA17, 0);
at91_set_gpio_input(AT91_PIN_PA25, 0);
at91_set_gpio_input(AT91_PIN_PA26, 0);
at91_set_gpio_input(AT91_PIN_PA28, 0);
rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0d << 8)) |
AT91_RSTC_URSTEN);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
/* Wait for end hardware reset */
while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(rstc) |
AT91_RSTC_URSTEN);
}
static struct atmel_mci_platform_data dss11_mci_data = {
.bus_width = 4,
.host_caps = MMC_MODE_HS,
};
static struct at91_usbh_data dss11_usbh_data = {
.ports = 2,
};
static int dss11_mem_init(void)
{
at91_add_device_sdram(64 * 1024 * 1024);
return 0;
}
mem_initcall(dss11_mem_init);
static int dss11_devices_init(void)
{
dss11_add_device_nand();
dss11_phy_reset();
at91_add_device_eth(&macb_pdata);
at91_add_device_mci(1, &dss11_mci_data);
at91_add_device_usbh_ohci(&dss11_usbh_data);
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(MACH_TYPE_DSS11);
devfs_add_partition("nand0", 0x00000, 0x20000, PARTITION_FIXED, "bootstrap");
dev_add_bb_dev("bootstrap", "bootstrap.bb");
devfs_add_partition("nand0", 0x20000, 0x40000, PARTITION_FIXED, "barebox");
dev_add_bb_dev("barebox", "barebox.bb");
devfs_add_partition("nand0", 0x60000, 0x40000, PARTITION_FIXED, "barebox-env");
dev_add_bb_dev("barebox-env", "env0");
return 0;
}
device_initcall(dss11_devices_init);
static int dss11_console_init(void)
{
at91_register_uart(0, 0);
return 0;
}
console_initcall(dss11_console_init);

2
arch/arm/boards/eukrea_cpuimx25/env/bin/init_board vendored
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@ -4,7 +4,7 @@ if [ -f /env/logo.bmp ]; then
bmp /env/logo.bmp
fb0.enable=1
elif [ -f /env/logo.bmp.lzo ]; then
unlzo /env/logo.bmp.lzo /logo.bmp
uncompress /env/logo.bmp.lzo /logo.bmp
bmp /logo.bmp
fb0.enable=1
fi

2
arch/arm/boards/eukrea_cpuimx27/env/bin/init vendored
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@ -20,7 +20,7 @@ if [ -f /env/logo.bmp ]; then
bmp /env/logo.bmp
fb0.enable=1
elif [ -f /env/logo.bmp.lzo ]; then
unlzo /env/logo.bmp.lzo /logo.bmp
uncompress /env/logo.bmp.lzo /logo.bmp
bmp /logo.bmp
fb0.enable=1
fi

2
arch/arm/boards/eukrea_cpuimx35/env/bin/init_board vendored
View File

@ -5,7 +5,7 @@ if [ -f /env/logo.bmp ]; then
fb0.enable=1
gpio_set_value 1 1
elif [ -f /env/logo.bmp.lzo ]; then
unlzo /env/logo.bmp.lzo /logo.bmp
uncompress /env/logo.bmp.lzo /logo.bmp
bmp /logo.bmp
fb0.enable=1
gpio_set_value 1 1

2
arch/arm/boards/eukrea_cpuimx51/env/bin/init_board vendored
View File

@ -5,7 +5,7 @@ if [ -f /env/logo.bmp ]; then
fb0.enable=1
gpio_set_value 1 1
elif [ -f /env/logo.bmp.lzo ]; then
unlzo /env/logo.bmp.lzo /logo.bmp
uncompress /env/logo.bmp.lzo /logo.bmp
bmp /logo.bmp
fb0.enable=1
gpio_set_value 1 1

36
arch/arm/boards/freescale-mx53-loco/board.c
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@ -72,6 +72,22 @@ static struct pad_desc loco_pads[] = {
MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
/* SD1_CD */
MX53_PAD_EIM_DA13__GPIO3_13,
/* SD3 */
MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
MX53_PAD_PATA_IORDY__ESDHC3_CLK,
MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
/* SD3_CD */
MX53_PAD_EIM_DA11__GPIO3_11,
/* SD3_WP */
MX53_PAD_EIM_DA12__GPIO3_12,
};
static int loco_mem_init(void)
@ -92,11 +108,29 @@ static void loco_fec_reset(void)
gpio_set_value(LOCO_FEC_PHY_RST, 1);
}
#define LOCO_SD3_CD IMX_GPIO_NR(3, 11)
#define LOCO_SD3_WP IMX_GPIO_NR(3, 12)
#define LOCO_SD1_CD IMX_GPIO_NR(3, 13)
static struct esdhc_platform_data loco_sd1_data = {
.cd_gpio = LOCO_SD1_CD,
.cd_type = ESDHC_CD_GPIO,
.wp_type = ESDHC_WP_NONE,
};
static struct esdhc_platform_data loco_sd3_data = {
.cd_gpio = LOCO_SD3_CD,
.wp_gpio = LOCO_SD3_WP,
.cd_type = ESDHC_CD_GPIO,
.wp_type = ESDHC_WP_GPIO,
};
static int loco_devices_init(void)
{
imx51_iim_register_fec_ethaddr();
imx53_add_fec(&fec_info);
imx53_add_mmc0(NULL);
imx53_add_mmc0(&loco_sd1_data);
imx53_add_mmc2(&loco_sd3_data);
loco_fec_reset();

2
arch/arm/boards/freescale-mx53-smd/Makefile Normal file
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@ -0,0 +1,2 @@
obj-y += board.o
obj-y += flash_header.o

170
arch/arm/boards/freescale-mx53-smd/board.c Normal file
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@ -0,0 +1,170 @@
/*
* Copyright (C) 2007 Sascha Hauer, Pengutronix
* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <environment.h>
#include <fcntl.h>
#include <fec.h>
#include <fs.h>
#include <init.h>
#include <nand.h>
#include <net.h>
#include <partition.h>
#include <sizes.h>
#include <generated/mach-types.h>
#include <mach/imx-regs.h>
#include <mach/iomux-mx53.h>
#include <mach/devices-imx53.h>
#include <mach/generic.h>
#include <mach/gpio.h>
#include <mach/imx-nand.h>
#include <mach/iim.h>
#include <mach/imx53.h>
#include <asm/armlinux.h>
#include <io.h>
#include <asm/mmu.h>
static struct fec_platform_data fec_info = {
.xcv_type = RMII,
};
static struct pad_desc smd_pads[] = {
/* UART1 */
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
/* UART2 */
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
/* UART3 */
MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
MX53_PAD_PATA_DA_1__UART3_CTS,
MX53_PAD_PATA_DA_2__UART3_RTS,
/* FEC */
MX53_PAD_FEC_MDC__FEC_MDC,
MX53_PAD_FEC_MDIO__FEC_MDIO,
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
MX53_PAD_FEC_RX_ER__FEC_RX_ER,
MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
MX53_PAD_FEC_RXD1__FEC_RDATA_1,
MX53_PAD_FEC_RXD0__FEC_RDATA_0,
MX53_PAD_FEC_TX_EN__FEC_TX_EN,
MX53_PAD_FEC_TXD1__FEC_TDATA_1,
MX53_PAD_FEC_TXD0__FEC_TDATA_0,
/* FEC_nRST */
MX53_PAD_PATA_DA_0__GPIO7_6,
/* SD1 */
MX53_PAD_SD1_CMD__ESDHC1_CMD,
MX53_PAD_SD1_CLK__ESDHC1_CLK,
MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
/* SD1_CD */
MX53_PAD_EIM_DA13__GPIO3_13,
/* SD1_WP */
MX53_PAD_KEY_ROW2__GPIO4_11,
/* SD3 */
MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
MX53_PAD_PATA_IORDY__ESDHC3_CLK,
MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
};
static int smd_mem_init(void)
{
arm_add_mem_device("ram0", 0x70000000, SZ_512M);
arm_add_mem_device("ram1", 0xb0000000, SZ_512M);
return 0;
}
mem_initcall(smd_mem_init);
#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
static void smd_fec_reset(void)
{
gpio_direction_output(SMD_FEC_PHY_RST, 0);
mdelay(1);
gpio_set_value(SMD_FEC_PHY_RST, 1);
}
#define LOCO_SD1_CD IMX_GPIO_NR(3, 13)
#define LOCO_SD1_WP IMX_GPIO_NR(4, 11)
static struct esdhc_platform_data loco_sd1_data = {
.cd_gpio = LOCO_SD1_CD,
.wp_gpio = LOCO_SD1_WP,
.cd_type = ESDHC_CD_GPIO,
.wp_type = ESDHC_WP_GPIO,
};
static struct esdhc_platform_data loco_sd3_data = {
.wp_type = ESDHC_WP_NONE,
.cd_type = ESDHC_CD_PERMANENT,
};
static int smd_devices_init(void)
{
imx51_iim_register_fec_ethaddr();
imx53_add_fec(&fec_info);
imx53_add_mmc0(&loco_sd1_data);
imx53_add_mmc2(&loco_sd3_data);
smd_fec_reset();
armlinux_set_bootparams((void *)0x70000100);
armlinux_set_architecture(MACH_TYPE_MX53_SMD);
return 0;
}
device_initcall(smd_devices_init);
static int smd_part_init(void)
{
devfs_add_partition("disk0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
devfs_add_partition("disk0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
return 0;
}
late_initcall(smd_part_init);
static int smd_console_init(void)
{
mxc_iomux_v3_setup_multiple_pads(smd_pads, ARRAY_SIZE(smd_pads));
mx53_init_lowlevel();
imx53_add_uart0();
imx53_add_uart1();
imx53_add_uart2();
return 0;
}
console_initcall(smd_console_init);

29
include/ata.h → arch/arm/boards/freescale-mx53-smd/config.h
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2009 Juergen Beisert, Pengutronix
/**
* @file
* @brief Global defintions for the ARM i.MX51 based babbage board
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -8,32 +9,16 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
/**
* @file
* @brief Declarations to communicate with ATA types of drives
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <types.h>
#include <driver.h>
/**
* Access functions from drives through the specified interface
*/
struct ata_interface {
/** write a count of sectors from a buffer to the drive */
int (*write)(struct device_d*, uint64_t, unsigned, const void*);
/** read a count of sectors from the drive into the buffer */
int (*read)(struct device_d*, uint64_t, unsigned, void*);
/** private interface data */
void *priv;
};
#endif /* __CONFIG_H */

51
arch/arm/boards/freescale-mx53-smd/env/config vendored Normal file
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@ -0,0 +1,51 @@
#!/bin/sh
machine=loco
eth0.serverip=
user=
# use 'dhcp' to do dhcp in barebox and in kernel
# use 'none' if you want to skip kernel ip autoconfiguration
ip=dhcp
# or set your networking parameters here
#eth0.ipaddr=a.b.c.d
#eth0.netmask=a.b.c.d
#eth0.gateway=a.b.c.d
#eth0.serverip=a.b.c.d
# can be either 'nfs', 'tftp', 'nor' or 'nand'
kernel_loc=tftp
# can be either 'net', 'nor', 'nand' or 'initrd'
rootfs_loc=net
# can be either 'jffs2' or 'ubifs'
rootfs_type=ubifs
rootfsimage=root-$machine.$rootfs_type
# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
kernelimage_type=zimage
kernelimage=zImage-$machine
#kernelimage_type=uimage
#kernelimage=uImage-$machine
#kernelimage_type=raw
#kernelimage=Image-$machine
#kernelimage_type=raw_lzo
#kernelimage=Image-$machine.lzo
if [ -n $user ]; then
kernelimage="$user"-"$kernelimage"
nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
rootfsimage="$user"-"$rootfsimage"
else
nfsroot="$eth0.serverip:/path/to/nfs/root"
fi
autoboot_timeout=3
bootargs="console=ttymxc0,115200"
disk_parts="256k(barebox)ro,128k(bareboxenv),4M(kernel),-(root)"
# set a fancy prompt (if support is compiled in)
PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "

101
arch/arm/boards/freescale-mx53-smd/flash_header.c Normal file
View File

@ -0,0 +1,101 @@
/*
* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <asm/byteorder.h>
#include <mach/imx-flash-header.h>
void __naked __flash_header_start go(void)
{
__asm__ __volatile__("b exception_vectors\n");
}
struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
{ .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00300040), },
{ .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x04000000), },
{ .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00300000), },
{ .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x35343535), },
{ .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x4d444c44), },
{ .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01370138), },
{ .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x013b013c), },
{ .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00011740), },
{ .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0xc3190000), },
{ .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x9f5152e3), },
{ .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb68e8a63), },
{ .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x01ff00db), },
{ .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), },
{ .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f0e21), },
{ .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12273030), },
{ .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x0002002d), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008033), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028031), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x052080b0), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008040), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803a), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803b), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028039), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x05208138), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008048), },
{ .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), },
{ .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), },
{ .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00022227), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
};
#define APP_DEST CONFIG_TEXT_BASE
struct imx_flash_header_v2 __flash_header_section flash_header = {
.header.tag = IVT_HEADER_TAG,
.header.length = cpu_to_be16(32),
.header.version = IVT_VERSION,
.entry = APP_DEST + 0x1000,
.dcd_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, dcd),
.boot_data_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, boot_data),
.self = APP_DEST + 0x400,
.boot_data.start = APP_DEST,
.boot_data.size = 0x40000,
.dcd.header.tag = DCD_HEADER_TAG,
.dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) + sizeof(dcd_entry)),
.dcd.header.version = DCD_VERSION,
.dcd.command.tag = DCD_COMMAND_WRITE_TAG,
.dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)),
.dcd.command.param = DCD_COMMAND_WRITE_PARAM,
};

4
arch/arm/boards/freescale-mx53-smd/mx53-smd.dox Normal file
View File

@ -0,0 +1,4 @@
/** @page board_loco Freescale i.MX53 SMD Board
*/

2
arch/arm/boards/mini2440/mini2440.c
View File

@ -314,6 +314,8 @@ static int mini2440_devices_init(void)
IORESOURCE_MEM, &mci_data);
add_generic_device("s3c_fb", 0, NULL, S3C2410_LCD_BASE, 0,
IORESOURCE_MEM, &s3c24x0_fb_data);
add_generic_device("ohci", 0, NULL, S3C2410_USB_HOST_BASE, 0x100,
IORESOURCE_MEM, NULL);
armlinux_set_bootparams((void*)CS6_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE_MINI2440);

31
arch/arm/boards/omap/board-beagle.c
View File

@ -313,34 +313,3 @@ static int beagle_devices_init(void)
return 0;
}
device_initcall(beagle_devices_init);
#ifdef CONFIG_SHELL_NONE
int run_shell(void)
{
int (*func)(void) = NULL;
switch (omap3_bootsrc()) {
case OMAP_BOOTSRC_MMC1:
printf("booting from MMC1\n");
func = omap_xload_boot_mmc();
break;
case OMAP_BOOTSRC_UNKNOWN:
printf("unknown boot source. Fall back to nand\n");
case OMAP_BOOTSRC_NAND:
printf("booting from NAND\n");
func = omap_xload_boot_nand(SZ_128K, SZ_256K);
break;
}
if (!func) {
printf("booting failed\n");
while (1);
}
shutdown_barebox();
func();
while (1);
}
#endif

19
arch/arm/boards/panda/board.c
View File

@ -170,22 +170,3 @@ static int panda_env_init(void)
}
late_initcall(panda_env_init);
#endif
#ifdef CONFIG_SHELL_NONE
int run_shell(void)
{
int (*func)(void);
func = omap_xload_boot_mmc();
if (!func) {
printf("booting failed\n");
while (1);
}
shutdown_barebox();
func();
while (1);
}
#endif

30
arch/arm/boards/pcm049/board.c
View File

@ -112,33 +112,3 @@ static int pcm049_devices_init(void)
return 0;
}
device_initcall(pcm049_devices_init);
#ifdef CONFIG_SHELL_NONE
int run_shell(void)
{
int (*func)(void) = NULL;
switch (omap4_bootsrc()) {
case OMAP_BOOTSRC_MMC1:
printf("booting from MMC1\n");
func = omap_xload_boot_mmc();
break;
case OMAP_BOOTSRC_UNKNOWN:
printf("unknown boot source. Fall back to nand\n");
case OMAP_BOOTSRC_NAND:
printf("booting from NAND\n");
func = omap_xload_boot_nand(SZ_128K, SZ_256K);
break;
}
if (!func) {
printf("booting failed\n");
while (1);
}
shutdown_barebox();
func();
while (1);
}
#endif

2
arch/arm/configs/at91rm9200ek_defconfig
View File

@ -33,7 +33,7 @@ CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
# CONFIG_SPI is not set
CONFIG_DRIVER_CFI=y
# CONFIG_DRIVER_CFI_INTEL is not set

2
arch/arm/configs/at91sam9261ek_defconfig
View File

@ -33,7 +33,7 @@ CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y

2
arch/arm/configs/at91sam9g10ek_defconfig
View File

@ -27,7 +27,7 @@ CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y

2
arch/arm/configs/at91sam9m10g45ek_defconfig
View File

@ -37,7 +37,7 @@ CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y

2
arch/arm/configs/cupid_defconfig
View File

@ -35,7 +35,7 @@ CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_BMP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y

48
arch/arm/configs/dss11_defconfig Normal file
View File

@ -0,0 +1,48 @@
CONFIG_ARCH_AT91SAM9G20=y
CONFIG_MACH_DSS11=y
CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_PARTITION_DISK_DOS=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_LED=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
CONFIG_NET_TFTP_PUSH=y
CONFIG_DRIVER_NET_MACB=y
CONFIG_DRIVER_SPI_ATMEL=y
CONFIG_MTD=y
CONFIG_NAND=y
# CONFIG_NAND_ECC_HW_SYNDROME is not set
# CONFIG_NAND_ECC_HW_NONE is not set
CONFIG_NAND_ATMEL=y
CONFIG_UBI=y
CONFIG_DISK_WRITE=y
CONFIG_USB=y
CONFIG_USB_OHCI=y
CONFIG_USB_OHCI_AT91=y
CONFIG_USB_STORAGE=y
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
# CONFIG_MCI_WRITE is not set
CONFIG_MCI_ATMEL=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_GPIO_RGB=y
CONFIG_LED_TRIGGERS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y

2
arch/arm/configs/eukrea_cpuimx25_defconfig
View File

@ -35,7 +35,7 @@ CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_BMP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_LED=y
CONFIG_CMD_LED_TRIGGER=y

2
arch/arm/configs/eukrea_cpuimx27_defconfig
View File

@ -33,7 +33,7 @@ CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_BMP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_I2C=y
CONFIG_NET=y
CONFIG_NET_DHCP=y

2
arch/arm/configs/eukrea_cpuimx35_defconfig
View File

@ -34,7 +34,7 @@ CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_BMP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_I2C=y
CONFIG_NET=y
CONFIG_NET_DHCP=y

2
arch/arm/configs/eukrea_cpuimx51_defconfig
View File

@ -32,7 +32,7 @@ CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y

2
arch/arm/configs/freescale_mx35_3stack_defconfig
View File

@ -29,7 +29,7 @@ CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_BMP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_I2C=y
CONFIG_NET=y
CONFIG_NET_DHCP=y

2
arch/arm/configs/freescale_mx53_loco_defconfig
View File

@ -33,7 +33,7 @@ CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y

51
arch/arm/configs/freescale_mx53_smd_defconfig Normal file
View File

@ -0,0 +1,51 @@
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX53=y
CONFIG_MACH_FREESCALE_MX53_SMD=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x7ff00000
CONFIG_MALLOC_SIZE=0x2000000
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/freescale-mx53-smd/env/"
CONFIG_DEBUG_INFO=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
CONFIG_NET_TFTP_PUSH=y
CONFIG_NET_NETCONSOLE=y
CONFIG_DRIVER_NET_FEC_IMX=y
# CONFIG_SPI is not set
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_IMX_ESDHC=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y

2
arch/arm/configs/neso_defconfig
View File

@ -34,7 +34,7 @@ CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_BMP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y

2
arch/arm/configs/nhk8815_defconfig
View File

@ -34,7 +34,7 @@ CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y

2
arch/arm/configs/omap3530_beagle_defconfig
View File

@ -31,7 +31,7 @@ CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_I2C=y
CONFIG_NET=y
CONFIG_NET_DHCP=y

2
arch/arm/configs/panda_defconfig
View File

@ -34,7 +34,7 @@ CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y

2
arch/arm/configs/pca100_defconfig
View File

@ -33,7 +33,7 @@ CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y

2
arch/arm/configs/pcm037_defconfig
View File

@ -31,7 +31,7 @@ CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y

2
arch/arm/configs/pcm043_defconfig
View File

@ -36,7 +36,7 @@ CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y

2
arch/arm/configs/pcm049_defconfig
View File

@ -35,7 +35,7 @@ CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y

2
arch/arm/configs/pm9261_defconfig
View File

@ -34,7 +34,7 @@ CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y

2
arch/arm/configs/pm9g45_defconfig
View File

@ -37,7 +37,7 @@ CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y

2
arch/arm/configs/scb9328_defconfig
View File

@ -28,7 +28,7 @@ CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_LED=y
CONFIG_CMD_LED_TRIGGER=y
CONFIG_NET=y

2
arch/arm/configs/versatilepb_defconfig
View File

@ -32,7 +32,7 @@ CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y

5
arch/arm/cpu/Kconfig
View File

@ -45,6 +45,11 @@ config CPU_V7
bool
select CPU_32v7
# Xscale PXA25x, PXA27x
config CPU_XSCALE
bool
select CPU_32v4T
# Figure out what processor architecture version we should be using.
# This defines the compiler instruction set which depends on the machine type.
config CPU_32v4T

21
arch/arm/cpu/exceptions.S
View File

@ -140,25 +140,6 @@ data_abort:
.globl irq
.globl fiq
#ifdef CONFIG_USE_IRQ
.align 5
irq:
get_irq_stack
irq_save_user_regs
bl do_irq
irq_restore_user_regs
.align 5
fiq:
get_fiq_stack
/* someone ought to write a more effiction fiq_save_user_regs */
irq_save_user_regs
bl do_fiq
irq_restore_user_regs
#else
.align 5
irq:
get_bad_stack
@ -171,5 +152,3 @@ fiq:
bad_save_user_regs
bl do_fiq
#endif

6
arch/arm/cpu/mmu.c
View File

@ -9,7 +9,7 @@
static unsigned long *ttb;
static void create_section(unsigned long virt, unsigned long phys, int size_m,
static void create_sections(unsigned long virt, unsigned long phys, int size_m,
unsigned int flags)
{
int i;
@ -226,7 +226,7 @@ static int mmu_init(void)
asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
/* create a flat mapping using 1MiB sections */
create_section(0, 0, 4096, PMD_SECT_AP_WRITE | PMD_SECT_AP_READ |
create_sections(0, 0, 4096, PMD_SECT_AP_WRITE | PMD_SECT_AP_READ |
PMD_TYPE_SECT);
vectors_init();
@ -237,7 +237,7 @@ static int mmu_init(void)
* below
*/
for_each_memory_bank(bank)
create_section(bank->start, bank->start, bank->size >> 20,
create_sections(bank->start, bank->start, bank->size >> 20,
PMD_SECT_DEF_CACHED);
asm volatile (

2
arch/arm/lib/arm.c
View File

@ -7,7 +7,7 @@
static int arm_mem_malloc_init(void)
{
mem_malloc_init((void *)MALLOC_BASE,
(void *)(MALLOC_BASE + MALLOC_SIZE));
(void *)(MALLOC_BASE + MALLOC_SIZE - 1));
return 0;
}

108
arch/arm/lib/armlinux.c
View File

@ -27,7 +27,6 @@
#include <driver.h>
#include <environment.h>
#include <image.h>
#include <zlib.h>
#include <init.h>
#include <fs.h>
#include <linux/list.h>
@ -37,6 +36,7 @@
#include <errno.h>
#include <memory.h>
#include <of.h>
#include <magicvar.h>
#include <asm/byteorder.h>
#include <asm/setup.h>
@ -45,11 +45,71 @@
#include <asm/system.h>
static struct tag *params;
static int armlinux_architecture = 0;
static void *armlinux_bootparams = NULL;
static unsigned int system_rev;
static u64 system_serial;
#ifndef CONFIG_ENVIRONMENT_VARIABLES
static int armlinux_architecture;
static u32 armlinux_system_rev;
static u64 armlinux_system_serial;
#endif
BAREBOX_MAGICVAR(armlinux_architecture, "ARM machine ID");
BAREBOX_MAGICVAR(armlinux_system_rev, "ARM system revision");
BAREBOX_MAGICVAR(armlinux_system_serial, "ARM system serial");
void armlinux_set_architecture(int architecture)
{
#ifdef CONFIG_ENVIRONMENT_VARIABLES
export_env_ull("armlinux_architecture", architecture);
#else
armlinux_architecture = architecture;
#endif
}
int armlinux_get_architecture(void)
{
#ifdef CONFIG_ENVIRONMENT_VARIABLES
return getenv_ull("armlinux_architecture");
#else
return armlinux_architecture;
#endif
}
void armlinux_set_revision(unsigned int rev)
{
#ifdef CONFIG_ENVIRONMENT_VARIABLES
export_env_ull("armlinux_system_rev", rev);
#else
return armlinux_system_rev;
#endif
}
unsigned int armlinux_get_revision(void)
{
#ifdef CONFIG_ENVIRONMENT_VARIABLES
return getenv_ull("armlinux_system_rev");
#else
return armlinux_system_rev;
#endif
}
void armlinux_set_serial(u64 serial)
{
#ifdef CONFIG_ENVIRONMENT_VARIABLES
export_env_ull("armlinux_system_serial", serial);
#else
armlinux_system_serial = serial;
#endif
}
u64 armlinux_get_serial(void)
{
#ifdef CONFIG_ENVIRONMENT_VARIABLES
return getenv_ull("armlinux_system_serial");
#else
return armlinux_system_serial;
#endif
}
static void setup_start_tag(void)
{
@ -117,6 +177,8 @@ static void setup_commandline_tag(const char *commandline, int swap)
static void setup_revision_tag(void)
{
u32 system_rev = armlinux_get_revision();
if (system_rev) {
params->hdr.tag = ATAG_REVISION;
params->hdr.size = tag_size(tag_revision);
@ -129,6 +191,8 @@ static void setup_revision_tag(void)
static void setup_serial_tag(void)
{
u64 system_serial = armlinux_get_serial();
if (system_serial) {
params->hdr.tag = ATAG_SERIAL;
params->hdr.size = tag_size(tag_serialnr);
@ -140,7 +204,7 @@ static void setup_serial_tag(void)
}
}
static void setup_initrd_tag(image_header_t *header)
static void setup_initrd_tag(unsigned long start, unsigned long size)
{
/* an ATAG_INITRD node tells the kernel where the compressed
* ramdisk can be found. ATAG_RDIMG is a better name, actually.
@ -148,8 +212,8 @@ static void setup_initrd_tag(image_header_t *header)
params->hdr.tag = ATAG_INITRD2;
params->hdr.size = tag_size(tag_initrd);
params->u.initrd.start = image_get_load(header);
params->u.initrd.size = image_get_data_size(header);
params->u.initrd.start = start;
params->u.initrd.size = size;
params = tag_next(params);
}
@ -168,15 +232,15 @@ static void setup_tags(struct image_data *data, int swap)
setup_memory_tags();
setup_commandline_tag(commandline, swap);
if (data && data->initrd)
setup_initrd_tag (&data->initrd->header);
if (data && (data->initrd_size > 0))
setup_initrd_tag(data->initrd_address, data->initrd_size);
setup_revision_tag();
setup_serial_tag();
setup_end_tag();
printf("commandline: %s\n"
"arch_number: %d\n", commandline, armlinux_architecture);
"arch_number: %d\n", commandline, armlinux_get_architecture());
}
@ -185,28 +249,6 @@ void armlinux_set_bootparams(void *params)
armlinux_bootparams = params;
}
void armlinux_set_architecture(int architecture)
{
char *arch_number = asprintf("%d", architecture);
armlinux_architecture = architecture;
setenv("arch_number", arch_number);
export("arch_number");
kfree(arch_number);
}
void armlinux_set_revision(unsigned int rev)
{
system_rev = rev;
}
void armlinux_set_serial(u64 serial)
{
system_serial = serial;
}
void start_linux(void *adr, int swap, struct image_data *data)
{
void (*kernel)(int zero, int arch, void *params) = adr;
@ -229,5 +271,5 @@ void start_linux(void *adr, int swap, struct image_data *data)
__asm__ __volatile__("mcr p15, 0, %0, c1, c0" :: "r" (reg));
}
kernel(0, armlinux_architecture, params);
kernel(0, armlinux_get_architecture(), params);
}

4
arch/arm/lib/barebox.lds.S
View File

@ -80,6 +80,10 @@ SECTIONS
.barebox_cmd : { BAREBOX_CMDS }
__barebox_cmd_end = .;
__barebox_magicvar_start = .;
.barebox_magicvar : { BAREBOX_MAGICVARS }
__barebox_magicvar_end = .;
__barebox_initcalls_start = .;
.barebox_initcalls : { INITCALLS }
__barebox_initcalls_end = .;

37
arch/arm/lib/bootm.c
View File

@ -4,7 +4,6 @@
#include <driver.h>
#include <environment.h>
#include <image.h>
#include <zlib.h>
#include <init.h>
#include <fs.h>
#include <linux/list.h>
@ -29,13 +28,6 @@ static int do_bootm_linux(struct image_data *data)
debug("## Transferring control to Linux (at address 0x%p) ...\n",
theKernel);
if (relocate_image(data->os, (void *)image_get_load(os_header)))
return -1;
if (data->initrd)
if (relocate_image(data->initrd, (void *)image_get_load(&data->initrd->header)))
return -1;
/* we assume that the kernel is in place */
printf("\nStarting kernel %s...\n\n", data->initrd ? "with initrd " : "");
@ -44,36 +36,7 @@ static int do_bootm_linux(struct image_data *data)
return -1;
}
static int image_handle_cmdline_parse(struct image_data *data, int opt,
char *optarg)
{
int ret = 1;
int no;
switch (opt) {
case 'a':
no = simple_strtoul(optarg, NULL, 0);
armlinux_set_architecture(no);
ret = 0;
break;
case 'R':
no = simple_strtoul(optarg, NULL, 0);
armlinux_set_revision(no);
ret = 0;
break;
default:
break;
}
return ret;
}
static struct image_handler handler = {
.cmdline_options = "a:R:",
.cmdline_parse = image_handle_cmdline_parse,
.help_string = " -a <arch> use architecture number <arch>\n"
" -R <system_rev> use system revison <system_rev>\n",
.bootm = do_bootm_linux,
.image_type = IH_OS_LINUX,
};

8
arch/arm/mach-at91/Kconfig
View File

@ -20,6 +20,7 @@ config BOARDINFO
default "Ronetix PM9261" if MACH_PM9261
default "Ronetix PM9263" if MACH_PM9263
default "Ronetix PM9G45" if MACH_PM9G45
default "Aizo dSS11" if MACH_DSS11
config HAVE_NAND_ATMEL_BUSWIDTH_16
bool
@ -175,6 +176,13 @@ config MACH_USB_A9G20
Select this if you are using a Calao Systems USB-A9G20.
<http://www.calao-systems.com>
config MACH_DSS11
bool "aizo dSS11"
select HAVE_NAND_ATMEL_BUSWIDTH_16
help
Select this if you are using aizo dSS11
that embeds only one SD/MMC slot.
endchoice
endif

41
arch/arm/mach-at91/at91sam9260_devices.c
View File

@ -63,8 +63,13 @@ void at91_add_device_eth(struct at91_ether_platform_data *data)
at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
if (data->flags & AT91SAM_ETX2_ETX3_ALTERNATIVE) {
at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */
at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */
} else {
at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
}
at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
}
@ -261,18 +266,32 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
/* CLK */
at91_set_A_periph(AT91_PIN_PA8, 0);
/* CMD */
at91_set_A_periph(AT91_PIN_PA7, 1);
/* DAT0, maybe DAT1..DAT3 */
at91_set_A_periph(AT91_PIN_PA6, 1);
if (data->bus_width == 4) {
at91_set_A_periph(AT91_PIN_PA9, 1);
at91_set_A_periph(AT91_PIN_PA10, 1);
at91_set_A_periph(AT91_PIN_PA11, 1);
if (mmc_id == 0) {
/* CMD */
at91_set_A_periph(AT91_PIN_PA7, 1);
/* DAT0, maybe DAT1..DAT3 */
at91_set_A_periph(AT91_PIN_PA6, 1);
if (data->bus_width == 4) {
at91_set_A_periph(AT91_PIN_PA9, 1);
at91_set_A_periph(AT91_PIN_PA10, 1);
at91_set_A_periph(AT91_PIN_PA11, 1);
}
} else if (mmc_id == 1) {
/* CMD */
at91_set_B_periph(AT91_PIN_PA1, 1);
/* DAT0, maybe DAT1..DAT3 */
at91_set_B_periph(AT91_PIN_PA0, 1);
if (data->bus_width == 4) {
at91_set_B_periph(AT91_PIN_PA3, 1);
at91_set_B_periph(AT91_PIN_PA4, 1);
at91_set_B_periph(AT91_PIN_PA5, 1);
}
}
dev = add_generic_device("atmel_mci", 0, NULL, AT91SAM9260_BASE_MCI, SZ_16K,
dev = add_generic_device("atmel_mci", mmc_id, NULL, AT91SAM9260_BASE_MCI, SZ_16K,
IORESOURCE_MEM, data);
}
#else

5
arch/arm/mach-imx/Kconfig
View File

@ -20,6 +20,7 @@ config ARCH_TEXT_BASE
default 0xa7e00000 if MACH_NESO
default 0x97f00000 if MACH_MX51_PDK
default 0x7ff00000 if MACH_MX53_LOCO
default 0x7ff00000 if MACH_MX53_SMD
default 0x87f00000 if MACH_GUF_CUPID
default 0x93d00000 if MACH_TX25
@ -40,6 +41,7 @@ config BOARDINFO
default "Garz+Fricke Neso" if MACH_NESO
default "Freescale i.MX51 PDK" if MACH_FREESCALE_MX51_PDK
default "Freescale i.MX53 LOCO" if MACH_FREESCALE_MX53_LOCO
default "Freescale i.MX53 SMD" if MACH_FREESCALE_MX53_SMD
default "Garz+Fricke Cupid" if MACH_GUF_CUPID
default "Ka-Ro tx25" if MACH_TX25
@ -402,6 +404,9 @@ choice
config MACH_FREESCALE_MX53_LOCO
bool "Freescale i.MX53 LOCO"
config MACH_FREESCALE_MX53_SMD
bool "Freescale i.MX53 SMD"
endchoice
endif

3
arch/arm/mach-imx/boot.c
View File

@ -18,6 +18,7 @@
#include <common.h>
#include <environment.h>
#include <init.h>
#include <magicvar.h>
#include <io.h>
#include <mach/imx-regs.h>
@ -88,4 +89,6 @@ static int imx_25_35_boot_save_loc(void)
coredevice_initcall(imx_25_35_boot_save_loc);
BAREBOX_MAGICVAR(barebox_loc, "The source barebox has been booted from");
#endif

2
arch/arm/mach-imx/devices.c
View File

@ -48,7 +48,7 @@ struct device_d *imx_add_mmc(void *base, int id, void *pdata)
return imx_add_device("imx-mmc", id, base, 0x1000, pdata);
}
struct device_d *imx_add_esdhc(void *base, int id, void *pdata)
struct device_d *imx_add_esdhc(void *base, int id, struct esdhc_platform_data *pdata)
{
return imx_add_device("imx-esdhc", id, base, 0x1000, pdata);
}

9
arch/arm/mach-imx/imx53.c
View File

@ -173,6 +173,15 @@ int mx53_init_lowlevel(void)
r = readl(ccm + MX5_CCM_CSCDR1);
r &= ~0x3f;
r |= 0x0a;
r &= ~MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK;
r &= ~MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK;
r |= 1 << MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET;
r &= ~MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK;
r &= ~MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK;
r |= 1 << MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET;
writel(r, ccm + MX5_CCM_CSCDR1);
/* Restore the default values in the Gate registers */

2
arch/arm/mach-imx/include/mach/devices-imx25.h
View File

@ -36,7 +36,7 @@ static inline struct device_d *imx25_add_fec(struct fec_platform_data *pdata)
return imx_add_fec((void *)IMX_FEC_BASE, pdata);
}
static inline struct device_d *imx25_add_mmc0(void *pdata)
static inline struct device_d *imx25_add_mmc0(struct esdhc_platform_data *pdata)
{
return imx_add_esdhc((void *)0x53fb4000, 0, pdata);
}

6
arch/arm/mach-imx/include/mach/devices-imx35.h
View File

@ -41,17 +41,17 @@ static inline struct device_d *imx35_add_fec(struct fec_platform_data *pdata)
return imx_add_fec((void *)IMX_FEC_BASE, pdata);
}
static inline struct device_d *imx35_add_mmc0(void *pdata)
static inline struct device_d *imx35_add_mmc0(struct esdhc_platform_data *pdata)
{
return imx_add_esdhc((void *)IMX_SDHC1_BASE, 0, pdata);
}
static inline struct device_d *imx35_add_mmc1(void *pdata)
static inline struct device_d *imx35_add_mmc1(struct esdhc_platform_data *pdata)
{
return imx_add_esdhc((void *)IMX_SDHC2_BASE, 1, pdata);
}
static inline struct device_d *imx35_add_mmc2(void *pdata)
static inline struct device_d *imx35_add_mmc2(struct esdhc_platform_data *pdata)
{
return imx_add_esdhc((void *)IMX_SDHC3_BASE, 2, pdata);
}

4
arch/arm/mach-imx/include/mach/devices-imx51.h
View File

@ -42,12 +42,12 @@ static inline struct device_d *imx51_add_fec(struct fec_platform_data *pdata)
return imx_add_fec((void *)MX51_MXC_FEC_BASE_ADDR, pdata);
}
static inline struct device_d *imx51_add_mmc0(void *pdata)
static inline struct device_d *imx51_add_mmc0(struct esdhc_platform_data *pdata)
{
return imx_add_esdhc((void *)MX51_MMC_SDHC1_BASE_ADDR, 0, pdata);
}
static inline struct device_d *imx51_add_mmc1(void *pdata)
static inline struct device_d *imx51_add_mmc1(struct esdhc_platform_data *pdata)
{
return imx_add_esdhc((void *)MX51_MMC_SDHC2_BASE_ADDR, 1, pdata);
}

15
arch/arm/mach-imx/include/mach/devices-imx53.h
View File

@ -31,24 +31,29 @@ static inline struct device_d *imx53_add_uart1(void)
return imx_add_uart((void *)MX53_UART2_BASE_ADDR, 1);
}
static inline struct device_d *imx53_add_uart2(void)
{
return imx_add_uart((void *)MX53_UART3_BASE_ADDR, 2);
}
static inline struct device_d *imx53_add_fec(struct fec_platform_data *pdata)
{
return imx_add_fec((void *)MX53_FEC_BASE_ADDR, pdata);
}
static inline struct device_d *imx53_add_mmc0(void *pdata)
static inline struct device_d *imx53_add_mmc0(struct esdhc_platform_data *pdata)
{
return imx_add_esdhc((void *)MX53_ESDHC1_BASE_ADDR, 0, pdata);
}
static inline struct device_d *imx53_add_mmc1(void *pdata)
static inline struct device_d *imx53_add_mmc1(struct esdhc_platform_data *pdata)
{
return imx_add_esdhc((void *)MX53_ESDHC2_BASE_ADDR, 0, pdata);
return imx_add_esdhc((void *)MX53_ESDHC2_BASE_ADDR, 1, pdata);
}
static inline struct device_d *imx53_add_mmc2(void *pdata)
static inline struct device_d *imx53_add_mmc2(struct esdhc_platform_data *pdata)
{
return imx_add_esdhc((void *)MX53_ESDHC3_BASE_ADDR, 0, pdata);
return imx_add_esdhc((void *)MX53_ESDHC3_BASE_ADDR, 2, pdata);
}
static inline struct device_d *imx53_add_nand(struct imx_nand_platform_data *pdata)

3
arch/arm/mach-imx/include/mach/devices.h
View File

@ -5,6 +5,7 @@
#include <mach/imx-nand.h>
#include <mach/imxfb.h>
#include <mach/imx-ipu-fb.h>
#include <mach/esdhc.h>
struct device_d *imx_add_fec(void *base, struct fec_platform_data *pdata);
struct device_d *imx_add_spi(void *base, int id, struct spi_imx_master *pdata);
@ -14,5 +15,5 @@ struct device_d *imx_add_nand(void *base, struct imx_nand_platform_data *pdata);
struct device_d *imx_add_fb(void *base, struct imx_fb_platform_data *pdata);
struct device_d *imx_add_ipufb(void *base, struct imx_ipu_fb_platform_data *pdata);
struct device_d *imx_add_mmc(void *base, int id, void *pdata);
struct device_d *imx_add_esdhc(void *base, int id, void *pdata);
struct device_d *imx_add_esdhc(void *base, int id, struct esdhc_platform_data *pdata);

43
arch/arm/mach-imx/include/mach/esdhc.h Normal file
View File

@ -0,0 +1,43 @@
/*
* Copyright 2010 Wolfram Sang <w.sang@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*/
#ifndef __ASM_ARCH_IMX_ESDHC_H
#define __ASM_ARCH_IMX_ESDHC_H
enum wp_types {
ESDHC_WP_NONE, /* no WP, neither controller nor gpio */
ESDHC_WP_CONTROLLER, /* mmc controller internal WP */
ESDHC_WP_GPIO, /* external gpio pin for WP */
};
enum cd_types {
ESDHC_CD_NONE, /* no CD, neither controller nor gpio */
ESDHC_CD_CONTROLLER, /* mmc controller internal CD */
ESDHC_CD_GPIO, /* external gpio pin for CD */
ESDHC_CD_PERMANENT, /* no CD, card permanently wired to host */
};
/**
* struct esdhc_platform_data - platform data for esdhc on i.MX
*
* ESDHC_WP(CD)_CONTROLLER type is not available on i.MX25/35.
*
* @wp_gpio: gpio for write_protect
* @cd_gpio: gpio for card_detect interrupt
* @wp_type: type of write_protect method (see wp_types enum above)
* @cd_type: type of card_detect method (see cd_types enum above)
*/
struct esdhc_platform_data {
unsigned int wp_gpio;
unsigned int cd_gpio;
enum wp_types wp_type;
enum cd_types cd_type;
};
#endif /* __ASM_ARCH_IMX_ESDHC_H */

3
arch/arm/mach-omap/Makefile
View File

@ -25,4 +25,5 @@ obj-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o
obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock_core.o omap3_clock.o
obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
obj-y += gpio.o xload.o
obj-$(CONFIG_SHELL_NONE) += xload.o
obj-y += gpio.o

41
arch/arm/mach-omap/xload.c
View File

@ -52,3 +52,44 @@ void *omap_xload_boot_mmc(void)
return buf;
}
enum omap_boot_src omap_bootsrc(void)
{
#if defined(CONFIG_ARCH_OMAP3)
return omap3_bootsrc();
#elif defined(CONFIG_ARCH_OMAP4)
return omap4_bootsrc();
#endif
}
/*
* Replaces the default shell in xload configuration
*/
int run_shell(void)
{
int (*func)(void) = NULL;
switch (omap_bootsrc())
{
case OMAP_BOOTSRC_MMC1:
printf("booting from MMC1\n");
func = omap_xload_boot_mmc();
break;
case OMAP_BOOTSRC_UNKNOWN:
printf("unknown boot source. Fall back to nand\n");
case OMAP_BOOTSRC_NAND:
printf("booting from NAND\n");
func = omap_xload_boot_nand(SZ_128K, SZ_256K);
break;
}
if (!func) {
printf("booting failed\n");
while (1);
}
shutdown_barebox();
func();
while (1);
}

37
arch/arm/mach-pxa/Kconfig Normal file
View File

@ -0,0 +1,37 @@
if ARCH_PXA
config ARCH_TEXT_BASE
hex
config BOARDINFO
string
# ----------------------------------------------------------
config ARCH_PXA2XX
bool
select CPU_XSCALE
choice
prompt "Intel/Marvell PXA Processor"
config ARCH_PXA27X
bool "PXA27x"
select ARCH_PXA2XX
endchoice
# ----------------------------------------------------------
if ARCH_PXA27X
choice
prompt "PXA27x Board Type"
endchoice
endif
# ----------------------------------------------------------
endif

6
arch/arm/mach-pxa/Makefile Normal file
View File

@ -0,0 +1,6 @@
obj-y += clocksource.o
obj-y += common.o
obj-y += gpio.o
obj-$(CONFIG_ARCH_PXA2XX) += mfp-pxa2xx.o
obj-$(CONFIG_ARCH_PXA27X) += speed-pxa27x.o

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/*
* (C) Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <init.h>
#include <clock.h>
#include <asm/io.h>
#define OSCR 0x40A00010
uint64_t pxa_clocksource_read(void)
{
return readl(OSCR);
}
static struct clocksource cs = {
.read = pxa_clocksource_read,
.mask = 0xffffffff,
.shift = 20,
};
static int clocksource_init(void)
{
cs.mult = clocksource_hz2mult(3250000, cs.shift);
init_clock(&cs);
return 0;
}
core_initcall(clocksource_init);

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/*
* (C) Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <asm/io.h>
#define OSMR3 0x40A0000C
#define OSCR 0x40A00010
#define OSSR 0x40A00014
#define OWER 0x40A00018
#define OWER_WME (1 << 0) /* Watch-dog Match Enable */
#define OSSR_M3 (1 << 3) /* Match status channel 3 */
void reset_cpu(ulong addr)
{
/* Initialize the watchdog and let it fire */
writel(OWER_WME, OWER);
writel(OSSR_M3, OSSR);
writel(readl(OSCR) + 368640, OSMR3); /* ... in 100 ms */
while (1);
}

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/*
* (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <driver.h>
#include <mach/devices.h>
#include <mach/pxafb.h>
static inline struct device_d *pxa_add_device(char *name, int id, void *base,
int size, void *pdata)
{
return add_generic_device(name, id, NULL, (resource_size_t)base, size,
IORESOURCE_MEM, pdata);
}
struct device_d *pxa_add_i2c(void *base, int id,
struct i2c_platform_data *pdata)
{
return pxa_add_device("i2c-pxa", id, base, 0x1000, pdata);
}
struct device_d *pxa_add_uart(void *base, int id)
{
return pxa_add_device("pxa_serial", id, base, 0x1000, NULL);
}
struct device_d *pxa_add_fb(void *base, struct pxafb_platform_data *pdata)
{
return pxa_add_device("pxafb", -1, base, 0x1000, pdata);
}
struct device_d *pxa_add_mmc(void *base, int id, void *pdata)
{
return pxa_add_device("pxa-mmc", id, base, 0x1000, pdata);
}

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/*
* Generic PXA GPIO handling
*
* Author: Nicolas Pitre
* Created: Jun 15, 2001
* Copyright: MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <common.h>
#include <errno.h>
#include <mach/gpio.h>
#include <asm/io.h>
int pxa_last_gpio;
struct pxa_gpio_chip {
void __iomem *regbase;
};
static struct pxa_gpio_chip *pxa_gpio_chips;
#define for_each_gpio_chip(i, c) \
for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
static int __init pxa_init_gpio_chip(int gpio_end)
{
int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
struct pxa_gpio_chip *chips;
chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
if (chips == NULL) {
pr_err("%s: failed to allocate GPIO chips\n", __func__);
return -ENOMEM;
}
for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32)
chips[i].regbase = (void __iomem *)GPIO_BANK(i);
pxa_gpio_chips = chips;
return 0;
}
int __init pxa_init_gpio(int start, int end)
{
struct pxa_gpio_chip *c;
int err, gpio;
pxa_last_gpio = end;
/* Initialize GPIO chips */
err = pxa_init_gpio_chip(end);
if (err)
return err;
for_each_gpio_chip(gpio, c) {
/* clear all GPIO edge detects */
__raw_writel(0, c->regbase + GFER_OFFSET);
__raw_writel(0, c->regbase + GRER_OFFSET);
__raw_writel(~0, c->regbase + GEDR_OFFSET);
}
return 0;
}

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/*
* clock.h - definitions of the PXA clock functions
*
* Copyright (C) 2010 by Marc Kleine-Budde <mkl@pengutronix.de>
*
* This file is released under the GPLv2
*
*/
#ifndef __MACH_CLOCK_H
#define __MACH_CLOCK_H
unsigned long pxa_get_uartclk(void);
#endif /* !__MACH_CLOCK_H */

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/*
* (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <i2c/i2c.h>
#include <mach/pxafb.h>
struct device_d *pxa_add_i2c(void *base, int id,
struct i2c_platform_data *pdata);
struct device_d *pxa_add_uart(void *base, int id);
struct device_d *pxa_add_fb(void *base, struct pxafb_platform_data *pdata);
struct device_d *pxa_add_mmc(void *base, int id, void *pdata);

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/*
* arch/arm/mach-pxa/include/mach/gpio.h
*
* PXA GPIO wrappers for arch-neutral GPIO calls
*
* Written by Philipp Zabel <philipp.zabel@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_PXA_GPIO_H
#define __ASM_ARCH_PXA_GPIO_H
#include <mach/hardware.h>
#define GPIO_REGS_VIRT (0x40E00000)
#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
#define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x)))
/* GPIO Pin Level Registers */
#define GPLR0 GPIO_REG(BANK_OFF(0) + 0x00)
#define GPLR1 GPIO_REG(BANK_OFF(1) + 0x00)
#define GPLR2 GPIO_REG(BANK_OFF(2) + 0x00)
#define GPLR3 GPIO_REG(BANK_OFF(3) + 0x00)
/* GPIO Pin Direction Registers */
#define GPDR0 GPIO_REG(BANK_OFF(0) + 0x0c)
#define GPDR1 GPIO_REG(BANK_OFF(1) + 0x0c)
#define GPDR2 GPIO_REG(BANK_OFF(2) + 0x0c)
#define GPDR3 GPIO_REG(BANK_OFF(3) + 0x0c)
/* GPIO Pin Output Set Registers */
#define GPSR0 GPIO_REG(BANK_OFF(0) + 0x18)
#define GPSR1 GPIO_REG(BANK_OFF(1) + 0x18)
#define GPSR2 GPIO_REG(BANK_OFF(2) + 0x18)
#define GPSR3 GPIO_REG(BANK_OFF(3) + 0x18)
/* GPIO Pin Output Clear Registers */
#define GPCR0 GPIO_REG(BANK_OFF(0) + 0x24)
#define GPCR1 GPIO_REG(BANK_OFF(1) + 0x24)
#define GPCR2 GPIO_REG(BANK_OFF(2) + 0x24)
#define GPCR3 GPIO_REG(BANK_OFF(3) + 0x24)
/* GPIO Rising Edge Detect Registers */
#define GRER0 GPIO_REG(BANK_OFF(0) + 0x30)
#define GRER1 GPIO_REG(BANK_OFF(1) + 0x30)
#define GRER2 GPIO_REG(BANK_OFF(2) + 0x30)
#define GRER3 GPIO_REG(BANK_OFF(3) + 0x30)
/* GPIO Falling Edge Detect Registers */
#define GFER0 GPIO_REG(BANK_OFF(0) + 0x3c)
#define GFER1 GPIO_REG(BANK_OFF(1) + 0x3c)
#define GFER2 GPIO_REG(BANK_OFF(2) + 0x3c)
#define GFER3 GPIO_REG(BANK_OFF(3) + 0x3c)
/* GPIO Edge Detect Status Registers */
#define GEDR0 GPIO_REG(BANK_OFF(0) + 0x48)
#define GEDR1 GPIO_REG(BANK_OFF(1) + 0x48)
#define GEDR2 GPIO_REG(BANK_OFF(2) + 0x48)
#define GEDR3 GPIO_REG(BANK_OFF(3) + 0x48)
/* GPIO Alternate Function Select Registers */
#define GAFR0_L GPIO_REG(0x0054)
#define GAFR0_U GPIO_REG(0x0058)
#define GAFR1_L GPIO_REG(0x005C)
#define GAFR1_U GPIO_REG(0x0060)
#define GAFR2_L GPIO_REG(0x0064)
#define GAFR2_U GPIO_REG(0x0068)
#define GAFR3_L GPIO_REG(0x006C)
#define GAFR3_U GPIO_REG(0x0070)
/* More handy macros. The argument is a literal GPIO number. */
#define GPIO_bit(x) (1 << ((x) & 0x1f))
#define GPLR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x00)
#define GPDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x0c)
#define GPSR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x18)
#define GPCR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x24)
#define GRER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x30)
#define GFER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x3c)
#define GEDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x48)
#define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2))
#define NR_BUILTIN_GPIO 128
#define gpio_to_bank(gpio) ((gpio) >> 5)
#ifdef CONFIG_CPU_PXA26x
/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
* as well as their Alternate Function value being '1' for GPIO in GAFRx.
*/
static inline int __gpio_is_inverted(unsigned gpio)
{
return cpu_is_pxa25x() && gpio > 85;
}
#else
static inline int __gpio_is_inverted(unsigned gpio) { return 0; }
#endif
/*
* On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
* function of a GPIO, and GPDRx cannot be altered once configured. It
* is attributed as "occupied" here (I know this terminology isn't
* accurate, you are welcome to propose a better one :-)
*/
static inline int __gpio_is_occupied(unsigned gpio)
{
if (cpu_is_pxa27x() || cpu_is_pxa25x()) {
int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3;
int dir = GPDR(gpio) & GPIO_bit(gpio);
if (__gpio_is_inverted(gpio))
return af != 1 || dir == 0;
else
return af != 0 || dir != 0;
} else
return GPDR(gpio) & GPIO_bit(gpio);
}
#include <plat/gpio.h>
#endif

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/*
* (c) 2010 by Marc Kleine-Budde <mkl@pengutronix.de>
*
* Copyright (C) 2010 by Marc Kleine-Budde <mkl@pengutronix.de>
*
* This file is released under the GPLv2
*
*/
#ifndef __MACH_HARDWARE_H
#define __MACH_HARDWARE_H
#ifdef CONFIG_ARCH_PXA2XX
#define cpu_is_pxa2xx() (1)
#else
#define cpi_is_pxa2xx() (0)
#endif
#ifdef CONFIG_ARCH_PXA25X
#define cpu_is_pxa25x() (1)
#else
#define cpu_is_pxa25x() (0)
#endif
#ifdef CONFIG_ARCH_PXA27X
#define cpu_is_pxa27x() (1)
#else
#define cpu_is_pxa27x() (0)
#endif
#endif /* !__MACH_HARDWARE_H */

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#ifndef __ASM_ARCH_MFP_PXA27X_H
#define __ASM_ARCH_MFP_PXA27X_H
/*
* NOTE: for those special-function bidirectional GPIOs, as described
* in the "PXA27x Developer's Manual" Section 24.4.2.1, only its input
* alternative is preserved, the direction is actually selected by the
* specific controller, and this should work in most cases.
*/
#include <mach/mfp-pxa2xx.h>
/* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN
* bit is set, regardless of the GPIO configuration
*/
#define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0)
#define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0)
/* GPIO */
#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0)
#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0)
#define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF0)
#define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF0)
#define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF0)
#define GPIO90_GPIO MFP_CFG_IN(GPIO90, AF0)
#define GPIO91_GPIO MFP_CFG_IN(GPIO91, AF0)
#define GPIO92_GPIO MFP_CFG_IN(GPIO92, AF0)
#define GPIO93_GPIO MFP_CFG_IN(GPIO93, AF0)
#define GPIO94_GPIO MFP_CFG_IN(GPIO94, AF0)
#define GPIO95_GPIO MFP_CFG_IN(GPIO95, AF0)
#define GPIO96_GPIO MFP_CFG_IN(GPIO96, AF0)
#define GPIO97_GPIO MFP_CFG_IN(GPIO97, AF0)
#define GPIO98_GPIO MFP_CFG_IN(GPIO98, AF0)
#define GPIO99_GPIO MFP_CFG_IN(GPIO99, AF0)
#define GPIO100_GPIO MFP_CFG_IN(GPIO100, AF0)
#define GPIO101_GPIO MFP_CFG_IN(GPIO101, AF0)
#define GPIO102_GPIO MFP_CFG_IN(GPIO102, AF0)
#define GPIO103_GPIO MFP_CFG_IN(GPIO103, AF0)
#define GPIO104_GPIO MFP_CFG_IN(GPIO104, AF0)
#define GPIO105_GPIO MFP_CFG_IN(GPIO105, AF0)
#define GPIO106_GPIO MFP_CFG_IN(GPIO106, AF0)
#define GPIO107_GPIO MFP_CFG_IN(GPIO107, AF0)
#define GPIO108_GPIO MFP_CFG_IN(GPIO108, AF0)
#define GPIO109_GPIO MFP_CFG_IN(GPIO109, AF0)
#define GPIO110_GPIO MFP_CFG_IN(GPIO110, AF0)
#define GPIO111_GPIO MFP_CFG_IN(GPIO111, AF0)
#define GPIO112_GPIO MFP_CFG_IN(GPIO112, AF0)
#define GPIO113_GPIO MFP_CFG_IN(GPIO113, AF0)
#define GPIO114_GPIO MFP_CFG_IN(GPIO114, AF0)
#define GPIO115_GPIO MFP_CFG_IN(GPIO115, AF0)
#define GPIO116_GPIO MFP_CFG_IN(GPIO116, AF0)
#define GPIO117_GPIO MFP_CFG_IN(GPIO117, AF0)
#define GPIO118_GPIO MFP_CFG_IN(GPIO118, AF0)
#define GPIO119_GPIO MFP_CFG_IN(GPIO119, AF0)
#define GPIO120_GPIO MFP_CFG_IN(GPIO120, AF0)
/* Crystal and Clock Signals */
#define GPIO9_HZ_CLK MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW)
#define GPIO10_HZ_CLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
#define GPIO11_48_MHz MFP_CFG_OUT(GPIO11, AF3, DRIVE_LOW)
#define GPIO12_48_MHz MFP_CFG_OUT(GPIO12, AF3, DRIVE_LOW)
#define GPIO13_CLK_EXT MFP_CFG_IN(GPIO13, AF1)
/* OS Timer Signals */
#define GPIO11_EXT_SYNC_0 MFP_CFG_IN(GPIO11, AF1)
#define GPIO12_EXT_SYNC_1 MFP_CFG_IN(GPIO12, AF1)
#define GPIO9_CHOUT_0 MFP_CFG_OUT(GPIO9, AF3, DRIVE_LOW)
#define GPIO10_CHOUT_1 MFP_CFG_OUT(GPIO10, AF3, DRIVE_LOW)
#define GPIO11_CHOUT_0 MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
#define GPIO12_CHOUT_1 MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW)
/* SDRAM and Static Memory I/O Signals */
#define GPIO20_nSDCS_2 MFP_CFG_OUT(GPIO20, AF1, DRIVE_HIGH)
#define GPIO21_nSDCS_3 MFP_CFG_OUT(GPIO21, AF1, DRIVE_HIGH)
#define GPIO15_nCS_1 MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH)
#define GPIO78_nCS_2 MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH)
#define GPIO79_nCS_3 MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH)
#define GPIO80_nCS_4 MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH)
#define GPIO33_nCS_5 MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH)
/* Miscellaneous I/O and DMA Signals */
#define GPIO21_DVAL_0 MFP_CFG_OUT(GPIO21, AF2, DRIVE_HIGH)
#define GPIO116_DVAL_0 MFP_CFG_OUT(GPIO116, AF1, DRIVE_HIGH)
#define GPIO33_DVAL_1 MFP_CFG_OUT(GPIO33, AF1, DRIVE_HIGH)
#define GPIO96_DVAL_1 MFP_CFG_OUT(GPIO96, AF2, DRIVE_HIGH)
#define GPIO18_RDY MFP_CFG_IN(GPIO18, AF1)
#define GPIO20_DREQ_0 MFP_CFG_IN(GPIO20, AF1)
#define GPIO115_DREQ_0 MFP_CFG_IN(GPIO115, AF1)
#define GPIO80_DREQ_1 MFP_CFG_IN(GPIO80, AF1)
#define GPIO97_DREQ_1 MFP_CFG_IN(GPIO97, AF2)
#define GPIO85_DREQ_2 MFP_CFG_IN(GPIO85, AF2)
#define GPIO100_DREQ_2 MFP_CFG_IN(GPIO100, AF2)
/* Alternate Bus Master Mode I/O Signals */
#define GPIO20_MBREQ MFP_CFG_IN(GPIO20, AF2)
#define GPIO80_MBREQ MFP_CFG_IN(GPIO80, AF2)
#define GPIO96_MBREQ MFP_CFG_IN(GPIO96, AF2)
#define GPIO115_MBREQ MFP_CFG_IN(GPIO115, AF3)
#define GPIO21_MBGNT MFP_CFG_OUT(GPIO21, AF3, DRIVE_LOW)
#define GPIO33_MBGNT MFP_CFG_OUT(GPIO33, AF3, DRIVE_LOW)
#define GPIO97_MBGNT MFP_CFG_OUT(GPIO97, AF2, DRIVE_LOW)
#define GPIO116_MBGNT MFP_CFG_OUT(GPIO116, AF3, DRIVE_LOW)
/* PC CARD */
#define GPIO15_nPCE_1 MFP_CFG_OUT(GPIO15, AF1, DRIVE_HIGH)
#define GPIO85_nPCE_1 MFP_CFG_OUT(GPIO85, AF1, DRIVE_HIGH)
#define GPIO86_nPCE_1 MFP_CFG_OUT(GPIO86, AF1, DRIVE_HIGH)
#define GPIO102_nPCE_1 MFP_CFG_OUT(GPIO102, AF1, DRIVE_HIGH)
#define GPIO54_nPCE_2 MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH)
#define GPIO78_nPCE_2 MFP_CFG_OUT(GPIO78, AF1, DRIVE_HIGH)
#define GPIO87_nPCE_2 MFP_CFG_IN(GPIO87, AF1)
#define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH)
#define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH)
#define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH)
#define GPIO49_nPWE MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH)
#define GPIO48_nPOE MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH)
#define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1)
#define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1)
#define GPIO79_PSKTSEL MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH)
#define GPIO104_PSKTSEL MFP_CFG_OUT(GPIO104, AF1, DRIVE_HIGH)
/* I2C */
#define GPIO117_I2C_SCL MFP_CFG_IN(GPIO117, AF1)
#define GPIO118_I2C_SDA MFP_CFG_IN(GPIO118, AF1)
/* FFUART */
#define GPIO9_FFUART_CTS MFP_CFG_IN(GPIO9, AF3)
#define GPIO26_FFUART_CTS MFP_CFG_IN(GPIO26, AF3)
#define GPIO35_FFUART_CTS MFP_CFG_IN(GPIO35, AF1)
#define GPIO100_FFUART_CTS MFP_CFG_IN(GPIO100, AF3)
#define GPIO10_FFUART_DCD MFP_CFG_IN(GPIO10, AF1)
#define GPIO36_FFUART_DCD MFP_CFG_IN(GPIO36, AF1)
#define GPIO33_FFUART_DSR MFP_CFG_IN(GPIO33, AF2)
#define GPIO37_FFUART_DSR MFP_CFG_IN(GPIO37, AF1)
#define GPIO38_FFUART_RI MFP_CFG_IN(GPIO38, AF1)
#define GPIO89_FFUART_RI MFP_CFG_IN(GPIO89, AF3)
#define GPIO19_FFUART_RXD MFP_CFG_IN(GPIO19, AF3)
#define GPIO33_FFUART_RXD MFP_CFG_IN(GPIO33, AF1)
#define GPIO34_FFUART_RXD MFP_CFG_IN(GPIO34, AF1)
#define GPIO41_FFUART_RXD MFP_CFG_IN(GPIO41, AF1)
#define GPIO53_FFUART_RXD MFP_CFG_IN(GPIO53, AF1)
#define GPIO85_FFUART_RXD MFP_CFG_IN(GPIO85, AF1)
#define GPIO96_FFUART_RXD MFP_CFG_IN(GPIO96, AF3)
#define GPIO102_FFUART_RXD MFP_CFG_IN(GPIO102, AF3)
#define GPIO16_FFUART_TXD MFP_CFG_OUT(GPIO16, AF3, DRIVE_HIGH)
#define GPIO37_FFUART_TXD MFP_CFG_OUT(GPIO37, AF3, DRIVE_HIGH)
#define GPIO39_FFUART_TXD MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH)
#define GPIO83_FFUART_TXD MFP_CFG_OUT(GPIO83, AF2, DRIVE_HIGH)
#define GPIO99_FFUART_TXD MFP_CFG_OUT(GPIO99, AF3, DRIVE_HIGH)
#define GPIO27_FFUART_RTS MFP_CFG_OUT(GPIO27, AF3, DRIVE_HIGH)
#define GPIO41_FFUART_RTS MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH)
#define GPIO83_FFUART_RTS MFP_CFG_OUT(GPIO83, AF3, DRIVE_HIGH)
#define GPIO98_FFUART_RTS MFP_CFG_OUT(GPIO98, AF3, DRIVE_HIGH)
#define GPIO40_FFUART_DTR MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH)
#define GPIO82_FFUART_DTR MFP_CFG_OUT(GPIO82, AF3, DRIVE_HIGH)
/* BTUART */
#define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1)
#define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1)
#define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
#define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
/* STUART */
#define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2)
#define GPIO47_STUART_TXD MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH)
/* FICP */
#define GPIO42_FICP_RXD MFP_CFG_IN(GPIO42, AF2)
#define GPIO46_FICP_RXD MFP_CFG_IN(GPIO46, AF1)
#define GPIO43_FICP_TXD MFP_CFG_OUT(GPIO43, AF1, DRIVE_HIGH)
#define GPIO47_FICP_TXD MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH)
/* PWM 0/1/2/3 */
#define GPIO11_PWM2_OUT MFP_CFG_OUT(GPIO11, AF2, DRIVE_LOW)
#define GPIO12_PWM3_OUT MFP_CFG_OUT(GPIO12, AF2, DRIVE_LOW)
#define GPIO16_PWM0_OUT MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW)
#define GPIO17_PWM1_OUT MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW)
#define GPIO38_PWM1_OUT MFP_CFG_OUT(GPIO38, AF3, DRIVE_LOW)
#define GPIO46_PWM2_OUT MFP_CFG_OUT(GPIO46, AF2, DRIVE_LOW)
#define GPIO47_PWM3_OUT MFP_CFG_OUT(GPIO47, AF3, DRIVE_LOW)
#define GPIO79_PWM2_OUT MFP_CFG_OUT(GPIO79, AF3, DRIVE_LOW)
#define GPIO80_PWM3_OUT MFP_CFG_OUT(GPIO80, AF3, DRIVE_LOW)
#define GPIO115_PWM1_OUT MFP_CFG_OUT(GPIO115, AF3, DRIVE_LOW)
/* AC97 */
#define GPIO31_AC97_SYNC MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW)
#define GPIO94_AC97_SYNC MFP_CFG_OUT(GPIO94, AF1, DRIVE_LOW)
#define GPIO30_AC97_SDATA_OUT MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW)
#define GPIO93_AC97_SDATA_OUT MFP_CFG_OUT(GPIO93, AF1, DRIVE_LOW)
#define GPIO45_AC97_SYSCLK MFP_CFG_OUT(GPIO45, AF1, DRIVE_LOW)
#define GPIO89_AC97_SYSCLK MFP_CFG_OUT(GPIO89, AF1, DRIVE_LOW)
#define GPIO98_AC97_SYSCLK MFP_CFG_OUT(GPIO98, AF1, DRIVE_LOW)
#define GPIO95_AC97_nRESET MFP_CFG_OUT(GPIO95, AF1, DRIVE_LOW)
#define GPIO113_AC97_nRESET MFP_CFG_OUT(GPIO113, AF2, DRIVE_LOW)
#define GPIO28_AC97_BITCLK MFP_CFG_IN(GPIO28, AF1)
#define GPIO29_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO29, AF1)
#define GPIO116_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO116, AF2)
#define GPIO99_AC97_SDATA_IN_1 MFP_CFG_IN(GPIO99, AF2)
/* I2S */
#define GPIO28_I2S_BITCLK_IN MFP_CFG_IN(GPIO28, AF2)
#define GPIO28_I2S_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW)
#define GPIO29_I2S_SDATA_IN MFP_CFG_IN(GPIO29, AF2)
#define GPIO30_I2S_SDATA_OUT MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW)
#define GPIO31_I2S_SYNC MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW)
#define GPIO113_I2S_SYSCLK MFP_CFG_OUT(GPIO113, AF1, DRIVE_LOW)
/* SSP 1 */
#define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW)
#define GPIO29_SSP1_SCLK MFP_CFG_IN(GPIO29, AF3)
#define GPIO27_SSP1_SYSCLK MFP_CFG_OUT(GPIO27, AF1, DRIVE_LOW)
#define GPIO53_SSP1_SYSCLK MFP_CFG_OUT(GPIO53, AF3, DRIVE_LOW)
#define GPIO24_SSP1_SFRM MFP_CFG_IN(GPIO24, AF2)
#define GPIO28_SSP1_SFRM MFP_CFG_IN(GPIO28, AF3)
#define GPIO25_SSP1_TXD MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW)
#define GPIO57_SSP1_TXD MFP_CFG_OUT(GPIO57, AF3, DRIVE_LOW)
#define GPIO26_SSP1_RXD MFP_CFG_IN(GPIO26, AF1)
#define GPIO27_SSP1_SCLKEN MFP_CFG_IN(GPIO27, AF2)
/* SSP 2 */
#define GPIO19_SSP2_SCLK MFP_CFG_IN(GPIO19, AF1)
#define GPIO22_SSP2_SCLK MFP_CFG_IN(GPIO22, AF3)
#define GPIO29_SSP2_SCLK MFP_CFG_OUT(GPIO29, AF3, DRIVE_LOW)
#define GPIO36_SSP2_SCLK MFP_CFG_IN(GPIO36, AF2)
#define GPIO50_SSP2_SCLK MFP_CFG_IN(GPIO50, AF3)
#define GPIO22_SSP2_SYSCLK MFP_CFG_OUT(GPIO22, AF2, DRIVE_LOW)
#define GPIO14_SSP2_SFRM MFP_CFG_IN(GPIO14, AF2)
#define GPIO37_SSP2_SFRM MFP_CFG_IN(GPIO37, AF2)
#define GPIO87_SSP2_SFRM MFP_CFG_OUT(GPIO87, AF3, DRIVE_LOW)
#define GPIO88_SSP2_SFRM MFP_CFG_IN(GPIO88, AF3)
#define GPIO13_SSP2_TXD MFP_CFG_OUT(GPIO13, AF1, DRIVE_LOW)
#define GPIO38_SSP2_TXD MFP_CFG_OUT(GPIO38, AF2, DRIVE_LOW)
#define GPIO87_SSP2_TXD MFP_CFG_OUT(GPIO87, AF1, DRIVE_LOW)
#define GPIO89_SSP2_TXD MFP_CFG_OUT(GPIO89, AF3, DRIVE_LOW)
#define GPIO11_SSP2_RXD MFP_CFG_IN(GPIO11, AF2)
#define GPIO29_SSP2_RXD MFP_CFG_OUT(GPIO29, AF1, DRIVE_LOW)
#define GPIO40_SSP2_RXD MFP_CFG_IN(GPIO40, AF1)
#define GPIO86_SSP2_RXD MFP_CFG_IN(GPIO86, AF1)
#define GPIO88_SSP2_RXD MFP_CFG_IN(GPIO88, AF2)
#define GPIO22_SSP2_EXTCLK MFP_CFG_IN(GPIO22, AF1)
#define GPIO27_SSP2_EXTCLK MFP_CFG_IN(GPIO27, AF1)
#define GPIO22_SSP2_SCLKEN MFP_CFG_IN(GPIO22, AF2)
#define GPIO23_SSP2_SCLKEN MFP_CFG_IN(GPIO23, AF2)
/* SSP 3 */
#define GPIO34_SSP3_SCLK MFP_CFG_IN(GPIO34, AF3)
#define GPIO40_SSP3_SCLK MFP_CFG_OUT(GPIO40, AF3, DRIVE_LOW)
#define GPIO52_SSP3_SCLK MFP_CFG_IN(GPIO52, AF2)
#define GPIO84_SSP3_SCLK MFP_CFG_IN(GPIO84, AF1)
#define GPIO45_SSP3_SYSCLK MFP_CFG_OUT(GPIO45, AF3, DRIVE_LOW)
#define GPIO35_SSP3_SFRM MFP_CFG_IN(GPIO35, AF3)
#define GPIO39_SSP3_SFRM MFP_CFG_IN(GPIO39, AF3)
#define GPIO83_SSP3_SFRM MFP_CFG_IN(GPIO83, AF1)
#define GPIO35_SSP3_TXD MFP_CFG_OUT(GPIO35, AF3, DRIVE_LOW)
#define GPIO38_SSP3_TXD MFP_CFG_OUT(GPIO38, AF1, DRIVE_LOW)
#define GPIO81_SSP3_TXD MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW)
#define GPIO41_SSP3_RXD MFP_CFG_IN(GPIO41, AF3)
#define GPIO82_SSP3_RXD MFP_CFG_IN(GPIO82, AF1)
#define GPIO89_SSP3_RXD MFP_CFG_IN(GPIO89, AF1)
/* MMC */
#define GPIO32_MMC_CLK MFP_CFG_OUT(GPIO32, AF2, DRIVE_LOW)
#define GPIO92_MMC_DAT_0 MFP_CFG_IN(GPIO92, AF1)
#define GPIO109_MMC_DAT_1 MFP_CFG_IN(GPIO109, AF1)
#define GPIO110_MMC_DAT_2 MFP_CFG_IN(GPIO110, AF1)
#define GPIO111_MMC_DAT_3 MFP_CFG_IN(GPIO111, AF1)
#define GPIO112_MMC_CMD MFP_CFG_IN(GPIO112, AF1)
/* LCD */
#define GPIO58_LCD_LDD_0 MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW)
#define GPIO59_LCD_LDD_1 MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW)
#define GPIO60_LCD_LDD_2 MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW)
#define GPIO61_LCD_LDD_3 MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW)
#define GPIO62_LCD_LDD_4 MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW)
#define GPIO63_LCD_LDD_5 MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW)
#define GPIO64_LCD_LDD_6 MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW)
#define GPIO65_LCD_LDD_7 MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW)
#define GPIO66_LCD_LDD_8 MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW)
#define GPIO67_LCD_LDD_9 MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW)
#define GPIO68_LCD_LDD_10 MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW)
#define GPIO69_LCD_LDD_11 MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW)
#define GPIO70_LCD_LDD_12 MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW)
#define GPIO71_LCD_LDD_13 MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW)
#define GPIO72_LCD_LDD_14 MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW)
#define GPIO73_LCD_LDD_15 MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW)
#define GPIO86_LCD_LDD_16 MFP_CFG_OUT(GPIO86, AF2, DRIVE_LOW)
#define GPIO87_LCD_LDD_17 MFP_CFG_OUT(GPIO87, AF2, DRIVE_LOW)
#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
#define GPIO14_LCD_VSYNC MFP_CFG_IN(GPIO14, AF1)
#define GPIO19_LCD_CS MFP_CFG_OUT(GPIO19, AF2, DRIVE_LOW)
/* Keypad */
#define GPIO93_KP_DKIN_0 MFP_CFG_IN(GPIO93, AF1)
#define GPIO94_KP_DKIN_1 MFP_CFG_IN(GPIO94, AF1)
#define GPIO95_KP_DKIN_2 MFP_CFG_IN(GPIO95, AF1)
#define GPIO96_KP_DKIN_3 MFP_CFG_IN(GPIO96, AF1)
#define GPIO97_KP_DKIN_4 MFP_CFG_IN(GPIO97, AF1)
#define GPIO98_KP_DKIN_5 MFP_CFG_IN(GPIO98, AF1)
#define GPIO99_KP_DKIN_6 MFP_CFG_IN(GPIO99, AF1)
#define GPIO13_KP_KDIN_7 MFP_CFG_IN(GPIO13, AF2)
#define GPIO100_KP_MKIN_0 MFP_CFG_IN(GPIO100, AF1)
#define GPIO101_KP_MKIN_1 MFP_CFG_IN(GPIO101, AF1)
#define GPIO102_KP_MKIN_2 MFP_CFG_IN(GPIO102, AF1)
#define GPIO34_KP_MKIN_3 MFP_CFG_IN(GPIO34, AF2)
#define GPIO37_KP_MKIN_3 MFP_CFG_IN(GPIO37, AF3)
#define GPIO97_KP_MKIN_3 MFP_CFG_IN(GPIO97, AF3)
#define GPIO98_KP_MKIN_4 MFP_CFG_IN(GPIO98, AF3)
#define GPIO38_KP_MKIN_4 MFP_CFG_IN(GPIO38, AF2)
#define GPIO39_KP_MKIN_4 MFP_CFG_IN(GPIO39, AF1)
#define GPIO16_KP_MKIN_5 MFP_CFG_IN(GPIO16, AF1)
#define GPIO90_KP_MKIN_5 MFP_CFG_IN(GPIO90, AF1)
#define GPIO99_KP_MKIN_5 MFP_CFG_IN(GPIO99, AF3)
#define GPIO17_KP_MKIN_6 MFP_CFG_IN(GPIO17, AF1)
#define GPIO91_KP_MKIN_6 MFP_CFG_IN(GPIO91, AF1)
#define GPIO95_KP_MKIN_6 MFP_CFG_IN(GPIO95, AF3)
#define GPIO13_KP_MKIN_7 MFP_CFG_IN(GPIO13, AF3)
#define GPIO36_KP_MKIN_7 MFP_CFG_IN(GPIO36, AF3)
#define GPIO103_KP_MKOUT_0 MFP_CFG_OUT(GPIO103, AF2, DRIVE_HIGH)
#define GPIO104_KP_MKOUT_1 MFP_CFG_OUT(GPIO104, AF2, DRIVE_HIGH)
#define GPIO105_KP_MKOUT_2 MFP_CFG_OUT(GPIO105, AF2, DRIVE_HIGH)
#define GPIO106_KP_MKOUT_3 MFP_CFG_OUT(GPIO106, AF2, DRIVE_HIGH)
#define GPIO107_KP_MKOUT_4 MFP_CFG_OUT(GPIO107, AF2, DRIVE_HIGH)
#define GPIO108_KP_MKOUT_5 MFP_CFG_OUT(GPIO108, AF2, DRIVE_HIGH)
#define GPIO35_KP_MKOUT_6 MFP_CFG_OUT(GPIO35, AF2, DRIVE_HIGH)
#define GPIO22_KP_MKOUT_7 MFP_CFG_OUT(GPIO22, AF1, DRIVE_HIGH)
#define GPIO40_KP_MKOUT_6 MFP_CFG_OUT(GPIO40, AF1, DRIVE_HIGH)
#define GPIO41_KP_MKOUT_7 MFP_CFG_OUT(GPIO41, AF1, DRIVE_HIGH)
#define GPIO96_KP_MKOUT_6 MFP_CFG_OUT(GPIO96, AF3, DRIVE_HIGH)
/* USB P3 */
#define GPIO10_USB_P3_5 MFP_CFG_IN(GPIO10, AF3)
#define GPIO11_USB_P3_1 MFP_CFG_IN(GPIO11, AF3)
#define GPIO30_USB_P3_2 MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW)
#define GPIO31_USB_P3_6 MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW)
#define GPIO56_USB_P3_4 MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW)
#define GPIO86_USB_P3_5 MFP_CFG_IN(GPIO86, AF3)
#define GPIO87_USB_P3_1 MFP_CFG_IN(GPIO87, AF3)
#define GPIO90_USB_P3_5 MFP_CFG_IN(GPIO90, AF2)
#define GPIO91_USB_P3_1 MFP_CFG_IN(GPIO91, AF2)
#define GPIO113_USB_P3_3 MFP_CFG_IN(GPIO113, AF3)
/* USB P2 */
#define GPIO34_USB_P2_2 MFP_CFG_OUT(GPIO34, AF1, DRIVE_LOW)
#define GPIO35_USB_P2_1 MFP_CFG_IN(GPIO35, AF2)
#define GPIO36_USB_P2_4 MFP_CFG_OUT(GPIO36, AF1, DRIVE_LOW)
#define GPIO37_USB_P2_8 MFP_CFG_OUT(GPIO37, AF1, DRIVE_LOW)
#define GPIO38_USB_P2_3 MFP_CFG_IN(GPIO38, AF3)
#define GPIO39_USB_P2_6 MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW)
#define GPIO40_USB_P2_5 MFP_CFG_IN(GPIO40, AF3)
#define GPIO41_USB_P2_7 MFP_CFG_IN(GPIO41, AF2)
#define GPIO53_USB_P2_3 MFP_CFG_IN(GPIO53, AF2)
/* USB Host Port 1/2 */
#define GPIO88_USBH1_PWR MFP_CFG_IN(GPIO88, AF1)
#define GPIO89_USBH1_PEN MFP_CFG_OUT(GPIO89, AF2, DRIVE_LOW)
#define GPIO119_USBH2_PWR MFP_CFG_IN(GPIO119, AF1)
#define GPIO120_USBH2_PEN MFP_CFG_OUT(GPIO120, AF2, DRIVE_LOW)
/* QCI - default to Master Mode: CIF_FV/CIF_LV Direction In */
#define GPIO115_CIF_DD_3 MFP_CFG_IN(GPIO115, AF2)
#define GPIO116_CIF_DD_2 MFP_CFG_IN(GPIO116, AF1)
#define GPIO12_CIF_DD_7 MFP_CFG_IN(GPIO12, AF2)
#define GPIO17_CIF_DD_6 MFP_CFG_IN(GPIO17, AF2)
#define GPIO23_CIF_MCLK MFP_CFG_OUT(GPIO23, AF1, DRIVE_LOW)
#define GPIO24_CIF_FV MFP_CFG_IN(GPIO24, AF1)
#define GPIO25_CIF_LV MFP_CFG_IN(GPIO25, AF1)
#define GPIO26_CIF_PCLK MFP_CFG_IN(GPIO26, AF2)
#define GPIO27_CIF_DD_0 MFP_CFG_IN(GPIO27, AF3)
#define GPIO42_CIF_MCLK MFP_CFG_OUT(GPIO42, AF3, DRIVE_LOW)
#define GPIO43_CIF_FV MFP_CFG_IN(GPIO43, AF3)
#define GPIO44_CIF_LV MFP_CFG_IN(GPIO44, AF3)
#define GPIO45_CIF_PCLK MFP_CFG_IN(GPIO45, AF3)
#define GPIO47_CIF_DD_0 MFP_CFG_IN(GPIO47, AF1)
#define GPIO48_CIF_DD_5 MFP_CFG_IN(GPIO48, AF1)
#define GPIO50_CIF_DD_3 MFP_CFG_IN(GPIO50, AF1)
#define GPIO51_CIF_DD_2 MFP_CFG_IN(GPIO51, AF1)
#define GPIO52_CIF_DD_4 MFP_CFG_IN(GPIO52, AF1)
#define GPIO53_CIF_MCLK MFP_CFG_OUT(GPIO53, AF2, DRIVE_LOW)
#define GPIO54_CIF_PCLK MFP_CFG_IN(GPIO54, AF3)
#define GPIO55_CIF_DD_1 MFP_CFG_IN(GPIO55, AF1)
#define GPIO81_CIF_DD_0 MFP_CFG_IN(GPIO81, AF2)
#define GPIO82_CIF_DD_5 MFP_CFG_IN(GPIO82, AF3)
#define GPIO83_CIF_DD_4 MFP_CFG_IN(GPIO83, AF3)
#define GPIO84_CIF_FV MFP_CFG_IN(GPIO84, AF3)
#define GPIO85_CIF_LV MFP_CFG_IN(GPIO85, AF3)
#define GPIO90_CIF_DD_4 MFP_CFG_IN(GPIO90, AF3)
#define GPIO91_CIF_DD_5 MFP_CFG_IN(GPIO91, AF3)
#define GPIO93_CIF_DD_6 MFP_CFG_IN(GPIO93, AF2)
#define GPIO94_CIF_DD_5 MFP_CFG_IN(GPIO94, AF2)
#define GPIO95_CIF_DD_4 MFP_CFG_IN(GPIO95, AF2)
#define GPIO98_CIF_DD_0 MFP_CFG_IN(GPIO98, AF2)
#define GPIO103_CIF_DD_3 MFP_CFG_IN(GPIO103, AF1)
#define GPIO104_CIF_DD_2 MFP_CFG_IN(GPIO104, AF1)
#define GPIO105_CIF_DD_1 MFP_CFG_IN(GPIO105, AF1)
#define GPIO106_CIF_DD_9 MFP_CFG_IN(GPIO106, AF1)
#define GPIO107_CIF_DD_8 MFP_CFG_IN(GPIO107, AF1)
#define GPIO108_CIF_DD_7 MFP_CFG_IN(GPIO108, AF1)
#define GPIO114_CIF_DD_1 MFP_CFG_IN(GPIO114, AF1)
/* Universal Subscriber ID Interface */
#define GPIO114_UVS0 MFP_CFG_OUT(GPIO114, AF2, DRIVE_LOW)
#define GPIO115_nUVS1 MFP_CFG_OUT(GPIO115, AF2, DRIVE_LOW)
#define GPIO116_nUVS2 MFP_CFG_OUT(GPIO116, AF2, DRIVE_LOW)
#define GPIO14_UCLK MFP_CFG_OUT(GPIO14, AF3, DRIVE_LOW)
#define GPIO91_UCLK MFP_CFG_OUT(GPIO91, AF2, DRIVE_LOW)
#define GPIO19_nURST MFP_CFG_OUT(GPIO19, AF3, DRIVE_LOW)
#define GPIO90_nURST MFP_CFG_OUT(GPIO90, AF2, DRIVE_LOW)
#define GPIO116_UDET MFP_CFG_IN(GPIO116, AF3)
#define GPIO114_UEN MFP_CFG_OUT(GPIO114, AF1, DRIVE_LOW)
#define GPIO115_UEN MFP_CFG_OUT(GPIO115, AF1, DRIVE_LOW)
/* Mobile Scalable Link (MSL) Interface */
#define GPIO81_BB_OB_DAT_0 MFP_CFG_OUT(GPIO81, AF2, DRIVE_LOW)
#define GPIO48_BB_OB_DAT_1 MFP_CFG_OUT(GPIO48, AF1, DRIVE_LOW)
#define GPIO50_BB_OB_DAT_2 MFP_CFG_OUT(GPIO50, AF1, DRIVE_LOW)
#define GPIO51_BB_OB_DAT_3 MFP_CFG_OUT(GPIO51, AF1, DRIVE_LOW)
#define GPIO52_BB_OB_CLK MFP_CFG_OUT(GPIO52, AF1, DRIVE_LOW)
#define GPIO53_BB_OB_STB MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW)
#define GPIO54_BB_OB_WAIT MFP_CFG_IN(GPIO54, AF2)
#define GPIO82_BB_IB_DAT_0 MFP_CFG_IN(GPIO82, AF2)
#define GPIO55_BB_IB_DAT_1 MFP_CFG_IN(GPIO55, AF2)
#define GPIO56_BB_IB_DAT_2 MFP_CFG_IN(GPIO56, AF2)
#define GPIO57_BB_IB_DAT_3 MFP_CFG_IN(GPIO57, AF2)
#define GPIO83_BB_IB_CLK MFP_CFG_IN(GPIO83, AF2)
#define GPIO84_BB_IB_STB MFP_CFG_IN(GPIO84, AF2)
#define GPIO85_BB_IB_WAIT MFP_CFG_OUT(GPIO85, AF2, DRIVE_LOW)
/* Memory Stick Host Controller */
#define GPIO92_MSBS MFP_CFG_OUT(GPIO92, AF2, DRIVE_LOW)
#define GPIO109_MSSDIO MFP_CFG_IN(GPIO109, AF2)
#define GPIO112_nMSINS MFP_CFG_IN(GPIO112, AF2)
#define GPIO32_MSSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW)
extern int keypad_set_wake(unsigned int on);
#endif /* __ASM_ARCH_MFP_PXA27X_H */

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arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h Normal file
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#ifndef __ASM_ARCH_MFP_PXA2XX_H
#define __ASM_ARCH_MFP_PXA2XX_H
#include <plat/mfp.h>
/*
* the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx:
*
* MFP_PIN(x)
* MFP_AFx
* MFP_LPM_DRIVE_{LOW, HIGH}
* MFP_LPM_EDGE_x
*
* other MFP_x bit definitions will be ignored
*
* and adds the below two bits specifically for pxa2xx:
*
* bit 23 - Input/Output (PXA2xx specific)
* bit 24 - Wakeup Enable(PXA2xx specific)
*/
#define MFP_DIR_IN (0x0 << 23)
#define MFP_DIR_OUT (0x1 << 23)
#define MFP_DIR_MASK (0x1 << 23)
#define MFP_DIR(x) (((x) >> 23) & 0x1)
#define MFP_LPM_CAN_WAKEUP (0x1 << 24)
#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
#define WAKEUP_ON_EDGE_FALL (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL)
#define WAKEUP_ON_EDGE_BOTH (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH)
/* specifically for enabling wakeup on keypad GPIOs */
#define WAKEUP_ON_LEVEL_HIGH (MFP_LPM_CAN_WAKEUP)
#define MFP_CFG_IN(pin, af) \
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\
(MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_IN))
/* NOTE: pins configured as output _must_ provide a low power state,
* and this state should help to minimize the power dissipation.
*/
#define MFP_CFG_OUT(pin, af, state) \
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\
(MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
/* Common configurations for pxa25x and pxa27x
*
* Note: pins configured as GPIO are always initialized to input
* so not to cause any side effect
*/
#define GPIO0_GPIO MFP_CFG_IN(GPIO0, AF0)
#define GPIO1_GPIO MFP_CFG_IN(GPIO1, AF0)
#define GPIO9_GPIO MFP_CFG_IN(GPIO9, AF0)
#define GPIO10_GPIO MFP_CFG_IN(GPIO10, AF0)
#define GPIO11_GPIO MFP_CFG_IN(GPIO11, AF0)
#define GPIO12_GPIO MFP_CFG_IN(GPIO12, AF0)
#define GPIO13_GPIO MFP_CFG_IN(GPIO13, AF0)
#define GPIO14_GPIO MFP_CFG_IN(GPIO14, AF0)
#define GPIO15_GPIO MFP_CFG_IN(GPIO15, AF0)
#define GPIO16_GPIO MFP_CFG_IN(GPIO16, AF0)
#define GPIO17_GPIO MFP_CFG_IN(GPIO17, AF0)
#define GPIO18_GPIO MFP_CFG_IN(GPIO18, AF0)
#define GPIO19_GPIO MFP_CFG_IN(GPIO19, AF0)
#define GPIO20_GPIO MFP_CFG_IN(GPIO20, AF0)
#define GPIO21_GPIO MFP_CFG_IN(GPIO21, AF0)
#define GPIO22_GPIO MFP_CFG_IN(GPIO22, AF0)
#define GPIO23_GPIO MFP_CFG_IN(GPIO23, AF0)
#define GPIO24_GPIO MFP_CFG_IN(GPIO24, AF0)
#define GPIO25_GPIO MFP_CFG_IN(GPIO25, AF0)
#define GPIO26_GPIO MFP_CFG_IN(GPIO26, AF0)
#define GPIO27_GPIO MFP_CFG_IN(GPIO27, AF0)
#define GPIO28_GPIO MFP_CFG_IN(GPIO28, AF0)
#define GPIO29_GPIO MFP_CFG_IN(GPIO29, AF0)
#define GPIO30_GPIO MFP_CFG_IN(GPIO30, AF0)
#define GPIO31_GPIO MFP_CFG_IN(GPIO31, AF0)
#define GPIO32_GPIO MFP_CFG_IN(GPIO32, AF0)
#define GPIO33_GPIO MFP_CFG_IN(GPIO33, AF0)
#define GPIO34_GPIO MFP_CFG_IN(GPIO34, AF0)
#define GPIO35_GPIO MFP_CFG_IN(GPIO35, AF0)
#define GPIO36_GPIO MFP_CFG_IN(GPIO36, AF0)
#define GPIO37_GPIO MFP_CFG_IN(GPIO37, AF0)
#define GPIO38_GPIO MFP_CFG_IN(GPIO38, AF0)
#define GPIO39_GPIO MFP_CFG_IN(GPIO39, AF0)
#define GPIO40_GPIO MFP_CFG_IN(GPIO40, AF0)
#define GPIO41_GPIO MFP_CFG_IN(GPIO41, AF0)
#define GPIO42_GPIO MFP_CFG_IN(GPIO42, AF0)
#define GPIO43_GPIO MFP_CFG_IN(GPIO43, AF0)
#define GPIO44_GPIO MFP_CFG_IN(GPIO44, AF0)
#define GPIO45_GPIO MFP_CFG_IN(GPIO45, AF0)
#define GPIO46_GPIO MFP_CFG_IN(GPIO46, AF0)
#define GPIO47_GPIO MFP_CFG_IN(GPIO47, AF0)
#define GPIO48_GPIO MFP_CFG_IN(GPIO48, AF0)
#define GPIO49_GPIO MFP_CFG_IN(GPIO49, AF0)
#define GPIO50_GPIO MFP_CFG_IN(GPIO50, AF0)
#define GPIO51_GPIO MFP_CFG_IN(GPIO51, AF0)
#define GPIO52_GPIO MFP_CFG_IN(GPIO52, AF0)
#define GPIO53_GPIO MFP_CFG_IN(GPIO53, AF0)
#define GPIO54_GPIO MFP_CFG_IN(GPIO54, AF0)
#define GPIO55_GPIO MFP_CFG_IN(GPIO55, AF0)
#define GPIO56_GPIO MFP_CFG_IN(GPIO56, AF0)
#define GPIO57_GPIO MFP_CFG_IN(GPIO57, AF0)
#define GPIO58_GPIO MFP_CFG_IN(GPIO58, AF0)
#define GPIO59_GPIO MFP_CFG_IN(GPIO59, AF0)
#define GPIO60_GPIO MFP_CFG_IN(GPIO60, AF0)
#define GPIO61_GPIO MFP_CFG_IN(GPIO61, AF0)
#define GPIO62_GPIO MFP_CFG_IN(GPIO62, AF0)
#define GPIO63_GPIO MFP_CFG_IN(GPIO63, AF0)
#define GPIO64_GPIO MFP_CFG_IN(GPIO64, AF0)
#define GPIO65_GPIO MFP_CFG_IN(GPIO65, AF0)
#define GPIO66_GPIO MFP_CFG_IN(GPIO66, AF0)
#define GPIO67_GPIO MFP_CFG_IN(GPIO67, AF0)
#define GPIO68_GPIO MFP_CFG_IN(GPIO68, AF0)
#define GPIO69_GPIO MFP_CFG_IN(GPIO69, AF0)
#define GPIO70_GPIO MFP_CFG_IN(GPIO70, AF0)
#define GPIO71_GPIO MFP_CFG_IN(GPIO71, AF0)
#define GPIO72_GPIO MFP_CFG_IN(GPIO72, AF0)
#define GPIO73_GPIO MFP_CFG_IN(GPIO73, AF0)
#define GPIO74_GPIO MFP_CFG_IN(GPIO74, AF0)
#define GPIO75_GPIO MFP_CFG_IN(GPIO75, AF0)
#define GPIO76_GPIO MFP_CFG_IN(GPIO76, AF0)
#define GPIO77_GPIO MFP_CFG_IN(GPIO77, AF0)
#define GPIO78_GPIO MFP_CFG_IN(GPIO78, AF0)
#define GPIO79_GPIO MFP_CFG_IN(GPIO79, AF0)
#define GPIO80_GPIO MFP_CFG_IN(GPIO80, AF0)
#define GPIO81_GPIO MFP_CFG_IN(GPIO81, AF0)
#define GPIO82_GPIO MFP_CFG_IN(GPIO82, AF0)
#define GPIO83_GPIO MFP_CFG_IN(GPIO83, AF0)
#define GPIO84_GPIO MFP_CFG_IN(GPIO84, AF0)
extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num);
extern void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm);
extern int gpio_set_wake(unsigned int gpio, unsigned int on);
#endif /* __ASM_ARCH_MFP_PXA2XX_H */

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/*
* arch/arm/mach-pxa/include/mach/mfp.h
*
* Multi-Function Pin Definitions
*
* Copyright (C) 2007 Marvell International Ltd.
*
* 2007-8-21: eric miao <eric.miao@marvell.com>
* initial version
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MFP_H
#define __ASM_ARCH_MFP_H
#include <plat/mfp.h>
#endif /* __ASM_ARCH_MFP_H */

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/*
* (c) 2010 by Marc Kleine-Budde <mkl@pengutronix.de>
*
* Copyright (C) 2010 by Marc Kleine-Budde <mkl@pengutronix.de>
*
* This file is released under the GPLv2
*
*/
#ifndef __MACH_PXA_REGS_H
#define __MACH_PXA_REGS_H
#ifndef __ASSEMBLY__
# define __REG(x) (*((volatile u32 *)(x)))
# define __REG16(x) (*(volatile u16 *)(x))
# define __REG2(x, y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
#else
# define __REG(x) (x)
# define __REG16(x) (x)
# define __REG2(x, y) ((x) + (y))
#endif
#ifdef CONFIG_ARCH_PXA2XX
# include <mach/pxa2xx-regs.h>
#endif
#ifdef CONFIG_ARCH_PXA27X
# include <mach/pxa27x-regs.h>
#else
# error "unknown PXA soc type"
#endif
#endif /* !__MACH_PXA_REGS_H */

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#ifndef __MACH_PXA27X_REGS
#define __MACH_PXA27X_REGS
/* this file intentionally left blank */
#endif /* !__MACH_PXA27X_REGS */

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/*
* arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
*
* Taken from pxa-regs.h by Russell King
*
* Author: Nicolas Pitre
* Copyright: MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PXA2XX_REGS_H
#define __PXA2XX_REGS_H
#include <mach/hardware.h>
/*
* PXA Chip selects
*/
#define PXA_CS0_PHYS 0x00000000
#define PXA_CS1_PHYS 0x04000000
#define PXA_CS2_PHYS 0x08000000
#define PXA_CS3_PHYS 0x0C000000
#define PXA_CS4_PHYS 0x10000000
#define PXA_CS5_PHYS 0x14000000
/*
* Memory controller
*/
#define MDCNFG_OFFSET 0x00000000
#define MDREFR_OFFSET 0x00000004
#define MSC0_OFFSET 0x00000008
#define MSC1_OFFSET 0x0000000C
#define MSC2_OFFSET 0x00000010
#define MECR_OFFSET 0x00000014
#define SXCNFG_OFFSET 0x0000001C
#define FLYCNFG_OFFSET 0x00000020
#define MCMEM0_OFFSET 0x00000028
#define MCMEM1_OFFSET 0x0000002C
#define MCATT0_OFFSET 0x00000030
#define MCATT1_OFFSET 0x00000034
#define MCIO0_OFFSET 0x00000038
#define MCIO1_OFFSET 0x0000003C
#define MDMRS_OFFSET 0x00000040
#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
/*
* More handy macros for PCMCIA
*
* Arg is socket number
*/
#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
/* MECR register defines */
#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
/*
* Power Manager
*/
#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */
#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */
#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */
#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
#define PCMD(x) __REG2(0x40F00080, (x)<<2)
#define PCMD0 __REG(0x40F00080 + 0 * 4)
#define PCMD1 __REG(0x40F00080 + 1 * 4)
#define PCMD2 __REG(0x40F00080 + 2 * 4)
#define PCMD3 __REG(0x40F00080 + 3 * 4)
#define PCMD4 __REG(0x40F00080 + 4 * 4)
#define PCMD5 __REG(0x40F00080 + 5 * 4)
#define PCMD6 __REG(0x40F00080 + 6 * 4)
#define PCMD7 __REG(0x40F00080 + 7 * 4)
#define PCMD8 __REG(0x40F00080 + 8 * 4)
#define PCMD9 __REG(0x40F00080 + 9 * 4)
#define PCMD10 __REG(0x40F00080 + 10 * 4)
#define PCMD11 __REG(0x40F00080 + 11 * 4)
#define PCMD12 __REG(0x40F00080 + 12 * 4)
#define PCMD13 __REG(0x40F00080 + 13 * 4)
#define PCMD14 __REG(0x40F00080 + 14 * 4)
#define PCMD15 __REG(0x40F00080 + 15 * 4)
#define PCMD16 __REG(0x40F00080 + 16 * 4)
#define PCMD17 __REG(0x40F00080 + 17 * 4)
#define PCMD18 __REG(0x40F00080 + 18 * 4)
#define PCMD19 __REG(0x40F00080 + 19 * 4)
#define PCMD20 __REG(0x40F00080 + 20 * 4)
#define PCMD21 __REG(0x40F00080 + 21 * 4)
#define PCMD22 __REG(0x40F00080 + 22 * 4)
#define PCMD23 __REG(0x40F00080 + 23 * 4)
#define PCMD24 __REG(0x40F00080 + 24 * 4)
#define PCMD25 __REG(0x40F00080 + 25 * 4)
#define PCMD26 __REG(0x40F00080 + 26 * 4)
#define PCMD27 __REG(0x40F00080 + 27 * 4)
#define PCMD28 __REG(0x40F00080 + 28 * 4)
#define PCMD29 __REG(0x40F00080 + 29 * 4)
#define PCMD30 __REG(0x40F00080 + 30 * 4)
#define PCMD31 __REG(0x40F00080 + 31 * 4)
#define PCMD_MBC (1<<12)
#define PCMD_DCE (1<<11)
#define PCMD_LC (1<<10)
/* FIXME: PCMD_SQC need be checked. */
#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
bit 9 should be 0 all day. */
#define PVCR_VCSA (0x1<<14)
#define PVCR_CommandDelay (0xf80)
#define PCFR_PI2C_EN (0x1 << 6)
#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
#define PSSR_RDH (1 << 5) /* Read Disable Hold */
#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
#define PSSR_STS (1 << 3) /* Standby Mode Status */
#define PSSR_VFS (1 << 2) /* VDD Fault Status */
#define PSSR_BFS (1 << 1) /* Battery Fault Status */
#define PSSR_SSS (1 << 0) /* Software Sleep Status */
#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
#define PCFR_RO (1 << 15) /* RDH Override */
#define PCFR_PO (1 << 14) /* PH Override */
#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
#define RCSR_GPR (1 << 3) /* GPIO Reset */
#define RCSR_SMR (1 << 2) /* Sleep Mode */
#define RCSR_WDR (1 << 1) /* Watchdog Reset */
#define RCSR_HWR (1 << 0) /* Hardware Reset */
#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
#define PWER_GPIO0 PWER_GPIO(0) /* GPIO [0] wake-up enable */
#define PWER_GPIO1 PWER_GPIO(1) /* GPIO [1] wake-up enable */
#define PWER_GPIO2 PWER_GPIO(2) /* GPIO [2] wake-up enable */
#define PWER_GPIO3 PWER_GPIO(3) /* GPIO [3] wake-up enable */
#define PWER_GPIO4 PWER_GPIO(4) /* GPIO [4] wake-up enable */
#define PWER_GPIO5 PWER_GPIO(5) /* GPIO [5] wake-up enable */
#define PWER_GPIO6 PWER_GPIO(6) /* GPIO [6] wake-up enable */
#define PWER_GPIO7 PWER_GPIO(7) /* GPIO [7] wake-up enable */
#define PWER_GPIO8 PWER_GPIO(8) /* GPIO [8] wake-up enable */
#define PWER_GPIO9 PWER_GPIO(9) /* GPIO [9] wake-up enable */
#define PWER_GPIO10 PWER_GPIO(10) /* GPIO [10] wake-up enable */
#define PWER_GPIO11 PWER_GPIO(11) /* GPIO [11] wake-up enable */
#define PWER_GPIO12 PWER_GPIO(12) /* GPIO [12] wake-up enable */
#define PWER_GPIO13 PWER_GPIO(13) /* GPIO [13] wake-up enable */
#define PWER_GPIO14 PWER_GPIO(14) /* GPIO [14] wake-up enable */
#define PWER_GPIO15 PWER_GPIO(15) /* GPIO [15] wake-up enable */
#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
/*
* PXA2xx specific Core clock definitions
*/
#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
#define CKEN __REG(0x41300004) /* Clock Enable Register */
#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
#define CKEN_AC97CONF (1 << 31) /* AC97 Controller Configuration */
#define CKEN_CAMERA (1 << 24) /* Camera Interface Clock Enable */
#define CKEN_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
#define CKEN_MEMC (1 << 22) /* Memory Controller Clock Enable */
#define CKEN_MEMSTK (1 << 21) /* Memory Stick Host Controller */
#define CKEN_IM (1 << 20) /* Internal Memory Clock Enable */
#define CKEN_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
#define CKEN_USIM (1 << 18) /* USIM Unit Clock Enable */
#define CKEN_MSL (1 << 17) /* MSL Unit Clock Enable */
#define CKEN_LCD (1 << 16) /* LCD Unit Clock Enable */
#define CKEN_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */
#define CKEN_I2C (1 << 14) /* I2C Unit Clock Enable */
#define CKEN_FICP (1 << 13) /* FICP Unit Clock Enable */
#define CKEN_MMC (1 << 12) /* MMC Unit Clock Enable */
#define CKEN_USB (1 << 11) /* USB Unit Clock Enable */
#define CKEN_ASSP (1 << 10) /* ASSP (1 << SSP3) Clock Enable */
#define CKEN_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
#define CKEN_OSTIMER (1 << 9) /* OS Timer Unit Clock Enable */
#define CKEN_NSSP (1 << 9) /* NSSP (1 << SSP2) Clock Enable */
#define CKEN_I2S (1 << 8) /* I2S Unit Clock Enable */
#define CKEN_BTUART (1 << 7) /* BTUART Unit Clock Enable */
#define CKEN_FFUART (1 << 6) /* FFUART Unit Clock Enable */
#define CKEN_STUART (1 << 5) /* STUART Unit Clock Enable */
#define CKEN_HWUART (1 << 4) /* HWUART Unit Clock Enable */
#define CKEN_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
#define CKEN_SSP (1 << 3) /* SSP Unit Clock Enable */
#define CKEN_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */
#define CKEN_AC97 (1 << 2) /* AC97 Unit Clock Enable */
#define CKEN_PWM1 (1 << 1) /* PWM1 Clock Enable */
#define CKEN_PWM0 (1 << 0) /* PWM0 Clock Enable */
#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
/* PWRMODE register M field values */
#define PWRMODE_IDLE 0x1
#define PWRMODE_STANDBY 0x2
#define PWRMODE_SLEEP 0x3
#define PWRMODE_DEEPSLEEP 0x7
#endif

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#ifndef __ASM_MACH_REGS_INTC_H
#define __ASM_MACH_REGS_INTC_H
#include <mach/hardware.h>
/*
* Interrupt Controller
*/
#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */
#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
#define ICIP3 __REG(0x40D00130) /* Interrupt Controller IRQ Pending Register 3 */
#define ICMR3 __REG(0x40D00134) /* Interrupt Controller Mask Register 3 */
#define ICLR3 __REG(0x40D00138) /* Interrupt Controller Level Register 3 */
#define ICFP3 __REG(0x40D0013C) /* Interrupt Controller FIQ Pending Register 3 */
#define ICPR3 __REG(0x40D00140) /* Interrupt Controller Pending Register 3 */
#define IPR(x) __REG(0x40D0001C + (x < 32 ? (x << 2) \
: (x < 64 ? (0x94 + ((x - 32) << 2)) \
: (0x128 + ((x - 64) << 2)))))
#endif /* __ASM_MACH_REGS_INTC_H */

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#ifndef __ASM_MACH_REGS_OST_H
#define __ASM_MACH_REGS_OST_H
#include <mach/hardware.h>
/*
* OS Timer & Match Registers
*/
#define OSMR0 __REG(0x40A00000) /* */
#define OSMR1 __REG(0x40A00004) /* */
#define OSMR2 __REG(0x40A00008) /* */
#define OSMR3 __REG(0x40A0000C) /* */
#define OSMR4 __REG(0x40A00080) /* */
#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
#define OMCR4 __REG(0x40A000C0) /* */
#define OSSR __REG(0x40A00014) /* OS Timer Status Register */
#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
#define OSSR_M3 (1 << 3) /* Match status channel 3 */
#define OSSR_M2 (1 << 2) /* Match status channel 2 */
#define OSSR_M1 (1 << 1) /* Match status channel 1 */
#define OSSR_M0 (1 << 0) /* Match status channel 0 */
#define OWER_WME (1 << 0) /* Watchdog Match Enable */
#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
#endif /* __ASM_MACH_REGS_OST_H */

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/*
* arch/arm/mach-pxa/include/mach/udc_pxa2xx.h
*
* This supports machine-specific differences in how the PXA2xx
* USB Device Controller (UDC) is wired.
*
* It is set in linux/arch/arm/mach-pxa/<machine>.c or in
* linux/arch/mach-ixp4xx/<machine>.c and used in
* the probe routine of linux/drivers/usb/gadget/pxa2xx_udc.c
*/
struct pxa2xx_udc_mach_info {
int (*udc_is_connected)(void); /* do we see host? */
void (*udc_command)(int cmd);
#define PXA2XX_UDC_CMD_CONNECT 0 /* let host see us */
#define PXA2XX_UDC_CMD_DISCONNECT 1 /* so host won't see us */
/* Boards following the design guidelines in the developer's manual,
* with on-chip GPIOs not Lubbock's weird hardware, can have a sane
* VBUS IRQ and omit the methods above. Store the GPIO number
* here. Note that sometimes the signals go through inverters...
*/
bool gpio_pullup_inverted;
int gpio_pullup; /* high == pullup activated */
};

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#ifndef __PLAT_GPIO_H
#define __PLAT_GPIO_H
#include <mach/gpio.h>
/*
* We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
* one set of registers. The register offsets are organized below:
*
* GPLR GPDR GPSR GPCR GRER GFER GEDR
* BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
* BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
* BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
*
* BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
* BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
* BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
*
* NOTE:
* BANK 3 is only available on PXA27x and later processors.
* BANK 4 and 5 are only available on PXA935
*/
#define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n))
#define GPLR_OFFSET 0x00
#define GPDR_OFFSET 0x0C
#define GPSR_OFFSET 0x18
#define GPCR_OFFSET 0x24
#define GRER_OFFSET 0x30
#define GFER_OFFSET 0x3C
#define GEDR_OFFSET 0x48
static inline int gpio_get_value(unsigned gpio)
{
return GPLR(gpio) & GPIO_bit(gpio);
}
static inline void gpio_set_value(unsigned gpio, int value)
{
if (value)
GPSR(gpio) = GPIO_bit(gpio);
else
GPCR(gpio) = GPIO_bit(gpio);
}
static inline int gpio_direction_input(unsigned gpio)
{
if (__gpio_is_inverted(gpio))
GPDR(gpio) |= GPIO_bit(gpio);
else
GPDR(gpio) &= ~GPIO_bit(gpio);
return 0;
}
static inline int gpio_direction_output(unsigned gpio, int value)
{
gpio_set_value(gpio, value);
if (__gpio_is_inverted(gpio))
GPDR(gpio) &= ~GPIO_bit(gpio);
else
GPDR(gpio) |= GPIO_bit(gpio);
return 0;
}
/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
* Those cases currently cause holes in the GPIO number space, the
* actual number of the last GPIO is recorded by 'pxa_last_gpio'.
*/
extern int pxa_last_gpio;
extern int pxa_init_gpio(int start, int end);
#endif /* __PLAT_GPIO_H */

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/*
* arch/arm/plat-pxa/include/plat/mfp.h
*
* Common Multi-Function Pin Definitions
*
* Copyright (C) 2007 Marvell International Ltd.
*
* 2007-8-21: eric miao <eric.miao@marvell.com>
* initial version
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_PLAT_MFP_H
#define __ASM_PLAT_MFP_H
#define mfp_to_gpio(m) ((m) % 256)
/* list of all the configurable MFP pins */
enum {
MFP_PIN_INVALID = -1,
MFP_PIN_GPIO0 = 0,
MFP_PIN_GPIO1,
MFP_PIN_GPIO2,
MFP_PIN_GPIO3,
MFP_PIN_GPIO4,
MFP_PIN_GPIO5,
MFP_PIN_GPIO6,
MFP_PIN_GPIO7,
MFP_PIN_GPIO8,
MFP_PIN_GPIO9,
MFP_PIN_GPIO10,
MFP_PIN_GPIO11,
MFP_PIN_GPIO12,
MFP_PIN_GPIO13,
MFP_PIN_GPIO14,
MFP_PIN_GPIO15,
MFP_PIN_GPIO16,
MFP_PIN_GPIO17,
MFP_PIN_GPIO18,
MFP_PIN_GPIO19,
MFP_PIN_GPIO20,
MFP_PIN_GPIO21,
MFP_PIN_GPIO22,
MFP_PIN_GPIO23,
MFP_PIN_GPIO24,
MFP_PIN_GPIO25,
MFP_PIN_GPIO26,
MFP_PIN_GPIO27,
MFP_PIN_GPIO28,
MFP_PIN_GPIO29,
MFP_PIN_GPIO30,
MFP_PIN_GPIO31,
MFP_PIN_GPIO32,
MFP_PIN_GPIO33,
MFP_PIN_GPIO34,
MFP_PIN_GPIO35,
MFP_PIN_GPIO36,
MFP_PIN_GPIO37,
MFP_PIN_GPIO38,
MFP_PIN_GPIO39,
MFP_PIN_GPIO40,
MFP_PIN_GPIO41,
MFP_PIN_GPIO42,
MFP_PIN_GPIO43,
MFP_PIN_GPIO44,
MFP_PIN_GPIO45,
MFP_PIN_GPIO46,
MFP_PIN_GPIO47,
MFP_PIN_GPIO48,
MFP_PIN_GPIO49,
MFP_PIN_GPIO50,
MFP_PIN_GPIO51,
MFP_PIN_GPIO52,
MFP_PIN_GPIO53,
MFP_PIN_GPIO54,
MFP_PIN_GPIO55,
MFP_PIN_GPIO56,
MFP_PIN_GPIO57,
MFP_PIN_GPIO58,
MFP_PIN_GPIO59,
MFP_PIN_GPIO60,
MFP_PIN_GPIO61,
MFP_PIN_GPIO62,
MFP_PIN_GPIO63,
MFP_PIN_GPIO64,
MFP_PIN_GPIO65,
MFP_PIN_GPIO66,
MFP_PIN_GPIO67,
MFP_PIN_GPIO68,
MFP_PIN_GPIO69,
MFP_PIN_GPIO70,
MFP_PIN_GPIO71,
MFP_PIN_GPIO72,
MFP_PIN_GPIO73,
MFP_PIN_GPIO74,
MFP_PIN_GPIO75,
MFP_PIN_GPIO76,
MFP_PIN_GPIO77,
MFP_PIN_GPIO78,
MFP_PIN_GPIO79,
MFP_PIN_GPIO80,
MFP_PIN_GPIO81,
MFP_PIN_GPIO82,
MFP_PIN_GPIO83,
MFP_PIN_GPIO84,
MFP_PIN_GPIO85,
MFP_PIN_GPIO86,
MFP_PIN_GPIO87,
MFP_PIN_GPIO88,
MFP_PIN_GPIO89,
MFP_PIN_GPIO90,
MFP_PIN_GPIO91,
MFP_PIN_GPIO92,
MFP_PIN_GPIO93,
MFP_PIN_GPIO94,
MFP_PIN_GPIO95,
MFP_PIN_GPIO96,
MFP_PIN_GPIO97,
MFP_PIN_GPIO98,
MFP_PIN_GPIO99,
MFP_PIN_GPIO100,
MFP_PIN_GPIO101,
MFP_PIN_GPIO102,
MFP_PIN_GPIO103,
MFP_PIN_GPIO104,
MFP_PIN_GPIO105,
MFP_PIN_GPIO106,
MFP_PIN_GPIO107,
MFP_PIN_GPIO108,
MFP_PIN_GPIO109,
MFP_PIN_GPIO110,
MFP_PIN_GPIO111,
MFP_PIN_GPIO112,
MFP_PIN_GPIO113,
MFP_PIN_GPIO114,
MFP_PIN_GPIO115,
MFP_PIN_GPIO116,
MFP_PIN_GPIO117,
MFP_PIN_GPIO118,
MFP_PIN_GPIO119,
MFP_PIN_GPIO120,
MFP_PIN_GPIO121,
MFP_PIN_GPIO122,
MFP_PIN_GPIO123,
MFP_PIN_GPIO124,
MFP_PIN_GPIO125,
MFP_PIN_GPIO126,
MFP_PIN_GPIO127,
MFP_PIN_GPIO128,
MFP_PIN_GPIO129,
MFP_PIN_GPIO130,
MFP_PIN_GPIO131,
MFP_PIN_GPIO132,
MFP_PIN_GPIO133,
MFP_PIN_GPIO134,
MFP_PIN_GPIO135,
MFP_PIN_GPIO136,
MFP_PIN_GPIO137,
MFP_PIN_GPIO138,
MFP_PIN_GPIO139,
MFP_PIN_GPIO140,
MFP_PIN_GPIO141,
MFP_PIN_GPIO142,
MFP_PIN_GPIO143,
MFP_PIN_GPIO144,
MFP_PIN_GPIO145,
MFP_PIN_GPIO146,
MFP_PIN_GPIO147,
MFP_PIN_GPIO148,
MFP_PIN_GPIO149,
MFP_PIN_GPIO150,
MFP_PIN_GPIO151,
MFP_PIN_GPIO152,
MFP_PIN_GPIO153,
MFP_PIN_GPIO154,
MFP_PIN_GPIO155,
MFP_PIN_GPIO156,
MFP_PIN_GPIO157,
MFP_PIN_GPIO158,
MFP_PIN_GPIO159,
MFP_PIN_GPIO160,
MFP_PIN_GPIO161,
MFP_PIN_GPIO162,
MFP_PIN_GPIO163,
MFP_PIN_GPIO164,
MFP_PIN_GPIO165,
MFP_PIN_GPIO166,
MFP_PIN_GPIO167,
MFP_PIN_GPIO168,
MFP_PIN_GPIO169,
MFP_PIN_GPIO170,
MFP_PIN_GPIO171,
MFP_PIN_GPIO172,
MFP_PIN_GPIO173,
MFP_PIN_GPIO174,
MFP_PIN_GPIO175,
MFP_PIN_GPIO176,
MFP_PIN_GPIO177,
MFP_PIN_GPIO178,
MFP_PIN_GPIO179,
MFP_PIN_GPIO180,
MFP_PIN_GPIO181,
MFP_PIN_GPIO182,
MFP_PIN_GPIO183,
MFP_PIN_GPIO184,
MFP_PIN_GPIO185,
MFP_PIN_GPIO186,
MFP_PIN_GPIO187,
MFP_PIN_GPIO188,
MFP_PIN_GPIO189,
MFP_PIN_GPIO190,
MFP_PIN_GPIO191,
MFP_PIN_GPIO255 = 255,
MFP_PIN_GPIO0_2,
MFP_PIN_GPIO1_2,
MFP_PIN_GPIO2_2,
MFP_PIN_GPIO3_2,
MFP_PIN_GPIO4_2,
MFP_PIN_GPIO5_2,
MFP_PIN_GPIO6_2,
MFP_PIN_GPIO7_2,
MFP_PIN_GPIO8_2,
MFP_PIN_GPIO9_2,
MFP_PIN_GPIO10_2,
MFP_PIN_GPIO11_2,
MFP_PIN_GPIO12_2,
MFP_PIN_GPIO13_2,
MFP_PIN_GPIO14_2,
MFP_PIN_GPIO15_2,
MFP_PIN_GPIO16_2,
MFP_PIN_GPIO17_2,
MFP_PIN_ULPI_STP,
MFP_PIN_ULPI_NXT,
MFP_PIN_ULPI_DIR,
MFP_PIN_nXCVREN,
MFP_PIN_DF_CLE_nOE,
MFP_PIN_DF_nADV1_ALE,
MFP_PIN_DF_SCLK_E,
MFP_PIN_DF_SCLK_S,
MFP_PIN_nBE0,
MFP_PIN_nBE1,
MFP_PIN_DF_nADV2_ALE,
MFP_PIN_DF_INT_RnB,
MFP_PIN_DF_nCS0,
MFP_PIN_DF_nCS1,
MFP_PIN_nLUA,
MFP_PIN_nLLA,
MFP_PIN_DF_nWE,
MFP_PIN_DF_ALE_nWE,
MFP_PIN_DF_nRE_nOE,
MFP_PIN_DF_ADDR0,
MFP_PIN_DF_ADDR1,
MFP_PIN_DF_ADDR2,
MFP_PIN_DF_ADDR3,
MFP_PIN_DF_IO0,
MFP_PIN_DF_IO1,
MFP_PIN_DF_IO2,
MFP_PIN_DF_IO3,
MFP_PIN_DF_IO4,
MFP_PIN_DF_IO5,
MFP_PIN_DF_IO6,
MFP_PIN_DF_IO7,
MFP_PIN_DF_IO8,
MFP_PIN_DF_IO9,
MFP_PIN_DF_IO10,
MFP_PIN_DF_IO11,
MFP_PIN_DF_IO12,
MFP_PIN_DF_IO13,
MFP_PIN_DF_IO14,
MFP_PIN_DF_IO15,
MFP_PIN_DF_nCS0_SM_nCS2,
MFP_PIN_DF_nCS1_SM_nCS3,
MFP_PIN_SM_nCS0,
MFP_PIN_SM_nCS1,
MFP_PIN_DF_WEn,
MFP_PIN_DF_REn,
MFP_PIN_DF_CLE_SM_OEn,
MFP_PIN_DF_ALE_SM_WEn,
MFP_PIN_DF_RDY0,
MFP_PIN_DF_RDY1,
MFP_PIN_SM_SCLK,
MFP_PIN_SM_BE0,
MFP_PIN_SM_BE1,
MFP_PIN_SM_ADV,
MFP_PIN_SM_ADVMUX,
MFP_PIN_SM_RDY,
MFP_PIN_MMC1_DAT7,
MFP_PIN_MMC1_DAT6,
MFP_PIN_MMC1_DAT5,
MFP_PIN_MMC1_DAT4,
MFP_PIN_MMC1_DAT3,
MFP_PIN_MMC1_DAT2,
MFP_PIN_MMC1_DAT1,
MFP_PIN_MMC1_DAT0,
MFP_PIN_MMC1_CMD,
MFP_PIN_MMC1_CLK,
MFP_PIN_MMC1_CD,
MFP_PIN_MMC1_WP,
/* additional pins on PXA930 */
MFP_PIN_GSIM_UIO,
MFP_PIN_GSIM_UCLK,
MFP_PIN_GSIM_UDET,
MFP_PIN_GSIM_nURST,
MFP_PIN_PMIC_INT,
MFP_PIN_RDY,
MFP_PIN_MAX,
};
/*
* a possible MFP configuration is represented by a 32-bit integer
*
* bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
* bit 10..12 - Alternate Function Selection
* bit 13..15 - Drive Strength
* bit 16..18 - Low Power Mode State
* bit 19..20 - Low Power Mode Edge Detection
* bit 21..22 - Run Mode Pull State
*
* to facilitate the definition, the following macros are provided
*
* MFP_CFG_DEFAULT - default MFP configuration value, with
* alternate function = 0,
* drive strength = fast 3mA (MFP_DS03X)
* low power mode = default
* edge detection = none
*
* MFP_CFG - default MFPR value with alternate function
* MFP_CFG_DRV - default MFPR value with alternate function and
* pin drive strength
* MFP_CFG_LPM - default MFPR value with alternate function and
* low power mode
* MFP_CFG_X - default MFPR value with alternate function,
* pin drive strength and low power mode
*/
typedef unsigned long mfp_cfg_t;
#define MFP_PIN(x) ((x) & 0x3ff)
#define MFP_AF0 (0x0 << 10)
#define MFP_AF1 (0x1 << 10)
#define MFP_AF2 (0x2 << 10)
#define MFP_AF3 (0x3 << 10)
#define MFP_AF4 (0x4 << 10)
#define MFP_AF5 (0x5 << 10)
#define MFP_AF6 (0x6 << 10)
#define MFP_AF7 (0x7 << 10)
#define MFP_AF_MASK (0x7 << 10)
#define MFP_AF(x) (((x) >> 10) & 0x7)
#define MFP_DS01X (0x0 << 13)
#define MFP_DS02X (0x1 << 13)
#define MFP_DS03X (0x2 << 13)
#define MFP_DS04X (0x3 << 13)
#define MFP_DS06X (0x4 << 13)
#define MFP_DS08X (0x5 << 13)
#define MFP_DS10X (0x6 << 13)
#define MFP_DS13X (0x7 << 13)
#define MFP_DS_MASK (0x7 << 13)
#define MFP_DS(x) (((x) >> 13) & 0x7)
#define MFP_LPM_DEFAULT (0x0 << 16)
#define MFP_LPM_DRIVE_LOW (0x1 << 16)
#define MFP_LPM_DRIVE_HIGH (0x2 << 16)
#define MFP_LPM_PULL_LOW (0x3 << 16)
#define MFP_LPM_PULL_HIGH (0x4 << 16)
#define MFP_LPM_FLOAT (0x5 << 16)
#define MFP_LPM_INPUT (0x6 << 16)
#define MFP_LPM_STATE_MASK (0x7 << 16)
#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7)
#define MFP_LPM_EDGE_NONE (0x0 << 19)
#define MFP_LPM_EDGE_RISE (0x1 << 19)
#define MFP_LPM_EDGE_FALL (0x2 << 19)
#define MFP_LPM_EDGE_BOTH (0x3 << 19)
#define MFP_LPM_EDGE_MASK (0x3 << 19)
#define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3)
#define MFP_PULL_NONE (0x0 << 21)
#define MFP_PULL_LOW (0x1 << 21)
#define MFP_PULL_HIGH (0x2 << 21)
#define MFP_PULL_BOTH (0x3 << 21)
#define MFP_PULL_FLOAT (0x4 << 21)
#define MFP_PULL_MASK (0x7 << 21)
#define MFP_PULL(x) (((x) >> 21) & 0x7)
#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\
MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
#define MFP_CFG(pin, af) \
((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\
(MFP_PIN(MFP_PIN_##pin) | MFP_##af))
#define MFP_CFG_DRV(pin, af, drv) \
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\
(MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
#define MFP_CFG_LPM(pin, af, lpm) \
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\
(MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
#define MFP_CFG_X(pin, af, drv, lpm) \
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
(MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
#if defined(CONFIG_PXA3xx) || defined(CONFIG_ARCH_MMP)
/*
* each MFP pin will have a MFPR register, since the offset of the
* register varies between processors, the processor specific code
* should initialize the pin offsets by mfp_init()
*
* mfp_init_base() - accepts a virtual base for all MFPR registers and
* initialize the MFP table to a default state
*
* mfp_init_addr() - accepts a table of "mfp_addr_map" structure, which
* represents a range of MFP pins from "start" to "end", with the offset
* begining at "offset", to define a single pin, let "end" = -1.
*
* use
*
* MFP_ADDR_X() to define a range of pins
* MFP_ADDR() to define a single pin
* MFP_ADDR_END to signal the end of pin offset definitions
*/
struct mfp_addr_map {
unsigned int start;
unsigned int end;
unsigned long offset;
};
#define MFP_ADDR_X(start, end, offset) \
{ MFP_PIN_##start, MFP_PIN_##end, offset }
#define MFP_ADDR(pin, offset) \
{ MFP_PIN_##pin, -1, offset }
#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
void __init mfp_init_base(unsigned long mfpr_base);
void __init mfp_init_addr(struct mfp_addr_map *map);
/*
* mfp_{read, write}() - for direct read/write access to the MFPR register
* mfp_config() - for configuring a group of MFPR registers
* mfp_config_lpm() - configuring all low power MFPR registers for suspend
* mfp_config_run() - configuring all run time MFPR registers after resume
*/
unsigned long mfp_read(int mfp);
void mfp_write(int mfp, unsigned long mfpr_val);
void mfp_config(unsigned long *mfp_cfgs, int num);
void mfp_config_run(void);
void mfp_config_lpm(void);
#endif /* CONFIG_PXA3xx || CONFIG_ARCH_MMP */
#endif /* __ASM_PLAT_MFP_H */

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/*
* linux/arch/arm/mach-pxa/mfp-pxa2xx.c
*
* PXA2xx pin mux configuration support
*
* The GPIOs on PXA2xx can be configured as one of many alternate
* functions, this is by concept samilar to the MFP configuration
* on PXA3xx, what's more important, the low power pin state and
* wakeup detection are also supported by the same framework.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <common.h>
#include <errno.h>
#include <init.h>
#include <mach/gpio.h>
#include <mach/hardware.h>
#include <mach/mfp-pxa2xx.h>
#include <mach/pxa-regs.h>
#define PGSR(x) __REG2(0x40F00020, (x) << 2)
#define __GAFR(u, x) __REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3)
#define GAFR_L(x) __GAFR(0, x)
#define GAFR_U(x) __GAFR(1, x)
struct gpio_desc {
unsigned valid:1;
unsigned dir_inverted:1;
unsigned long config;
};
static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1];
static unsigned long gpdr_lpm[4];
static int __mfp_config_gpio(unsigned gpio, unsigned long c)
{
unsigned long gafr, mask = GPIO_bit(gpio);
int bank = gpio_to_bank(gpio);
int uorl = !!(gpio & 0x10); /* GAFRx_U or GAFRx_L ? */
int shft = (gpio & 0xf) << 1;
int fn = MFP_AF(c);
int is_out = (c & MFP_DIR_OUT) ? 1 : 0;
if (fn > 3)
return -EINVAL;
/* alternate function and direction at run-time */
gafr = (uorl == 0) ? GAFR_L(bank) : GAFR_U(bank);
gafr = (gafr & ~(0x3 << shft)) | (fn << shft);
if (uorl == 0)
GAFR_L(bank) = gafr;
else
GAFR_U(bank) = gafr;
if (is_out ^ gpio_desc[gpio].dir_inverted)
GPDR(gpio) |= mask;
else
GPDR(gpio) &= ~mask;
/* alternate function and direction at low power mode */
switch (c & MFP_LPM_STATE_MASK) {
case MFP_LPM_DRIVE_HIGH:
PGSR(bank) |= mask;
is_out = 1;
break;
case MFP_LPM_DRIVE_LOW:
PGSR(bank) &= ~mask;
is_out = 1;
break;
case MFP_LPM_DEFAULT:
break;
default:
/* warning and fall through, treat as MFP_LPM_DEFAULT */
pr_warning("%s: GPIO%d: unsupported low power mode\n",
__func__, gpio);
break;
}
if (is_out ^ gpio_desc[gpio].dir_inverted)
gpdr_lpm[bank] |= mask;
else
gpdr_lpm[bank] &= ~mask;
return 0;
}
static inline int __mfp_validate(int mfp)
{
int gpio = mfp_to_gpio(mfp);
if ((mfp > MFP_PIN_GPIO127) || !gpio_desc[gpio].valid) {
pr_warning("%s: GPIO%d is invalid pin\n", __func__, gpio);
return -1;
}
return gpio;
}
void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num)
{
unsigned long *c;
int i, gpio;
for (i = 0, c = mfp_cfgs; i < num; i++, c++) {
gpio = __mfp_validate(MFP_PIN(*c));
if (gpio < 0)
continue;
gpio_desc[gpio].config = *c;
__mfp_config_gpio(gpio, *c);
}
}
void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm)
{
unsigned long c;
int gpio;
gpio = __mfp_validate(mfp);
if (gpio < 0)
return;
c = gpio_desc[gpio].config;
c = (c & ~MFP_LPM_STATE_MASK) | lpm;
__mfp_config_gpio(gpio, c);
}
static void __init pxa25x_mfp_init(void)
{
int i;
for (i = 0; i <= pxa_last_gpio; i++)
gpio_desc[i].valid = 1;
/* PXA26x has additional 4 GPIOs (86/87/88/89) which has the
* direction bit inverted in GPDR2. See PXA26x DM 4.1.1.
*/
for (i = 86; i <= pxa_last_gpio; i++)
gpio_desc[i].dir_inverted = 1;
}
static void __init pxa27x_mfp_init(void)
{
int i;
for (i = 0; i <= pxa_last_gpio; i++) {
/*
* skip GPIO2, 5, 6, 7, 8, they are not
* valid pins allow configuration
*/
if (i == 2 || i == 5 || i == 6 || i == 7 || i == 8)
continue;
gpio_desc[i].valid = 1;
}
}
static int __init pxa2xx_mfp_init(void)
{
int i;
if (!cpu_is_pxa2xx())
return 0;
if (cpu_is_pxa25x())
pxa25x_mfp_init();
if (cpu_is_pxa27x()) {
pxa_init_gpio(2, 120);
pxa27x_mfp_init();
}
/* clear RDH bit to enable GPIO receivers after reset/sleep exit */
PSSR = PSSR_RDH;
/* initialize gafr_run[], pgsr_lpm[] from existing values */
for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++)
gpdr_lpm[i] = GPDR(i * 32);
return 0;
}
postcore_initcall(pxa2xx_mfp_init);

20
arch/arm/mach-pxa/speed-pxa27x.c Normal file
View File

@ -0,0 +1,20 @@
/*
* clock.h - implementation of the PXA clock functions
*
* Copyright (C) 2010 by Marc Kleine-Budde <mkl@pengutronix.de>
*
* This file is released under the GPLv2
*
*/
#include <common.h>
#include <mach/clock.h>
#include <mach/pxa-regs.h>
/* Crystal clock: 13MHz */
#define BASE_CLK 13000000
unsigned long pxa_get_uartclk(void)
{
return 14857000;
}

473
arch/arm/tools/mach-types
View File

@ -12,7 +12,7 @@
#
# http://www.arm.linux.org.uk/developer/machines/?action=new
#
# Last update: Wed Mar 30 09:36:58 2011
# Last update: Tue Dec 6 15:54:16 2011
#
# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
#
@ -1319,6 +1319,7 @@ mistral MACH_MISTRAL MISTRAL 1315
msm MACH_MSM MSM 1316
ct5910 MACH_CT5910 CT5910 1317
ct5912 MACH_CT5912 CT5912 1318
argonst_mp MACH_HYNET_INE HYNET_INE 1319
hynet_app MACH_HYNET_APP HYNET_APP 1320
msm7200 MACH_MSM7200 MSM7200 1321
msm7600 MACH_MSM7600 MSM7600 1322
@ -1557,7 +1558,7 @@ otter MACH_OTTER OTTER 1561
davinci_ldk MACH_DAVINCI_LDK DAVINCI_LDK 1562
phreedom MACH_PHREEDOM PHREEDOM 1563
sg310 MACH_SG310 SG310 1564
ts_x09 MACH_TS209 TS209 1565
ts209 MACH_TS209 TS209 1565
at91cap9adk MACH_AT91CAP9ADK AT91CAP9ADK 1566
tion9315 MACH_TION9315 TION9315 1567
mast MACH_MAST MAST 1568
@ -1960,7 +1961,7 @@ ethernut5 MACH_ETHERNUT5 ETHERNUT5 1971
arm11 MACH_ARM11 ARM11 1972
cpuat9260 MACH_CPUAT9260 CPUAT9260 1973
cpupxa255 MACH_CPUPXA255 CPUPXA255 1974
eukrea_cpuimx27 MACH_CPUIMX27 CPUIMX27 1975
eukrea_cpuimx27 MACH_EUKREA_CPUIMX27 EUKREA_CPUIMX27 1975
cheflux MACH_CHEFLUX CHEFLUX 1976
eb_cpux9k2 MACH_EB_CPUX9K2 EB_CPUX9K2 1977
opcotec MACH_OPCOTEC OPCOTEC 1978
@ -2554,6 +2555,7 @@ magnolia2 MACH_MAGNOLIA2 MAGNOLIA2 2573
emxx MACH_EMXX EMXX 2574
outlaw MACH_OUTLAW OUTLAW 2575
riot_bei2 MACH_RIOT_BEI2 RIOT_BEI2 2576
riot_gx2 MACH_RIOT_VOX RIOT_VOX 2577
riot_x37 MACH_RIOT_X37 RIOT_X37 2578
mega25mx MACH_MEGA25MX MEGA25MX 2579
benzina2 MACH_BENZINA2 BENZINA2 2580
@ -2567,7 +2569,7 @@ p3600 MACH_P3600 P3600 2587
dlt2 MACH_DLT2 DLT2 2588
df3120 MACH_DF3120 DF3120 2589
ecucore_9g20 MACH_ECUCORE_9G20 ECUCORE_9G20 2590
nautel_lpc3240 MACH_NAUTEL_LPC3240 NAUTEL_LPC3240 2591
nautel_am35xx MACH_NAUTEL_LPC3240 NAUTEL_LPC3240 2591
glacier MACH_GLACIER GLACIER 2592
phrazer_bulldog MACH_PHRAZER_BULLDOG PHRAZER_BULLDOG 2593
omap3_bulldog MACH_OMAP3_BULLDOG OMAP3_BULLDOG 2594
@ -2599,7 +2601,7 @@ fujitsu_tvstbsoc1 MACH_FUJITSU_TVSTBSOC1 FUJITSU_TVSTBSOC1 2621
lexikon MACH_LEXIKON LEXIKON 2622
mini2440v2 MACH_MINI2440V2 MINI2440V2 2623
icontrol MACH_ICONTROL ICONTROL 2624
gplugd MACH_SHEEVAD SHEEVAD 2625
gplugd MACH_GPLUGD GPLUGD 2625
qsd8x50a_st1_1 MACH_QSD8X50A_ST1_1 QSD8X50A_ST1_1 2626
qsd8x50a_st1_5 MACH_QSD8X50A_ST1_5 QSD8X50A_ST1_5 2627
bee MACH_BEE BEE 2628
@ -2652,7 +2654,7 @@ htcpanther_cdma MACH_HTCPANTHER_CDMA HTCPANTHER_CDMA 2674
reb01 MACH_REB01 REB01 2675
aquila MACH_AQUILA AQUILA 2676
spark_sls_hw2 MACH_SPARK_SLS_HW2 SPARK_SLS_HW2 2677
sheeva_esata MACH_ESATA_SHEEVAPLUG ESATA_SHEEVAPLUG 2678
esata_sheevaplug MACH_ESATA_SHEEVAPLUG ESATA_SHEEVAPLUG 2678
msm7x30_surf MACH_MSM7X30_SURF MSM7X30_SURF 2679
micro2440 MACH_MICRO2440 MICRO2440 2680
am2440 MACH_AM2440 AM2440 2681
@ -2724,7 +2726,7 @@ vpnext_mpu MACH_VPNEXT_MPU VPNEXT_MPU 2747
bcmring_tablet_v1 MACH_BCMRING_TABLET_V1 BCMRING_TABLET_V1 2748
sgarm10 MACH_SGARM10 SGARM10 2749
cm_t3517 MACH_CM_T3517 CM_T3517 2750
omap3_cps MACH_OMAP3_CPS OMAP3_CPS 2751
dig297 MACH_OMAP3_CPS OMAP3_CPS 2751
axar1500_receiver MACH_AXAR1500_RECEIVER AXAR1500_RECEIVER 2752
wbd222 MACH_WBD222 WBD222 2753
mt65xx MACH_MT65XX MT65XX 2754
@ -2748,6 +2750,7 @@ oreo_controller MACH_OREO_CONTROLLER OREO_CONTROLLER 2773
kopin_models MACH_KOPIN_MODELS KOPIN_MODELS 2774
ttc_vision2 MACH_TTC_VISION2 TTC_VISION2 2775
cns3420vb MACH_CNS3420VB CNS3420VB 2776
lpc_evo MACH_LPC2 LPC2 2777
olympus MACH_OLYMPUS OLYMPUS 2778
vortex MACH_VORTEX VORTEX 2779
s5pc200 MACH_S5PC200 S5PC200 2780
@ -2789,8 +2792,8 @@ teton_bga MACH_TETON_BGA TETON_BGA 2816
snapper9g45 MACH_SNAPPER9G45 SNAPPER9G45 2817
tam3517 MACH_TAM3517 TAM3517 2818
pdc100 MACH_PDC100 PDC100 2819
eukrea_cpuimx25sd MACH_EUKREA_CPUIMX25 EUKREA_CPUIMX25 2820
eukrea_cpuimx35sd MACH_EUKREA_CPUIMX35 EUKREA_CPUIMX35 2821
eukrea_cpuimx25sd MACH_EUKREA_CPUIMX25SD EUKREA_CPUIMX25SD 2820
eukrea_cpuimx35sd MACH_EUKREA_CPUIMX35SD EUKREA_CPUIMX35SD 2821
eukrea_cpuimx51sd MACH_EUKREA_CPUIMX51SD EUKREA_CPUIMX51SD 2822
eukrea_cpuimx51 MACH_EUKREA_CPUIMX51 EUKREA_CPUIMX51 2823
p565 MACH_P565 P565 2824
@ -3018,6 +3021,7 @@ s5pc110_crespo MACH_S5PC110_CRESPO S5PC110_CRESPO 3052
controltek9g20 MACH_CONTROLTEK9G20 CONTROLTEK9G20 3053
tin307 MACH_TIN307 TIN307 3054
tin510 MACH_TIN510 TIN510 3055
ep3505 MACH_EP3517 EP3517 3056
bluecheese MACH_BLUECHEESE BLUECHEESE 3057
tem3x30 MACH_TEM3X30 TEM3X30 3058
harvest_desoto MACH_HARVEST_DESOTO HARVEST_DESOTO 3059
@ -3236,7 +3240,7 @@ omapl138_case_a3 MACH_OMAPL138_CASE_A3 OMAPL138_CASE_A3 3280
uemd MACH_UEMD UEMD 3281
ccwmx51mut MACH_CCWMX51MUT CCWMX51MUT 3282
rockhopper MACH_ROCKHOPPER ROCKHOPPER 3283
nookcolor MACH_NOOKCOLOR NOOKCOLOR 3284
encore MACH_ENCORE ENCORE 3284
hkdkc100 MACH_HKDKC100 HKDKC100 3285
ts42xx MACH_TS42XX TS42XX 3286
aebl MACH_AEBL AEBL 3287
@ -3247,9 +3251,9 @@ isc3 MACH_ISC3 ISC3 3291
rascal MACH_RASCAL RASCAL 3292
hrefv60 MACH_HREFV60 HREFV60 3293
tpt_2_0 MACH_TPT_2_0 TPT_2_0 3294
pyramid_td MACH_PYRAMID_TD PYRAMID_TD 3295
pydtd MACH_PYRAMID_TD PYRAMID_TD 3295
splendor MACH_SPLENDOR SPLENDOR 3296
guf_planet MACH_GUF_PLANET GUF_PLANET 3297
guf_vincell MACH_GUF_PLANET GUF_PLANET 3297
msm8x60_qt MACH_MSM8X60_QT MSM8X60_QT 3298
htc_hd_mini MACH_HTC_HD_MINI HTC_HD_MINI 3299
athene MACH_ATHENE ATHENE 3300
@ -3348,7 +3352,7 @@ geneva_b5 MACH_GENEVA_B5 GENEVA_B5 3393
spear1340 MACH_SPEAR1340 SPEAR1340 3394
rexmas MACH_REXMAS REXMAS 3395
msm8960_cdp MACH_MSM8960_CDP MSM8960_CDP 3396
msm8960_mdp MACH_MSM8960_MDP MSM8960_MDP 3397
msm8960_mtp MACH_MSM8960_MDP MSM8960_MDP 3397
msm8960_fluid MACH_MSM8960_FLUID MSM8960_FLUID 3398
msm8960_apq MACH_MSM8960_APQ MSM8960_APQ 3399
helios_v2 MACH_HELIOS_V2 HELIOS_V2 3400
@ -3396,3 +3400,446 @@ nuc740evb MACH_NUC740EVB NUC740EVB 3441
nuc745evb MACH_NUC745EVB NUC745EVB 3442
transcede MACH_TRANSCEDE TRANSCEDE 3443
mora MACH_MORA MORA 3444
nda_evm MACH_NDA_EVM NDA_EVM 3445
timu MACH_TIMU TIMU 3446
expressh MACH_EXPRESSH EXPRESSH 3447
veridis_a300 MACH_VERIDIS_A300 VERIDIS_A300 3448
dm368_leopard MACH_DM368_LEOPARD DM368_LEOPARD 3449
omap_mcop MACH_OMAP_MCOP OMAP_MCOP 3450
tritip MACH_TRITIP TRITIP 3451
sm1k MACH_SM1K SM1K 3452
monch MACH_MONCH MONCH 3453
curacao MACH_CURACAO CURACAO 3454
origen MACH_ORIGEN ORIGEN 3455
epc10 MACH_EPC10 EPC10 3456
sgh_i740 MACH_SGH_I740 SGH_I740 3457
tuna MACH_TUNA TUNA 3458
mx51_tulip MACH_MX51_TULIP MX51_TULIP 3459
mx51_aster7 MACH_MX51_ASTER7 MX51_ASTER7 3460
acro37xbrd MACH_ACRO37XBRD ACRO37XBRD 3461
elke MACH_ELKE ELKE 3462
sbc6000x MACH_SBC6000X SBC6000X 3463
r1801e MACH_R1801E R1801E 3464
h1600 MACH_H1600 H1600 3465
mini210 MACH_MINI210 MINI210 3466
mini8168 MACH_MINI8168 MINI8168 3467
pc7308 MACH_PC7308 PC7308 3468
ge863pro3 MACH_GE863 GE863 3469
kmm2m01 MACH_KMM2M01 KMM2M01 3470
mx51erebus MACH_MX51EREBUS MX51EREBUS 3471
wm8650refboard MACH_WM8650REFBOARD WM8650REFBOARD 3472
tuxrail MACH_TUXRAIL TUXRAIL 3473
arthur MACH_ARTHUR ARTHUR 3474
doorboy MACH_DOORBOY DOORBOY 3475
xarina MACH_XARINA XARINA 3476
roverx7 MACH_ROVERX7 ROVERX7 3477
sdvr MACH_SDVR SDVR 3478
acer_maya MACH_ACER_MAYA ACER_MAYA 3479
pico MACH_PICO PICO 3480
cwmx233 MACH_CWMX233 CWMX233 3481
cwam1808 MACH_CWAM1808 CWAM1808 3482
cwdm365 MACH_CWDM365 CWDM365 3483
mx51_moray MACH_MX51_MORAY MX51_MORAY 3484
thales_cbc MACH_THALES_CBC THALES_CBC 3485
bluepoint MACH_BLUEPOINT BLUEPOINT 3486
dir665 MACH_DIR665 DIR665 3487
acmerover1 MACH_ACMEROVER1 ACMEROVER1 3488
shooter_ct MACH_SHOOTER_CT SHOOTER_CT 3489
bliss MACH_BLISS BLISS 3490
blissc MACH_BLISSC BLISSC 3491
thales_adc MACH_THALES_ADC THALES_ADC 3492
ubisys_p9d_evp MACH_UBISYS_P9D_EVP UBISYS_P9D_EVP 3493
atdgp318 MACH_ATDGP318 ATDGP318 3494
dma210u MACH_DMA210U DMA210U 3495
em_t3 MACH_EM_T3 EM_T3 3496
htx3250 MACH_HTX3250 HTX3250 3497
g50 MACH_G50 G50 3498
eco5 MACH_ECO5 ECO5 3499
wintergrasp MACH_WINTERGRASP WINTERGRASP 3500
puro MACH_PURO PURO 3501
shooter_k MACH_SHOOTER_K SHOOTER_K 3502
nspire MACH_NSPIRE NSPIRE 3503
mickxx MACH_MICKXX MICKXX 3504
lxmb MACH_LXMB LXMB 3505
tmdxscbp6618x MACH_TMDXSCBP6616X TMDXSCBP6616X 3506
adam MACH_ADAM ADAM 3507
b1004 MACH_B1004 B1004 3508
oboea MACH_OBOEA OBOEA 3509
a1015 MACH_A1015 A1015 3510
robin_vbdt30 MACH_ROBIN_VBDT30 ROBIN_VBDT30 3511
tegra_enterprise MACH_TEGRA_ENTERPRISE TEGRA_ENTERPRISE 3512
rfl108200_mk10 MACH_RFL108200_MK10 RFL108200_MK10 3513
rfl108300_mk16 MACH_RFL108300_MK16 RFL108300_MK16 3514
rover_v7 MACH_ROVER_V7 ROVER_V7 3515
miphone MACH_MIPHONE MIPHONE 3516
femtobts MACH_FEMTOBTS FEMTOBTS 3517
monopoli MACH_MONOPOLI MONOPOLI 3518
boss MACH_BOSS BOSS 3519
davinci_dm368_vtam MACH_DAVINCI_DM368_VTAM DAVINCI_DM368_VTAM 3520
clcon MACH_CLCON CLCON 3521
nokia_rm696 MACH_NOKIA_RM696 NOKIA_RM696 3522
tahiti MACH_TAHITI TAHITI 3523
fighter MACH_FIGHTER FIGHTER 3524
sgh_i710 MACH_SGH_I710 SGH_I710 3525
integreproscb MACH_INTEGREPROSCB INTEGREPROSCB 3526
monza MACH_MONZA MONZA 3527
calimain MACH_CALIMAIN CALIMAIN 3528
mx6q_sabreauto MACH_MX6Q_SABREAUTO MX6Q_SABREAUTO 3529
gma01x MACH_GMA01X GMA01X 3530
sbc51 MACH_SBC51 SBC51 3531
fit MACH_FIT FIT 3532
steelhead MACH_STEELHEAD STEELHEAD 3533
panther MACH_PANTHER PANTHER 3534
msm8960_liquid MACH_MSM8960_LIQUID MSM8960_LIQUID 3535
lexikonct MACH_LEXIKONCT LEXIKONCT 3536
ns2816_stb MACH_NS2816_STB NS2816_STB 3537
sei_mm2_lpc3250 MACH_SEI_MM2_LPC3250 SEI_MM2_LPC3250 3538
cmimx53 MACH_CMIMX53 CMIMX53 3539
sandwich MACH_SANDWICH SANDWICH 3540
chief MACH_CHIEF CHIEF 3541
pogo_e02 MACH_POGO_E02 POGO_E02 3542
mikrap_x168 MACH_MIKRAP_X168 MIKRAP_X168 3543
htcmozart MACH_HTCMOZART HTCMOZART 3544
htcgold MACH_HTCGOLD HTCGOLD 3545
mt72xx MACH_MT72XX MT72XX 3546
mx51_ivy MACH_MX51_IVY MX51_IVY 3547
mx51_lvd MACH_MX51_LVD MX51_LVD 3548
omap3_wiser2 MACH_OMAP3_WISER2 OMAP3_WISER2 3549
dreamplug MACH_DREAMPLUG DREAMPLUG 3550
cobas_c_111 MACH_COBAS_C_111 COBAS_C_111 3551
cobas_u_411 MACH_COBAS_U_411 COBAS_U_411 3552
hssd MACH_HSSD HSSD 3553
iom35x MACH_IOM35X IOM35X 3554
psom_omap MACH_PSOM_OMAP PSOM_OMAP 3555
iphone_2g MACH_IPHONE_2G IPHONE_2G 3556
iphone_3g MACH_IPHONE_3G IPHONE_3G 3557
ipod_touch_1g MACH_IPOD_TOUCH_1G IPOD_TOUCH_1G 3558
pharos_tpc MACH_PHAROS_TPC PHAROS_TPC 3559
mx53_hydra MACH_MX53_HYDRA MX53_HYDRA 3560
ns2816_dev_board MACH_NS2816_DEV_BOARD NS2816_DEV_BOARD 3561
iphone_3gs MACH_IPHONE_3GS IPHONE_3GS 3562
iphone_4 MACH_IPHONE_4 IPHONE_4 3563
ipod_touch_4g MACH_IPOD_TOUCH_4G IPOD_TOUCH_4G 3564
dragon_e1100 MACH_DRAGON_E1100 DRAGON_E1100 3565
topside MACH_TOPSIDE TOPSIDE 3566
irisiii MACH_IRISIII IRISIII 3567
deto_macarm9 MACH_DETO_MACARM9 DETO_MACARM9 3568
eti_d1 MACH_ETI_D1 ETI_D1 3569
som3530sdk MACH_SOM3530SDK SOM3530SDK 3570
oc_engine MACH_OC_ENGINE OC_ENGINE 3571
apq8064_sim MACH_APQ8064_SIM APQ8064_SIM 3572
alps MACH_ALPS ALPS 3575
tny_t3730 MACH_TNY_T3730 TNY_T3730 3576
geryon_nfe MACH_GERYON_NFE GERYON_NFE 3577
ns2816_ref_board MACH_NS2816_REF_BOARD NS2816_REF_BOARD 3578
silverstone MACH_SILVERSTONE SILVERSTONE 3579
mtt2440 MACH_MTT2440 MTT2440 3580
ynicdb MACH_YNICDB YNICDB 3581
bct MACH_BCT BCT 3582
tuscan MACH_TUSCAN TUSCAN 3583
xbt_sam9g45 MACH_XBT_SAM9G45 XBT_SAM9G45 3584
enbw_cmc MACH_ENBW_CMC ENBW_CMC 3585
msm8x60_dragon MACH_APQ8060_DRAGON APQ8060_DRAGON 3586
ch104mx257 MACH_CH104MX257 CH104MX257 3587
openpri MACH_OPENPRI OPENPRI 3588
am335xevm MACH_AM335XEVM AM335XEVM 3589
picodmb MACH_PICODMB PICODMB 3590
waluigi MACH_WALUIGI WALUIGI 3591
punicag7 MACH_PUNICAG7 PUNICAG7 3592
ipad_1g MACH_IPAD_1G IPAD_1G 3593
appletv_2g MACH_APPLETV_2G APPLETV_2G 3594
mach_ecog45 MACH_MACH_ECOG45 MACH_ECOG45 3595
ait_cam_enc_4xx MACH_AIT_CAM_ENC_4XX AIT_CAM_ENC_4XX 3596
runnymede MACH_RUNNYMEDE RUNNYMEDE 3597
play MACH_PLAY PLAY 3598
hw90260 MACH_HW90260 HW90260 3599
tagh MACH_TAGH TAGH 3600
filbert MACH_FILBERT FILBERT 3601
getinge_netcomv3 MACH_GETINGE_NETCOMV3 GETINGE_NETCOMV3 3602
cw20 MACH_CW20 CW20 3603
cinema MACH_CINEMA CINEMA 3604
cinema_tea MACH_CINEMA_TEA CINEMA_TEA 3605
cinema_coffee MACH_CINEMA_COFFEE CINEMA_COFFEE 3606
cinema_juice MACH_CINEMA_JUICE CINEMA_JUICE 3607
linux_pad MACH_THEPAD THEPAD 3608
mx53_mirage2 MACH_MX53_MIRAGE2 MX53_MIRAGE2 3609
mx53_efikasb MACH_MX53_EFIKASB MX53_EFIKASB 3610
stm_b2000 MACH_STM_B2000 STM_B2000 3612
m28evk MACH_M28EVK M28EVK 3613
pda MACH_PDA PDA 3614
meraki_mr58 MACH_MERAKI_MR58 MERAKI_MR58 3615
kota2 MACH_KOTA2 KOTA2 3616
letcool MACH_LETCOOL LETCOOL 3617
mx27iat MACH_MX27IAT MX27IAT 3618
apollo_td MACH_APOLLO_TD APOLLO_TD 3619
arena MACH_ARENA ARENA 3620
gsngateway MACH_GSNGATEWAY GSNGATEWAY 3621
lf2000 MACH_LF2000 LF2000 3622
bonito MACH_BONITO BONITO 3623
asymptote MACH_ASYMPTOTE ASYMPTOTE 3624
bst2brd MACH_BST2BRD BST2BRD 3625
tx335s MACH_TX335S TX335S 3626
pelco_tesla MACH_PELCO_TESLA PELCO_TESLA 3627
rrhtestplat MACH_RRHTESTPLAT RRHTESTPLAT 3628
vidtonic_pro MACH_VIDTONIC_PRO VIDTONIC_PRO 3629
pl_apollo MACH_PL_APOLLO PL_APOLLO 3630
pl_phoenix MACH_PL_PHOENIX PL_PHOENIX 3631
m28cu3 MACH_M28CU3 M28CU3 3632
vvbox_hd MACH_VVBOX_HD VVBOX_HD 3633
coreware_sam9260_ MACH_COREWARE_SAM9260_ COREWARE_SAM9260_ 3634
marmaduke MACH_MARMADUKE MARMADUKE 3635
amg_xlcore_camera MACH_AMG_XLCORE_CAMERA AMG_XLCORE_CAMERA 3636
omap3_egf MACH_OMAP3_EGF OMAP3_EGF 3637
smdk4212 MACH_SMDK4212 SMDK4212 3638
dnp9200 MACH_DNP9200 DNP9200 3639
tf101 MACH_TF101 TF101 3640
omap3silvio MACH_OMAP3SILVIO OMAP3SILVIO 3641
picasso2 MACH_PICASSO2 PICASSO2 3642
vangogh2 MACH_VANGOGH2 VANGOGH2 3643
olpc_xo_1_75 MACH_OLPC_XO_1_75 OLPC_XO_1_75 3644
gx400 MACH_GX400 GX400 3645
gs300 MACH_GS300 GS300 3646
acer_a9 MACH_ACER_A9 ACER_A9 3647
vivow_evm MACH_VIVOW_EVM VIVOW_EVM 3648
veloce_cxq MACH_VELOCE_CXQ VELOCE_CXQ 3649
veloce_cxm MACH_VELOCE_CXM VELOCE_CXM 3650
p1852 MACH_P1852 P1852 3651
naxy100 MACH_NAXY100 NAXY100 3652
taishan MACH_TAISHAN TAISHAN 3653
touchlink MACH_TOUCHLINK TOUCHLINK 3654
stm32f103ze MACH_STM32F103ZE STM32F103ZE 3655
mcx MACH_MCX MCX 3656
stm_nmhdk_fli7610 MACH_STM_NMHDK_FLI7610 STM_NMHDK_FLI7610 3657
top28x MACH_TOP28X TOP28X 3658
okl4vp_microvisor MACH_OKL4VP_MICROVISOR OKL4VP_MICROVISOR 3659
pop MACH_POP POP 3660
layer MACH_LAYER LAYER 3661
trondheim MACH_TRONDHEIM TRONDHEIM 3662
eva MACH_EVA EVA 3663
trust_taurus MACH_TRUST_TAURUS TRUST_TAURUS 3664
ns2816_huashan MACH_NS2816_HUASHAN NS2816_HUASHAN 3665
ns2816_yangcheng MACH_NS2816_YANGCHENG NS2816_YANGCHENG 3666
p852 MACH_P852 P852 3667
flea3 MACH_FLEA3 FLEA3 3668
bowfin MACH_BOWFIN BOWFIN 3669
mv88de3100 MACH_MV88DE3100 MV88DE3100 3670
pia_am35x MACH_PIA_AM35X PIA_AM35X 3671
cedar MACH_CEDAR CEDAR 3672
picasso_e MACH_PICASSO_E PICASSO_E 3673
samsung_e60 MACH_SAMSUNG_E60 SAMSUNG_E60 3674
msm9615_cdp MACH_MDM9615 MDM9615 3675
sdvr_mini MACH_SDVR_MINI SDVR_MINI 3676
omap3_ij3k MACH_OMAP3_IJ3K OMAP3_IJ3K 3677
modasmc1 MACH_MODASMC1 MODASMC1 3678
apq8064_rumi3 MACH_APQ8064_RUMI3 APQ8064_RUMI3 3679
matrix506 MACH_MATRIX506 MATRIX506 3680
msm9615_mtp MACH_MSM9615_MTP MSM9615_MTP 3681
dm36x_spawndc MACH_DM36X_SPAWNDC DM36X_SPAWNDC 3682
sff792 MACH_SFF792 SFF792 3683
am335xiaevm MACH_AM335XIAEVM AM335XIAEVM 3684
g3c2440 MACH_G3C2440 G3C2440 3685
tion270 MACH_TION270 TION270 3686
w22q7arm02 MACH_W22Q7ARM02 W22Q7ARM02 3687
omap_cat MACH_OMAP_CAT OMAP_CAT 3688
at91sam9n12ek MACH_AT91SAM9N12EK AT91SAM9N12EK 3689
morrison MACH_MORRISON MORRISON 3690
svdu MACH_SVDU SVDU 3691
lpp01 MACH_LPP01 LPP01 3692
ubc283 MACH_UBC283 UBC283 3693
zeppelin MACH_ZEPPELIN ZEPPELIN 3694
motus MACH_MOTUS MOTUS 3695
neomainboard MACH_NEOMAINBOARD NEOMAINBOARD 3696
devkit3250 MACH_DEVKIT3250 DEVKIT3250 3697
devkit7000 MACH_DEVKIT7000 DEVKIT7000 3698
fmc_uic MACH_FMC_UIC FMC_UIC 3699
fmc_dcm MACH_FMC_DCM FMC_DCM 3700
batwm MACH_BATWM BATWM 3701
atlas6cb MACH_ATLAS6CB ATLAS6CB 3702
quattro_f MACH_QUATTROF QUATTROF 3703
quattro_u MACH_QUATTROU QUATTROU 3704
blue MACH_BLUE BLUE 3705
colorado MACH_COLORADO COLORADO 3706
popc MACH_POPC POPC 3707
promwad_jade MACH_PROMWAD_JADE PROMWAD_JADE 3708
amp MACH_AMP AMP 3709
gnet_amp MACH_GNET_AMP GNET_AMP 3710
toques MACH_TOQUES TOQUES 3711
apx4devkit MACH_APX4 APX4 3712
dct_storm MACH_DCT_STORM DCT_STORM 3713
dm8168z3 MACH_Z3 Z3 3714
owl MACH_OWL OWL 3715
cogent_csb1741 MACH_COGENT_CSB1741 COGENT_CSB1741 3716
omap3_kiko MACH_OMAP3 OMAP3 3717
adillustra610 MACH_ADILLUSTRA610 ADILLUSTRA610 3718
ecafe_na04 MACH_ECAFE_NA04 ECAFE_NA04 3719
popct MACH_POPCT POPCT 3720
omap3_helena MACH_OMAP3_HELENA OMAP3_HELENA 3721
ach MACH_ACH ACH 3722
module_dtb MACH_MODULE_DTB MODULE_DTB 3723
ratebox MACH_RACKBOX RACKBOX 3724
oslo_elisabeth MACH_OSLO_ELISABETH OSLO_ELISABETH 3725
tt01 MACH_TT01 TT01 3726
msm8930_cdp MACH_MSM8930_CDP MSM8930_CDP 3727
msm8930_mtp MACH_MSM8930_MTP MSM8930_MTP 3728
msm8930_fluid MACH_MSM8930_FLUID MSM8930_FLUID 3729
ltu11 MACH_LTU11 LTU11 3730
am1808_spawnco MACH_AM1808_SPAWNCO AM1808_SPAWNCO 3731
flx6410 MACH_FLX6410 FLX6410 3732
mx6q_qsb MACH_MX6Q_QSB MX6Q_QSB 3733
mx53_plt424 MACH_MX53_PLT424 MX53_PLT424 3734
jasmine MACH_JASMINE JASMINE 3735
l138_owlboard_plus MACH_L138_OWLBOARD_PLUS L138_OWLBOARD_PLUS 3736
wr21 MACH_WR21 WR21 3737
peaboy MACH_PEABOY PEABOY 3739
mx28_plato MACH_MX28_PLATO MX28_PLATO 3740
kacom2 MACH_KACOM2 KACOM2 3741
slco MACH_SLCO SLCO 3742
imx51pico MACH_IMX51PICO IMX51PICO 3743
glink1 MACH_GLINK1 GLINK1 3744
diamond MACH_DIAMOND DIAMOND 3745
d9000 MACH_D9000 D9000 3746
w5300e01 MACH_W5300E01 W5300E01 3747
im6000 MACH_IM6000 IM6000 3748
mx51_fred51 MACH_MX51_FRED51 MX51_FRED51 3749
stm32f2 MACH_STM32F2 STM32F2 3750
ville MACH_VILLE VILLE 3751
ptip_murnau MACH_PTIP_MURNAU PTIP_MURNAU 3752
ptip_classic MACH_PTIP_CLASSIC PTIP_CLASSIC 3753
mx53grb MACH_MX53GRB MX53GRB 3754
gagarin MACH_GAGARIN GAGARIN 3755
msm7627a_qrd1 MACH_MSM7X27A_QRD1 MSM7X27A_QRD1 3756
nas2big MACH_NAS2BIG NAS2BIG 3757
superfemto MACH_SUPERFEMTO SUPERFEMTO 3758
teufel MACH_TEUFEL TEUFEL 3759
dinara MACH_DINARA DINARA 3760
vanquish MACH_VANQUISH VANQUISH 3761
zipabox1 MACH_ZIPABOX1 ZIPABOX1 3762
u9540 MACH_U9540 U9540 3763
jet MACH_JET JET 3764
smdk4412 MACH_SMDK4412 SMDK4412 3765
elite MACH_ELITE ELITE 3766
spear320_hmi MACH_SPEAR320_HMI SPEAR320_HMI 3767
ontario MACH_ONTARIO ONTARIO 3768
mx6q_sabrelite MACH_MX6Q_SABRELITE MX6Q_SABRELITE 3769
vc200 MACH_VC200 VC200 3770
msm7625a_ffa MACH_MSM7625A_FFA MSM7625A_FFA 3771
msm7625a_surf MACH_MSM7625A_SURF MSM7625A_SURF 3772
benthossbp MACH_BENTHOSSBP BENTHOSSBP 3773
smdk5210 MACH_SMDK5210 SMDK5210 3774
empq2300 MACH_EMPQ2300 EMPQ2300 3775
minipos MACH_MINIPOS MINIPOS 3776
omap5_sevm MACH_OMAP5_SEVM OMAP5_SEVM 3777
shelter MACH_SHELTER SHELTER 3778
omap3_devkit8500 MACH_OMAP3_DEVKIT8500 OMAP3_DEVKIT8500 3779
edgetd MACH_EDGETD EDGETD 3780
copperyard MACH_COPPERYARD COPPERYARD 3781
edge MACH_EDGE EDGE 3782
edge_u MACH_EDGE_U EDGE_U 3783
edge_td MACH_EDGE_TD EDGE_TD 3784
wdss MACH_WDSS WDSS 3785
dl_pb25 MACH_DL_PB25 DL_PB25 3786
dss11 MACH_DSS11 DSS11 3787
cpa MACH_CPA CPA 3788
aptp2000 MACH_APTP2000 APTP2000 3789
marzen MACH_MARZEN MARZEN 3790
st_turbine MACH_ST_TURBINE ST_TURBINE 3791
gtl_it3300 MACH_GTL_IT3300 GTL_IT3300 3792
mx6_mule MACH_MX6_MULE MX6_MULE 3793
v7pxa_dt MACH_V7PXA_DT V7PXA_DT 3794
v7mmp_dt MACH_V7MMP_DT V7MMP_DT 3795
dragon7 MACH_DRAGON7 DRAGON7 3796
krome MACH_KROME KROME 3797
oratisdante MACH_ORATISDANTE ORATISDANTE 3798
fathom MACH_FATHOM FATHOM 3799
dns325 MACH_DNS325 DNS325 3800
sarnen MACH_SARNEN SARNEN 3801
ubisys_g1 MACH_UBISYS_G1 UBISYS_G1 3802
mx53_pf1 MACH_MX53_PF1 MX53_PF1 3803
asanti MACH_ASANTI ASANTI 3804
volta MACH_VOLTA VOLTA 3805
potenza MACH_S5P6450 S5P6450 3806
knight MACH_KNIGHT KNIGHT 3807
beaglebone MACH_BEAGLEBONE BEAGLEBONE 3808
becker MACH_BECKER BECKER 3809
fc360 MACH_FC360 FC360 3810
pmi2_xls MACH_PMI2_XLS PMI2_XLS 3811
taranto MACH_TARANTO TARANTO 3812
plutux MACH_PLUTUX PLUTUX 3813
ipmp_medcom MACH_IPMP_MEDCOM IPMP_MEDCOM 3814
absolut MACH_ABSOLUT ABSOLUT 3815
awpb3 MACH_AWPB3 AWPB3 3816
nfp32xx_dt MACH_NFP32XX_DT NFP32XX_DT 3817
dl_pb53 MACH_DL_PB53 DL_PB53 3818
acu_ii MACH_ACU_II ACU_II 3819
avalon MACH_AVALON AVALON 3820
sphinx MACH_SPHINX SPHINX 3821
titan_t MACH_TITAN_T TITAN_T 3822
harvest_boris MACH_HARVEST_BORIS HARVEST_BORIS 3823
mach_msm7x30_m3s MACH_MACH_MSM7X30_M3S MACH_MSM7X30_M3S 3824
smdk5250 MACH_SMDK5250 SMDK5250 3825
imxt_lite MACH_IMXT_LITE IMXT_LITE 3826
imxt_std MACH_IMXT_STD IMXT_STD 3827
imxt_log MACH_IMXT_LOG IMXT_LOG 3828
imxt_nav MACH_IMXT_NAV IMXT_NAV 3829
imxt_full MACH_IMXT_FULL IMXT_FULL 3830
ag09015 MACH_AG09015 AG09015 3831
am3517_mt_ventoux MACH_AM3517_MT_VENTOUX AM3517_MT_VENTOUX 3832
dp1arm9 MACH_DP1ARM9 DP1ARM9 3833
picasso_m MACH_PICASSO_M PICASSO_M 3834
video_gadget MACH_VIDEO_GADGET VIDEO_GADGET 3835
mtt_om3x MACH_MTT_OM3X MTT_OM3X 3836
mx6q_arm2 MACH_MX6Q_ARM2 MX6Q_ARM2 3837
picosam9g45 MACH_PICOSAM9G45 PICOSAM9G45 3838
vpm_dm365 MACH_VPM_DM365 VPM_DM365 3839
bonfire MACH_BONFIRE BONFIRE 3840
mt2p2d MACH_MT2P2D MT2P2D 3841
sigpda01 MACH_SIGPDA01 SIGPDA01 3842
cn27 MACH_CN27 CN27 3843
mx25_cwtap MACH_MX25_CWTAP MX25_CWTAP 3844
apf28 MACH_APF28 APF28 3845
pelco_maxwell MACH_PELCO_MAXWELL PELCO_MAXWELL 3846
ge_phoenix MACH_GE_PHOENIX GE_PHOENIX 3847
empc_a500 MACH_EMPC_A500 EMPC_A500 3848
ims_arm9 MACH_IMS_ARM9 IMS_ARM9 3849
mini2416 MACH_MINI2416 MINI2416 3850
mini2450 MACH_MINI2450 MINI2450 3851
mini310 MACH_MINI310 MINI310 3852
spear_hurricane MACH_SPEAR_HURRICANE SPEAR_HURRICANE 3853
mt7208 MACH_MT7208 MT7208 3854
lpc178x MACH_LPC178X LPC178X 3855
farleys MACH_FARLEYS FARLEYS 3856
efm32gg_dk3750 MACH_EFM32GG_DK3750 EFM32GG_DK3750 3857
zeus_board MACH_ZEUS_BOARD ZEUS_BOARD 3858
cc51 MACH_CC51 CC51 3859
fxi_c210 MACH_FXI_C210 FXI_C210 3860
msm8627_cdp MACH_MSM8627_CDP MSM8627_CDP 3861
msm8627_mtp MACH_MSM8627_MTP MSM8627_MTP 3862
armadillo800eva MACH_ARMADILLO800EVA ARMADILLO800EVA 3863
primou MACH_PRIMOU PRIMOU 3864
primoc MACH_PRIMOC PRIMOC 3865
primoct MACH_PRIMOCT PRIMOCT 3866
a9500 MACH_A9500 A9500 3867
pue_td MACH_PULSE_TD PULSE_TD 3868
pluto MACH_PLUTO PLUTO 3869
acfx100 MACH_ACFX100 ACFX100 3870
msm8625_rumi3 MACH_MSM8625_RUMI3 MSM8625_RUMI3 3871
valente MACH_VALENTE VALENTE 3872
crfs_rfeye MACH_CRFS_RFEYE CRFS_RFEYE 3873
rfeye MACH_RFEYE RFEYE 3874
phidget_sbc3 MACH_PHIDGET_SBC3 PHIDGET_SBC3 3875
tcw_mika MACH_TCW_MIKA TCW_MIKA 3876
imx28_egf MACH_IMX28_EGF IMX28_EGF 3877
valente_wx MACH_VALENTE_WX VALENTE_WX 3878
huangshans MACH_HUANGSHANS HUANGSHANS 3879
bosphorus1 MACH_BOSPHORUS1 BOSPHORUS1 3880
prima MACH_PRIMA PRIMA 3881
meson3_skt MACH_M3_SKT M3_SKT 3882
meson3_ref MACH_M3_REF M3_REF 3883
evita_ulk MACH_EVITA_ULK EVITA_ULK 3884
merisc600 MACH_MERISC600 MERISC600 3885
dolak MACH_DOLAK DOLAK 3886
sbc53 MACH_SBC53 SBC53 3887
elite_ulk MACH_ELITE_ULK ELITE_ULK 3888
pov2 MACH_POV2 POV2 3889
ipod_touch_2g MACH_IPOD_TOUCH_2G IPOD_TOUCH_2G 3890
da850_pqab MACH_DA850_PQAB DA850_PQAB 3891

4
arch/blackfin/boards/ipe337/barebox.lds.S
View File

@ -71,6 +71,10 @@ SECTIONS
.barebox_cmd : { BAREBOX_CMDS }
___barebox_cmd_end = .;
__barebox_magicvar_start = .;
.barebox_magicvar : { BAREBOX_MAGICVARS }
__barebox_magicvar_end = .;
___barebox_initcalls_start = .;
.barebox_initcalls : { INITCALLS }
___barebox_initcalls_end = .;

3
arch/blackfin/lib/blackfin_linux.c
View File

@ -50,9 +50,6 @@ static int do_bootm_linux(struct image_data *idata)
appl = (int (*)(char *))image_get_ep(os_header);
printf("Starting Kernel at 0x%p\n", appl);
if (relocate_image(os_handle, (void *)image_get_load(os_header)))
return -1;
icache_disable();
strncpy(cmdlinedest, cmdline, 0x1000);

2
arch/blackfin/lib/board.c
View File

@ -38,7 +38,7 @@
int blackfin_mem_malloc_init(void)
{
mem_malloc_init((void *)(MALLOC_BASE),
(void *)(MALLOC_BASE + MALLOC_SIZE));
(void *)(MALLOC_BASE + MALLOC_SIZE - 1));
return 0;
}

2
arch/mips/configs/dlink-dir-320_defconfig
View File

@ -41,7 +41,7 @@ CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y

2
arch/mips/configs/qemu-malta_defconfig
View File

@ -40,7 +40,7 @@ CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_UNLZO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y

4
arch/mips/lib/barebox.lds.S
View File

@ -56,6 +56,10 @@ SECTIONS
.barebox_cmd : { BAREBOX_CMDS }
__barebox_cmd_end = .;
__barebox_magicvar_start = .;
.barebox_magicvar : { BAREBOX_MAGICVARS }
__barebox_magicvar_end = .;
__barebox_initcalls_start = .;
.barebox_initcalls : { INITCALLS }
__barebox_initcalls_end = .;

2
arch/mips/lib/memory.c
View File

@ -26,7 +26,7 @@
static int mips_mem_malloc_init(void)
{
mem_malloc_init((void *)MALLOC_BASE,
(void *)(MALLOC_BASE + MALLOC_SIZE));
(void *)(MALLOC_BASE + MALLOC_SIZE - 1));
return 0;
}
core_initcall(mips_mem_malloc_init);

1
arch/nios2/cpu/Makefile
View File

@ -1,6 +1,5 @@
obj-y += start.o
obj-y += exceptions.o
obj-y += cpu.o
obj-$(CONFIG_USE_IRQ) += interrupts.o
obj-y += traps.o
extra-y += barebox.lds

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