[mmccpu] add new board: Bucyrus MMC-CPU
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Marc Kleine-Budde
parent
6f61b3f34d
commit
0780441a3f
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@ -16,6 +16,7 @@ config ARCH_TEXT_BASE
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default 0x87f00000 if MACH_FREESCALE_MX35_3STACK
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default 0x87f00000 if MACH_PCM043
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default 0xa7f00000 if MACH_PCA100
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default 0x23f00000 if MACH_MMCCPU
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config BOARDINFO
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default "Synertronixx scb9328" if MACH_SCB9328
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@ -29,6 +30,7 @@ config BOARDINFO
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default "Freescale MX35 3Stack" if MACH_FREESCALE_MX35_3STACK
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default "Phytec phyCORE-i.MX35" if MACH_PCM043
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default "Phytec phyCard-i.MX27" if MACH_PCA100
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default "Bucyrus MMC-CPU" if MACH_MMCCPU
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config BOARD_LINKER_SCRIPT
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bool
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@ -200,6 +202,12 @@ config MACH_PCA100
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Say Y here if you are using Phytec's phyCard-i.MX27 (pca100) equipped
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with a Freescale i.MX27 Processor
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config MACH_MMCCPU
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bool "Bucyrus MMC-CPU"
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select ARCH_AT91SAM9263
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help
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Say y here if you are using the Bucyrus MMC-CPU
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endchoice
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source arch/arm/mach-imx/Kconfig
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@ -21,6 +21,7 @@ board-$(CONFIG_MACH_PM9263) := pm9263
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board-$(CONFIG_MACH_FREESCALE_MX35_3STACK) := freescale-mx35-3-stack
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board-$(CONFIG_MACH_PCM043) := pcm043
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board-$(CONFIG_MACH_PCA100) := phycard-i.MX27
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board-$(CONFIG_MACH_MMCCPU) := mmccpu
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# FIXME "cpu-y" never used on ARM!
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cpu-$(CONFIG_ARM920T) := arm920t
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@ -0,0 +1,229 @@
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#
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# Automatically generated make config: don't edit
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# U-Boot version: 2.0.0-rc8
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# Tue May 19 09:44:44 2009
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#
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CONFIG_ARCH_TEXT_BASE=0x23f00000
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CONFIG_BOARDINFO="Bucyrus MMC-CPU"
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# CONFIG_BOARD_LINKER_SCRIPT is not set
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CONFIG_GENERIC_LINKER_SCRIPT=y
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CONFIG_ARM=y
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CONFIG_ARM926EJS=y
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CONFIG_ARCH_AT91SAM9=y
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CONFIG_ARCH_AT91SAM9263=y
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# CONFIG_MACH_MX1ADS is not set
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# CONFIG_MACH_SCB9328 is not set
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# CONFIG_MACH_PCM038 is not set
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# CONFIG_MACH_IMX21ADS is not set
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# CONFIG_MACH_IMX27ADS is not set
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# CONFIG_MACH_PCM043 is not set
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# CONFIG_MACH_FREESCALE_MX35_3STACK is not set
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# CONFIG_MACH_ECO920 is not set
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# CONFIG_MACH_NXDB500 is not set
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# CONFIG_MACH_PCM037 is not set
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# CONFIG_MACH_OMAP is not set
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# CONFIG_MACH_AT91SAM9260_EK is not set
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# CONFIG_MACH_PM9263 is not set
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# CONFIG_MACH_PCA100 is not set
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CONFIG_MACH_MMCCPU=y
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#
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# Board specific settings
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#
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#
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# i.MX specific settings
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#
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#
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# Arm specific settings
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#
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CONFIG_CMD_ARM_CPUINFO=y
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CONFIG_CMDLINE_TAG=y
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CONFIG_SETUP_MEMORY_TAGS=y
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# CONFIG_INITRD_TAG is not set
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CONFIG_GREGORIAN_CALENDER=y
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CONFIG_HAS_KALLSYMS=y
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CONFIG_HAS_MODULES=y
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CONFIG_CMD_MEMORY=y
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CONFIG_ENV_HANDLING=y
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#
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# General Settings
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#
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CONFIG_LOCALVERSION_AUTO=y
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#
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# memory layout
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#
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CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y
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CONFIG_TEXT_BASE=0x23f00000
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CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y
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CONFIG_MEMORY_LAYOUT_DEFAULT=y
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# CONFIG_MEMORY_LAYOUT_FIXED is not set
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CONFIG_STACK_SIZE=0x8000
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CONFIG_MALLOC_SIZE=0x400000
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# CONFIG_BROKEN is not set
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# CONFIG_EXPERIMENTAL is not set
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CONFIG_MACH_HAS_LOWLEVEL_INIT=y
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CONFIG_MACH_DO_LOWLEVEL_INIT=y
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CONFIG_PROMPT="uboot:"
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CONFIG_BAUDRATE=115200
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CONFIG_LONGHELP=y
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CONFIG_CBSIZE=1024
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CONFIG_MAXARGS=16
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CONFIG_SHELL_HUSH=y
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# CONFIG_SHELL_SIMPLE is not set
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CONFIG_GLOB=y
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CONFIG_PROMPT_HUSH_PS2="y"
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CONFIG_CMDLINE_EDITING=y
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CONFIG_AUTO_COMPLETE=y
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CONFIG_DYNAMIC_CRC_TABLE=y
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CONFIG_ERRNO_MESSAGES=y
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CONFIG_TIMESTAMP=y
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CONFIG_CONSOLE_FULL=y
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CONFIG_CONSOLE_ACTIVATE_FIRST=y
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# CONFIG_OF_FLAT_TREE is not set
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CONFIG_PARTITION=y
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CONFIG_DEFAULT_ENVIRONMENT=y
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CONFIG_DEFAULT_ENVIRONMENT_PATH="board/mmccpu/env"
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#
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# Debugging
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#
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# CONFIG_DEBUG_INFO is not set
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# CONFIG_ENABLE_FLASH_NOISE is not set
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# CONFIG_ENABLE_PARTITION_NOISE is not set
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# CONFIG_ENABLE_DEVICE_NOISE is not set
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#
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# Commands
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#
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#
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# scripting
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#
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CONFIG_CMD_EDIT=y
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CONFIG_CMD_SLEEP=y
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CONFIG_CMD_SAVEENV=y
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CONFIG_CMD_LOADENV=y
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CONFIG_CMD_EXPORT=y
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CONFIG_CMD_PRINTENV=y
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CONFIG_CMD_READLINE=y
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CONFIG_CMD_TRUE=y
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CONFIG_CMD_FALSE=y
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#
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# file commands
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#
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CONFIG_CMD_LS=y
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CONFIG_CMD_RM=y
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CONFIG_CMD_CAT=y
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CONFIG_CMD_MKDIR=y
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CONFIG_CMD_RMDIR=y
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CONFIG_CMD_CP=y
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CONFIG_CMD_PWD=y
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CONFIG_CMD_CD=y
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CONFIG_CMD_MOUNT=y
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CONFIG_CMD_UMOUNT=y
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#
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# console
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#
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CONFIG_CMD_CLEAR=y
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CONFIG_CMD_ECHO=y
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#
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# memory
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#
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# CONFIG_CMD_LOADB is not set
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CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_CRC=y
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CONFIG_CMD_MTEST=y
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CONFIG_CMD_MTEST_ALTERNATIVE=y
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#
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# flash
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#
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CONFIG_CMD_FLASH=y
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#
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# i2c
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#
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CONFIG_CMD_I2C=y
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#
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# booting
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#
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CONFIG_CMD_BOOTM=y
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# CONFIG_CMD_BOOTM_ZLIB is not set
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# CONFIG_CMD_BOOTM_BZLIB is not set
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CONFIG_CMD_BOOTM_SHOW_TYPE=y
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CONFIG_CMD_RESET=y
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CONFIG_CMD_GO=y
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CONFIG_CMD_TIMEOUT=y
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CONFIG_CMD_PARTITION=y
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CONFIG_CMD_TEST=y
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CONFIG_CMD_VERSION=y
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CONFIG_CMD_HELP=y
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CONFIG_CMD_DEVINFO=y
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CONFIG_NET=y
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CONFIG_NET_BOOTP=y
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CONFIG_NET_DHCP=y
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# CONFIG_NET_RARP is not set
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# CONFIG_NET_SNTP is not set
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# CONFIG_NET_NFS is not set
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CONFIG_NET_PING=y
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CONFIG_NET_TFTP=y
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#
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# Drivers
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#
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#
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# serial drivers
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#
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# CONFIG_DRIVER_SERIAL_NS16550 is not set
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CONFIG_DRIVER_SERIAL_ATMEL=y
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CONFIG_MIIPHY=y
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#
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# Network drivers
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#
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# CONFIG_DRIVER_NET_SMC911X is not set
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CONFIG_DRIVER_NET_MACB=y
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#
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# SPI drivers
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#
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# CONFIG_SPI is not set
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#
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# flash drivers
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#
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CONFIG_DRIVER_CFI=y
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CONFIG_DRIVER_CFI_NEW=y
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CONFIG_DRIVER_CFI_INTEL=y
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CONFIG_DRIVER_CFI_AMD=y
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CONFIG_DRIVER_CFI_BANK_WIDTH_1=y
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CONFIG_DRIVER_CFI_BANK_WIDTH_2=y
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CONFIG_DRIVER_CFI_BANK_WIDTH_4=y
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# CONFIG_DRIVER_CFI_BANK_WIDTH_8 is not set
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CONFIG_CFI_BUFFER_WRITE=y
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# CONFIG_NAND is not set
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# CONFIG_USB is not set
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#
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# I2C drivers
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#
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CONFIG_I2C=y
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CONFIG_DRIVER_I2C_BITBANG=y
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#
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# Filesystem support
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#
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# CONFIG_FS_CRAMFS is not set
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CONFIG_FS_RAMFS=y
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CONFIG_FS_DEVFS=y
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CONFIG_CRC32=y
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# CONFIG_GENERIC_FIND_NEXT_BIT is not set
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@ -0,0 +1,2 @@
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obj-y += lowlevel_init.o
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obj-y += init.o
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@ -0,0 +1,6 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define AT91_MASTER_CLOCK 99532800 /* peripheral = main / 2 */
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#endif /* __CONFIG_H */
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@ -0,0 +1,36 @@
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#!/bin/sh
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if [ -z "$part" -o -z "$image" ]; then
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echo "define \$part and \$image"
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exit 1
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fi
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if [ \! -e "$part" ]; then
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echo "Partition $part does not exist"
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exit 1
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fi
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if [ $# = 1 ]; then
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image=$1
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fi
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if [ x$ip = xdhcp ]; then
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dhcp
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fi
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ping $eth0.serverip
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if [ $? -ne 0 ] ; then
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echo "update aborted"
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exit 1
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fi
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unprotect $part
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echo
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echo "erasing partition $part"
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erase $part
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echo
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echo "flashing $image to $part"
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echo
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tftp $image $part
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@ -0,0 +1,47 @@
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#!/bin/sh
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. /env/config
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if [ x$1 = xnand ]; then
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root=nand
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kernel=nand
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fi
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if [ x$1 = xnet ]; then
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root=net
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kernel=net
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fi
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if [ x$1 = xnor ]; then
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root=nor
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kernel=nor
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fi
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if [ x$ip = xdhcp ]; then
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bootargs="$bootargs ip=dhcp"
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else
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bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
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fi
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if [ x$root = xnand ]; then
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bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
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elif [ x$root = xnor ]; then
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bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2"
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else
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bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
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fi
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bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts"
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if [ $kernel = net ]; then
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if [ x$ip = xdhcp ]; then
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dhcp
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fi
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tftp $uimage uImage || exit 1
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bootm uImage
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elif [ $kernel = nor ]; then
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bootm /dev/nor0.kernel
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else
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bootm /dev/nand0.kernel.bb
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fi
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@ -0,0 +1 @@
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nand -a /dev/nand0.*
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@ -0,0 +1,37 @@
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#!/bin/sh
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PATH=/env/bin
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export PATH
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. /env/config
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if [ -e /dev/nor0 ]; then
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addpart /dev/nor0 $nor_parts
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fi
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if [ -e /dev/nand0 ]; then
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addpart /dev/nand0 $nand_parts
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# Uh, oh, hush first expands wildcards and then starts executing
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# commands. What a bug!
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source /env/bin/hush_hack
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fi
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if [ -z $eth0.ethaddr ]; then
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while [ -z $eth0.ethaddr ]; do
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readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
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done
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echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
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fi
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echo
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echo -n "Hit any key to stop autoboot: "
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timeout -a $autoboot_timeout
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if [ $? != 0 ]; then
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echo
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echo "type update_kernel nor [<imagename>] to update kernel into flash"
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echo "type update_root nor [<imagename>] to update rootfs into flash"
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echo
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exit
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fi
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boot
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@ -0,0 +1,15 @@
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#!/bin/sh
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. /env/config
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image=$uimage
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if [ x$1 = xnand ]; then
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part=/dev/nand0.kernel.bb
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elif [ x$1 = xnor ]; then
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part=/dev/nor0.kernel
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else
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echo "usage: $0 nor|nand [imagename]"
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exit 1
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fi
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. /env/bin/_update $2
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@ -0,0 +1,16 @@
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#!/bin/sh
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. /env/config
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image=$jffs2
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if [ x$1 = xnand ]; then
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part=/dev/nand0.root.bb
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elif [ x$1 = xnor ]; then
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part=/dev/nor0.root
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else
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echo "usage: $0 nor|nand [imagename]"
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exit 1
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fi
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. /env/bin/_update $2
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@ -0,0 +1,30 @@
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#!/bin/sh
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# can be either 'net', 'nor' or 'nand''
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kernel=nor
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root=nor
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uimage=uImage-mmccpu
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jffs2=root-mmccpu.jffs2
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autoboot_timeout=3
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nfsroot="/home/kschwinne/src/pengutronix/OSELAS.BSP-Bucyrus-Grabowski-trunk/platform-Bucyrus-mmccpu/root"
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bootargs="console=ttyS0,115200 mmccpu=p299"
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#nor_parts="256k(uboot)ro,128k(ubootenv),1536k(kernel),-(root)"
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nor_parts="256k(uboot)ro,128k(ubootenv),1536k(kernel),10240k(root),10240k(rootbu),-(data)"
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rootpart_nor="/dev/mtdblock3"
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#nand_parts="256k(uboot)ro,64k(ubootenv),1536k(kernel),-(root)"
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#rootpart_nand="/dev/mtdblock7"
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# use 'dhcp' to do dhcp in uboot and in kernel
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ip=dhcp
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# or set your networking parameters here
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#eth0.ipaddr=a.b.c.d
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#eth0.netmask=a.b.c.d
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#eth0.gateway=a.b.c.d
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#eth0.serverip=a.b.c.d
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@ -0,0 +1,137 @@
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/*
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <net.h>
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#include <cfi_flash.h>
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#include <init.h>
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#include <environment.h>
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#include <fec.h>
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#include <asm/armlinux.h>
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#include <asm/mach-types.h>
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#include <partition.h>
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#include <fs.h>
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#include <fcntl.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/hardware.h>
|
||||
#include <nand.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <asm/arch/ether.h>
|
||||
|
||||
static struct device_d sdram_dev = {
|
||||
.name = "ram",
|
||||
.id = "ram0",
|
||||
|
||||
.map_base = 0x20000000,
|
||||
.size = 128 * 1024 * 1024,
|
||||
|
||||
.type = DEVICE_TYPE_DRAM,
|
||||
};
|
||||
|
||||
static struct device_d cfi_dev = {
|
||||
.name = "cfi_flash",
|
||||
.id = "nor0",
|
||||
|
||||
.map_base = 0x10000000,
|
||||
.size = 0, /* zero means autodetect size */
|
||||
};
|
||||
|
||||
static struct at91sam_ether_platform_data macb_pdata = {
|
||||
.flags = AT91SAM_ETHER_MII | AT91SAM_ETHER_FORCE_LINK,
|
||||
.phy_addr = 4,
|
||||
};
|
||||
|
||||
static struct device_d macb_dev = {
|
||||
.name = "macb",
|
||||
.id = "eth0",
|
||||
.map_base = AT91C_BASE_MACB,
|
||||
.size = 0x1000,
|
||||
.type = DEVICE_TYPE_ETHER,
|
||||
.platform_data = &macb_pdata,
|
||||
};
|
||||
|
||||
static int mmccpu_devices_init(void)
|
||||
{
|
||||
u32 pe = AT91C_PC25_ERXDV |
|
||||
AT91C_PC22_ERX2 |
|
||||
AT91C_PC23_ERX3 |
|
||||
AT91C_PC20_ETX2 |
|
||||
AT91C_PC21_ETX3;
|
||||
|
||||
writel(pe, AT91C_BASE_PIOC + PIO_BSR(0));
|
||||
writel(pe, AT91C_BASE_PIOC + PIO_PDR(0));
|
||||
|
||||
pe = AT91C_PE21_ETXCK |
|
||||
AT91C_PE23_ETX0 |
|
||||
AT91C_PE24_ETX1 |
|
||||
AT91C_PE25_ERX0 |
|
||||
AT91C_PE26_ERX1 |
|
||||
AT91C_PE27_ERXER |
|
||||
AT91C_PE28_ETXEN |
|
||||
AT91C_PE29_EMDC |
|
||||
AT91C_PE30_EMDIO;
|
||||
|
||||
writel(pe, AT91C_BASE_PIOE + PIO_ASR(0));
|
||||
writel(pe, AT91C_BASE_PIOE + PIO_PDR(0));
|
||||
|
||||
/* set PB27 to '1', enable 50MHz oscillator */
|
||||
writel(AT91C_PIO_PB27, AT91C_BASE_PIOB + PIO_PER(0));
|
||||
writel(AT91C_PIO_PB27, AT91C_BASE_PIOB + PIO_OER(0));
|
||||
writel(AT91C_PIO_PB27, AT91C_BASE_PIOB + PIO_SODR(0));
|
||||
|
||||
/* set PB4, PB5 to '1', enable 50MHz oscillator */
|
||||
writel(AT91C_PIO_PB4|AT91C_PIO_PB5, AT91C_BASE_PIOB + PIO_PER(0));
|
||||
writel(AT91C_PIO_PB4|AT91C_PIO_PB5, AT91C_BASE_PIOB + PIO_OER(0));
|
||||
writel(AT91C_PIO_PB4|AT91C_PIO_PB5, AT91C_BASE_PIOB + PIO_SODR(0));
|
||||
|
||||
writel(1 << AT91C_ID_EMAC, AT91C_PMC_PCER);
|
||||
|
||||
register_device(&sdram_dev);
|
||||
register_device(&macb_dev);
|
||||
register_device(&cfi_dev);
|
||||
|
||||
dev_add_partition(&cfi_dev, 0x00000, 256 * 1024, PARTITION_FIXED, "self");
|
||||
dev_add_partition(&cfi_dev, 0x40000, 128 * 1024, PARTITION_FIXED, "env");
|
||||
|
||||
armlinux_set_bootparams((void *)0x20000100);
|
||||
armlinux_set_architecture(MACH_TYPE_MMCCPU);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
device_initcall(mmccpu_devices_init);
|
||||
|
||||
static struct device_d mmccpu_serial_device = {
|
||||
.name = "atmel_serial",
|
||||
.id = "cs0",
|
||||
.map_base = AT91C_BASE_DBGU,
|
||||
.size = 4096,
|
||||
.type = DEVICE_TYPE_CONSOLE,
|
||||
};
|
||||
|
||||
static int mmccpu_console_init(void)
|
||||
{
|
||||
writel(AT91C_PC31_DTXD | AT91C_PC30_DRXD, AT91C_PIOC_PDR);
|
||||
|
||||
register_device(&mmccpu_serial_device);
|
||||
return 0;
|
||||
}
|
||||
|
||||
console_initcall(mmccpu_console_init);
|
||||
|
|
@ -0,0 +1,329 @@
|
|||
/*
|
||||
* Board specific setup info
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
#define SDRAM 0x20000000 /* address of the SDRAM */
|
||||
|
||||
/* values */
|
||||
#define MASTER_PLL_MUL 54
|
||||
#define MASTER_PLL_DIV 4
|
||||
|
||||
/* clocks */
|
||||
#define MOR_VAL 0x00002001 /* CKGR_MOR - enable main osc. */
|
||||
#define PLLAR_VAL (0x2000BF00 | ((MASTER_PLL_MUL - 1)<< 16) | MASTER_PLL_DIV)
|
||||
#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz for USB) */
|
||||
|
||||
#define MCKR1_VAL 0x00000100 /* slowclock */
|
||||
#define MCKR2_VAL 0x00000102 /* PCK/2 = MCK Master Clock from PLLA */
|
||||
|
||||
#define WDTC_WDMR_VAL 0x3fff8fff /* disable watchdog */
|
||||
#define PIOD_PDR_VAL1 0xFFFF0000 /* define PDC[31:16] as DATA[31:16] */
|
||||
#define PIOD_PPUDR_VAL 0xFFFF0000 /* no pull-up for D[31:16] */
|
||||
#define MATRIX_EBI0CSA_VAL 0x0000010A /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 1.8V memories */
|
||||
#define MATRIX_EBI1CSA_VAL 0x00010100 /* EBI1_CSA, 3.3v, no pull-ups */
|
||||
|
||||
/* SDRAM */
|
||||
#define SDRC_MR_VAL1 0 /* SDRAMC_MR Mode register */
|
||||
#define SDRC_TR_VAL1 0x13c /* SDRAMC_TR - Refresh Timer register */
|
||||
#define SDRC_CR_VAL 0xc533827a /* SDRAMC_CR - Configuration register */
|
||||
#define SDRC_MDR_VAL 0 /* Memory Device Register -> SDRAM */
|
||||
#define SDRC_MR_VAL2 0x00000002 /* SDRAMC_MR */
|
||||
#define SDRAM_VAL1 0 /* SDRAM_BASE */
|
||||
#define SDRC_MR_VAL3 4 /* SDRC_MR */
|
||||
#define SDRAM_VAL2 0 /* SDRAM_BASE */
|
||||
#define SDRAM_VAL3 0 /* SDRAM_BASE */
|
||||
#define SDRAM_VAL4 0 /* SDRAM_BASE */
|
||||
#define SDRAM_VAL5 0 /* SDRAM_BASE */
|
||||
#define SDRAM_VAL6 0 /* SDRAM_BASE */
|
||||
#define SDRAM_VAL7 0 /* SDRAM_BASE */
|
||||
#define SDRAM_VAL8 0 /* SDRAM_BASE */
|
||||
#define SDRAM_VAL9 0 /* SDRAM_BASE */
|
||||
#define SDRC_MR_VAL4 3 /* SDRC_MR */
|
||||
#define SDRAM_VAL10 0 /* SDRAM_BASE */
|
||||
#define SDRC_MR_VAL5 0 /* SDRC_MR */
|
||||
#define SDRAM_VAL11 0 /* SDRAM_BASE */
|
||||
#define SDRC_TR_VAL2 0x30c /* SDRAM_TR */
|
||||
#define SDRAM_VAL12 0 /* SDRAM_BASE */
|
||||
|
||||
/* setup CS0 (NOR Flash) - 16-bit */
|
||||
#if 1
|
||||
#define SMC0_SETUP0_VAL 0x00080203 /* SMC_SETUP */
|
||||
#define SMC0_PULSE0_VAL 0x0d050705 /* SMC_PULSE */
|
||||
#define SMC0_CYCLE0_VAL 0x00100010 /* SMC_CYCLE */
|
||||
#define SMC0_CTRL0_VAL 0x00161003 /* SMC_MODE */
|
||||
#elif 0 /* slow setup */
|
||||
#define SMC0_SETUP0_VAL 0x00080203 /* SMC_SETUP */
|
||||
#define SMC0_PULSE0_VAL 0x0d050705 /* SMC_PULSE */
|
||||
#define SMC0_CYCLE0_VAL 0x0d000d00 /* SMC_CYCLE */
|
||||
#define SMC0_CTRL0_VAL 0x00111003 /* SMC_MODE */
|
||||
#else /* RONETIX' original values */
|
||||
#define SMC0_SETUP0_VAL 0x0A0A0A0A /* SMC_SETUP */
|
||||
#define SMC0_PULSE0_VAL 0x0B0B0B0B /* SMC_PULSE */
|
||||
#define SMC0_CYCLE0_VAL 0x00160016 /* SMC_CYCLE */
|
||||
#define SMC0_CTRL0_VAL 0x00161003 /* SMC_MODE */
|
||||
#endif
|
||||
|
||||
|
||||
#define RSTC_RMR_VAL 0xA5000301 /* user reset enable */
|
||||
|
||||
|
||||
_TEXT_BASE:
|
||||
.word TEXT_BASE
|
||||
|
||||
.globl board_init_lowlevel
|
||||
board_init_lowlevel:
|
||||
|
||||
mov r5, pc // r5 = POS1 + 4 current
|
||||
POS1:
|
||||
ldr r0, =POS1 // r0 = POS1 compile
|
||||
ldr r2, _TEXT_BASE
|
||||
sub r0, r0, r2 // r0 = POS1-_TEXT_BASE (POS1 relative)
|
||||
sub r5, r5, r0 // r0 = TEXT_BASE-1
|
||||
sub r5, r5, #4 // r1 = text base - current
|
||||
|
||||
/* memory control configuration 1 */
|
||||
ldr r0, =SMRDATA
|
||||
ldr r2, =SMRDATA1
|
||||
ldr r1, _TEXT_BASE
|
||||
sub r0, r0, r1
|
||||
sub r2, r2, r1
|
||||
add r0, r0, r5
|
||||
add r2, r2, r5
|
||||
0:
|
||||
/* the address */
|
||||
ldr r1, [r0], #4
|
||||
/* the value */
|
||||
ldr r3, [r0], #4
|
||||
str r3, [r1]
|
||||
cmp r2, r0
|
||||
bne 0b
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
;PMC Init Step 1.
|
||||
;------------------------------------------------------------------------------
|
||||
;- Enable the Main Oscillator
|
||||
;----------------------------------------------------------------------------*/
|
||||
/* Test if main oscillator is enabled */
|
||||
ldr r0,=AT91C_PMC_SR
|
||||
ldr r1, [r0]
|
||||
ldr r2,=AT91C_PMC_MOSCS
|
||||
ands r1, r1, r2
|
||||
|
||||
ldr r1, =AT91C_CKGR_MOR
|
||||
|
||||
/* Main oscillator Enable register PMC_MOR: */
|
||||
/* Enable main oscillator, OSCOUNT = 0xFF */
|
||||
ldr r0, =0x0000FF01
|
||||
str r0, [r1]
|
||||
|
||||
/* Reading the PMC Status register to detect when the */
|
||||
/* Main Oscillator is enabled */
|
||||
mov r4, #AT91C_PMC_MOSCS
|
||||
ldr r0,=AT91C_PMC_SR
|
||||
MOSCS_Loop:
|
||||
ldr r3, [r0]
|
||||
and r3, r4, r3
|
||||
cmp r3, #AT91C_PMC_MOSCS
|
||||
bne MOSCS_Loop
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
;PMC Init Step 2.
|
||||
;------------------------------------------------------------------------------
|
||||
;- Setup PLLA
|
||||
;----------------------------------------------------------------------------*/
|
||||
ldr r1, =AT91C_CKGR_PLLAR
|
||||
/* (18.432 MHz / 1) * 13 = 239 MHz */
|
||||
ldr r0, =PLLAR_VAL
|
||||
str r0, [r1]
|
||||
|
||||
/* Reading the PMC Status register to detect */
|
||||
/* when the PLLA is locked */
|
||||
mov r4, #AT91C_PMC_LOCKA
|
||||
ldr r0,=AT91C_PMC_SR
|
||||
MOSCS_Loop1:
|
||||
ldr r3, [r0]
|
||||
and r3, r4, r3
|
||||
cmp r3, #AT91C_PMC_LOCKA
|
||||
bne MOSCS_Loop1
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
;PMC Init Step 3.
|
||||
;------------------------------------------------------------------------------
|
||||
;- Switch on the Main Oscillator 18.432 MHz
|
||||
;----------------------------------------------------------------------------*/
|
||||
Init_MCKR:
|
||||
|
||||
/* -Master Clock Controller register PMC_MCKR */
|
||||
ldr r0, =MCKR1_VAL
|
||||
ldr r1, =AT91C_PMC_MCKR
|
||||
str r0, [r1]
|
||||
|
||||
/* Reading the PMC Status register to detect */
|
||||
/* when the Master clock is ready */
|
||||
mov r4, #AT91C_PMC_MCKRDY
|
||||
MCKRDY_Loop:
|
||||
ldr r1, =AT91C_PMC_SR
|
||||
ldr r3, [r1]
|
||||
and r3, r4, r3
|
||||
cmp r3, #AT91C_PMC_MCKRDY
|
||||
bne MCKRDY_Loop
|
||||
|
||||
ldr r0, =MCKR2_VAL
|
||||
ldr r1, =AT91C_PMC_MCKR
|
||||
str r0, [r1]
|
||||
|
||||
/* Reading the PMC Status register to detect */
|
||||
/* when the Master clock is ready */
|
||||
mov r4, #AT91C_PMC_MCKRDY
|
||||
MCKRDY_Loop1:
|
||||
ldr r1, =AT91C_PMC_SR
|
||||
ldr r3, [r1]
|
||||
and r3, r4, r3
|
||||
cmp r3, #AT91C_PMC_MCKRDY
|
||||
bne MCKRDY_Loop1
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
;PMC Init Step 4.
|
||||
;------------------------------------------------------------------------------
|
||||
;- Setup PLLB
|
||||
;----------------------------------------------------------------------------*/
|
||||
ldr r1, = AT91C_PMC_PLLBR
|
||||
|
||||
/* 48.054857 MHz = 18432000 * 72 / 14 / 2 for USB) */
|
||||
ldr r0, =PLLBR_VAL
|
||||
str r0, [r1]
|
||||
|
||||
/* Reading the PMC Status register to detect */
|
||||
/* when the PLLB is locked */
|
||||
mov r4, #AT91C_PMC_LOCKB
|
||||
MOSCS_Loop2:
|
||||
ldr r1, = AT91C_PMC_SR
|
||||
ldr r3, [r1]
|
||||
and r3, r4, r3
|
||||
cmp r3, #AT91C_PMC_LOCKB
|
||||
bne MOSCS_Loop2
|
||||
|
||||
/* memory control configuration 2 */
|
||||
ldr r0, =SMRDATA1
|
||||
ldr r2, =SMRDATA2
|
||||
ldr r1, _TEXT_BASE
|
||||
sub r0, r0, r1
|
||||
sub r2, r2, r1
|
||||
add r0, r0, r5
|
||||
add r2, r2, r5
|
||||
|
||||
2:
|
||||
/* the address */
|
||||
ldr r1, [r0], #4
|
||||
/* the value */
|
||||
ldr r3, [r0], #4
|
||||
str r3, [r1]
|
||||
cmp r2, r0
|
||||
bne 2b
|
||||
|
||||
/* everything is fine now */
|
||||
mov pc, lr
|
||||
|
||||
.ltorg
|
||||
|
||||
SMRDATA:
|
||||
.word AT91C_WDTC_WDMR
|
||||
.word WDTC_WDMR_VAL
|
||||
.word AT91C_PIOD_PDR
|
||||
.word PIOD_PDR_VAL1
|
||||
.word AT91C_PIOD_PPUDR
|
||||
.word PIOD_PPUDR_VAL
|
||||
.word AT91C_PIOD_ASR
|
||||
.word PIOD_PPUDR_VAL
|
||||
|
||||
.word AT91C_CCFG_EBI0CSA
|
||||
.word MATRIX_EBI0CSA_VAL
|
||||
.word AT91C_CCFG_EBI1CSA
|
||||
.word MATRIX_EBI1CSA_VAL
|
||||
|
||||
/* flash */
|
||||
.word AT91C_SMC0_CTRL0
|
||||
.word SMC0_CTRL0_VAL
|
||||
|
||||
.word AT91C_SMC0_CYCLE0
|
||||
.word SMC0_CYCLE0_VAL
|
||||
|
||||
.word AT91C_SMC0_PULSE0
|
||||
.word SMC0_PULSE0_VAL
|
||||
|
||||
.word AT91C_SMC0_SETUP0
|
||||
.word SMC0_SETUP0_VAL
|
||||
|
||||
SMRDATA1:
|
||||
|
||||
.word AT91C_SDRAMC0_MR
|
||||
.word SDRC_MR_VAL1
|
||||
.word AT91C_SDRAMC0_TR
|
||||
.word SDRC_TR_VAL1
|
||||
.word AT91C_SDRAMC0_CR
|
||||
.word SDRC_CR_VAL
|
||||
.word AT91C_SDRAMC0_MDR
|
||||
.word SDRC_MDR_VAL
|
||||
.word AT91C_SDRAMC0_MR
|
||||
.word SDRC_MR_VAL2
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL1
|
||||
.word AT91C_SDRAMC0_MR
|
||||
.word SDRC_MR_VAL3
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL2
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL3
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL4
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL5
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL6
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL7
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL8
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL9
|
||||
.word AT91C_SDRAMC0_MR
|
||||
.word SDRC_MR_VAL4
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL10
|
||||
.word AT91C_SDRAMC0_MR
|
||||
.word SDRC_MR_VAL5
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL11
|
||||
.word AT91C_SDRAMC0_TR
|
||||
.word SDRC_TR_VAL2
|
||||
.word SDRAM
|
||||
.word SDRAM_VAL12
|
||||
/* User reset enable */
|
||||
.word AT91C_RSTC_RMR
|
||||
.word RSTC_RMR_VAL
|
||||
/* MATRIX_MCFG - REMAP all masters */
|
||||
|
||||
SMRDATA2:
|
||||
.word 0
|
||||
Loading…
Reference in New Issue