/*
 * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
 *
 * Device initialization for the following modules and board variants:
 *   - phyCORE: PCM-953, phyBOARD-MAIA, phyBOARD-WEGA
 *   - phyFLEX: PBA-B-01
 *   - phyCARD: PCA-A-XS1
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <bootsource.h>
#include <common.h>
#include <nand.h>
#include <init.h>
#include <io.h>
#include <linux/sizes.h>
#include <envfs.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <linux/phy.h>
#include <linux/micrel_phy.h>
#include <mach/am33xx-generic.h>
#include <mach/am33xx-silicon.h>
#include <mach/bbu.h>
#include <net.h>
#include <gpio.h>
#include <reset_source.h>

#include "sob_odu_eeprom.h"

static int physom_coredevice_init(void)
{
	if (!of_machine_is_compatible("phytec,am335x-som"))
		return 0;

	am33xx_register_ethaddr(0, 0);

	return 0;
}
coredevice_initcall(physom_coredevice_init);

static struct omap_barebox_part physom_barebox_part = {
	.nand_offset = SZ_512K,
	.nand_size = SZ_512K,
	.nor_offset = SZ_128K,
	.nor_size = SZ_512K,
};

static char *xloadslots[] = {
	"/dev/nand0.xload.bb",
	"/dev/nand0.xload_backup1.bb",
	"/dev/nand0.xload_backup2.bb",
	"/dev/nand0.xload_backup3.bb"
};

#define OWHW_GPIO_SWITCH_RESET 56

static void owhw_switch_reset(void)
{
	pr_info("Resetting OWHW switch\n");
	gpio_set_value(OWHW_GPIO_SWITCH_RESET, 0);
	/* spec states at least 10ms; using 20 here actualy results in
	 * something like 16ms as measured by the scope */
	mdelay(20);
	gpio_set_value(OWHW_GPIO_SWITCH_RESET, 1);
}

static int physom_devices_init(void)
{
	if (!of_machine_is_compatible("phytec,am335x-som"))
		return 0;

	switch (bootsource_get()) {
	case BOOTSOURCE_SPI:
		of_device_enable_path("/chosen/environment-spi");
		break;
	case BOOTSOURCE_MMC:
		omap_set_bootmmc_devname("mmc0");
		break;
	default:
		of_device_enable_path("/chosen/environment-nand");
		break;
	}

	omap_set_barebox_part(&physom_barebox_part);

	if (of_machine_is_compatible("gsmk,owhw")) {
		defaultenv_append_directory(defaultenv_gsmk_owhw);
		/* claim + initialize the switch_reset GPIO */
		gpio_request(OWHW_GPIO_SWITCH_RESET, "switch-reset");
		gpio_direction_output(OWHW_GPIO_SWITCH_RESET, 1);
		switch (reset_source_get()) {
		case RESET_POR:
		case RESET_UKWN:
			/* actually perform a switch reset, as we cannot rely
			 * on the power-up reset to properly rest it */
			owhw_switch_reset();
			break;
		default:
			break;
		}
	} else if (of_machine_is_compatible("sysmocom,odu")) {
		defaultenv_append_directory(defaultenv_sysmocom_odu);
	} else {
		defaultenv_append_directory(defaultenv_physom_am335x);
	}

	/* Special module set up */
	if (of_machine_is_compatible("phytec,phycore-am335x-som")) {
		armlinux_set_architecture(MACH_TYPE_PCM051);
		barebox_set_hostname("pcm051");
	}

	if (of_machine_is_compatible("phytec,phyflex-am335x-som")) {
		armlinux_set_architecture(MACH_TYPE_PFLA03);
		am33xx_select_rmii2_crs_dv();
		barebox_set_hostname("pfla03");
	}

	if (of_machine_is_compatible("phytec,phycard-am335x-som")) {
		armlinux_set_architecture(MACH_TYPE_PCAAXS1);
		barebox_set_hostname("pcaaxs1");
	}

	/* Register update handler */
	am33xx_bbu_spi_nor_mlo_register_handler("MLO.spi", "/dev/m25p0.xload");
	am33xx_bbu_spi_nor_register_handler("spi", "/dev/m25p0.barebox");
	am33xx_bbu_nand_xloadslots_register_handler("MLO.nand",
		xloadslots, ARRAY_SIZE(xloadslots));
	am33xx_bbu_nand_register_handler("nand", "/dev/nand0.barebox.bb");

	if (IS_ENABLED(CONFIG_SHELL_NONE))
		return am33xx_of_register_bootdevice();

	return 0;
}
device_initcall(physom_devices_init);

#define CRCPOLY_LE 0xedb88320
static inline u32 __pure crc32_le_generic(u32 crc, unsigned char const *p,
					  size_t len, u32 polynomial)
{
	int i;
	while (len--) {
		crc ^= *p++;
		for (i = 0; i < 8; i++)
			crc = (crc >> 1) ^ ((crc & 1) ? polynomial : 0);
	}
	return crc;
}
u32 __pure crc32_le(u32 crc, unsigned char const *p, size_t len)
{
	return crc32_le_generic(crc, p, len, CRCPOLY_LE);
}

static int sob_odu_eeprom_init(void)
{
	struct sob_odu_eeprom soe;
	uint32_t crc32_comp;
	struct cdev *cdev;
	int ret;

	if (!of_machine_is_compatible("sysmocom,odu"))
		return 0;

	cdev = cdev_by_name("eeprom0");
	if (!cdev)
		return -ENODEV;

	ret = cdev_read(cdev, &soe, sizeof(soe), 0, 0);
	if (ret < 0)
		return ret;

        if (soe.magic != SOBJB_EE_MAGIC || soe.version != SOBJB_EE_VERSION) {
                pr_err("EEPROM magic/version wrong\n");
                return -EINVAL;
        }
        crc32_comp = crc32_le(0xffffffff, (void *)(&soe) + 8, sizeof(soe)-8);
        if (soe.crc32 != crc32_comp) {
                pr_err("EEPROM CRC32 mismatch (eeprom=0x%08x, computed=0x%08x)\n",
                        soe.crc32, crc32_comp);
                return -EINVAL;
        }
        pr_info("SOB-ODU board v%u, serial number %u, mfg %u, hw_options=0x%08x\n",
                soe.model, soe.serial, soe.manuf_date, soe.hw_options);

	eth_register_ethaddr(0, soe.mac_eth0);
	eth_register_ethaddr(1, soe.mac_eth1);

	return 0;
}
late_initcall(sob_odu_eeprom_init);
