/*
 * dts file for Xilinx ZynqMP
 *
 * (C) Copyright 2014 - 2015, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

/ {
	compatible = "xlnx,zynqmp";
	#address-cells = <2>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x1>;
		};

		cpu@2 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x3>;
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <0 143 4>,
			     <0 144 4>,
			     <0 145 4>,
			     <0 146 4>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <1 13 0xf01>,
			     <1 14 0xf01>,
			     <1 11 0xf01>,
			     <1 10 0xf01>;
	};

	amba_apu {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges;

		gic: interrupt-controller@f9010000 {
			compatible = "arm,gic-400", "arm,cortex-a15-gic";
			#interrupt-cells = <3>;
			reg = <0x0 0xf9010000 0x10000>,
			      <0x0 0xf902f000 0x2000>,
			      <0x0 0xf9040000 0x20000>,
			      <0x0 0xf906f000 0x2000>;
			interrupt-controller;
			interrupt-parent = <&gic>;
			interrupts = <1 9 0xf04>;
		};
	};

	amba {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges;

		misc_clk: misc_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};

		ttc0: timer@ff110000 {
			compatible = "cdns,ttc";
			status = "disabled";
			interrupt-parent = <&gic>;
			interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
			reg = <0x0 0xff110000 0x1000>;
			clocks = <&misc_clk>;
			timer-width = <32>;
		};

		ttc1: timer@ff120000 {
			compatible = "cdns,ttc";
			status = "disabled";
			interrupt-parent = <&gic>;
			interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
			reg = <0x0 0xff120000 0x1000>;
			clocks = <&misc_clk>;
			timer-width = <32>;
		};

		ttc2: timer@ff130000 {
			compatible = "cdns,ttc";
			status = "disabled";
			interrupt-parent = <&gic>;
			interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
			reg = <0x0 0xff130000 0x1000>;
			clocks = <&misc_clk>;
			timer-width = <32>;
		};

		ttc3: timer@ff140000 {
			compatible = "cdns,ttc";
			status = "disabled";
			interrupt-parent = <&gic>;
			interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
			reg = <0x0 0xff140000 0x1000>;
			clocks = <&misc_clk>;
			timer-width = <32>;
		};

		uart0: serial@ff000000 {
			compatible = "cdns,uart-r1p8";
			status = "disabled";
			interrupt-parent = <&gic>;
			interrupts = <0 21 4>;
			reg = <0x0 0xff000000 0x1000>;
			clock-names = "uart_clk", "pclk";
			clocks = <&misc_clk &misc_clk>;
		};

		uart1: serial@ff010000 {
			compatible = "cdns,uart-r1p8";
			status = "disabled";
			interrupt-parent = <&gic>;
			interrupts = <0 22 4>;
			reg = <0x0 0xff010000 0x1000>;
			clock-names = "uart_clk", "pclk";
			clocks = <&misc_clk &misc_clk>;
		};

		gpio: gpio@ff0a0000 {
			compatible = "xlnx,zynq-gpio-1.0";
			status = "disabled";
			#gpio-cells = <0x2>;
			clocks = <&misc_clk>;
			interrupt-parent = <&gic>;
			interrupts = <0 16 4>;
			reg = <0x0 0xff0a0000 0x1000>;
		};

		gem0: ethernet@ff0b0000 {
			compatible = "cdns,gem";
			status = "disabled";
			interrupt-parent = <&gic>;
			interrupts = <0 57 4>, <0 57 4>;
			reg = <0x0 0xff0b0000 0x1000>;
			clock-names = "pclk", "hclk", "tx_clk";
			clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gem1: ethernet@ff0c0000 {
			compatible = "cdns,gem";
			status = "disabled";
			interrupt-parent = <&gic>;
			interrupts = <0 59 4>, <0 59 4>;
			reg = <0x0 0xff0c0000 0x1000>;
			clock-names = "pclk", "hclk", "tx_clk";
			clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gem2: ethernet@ff0d0000 {
			compatible = "cdns,gem";
			status = "disabled";
			interrupt-parent = <&gic>;
			interrupts = <0 61 4>, <0 61 4>;
			reg = <0x0 0xff0d0000 0x1000>;
			clock-names = "pclk", "hclk", "tx_clk";
			clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gem3: ethernet@ff0e0000 {
			compatible = "cdns,gem";
			status = "disabled";
			interrupt-parent = <&gic>;
			interrupts = <0 63 4>, <0 63 4>;
			reg = <0x0 0xff0e0000 0x1000>;
			clock-names = "pclk", "hclk", "tx_clk";
			clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi0: spi@ff040000 {
			compatible = "cdns,spi-r1p6";
			status = "disabled";
			interrupt-parent = <&gic>;
			interrupts = <0 19 4>;
			reg = <0x0 0xff040000 0x1000>;
			clock-names = "ref_clk", "pclk";
			clocks = <&misc_clk &misc_clk>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@ff050000 {
			compatible = "cdns,spi-r1p6";
			status = "disabled";
			interrupt-parent = <&gic>;
			interrupts = <0 20 4>;
			reg = <0x0 0xff050000 0x1000>;
			clock-names = "ref_clk", "pclk";
			clocks = <&misc_clk &misc_clk>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c_clk: i2c_clk {
			compatible = "fixed-clock";
			#clock-cells = <0x0>;
			clock-frequency = <111111111>;
		};

		i2c0: i2c@ff020000 {
			compatible = "cdns,i2c-r1p10";
			status = "disabled";
			interrupt-parent = <&gic>;
			interrupts = <0 17 4>;
			reg = <0x0 0xff020000 0x1000>;
			clocks = <&i2c_clk>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@ff030000 {
			compatible = "cdns,i2c-r1p10";
			status = "disabled";
			interrupt-parent = <&gic>;
			interrupts = <0 18 4>;
			reg = <0x0 0xff030000 0x1000>;
			clocks = <&i2c_clk>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		sdhci0: sdhci@ff160000 {
			compatible = "arasan,sdhci-8.9a";
			status = "disabled";
			interrupt-parent = <&gic>;
			interrupts = <0 48 4>;
			reg = <0x0 0xff160000 0x1000>;
			clock-names = "clk_xin", "clk_ahb";
			clocks = <&misc_clk>, <&misc_clk>;
		};

		sdhci1: sdhci@ff170000 {
			compatible = "arasan,sdhci-8.9a";
			status = "disabled";
			interrupt-parent = <&gic>;
			interrupts = <0 49 4>;
			reg = <0x0 0xff170000 0x1000>;
			clock-names = "clk_xin", "clk_ahb";
			clocks = <&misc_clk>, <&misc_clk>;
		};

		watchdog0: watchdog@fd4d0000 {
			compatible = "cdns,wdt-r1p2";
			status = "disabled";
			clocks= <&misc_clk>;
			interrupt-parent = <&gic>;
			interrupts = <0 52 1>;
			reg = <0x0 0xfd4d0000 0x1000>;
			timeout-sec = <10>;
		};
	};
};
