/* MDMISC	mirroring	interleaved (row/bank/col) */
wm 32 MX6_MMDC_P0_MDMISC		0x00000742
check 32 while_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002

wm 32 MX6_MMDC_P0_MDSCR			0x00008000
check 32 while_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000

wm 32 MX6_MMDC_P0_MDCTL			0x831a0000
check 32 while_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000

wm 32 MX6_MMDC_P0_MDCFG0		0x3f435333
wm 32 MX6_MMDC_P0_MDCFG1		0x926e8a63
wm 32 MX6_MMDC_P0_MDCFG2		0x01ff00db
wm 32 MX6_MMDC_P0_MDRWD			0x000026d2
wm 32 MX6_MMDC_P0_MDOR			0x00431023
wm 32 MX6_MMDC_P0_MDOTC			0x1b333030
wm 32 MX6_MMDC_P0_MDPDC			0x0002006d
wm 32 MX6_MMDC_P1_MDPDC			0x0002006d
wm 32 MX6_MMDC_P0_MDASP			0x00000027

wm 32 MX6_MMDC_P0_MDSCR			0x05208030
wm 32 MX6_MMDC_P0_MDSCR			0x00048031
wm 32 MX6_MMDC_P0_MDSCR			0x00408032
wm 32 MX6_MMDC_P0_MDSCR			0x00008033
wm 32 MX6_MMDC_P0_MDREF			0x0000c000
wm 32 MX6_MMDC_P0_MDSCR			0x00008020

wm 32 MX6_MMDC_P0_MPODTCTRL		0x00022222
wm 32 MX6_MMDC_P1_MPODTCTRL		0x00022222

wm 32 MX6_MMDC_P0_MPPDCMPR2		0x00000003
wm 32 MX6_MMDC_P0_MAPSR			0x00001007
wm 32 MX6_MMDC_P0_MDSCR			0x04008010
wm 32 MX6_MMDC_P0_MDSCR			0x04008040

wm 32 MX6_MMDC_P0_MPZQHWCTRL		0xA1390001
check 32 while_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000
wm 32 MX6_MMDC_P0_MPZQHWCTRL		0xA1380000

wm 32 MX6_MMDC_P0_MPWLDECTRL0	0x001e001e
wm 32 MX6_MMDC_P0_MPWLDECTRL1	0x001e001e
wm 32 MX6_MMDC_P1_MPWLDECTRL0	0x001e001e
wm 32 MX6_MMDC_P1_MPWLDECTRL1	0x001e001e

wm 32 MX6_MMDC_P0_MDSCR			0x00048033
wm 32 MX6_IOM_DRAM_SDQS0		0x00007030
wm 32 MX6_IOM_DRAM_SDQS1		0x00007030
wm 32 MX6_IOM_DRAM_SDQS2		0x00007030
wm 32 MX6_IOM_DRAM_SDQS3		0x00007030
wm 32 MX6_IOM_DRAM_SDQS4		0x00007030
wm 32 MX6_IOM_DRAM_SDQS5		0x00007030
wm 32 MX6_IOM_DRAM_SDQS6		0x00007030
wm 32 MX6_IOM_DRAM_SDQS7		0x00007030

wm 32 MX6_MMDC_P0_MDSCR			0x00008020
wm 32 MX6_MMDC_P0_MDSCR			0x04008050

wm 32 MX6_MMDC_P0_MPRDDLCTL		0x40404040
wm 32 MX6_MMDC_P0_MPWRDLCTL		0x40404040
wm 32 MX6_MMDC_P1_MPRDDLCTL		0x40404040
wm 32 MX6_MMDC_P1_MPWRDLCTL		0x40404040
wm 32 MX6_MMDC_P0_MPMUR0		0x00000800

wm 32 MX6_MMDC_P0_MPDGCTRL0		0x80000000
check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000
wm 32 MX6_MMDC_P0_MPDGCTRL0		0x80000000
check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000
wm 32 MX6_MMDC_P0_MPDGCTRL0		0x50800000
check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x10001000

wm 32 MX6_IOM_DRAM_SDQS0		0x00000030
wm 32 MX6_IOM_DRAM_SDQS1		0x00000030
wm 32 MX6_IOM_DRAM_SDQS2		0x00000030
wm 32 MX6_IOM_DRAM_SDQS3		0x00000030
wm 32 MX6_IOM_DRAM_SDQS4		0x00000030
wm 32 MX6_IOM_DRAM_SDQS5		0x00000030
wm 32 MX6_IOM_DRAM_SDQS6		0x00000030
wm 32 MX6_IOM_DRAM_SDQS7		0x00000030

wm 32 MX6_MMDC_P0_MDSCR			0x04008050
wm 32 MX6_MMDC_P0_MPRDDLHWCTL		0x00000030
wm 32 MX6_MMDC_P1_MPRDDLHWCTL		0x00000030

check 32 while_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
check 32 while_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f

wm 32 MX6_MMDC_P0_MDSCR			0x04008050
wm 32 MX6_MMDC_P0_MPWRDLHWCTL		0x00000030
check 32 while_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f

wm 32 MX6_MMDC_P0_MDSCR			0x04008050
wm 32 MX6_MMDC_P1_MPWRDLHWCTL		0x00000030
check 32 while_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
wm 32 MX6_MMDC_P0_MDSCR			0x00008033
wm 32 MX6_MMDC_P0_MPZQHWCTRL		0xa138002b
wm 32 MX6_MMDC_P0_MDREF			0x00001800
wm 32 MX6_MMDC_P0_MAPSR			0x00001006
wm 32 MX6_MMDC_P0_MDPDC			0x0002556d
wm 32 MX6_MMDC_P1_MDPDC			0x0002556d
wm 32 MX6_MMDC_P0_MDSCR			0x00000000
check 32 while_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000
